1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
133 struct sdvo_device_mapping {
140 struct drm_i915_error_state {
155 struct drm_i915_error_object {
159 } *ringbuffer, *batchbuffer[2];
160 struct drm_i915_error_buffer {
176 struct drm_i915_display_funcs {
177 void (*dpms)(struct drm_crtc *crtc, int mode);
178 bool (*fbc_enabled)(struct drm_crtc *crtc);
179 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
180 void (*disable_fbc)(struct drm_device *dev);
181 int (*get_display_clock_speed)(struct drm_device *dev);
182 int (*get_fifo_size)(struct drm_device *dev, int plane);
183 void (*update_wm)(struct drm_device *dev, int planea_clock,
184 int planeb_clock, int sr_hdisplay, int pixel_size);
185 /* clock updates for mode set */
187 /* render clock increase/decrease */
188 /* display clock increase/decrease */
189 /* pll clock increase/decrease */
190 /* clock gating init */
193 struct intel_overlay;
195 struct intel_device_info {
212 u8 has_pipe_cxsr : 1;
214 u8 cursor_needs_physical : 1;
218 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
219 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
220 FBC_MODE_TOO_LARGE, /* mode too large for compression */
221 FBC_BAD_PLANE, /* fbc not supported on plane */
222 FBC_NOT_TILED, /* buffer not tiled */
225 typedef struct drm_i915_private {
226 struct drm_device *dev;
228 const struct intel_device_info *info;
234 struct pci_dev *bridge_dev;
235 drm_i915_ring_buffer_t ring;
237 drm_dma_handle_t *status_page_dmah;
238 void *hw_status_page;
240 dma_addr_t dma_status_page;
242 unsigned int status_gfx_addr;
243 unsigned int seqno_gfx_addr;
244 drm_local_map_t hws_map;
245 struct drm_gem_object *hws_obj;
246 struct drm_gem_object *seqno_obj;
247 struct drm_gem_object *pwrctx;
249 struct resource mch_res;
257 wait_queue_head_t irq_queue;
258 atomic_t irq_received;
259 /** Protects user_irq_refcount and irq_mask_reg */
260 spinlock_t user_irq_lock;
261 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
262 int user_irq_refcount;
264 /** Cached value of IMR to avoid reads in updating the bitfield */
267 /** splitted irq regs for graphics and display engine on Ironlake,
268 irq_mask_reg is still used for display irq. */
270 u32 gt_irq_enable_reg;
271 u32 de_irq_enable_reg;
272 u32 pch_irq_mask_reg;
273 u32 pch_irq_enable_reg;
275 u32 hotplug_supported_mask;
276 struct work_struct hotplug_work;
278 int tex_lru_log_granularity;
279 int allow_batchbuffer;
280 struct mem_block *agp_heap;
281 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
284 /* For hangcheck timer */
285 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
286 struct timer_list hangcheck_timer;
292 unsigned long cfb_size;
293 unsigned long cfb_pitch;
299 struct intel_opregion opregion;
302 struct intel_overlay *overlay;
305 int backlight_duty_cycle; /* restore backlight to this value */
306 bool panel_wants_dither;
307 struct drm_display_mode *panel_fixed_mode;
308 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
309 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
311 /* Feature bits from the VBIOS */
312 unsigned int int_tv_support:1;
313 unsigned int lvds_dither:1;
314 unsigned int lvds_vbt:1;
315 unsigned int int_crt_support:1;
316 unsigned int lvds_use_ssc:1;
317 unsigned int edp_support:1;
321 struct notifier_block lid_notifier;
323 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
324 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
325 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
326 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
328 unsigned int fsb_freq, mem_freq;
330 spinlock_t error_lock;
331 struct drm_i915_error_state *first_error;
332 struct work_struct error_work;
333 struct workqueue_struct *wq;
335 /* Display functions */
336 struct drm_i915_display_funcs display;
361 u32 saveTRANS_HTOTAL_A;
362 u32 saveTRANS_HBLANK_A;
363 u32 saveTRANS_HSYNC_A;
364 u32 saveTRANS_VTOTAL_A;
365 u32 saveTRANS_VBLANK_A;
366 u32 saveTRANS_VSYNC_A;
374 u32 savePFIT_PGM_RATIOS;
375 u32 saveBLC_HIST_CTL;
377 u32 saveBLC_PWM_CTL2;
378 u32 saveBLC_CPU_PWM_CTL;
379 u32 saveBLC_CPU_PWM_CTL2;
392 u32 saveTRANS_HTOTAL_B;
393 u32 saveTRANS_HBLANK_B;
394 u32 saveTRANS_HSYNC_B;
395 u32 saveTRANS_VTOTAL_B;
396 u32 saveTRANS_VBLANK_B;
397 u32 saveTRANS_VSYNC_B;
411 u32 savePP_ON_DELAYS;
412 u32 savePP_OFF_DELAYS;
420 u32 savePFIT_CONTROL;
421 u32 save_palette_a[256];
422 u32 save_palette_b[256];
423 u32 saveDPFC_CB_BASE;
424 u32 saveFBC_CFB_BASE;
427 u32 saveFBC_CONTROL2;
437 u32 saveCACHE_MODE_0;
438 u32 saveMI_ARB_STATE;
449 uint64_t saveFENCE[16];
460 u32 savePIPEA_GMCH_DATA_M;
461 u32 savePIPEB_GMCH_DATA_M;
462 u32 savePIPEA_GMCH_DATA_N;
463 u32 savePIPEB_GMCH_DATA_N;
464 u32 savePIPEA_DP_LINK_M;
465 u32 savePIPEB_DP_LINK_M;
466 u32 savePIPEA_DP_LINK_N;
467 u32 savePIPEB_DP_LINK_N;
478 u32 savePCH_DREF_CONTROL;
479 u32 saveDISP_ARB_CTL;
480 u32 savePIPEA_DATA_M1;
481 u32 savePIPEA_DATA_N1;
482 u32 savePIPEA_LINK_M1;
483 u32 savePIPEA_LINK_N1;
484 u32 savePIPEB_DATA_M1;
485 u32 savePIPEB_DATA_N1;
486 u32 savePIPEB_LINK_M1;
487 u32 savePIPEB_LINK_N1;
488 u32 saveMCHBAR_RENDER_STANDBY;
491 struct drm_mm gtt_space;
493 struct io_mapping *gtt_mapping;
497 * Membership on list of all loaded devices, used to evict
498 * inactive buffers under memory pressure.
500 * Modifications should only be done whilst holding the
501 * shrink_list_lock spinlock.
503 struct list_head shrink_list;
506 * List of objects currently involved in rendering from the
509 * Includes buffers having the contents of their GPU caches
510 * flushed, not necessarily primitives. last_rendering_seqno
511 * represents when the rendering involved will be completed.
513 * A reference is held on the buffer while on this list.
515 spinlock_t active_list_lock;
516 struct list_head active_list;
519 * List of objects which are not in the ringbuffer but which
520 * still have a write_domain which needs to be flushed before
523 * last_rendering_seqno is 0 while an object is in this list.
525 * A reference is held on the buffer while on this list.
527 struct list_head flushing_list;
530 * List of objects currently pending a GPU write flush.
532 * All elements on this list will belong to either the
533 * active_list or flushing_list, last_rendering_seqno can
534 * be used to differentiate between the two elements.
536 struct list_head gpu_write_list;
539 * LRU list of objects which are not in the ringbuffer and
540 * are ready to unbind, but are still in the GTT.
542 * last_rendering_seqno is 0 while an object is in this list.
544 * A reference is not held on the buffer while on this list,
545 * as merely being GTT-bound shouldn't prevent its being
546 * freed, and we'll pull it off the list in the free path.
548 struct list_head inactive_list;
550 /** LRU list of objects with fence regs on them. */
551 struct list_head fence_list;
554 * List of breadcrumbs associated with GPU requests currently
557 struct list_head request_list;
560 * We leave the user IRQ off as much as possible,
561 * but this means that requests will finish and never
562 * be retired once the system goes idle. Set a timer to
563 * fire periodically while the ring is running. When it
564 * fires, go retire requests.
566 struct delayed_work retire_work;
568 uint32_t next_gem_seqno;
571 * Waiting sequence number, if any
573 uint32_t waiting_gem_seqno;
576 * Last seq seen at irq time
578 uint32_t irq_gem_seqno;
581 * Flag if the X Server, and thus DRM, is not currently in
582 * control of the device.
584 * This is set between LeaveVT and EnterVT. It needs to be
585 * replaced with a semaphore. It also needs to be
586 * transitioned away from for kernel modesetting.
591 * Flag if the hardware appears to be wedged.
593 * This is set when attempts to idle the device timeout.
594 * It prevents command submission from occuring and makes
595 * every pending request fail
599 /** Bit 6 swizzling required for X tiling */
600 uint32_t bit_6_swizzle_x;
601 /** Bit 6 swizzling required for Y tiling */
602 uint32_t bit_6_swizzle_y;
604 /* storage for physical objects */
605 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
607 struct sdvo_device_mapping sdvo_mappings[2];
608 /* indicate whether the LVDS_BORDER should be enabled or not */
609 unsigned int lvds_border_bits;
611 struct drm_crtc *plane_to_crtc_mapping[2];
612 struct drm_crtc *pipe_to_crtc_mapping[2];
613 wait_queue_head_t pending_flip_queue;
615 /* Reclocking support */
616 bool render_reclock_avail;
617 bool lvds_downclock_avail;
618 /* indicate whether the LVDS EDID is OK */
620 /* indicates the reduced downclock for LVDS*/
622 struct work_struct idle_work;
623 struct timer_list idle_timer;
627 struct child_device_config *child_dev;
628 struct drm_connector *int_lvds_connector;
630 bool mchbar_need_disable;
636 enum no_fbc_reason no_fbc_reason;
638 struct drm_mm_node *compressed_fb;
639 struct drm_mm_node *compressed_llb;
640 } drm_i915_private_t;
642 /** driver private structure attached to each drm_gem_object */
643 struct drm_i915_gem_object {
644 struct drm_gem_object *obj;
646 /** Current space allocated to this object in the GTT, if any. */
647 struct drm_mm_node *gtt_space;
649 /** This object's place on the active/flushing/inactive lists */
650 struct list_head list;
651 /** This object's place on GPU write list */
652 struct list_head gpu_write_list;
654 /** This object's place on the fenced object LRU */
655 struct list_head fence_list;
658 * This is set if the object is on the active or flushing lists
659 * (has pending rendering), and is not set if it's on inactive (ready
665 * This is set if the object has been written to since last bound
670 /** AGP memory structure for our GTT binding. */
671 DRM_AGP_MEM *agp_mem;
677 * Current offset of the object in GTT space.
679 * This is the same as gtt_space->start
684 * Fake offset for use by mmap(2)
686 uint64_t mmap_offset;
689 * Fence register bits (if any) for this object. Will be set
690 * as needed when mapped into the GTT.
691 * Protected by dev->struct_mutex.
695 /** How many users have pinned this object in GTT space */
698 /** Breadcrumb of last rendering to the buffer. */
699 uint32_t last_rendering_seqno;
701 /** Current tiling mode for the object. */
702 uint32_t tiling_mode;
705 /** Record of address bit 17 of each page at last unbind. */
708 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
712 * If present, while GEM_DOMAIN_CPU is in the read domain this array
713 * flags which individual pages are valid.
715 uint8_t *page_cpu_valid;
717 /** User space pin count and filp owning the pin */
718 uint32_t user_pin_count;
719 struct drm_file *pin_filp;
721 /** for phy allocated objects */
722 struct drm_i915_gem_phys_object *phys_obj;
725 * Used for checking the object doesn't appear more than once
726 * in an execbuffer object list.
731 * Advice: are the backing pages purgeable?
736 * Number of crtcs where this object is currently the fb, but
737 * will be page flipped away on the next vblank. When it
738 * reaches 0, dev_priv->pending_flip_queue will be woken up.
740 atomic_t pending_flip;
743 #define to_intel_bo(x) ((struct drm_i915_gem_object *) (x)->driver_private)
746 * Request queue structure.
748 * The request queue allows us to note sequence numbers that have been emitted
749 * and may be associated with active buffers to be retired.
751 * By keeping this list, we can avoid having to do questionable
752 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
753 * an emission time with seqnos for tracking how far ahead of the GPU we are.
755 struct drm_i915_gem_request {
756 /** GEM sequence number associated with this request. */
759 /** Time at which this request was emitted, in jiffies. */
760 unsigned long emitted_jiffies;
762 /** global list entry for this request */
763 struct list_head list;
765 /** file_priv list entry for this request */
766 struct list_head client_list;
769 struct drm_i915_file_private {
771 struct list_head request_list;
775 enum intel_chip_family {
782 extern struct drm_ioctl_desc i915_ioctls[];
783 extern int i915_max_ioctl;
784 extern unsigned int i915_fbpercrtc;
785 extern unsigned int i915_powersave;
786 extern unsigned int i915_lvds_downclock;
788 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
789 extern int i915_resume(struct drm_device *dev);
790 extern void i915_save_display(struct drm_device *dev);
791 extern void i915_restore_display(struct drm_device *dev);
792 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
793 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
796 extern void i915_kernel_lost_context(struct drm_device * dev);
797 extern int i915_driver_load(struct drm_device *, unsigned long flags);
798 extern int i915_driver_unload(struct drm_device *);
799 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
800 extern void i915_driver_lastclose(struct drm_device * dev);
801 extern void i915_driver_preclose(struct drm_device *dev,
802 struct drm_file *file_priv);
803 extern void i915_driver_postclose(struct drm_device *dev,
804 struct drm_file *file_priv);
805 extern int i915_driver_device_is_agp(struct drm_device * dev);
806 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
808 extern int i915_emit_box(struct drm_device *dev,
809 struct drm_clip_rect *boxes,
810 int i, int DR1, int DR4);
811 extern int i965_reset(struct drm_device *dev, u8 flags);
814 void i915_hangcheck_elapsed(unsigned long data);
815 void i915_destroy_error_state(struct drm_device *dev);
816 extern int i915_irq_emit(struct drm_device *dev, void *data,
817 struct drm_file *file_priv);
818 extern int i915_irq_wait(struct drm_device *dev, void *data,
819 struct drm_file *file_priv);
820 void i915_user_irq_get(struct drm_device *dev);
821 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
822 void i915_user_irq_put(struct drm_device *dev);
823 extern void i915_enable_interrupt (struct drm_device *dev);
825 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
826 extern void i915_driver_irq_preinstall(struct drm_device * dev);
827 extern int i915_driver_irq_postinstall(struct drm_device *dev);
828 extern void i915_driver_irq_uninstall(struct drm_device * dev);
829 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
830 struct drm_file *file_priv);
831 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
832 struct drm_file *file_priv);
833 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
834 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
835 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
836 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
837 extern int i915_vblank_swap(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
839 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
842 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
845 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
847 void intel_enable_asle (struct drm_device *dev);
851 extern int i915_mem_alloc(struct drm_device *dev, void *data,
852 struct drm_file *file_priv);
853 extern int i915_mem_free(struct drm_device *dev, void *data,
854 struct drm_file *file_priv);
855 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
856 struct drm_file *file_priv);
857 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
858 struct drm_file *file_priv);
859 extern void i915_mem_takedown(struct mem_block **heap);
860 extern void i915_mem_release(struct drm_device * dev,
861 struct drm_file *file_priv, struct mem_block *heap);
863 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
864 struct drm_file *file_priv);
865 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
866 struct drm_file *file_priv);
867 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
868 struct drm_file *file_priv);
869 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
871 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
872 struct drm_file *file_priv);
873 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
874 struct drm_file *file_priv);
875 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
876 struct drm_file *file_priv);
877 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file_priv);
879 int i915_gem_execbuffer(struct drm_device *dev, void *data,
880 struct drm_file *file_priv);
881 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897 int i915_gem_set_tiling(struct drm_device *dev, void *data,
898 struct drm_file *file_priv);
899 int i915_gem_get_tiling(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903 void i915_gem_load(struct drm_device *dev);
904 int i915_gem_init_object(struct drm_gem_object *obj);
905 void i915_gem_free_object(struct drm_gem_object *obj);
906 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
907 void i915_gem_object_unpin(struct drm_gem_object *obj);
908 int i915_gem_object_unbind(struct drm_gem_object *obj);
909 void i915_gem_release_mmap(struct drm_gem_object *obj);
910 void i915_gem_lastclose(struct drm_device *dev);
911 uint32_t i915_get_gem_seqno(struct drm_device *dev);
912 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
913 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
914 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
915 void i915_gem_retire_requests(struct drm_device *dev);
916 void i915_gem_retire_work_handler(struct work_struct *work);
917 void i915_gem_clflush_object(struct drm_gem_object *obj);
918 int i915_gem_object_set_domain(struct drm_gem_object *obj,
919 uint32_t read_domains,
920 uint32_t write_domain);
921 int i915_gem_init_ringbuffer(struct drm_device *dev);
922 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
923 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
925 int i915_gem_idle(struct drm_device *dev);
926 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
927 uint32_t flush_domains);
928 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
929 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
930 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
932 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
933 int i915_gem_attach_phys_object(struct drm_device *dev,
934 struct drm_gem_object *obj, int id);
935 void i915_gem_detach_phys_object(struct drm_device *dev,
936 struct drm_gem_object *obj);
937 void i915_gem_free_all_phys_object(struct drm_device *dev);
938 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
939 void i915_gem_object_put_pages(struct drm_gem_object *obj);
940 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
941 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
943 void i915_gem_shrinker_init(void);
944 void i915_gem_shrinker_exit(void);
946 /* i915_gem_tiling.c */
947 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
948 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
949 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
950 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
952 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
955 /* i915_gem_debug.c */
956 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
957 const char *where, uint32_t mark);
959 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
961 #define i915_verify_inactive(dev, file, line)
963 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
964 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
965 const char *where, uint32_t mark);
966 void i915_dump_lru(struct drm_device *dev, const char *where);
969 int i915_debugfs_init(struct drm_minor *minor);
970 void i915_debugfs_cleanup(struct drm_minor *minor);
973 extern int i915_save_state(struct drm_device *dev);
974 extern int i915_restore_state(struct drm_device *dev);
977 extern int i915_save_state(struct drm_device *dev);
978 extern int i915_restore_state(struct drm_device *dev);
981 /* i915_opregion.c */
982 extern int intel_opregion_init(struct drm_device *dev, int resume);
983 extern void intel_opregion_free(struct drm_device *dev, int suspend);
984 extern void opregion_asle_intr(struct drm_device *dev);
985 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
986 extern void opregion_enable_asle(struct drm_device *dev);
988 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
989 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
990 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
991 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
992 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
996 extern void intel_modeset_init(struct drm_device *dev);
997 extern void intel_modeset_cleanup(struct drm_device *dev);
998 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
999 extern void i8xx_disable_fbc(struct drm_device *dev);
1000 extern void g4x_disable_fbc(struct drm_device *dev);
1003 * Lock test for when it's just for synchronization of ring access.
1005 * In that case, we don't need to do it when GEM is initialized as nobody else
1006 * has access to the ring.
1008 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1009 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
1010 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1013 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1014 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1015 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1016 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1017 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1018 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1019 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1020 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1021 #define POSTING_READ(reg) (void)I915_READ(reg)
1023 #define I915_VERBOSE 0
1025 #define RING_LOCALS volatile unsigned int *ring_virt__;
1027 #define BEGIN_LP_RING(n) do { \
1028 int bytes__ = 4*(n); \
1029 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
1030 /* a wrap must occur between instructions so pad beforehand */ \
1031 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
1032 i915_wrap_ring(dev); \
1033 if (unlikely (dev_priv->ring.space < bytes__)) \
1034 i915_wait_ring(dev, bytes__, __func__); \
1035 ring_virt__ = (unsigned int *) \
1036 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
1037 dev_priv->ring.tail += bytes__; \
1038 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
1039 dev_priv->ring.space -= bytes__; \
1042 #define OUT_RING(n) do { \
1043 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
1044 *ring_virt__++ = (n); \
1047 #define ADVANCE_LP_RING() do { \
1049 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
1050 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1054 * Reads a dword out of the status page, which is written to from the command
1055 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1056 * MI_STORE_DATA_IMM.
1058 * The following dwords have a reserved meaning:
1059 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1060 * 0x04: ring 0 head pointer
1061 * 0x05: ring 1 head pointer (915-class)
1062 * 0x06: ring 2 head pointer (915-class)
1063 * 0x10-0x1b: Context status DWords (GM45)
1064 * 0x1f: Last written status offset. (GM45)
1066 * The area from dword 0x20 to 0x3ff is available for driver usage.
1068 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1069 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1070 #define I915_GEM_HWS_INDEX 0x20
1071 #define I915_BREADCRUMB_INDEX 0x21
1073 extern int i915_wrap_ring(struct drm_device * dev);
1074 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1076 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1078 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1079 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1080 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1081 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1082 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1083 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1084 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1085 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1086 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1087 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1088 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1089 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1090 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1091 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1092 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1093 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1094 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1095 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1096 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1097 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1098 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1099 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1100 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1102 #define IS_GEN3(dev) (IS_I915G(dev) || \
1108 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1109 (dev)->pci_device == 0x2982 || \
1110 (dev)->pci_device == 0x2992 || \
1111 (dev)->pci_device == 0x29A2 || \
1112 (dev)->pci_device == 0x2A02 || \
1113 (dev)->pci_device == 0x2A12 || \
1114 (dev)->pci_device == 0x2E02 || \
1115 (dev)->pci_device == 0x2E12 || \
1116 (dev)->pci_device == 0x2E22 || \
1117 (dev)->pci_device == 0x2E32 || \
1118 (dev)->pci_device == 0x2A42 || \
1119 (dev)->pci_device == 0x2E42)
1121 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1123 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1124 * rows, which changed the alignment requirements and fence programming.
1126 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1128 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1129 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1130 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1131 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1132 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1133 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
1134 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1135 /* dsparb controlled by hw only */
1136 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1138 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1139 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1140 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1141 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1143 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1145 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1147 #define PRIMARY_RINGBUFFER_SIZE (128*1024)