drivers/dma/mv_xor.c

   1 /*
   2  * offload engine driver for the Marvell XOR engine
   3  * Copyright (C) 2007, 2008, Marvell International Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/memory.h>
  27 #include <plat/mv_xor.h>
  28 #include "mv_xor.h"
  29
  30 static void mv_xor_issue_pending(struct dma_chan *chan);
  31
  32 #define to_mv_xor_chan(chan)            \
  33         container_of(chan, struct mv_xor_chan, common)
  34
  35 #define to_mv_xor_device(dev)           \
  36         container_of(dev, struct mv_xor_device, common)
  37
  38 #define to_mv_xor_slot(tx)              \
  39         container_of(tx, struct mv_xor_desc_slot, async_tx)
  40
  41 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
  42 {
  43         struct mv_xor_desc *hw_desc = desc->hw_desc;
  44
  45         hw_desc->status = (1 << 31);
  46         hw_desc->phy_next_desc = 0;
  47         hw_desc->desc_command = (1 << 31);
  48 }
  49
  50 static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc)
  51 {
  52         struct mv_xor_desc *hw_desc = desc->hw_desc;
  53         return hw_desc->phy_dest_addr;
  54 }
  55
  56 static u32 mv_desc_get_src_addr(struct mv_xor_desc_slot *desc,
  57                                 int src_idx)
  58 {
  59         struct mv_xor_desc *hw_desc = desc->hw_desc;
  60         return hw_desc->phy_src_addr[src_idx];
  61 }
  62
  63
  64 static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
  65                                    u32 byte_count)
  66 {
  67         struct mv_xor_desc *hw_desc = desc->hw_desc;
  68         hw_desc->byte_count = byte_count;
  69 }
  70
  71 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
  72                                   u32 next_desc_addr)
  73 {
  74         struct mv_xor_desc *hw_desc = desc->hw_desc;
  75         BUG_ON(hw_desc->phy_next_desc);
  76         hw_desc->phy_next_desc = next_desc_addr;
  77 }
  78
  79 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
  80 {
  81         struct mv_xor_desc *hw_desc = desc->hw_desc;
  82         hw_desc->phy_next_desc = 0;
  83 }
  84
  85 static void mv_desc_set_block_fill_val(struct mv_xor_desc_slot *desc, u32 val)
  86 {
  87         desc->value = val;
  88 }
  89
  90 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
  91                                   dma_addr_t addr)
  92 {
  93         struct mv_xor_desc *hw_desc = desc->hw_desc;
  94         hw_desc->phy_dest_addr = addr;
  95 }
  96
  97 static int mv_chan_memset_slot_count(size_t len)
  98 {
  99         return 1;
 100 }
 101
 102 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
 103
 104 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
 105                                  int index, dma_addr_t addr)
 106 {
 107         struct mv_xor_desc *hw_desc = desc->hw_desc;
 108         hw_desc->phy_src_addr[index] = addr;
 109         if (desc->type == DMA_XOR)
 110                 hw_desc->desc_command |= (1 << index);
 111 }
 112
 113 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
 114 {
 115         return __raw_readl(XOR_CURR_DESC(chan));
 116 }
 117
 118 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
 119                                         u32 next_desc_addr)
 120 {
 121         __raw_writel(next_desc_addr, XOR_NEXT_DESC(chan));
 122 }
 123
 124 static void mv_chan_set_dest_pointer(struct mv_xor_chan *chan, u32 desc_addr)
 125 {
 126         __raw_writel(desc_addr, XOR_DEST_POINTER(chan));
 127 }
 128
 129 static void mv_chan_set_block_size(struct mv_xor_chan *chan, u32 block_size)
 130 {
 131         __raw_writel(block_size, XOR_BLOCK_SIZE(chan));
 132 }
 133
 134 static void mv_chan_set_value(struct mv_xor_chan *chan, u32 value)
 135 {
 136         __raw_writel(value, XOR_INIT_VALUE_LOW(chan));
 137         __raw_writel(value, XOR_INIT_VALUE_HIGH(chan));
 138 }
 139
 140 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
 141 {
 142         u32 val = __raw_readl(XOR_INTR_MASK(chan));
 143         val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
 144         __raw_writel(val, XOR_INTR_MASK(chan));
 145 }
 146
 147 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
 148 {
 149         u32 intr_cause = __raw_readl(XOR_INTR_CAUSE(chan));
 150         intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
 151         return intr_cause;
 152 }
 153
 154 static int mv_is_err_intr(u32 intr_cause)
 155 {
 156         if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
 157                 return 1;
 158
 159         return 0;
 160 }
 161
 162 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
 163 {
 164         u32 val = (1 << (1 + (chan->idx * 16)));
 165         dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
 166         __raw_writel(val, XOR_INTR_CAUSE(chan));
 167 }
 168
 169 static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
 170 {
 171         u32 val = 0xFFFF0000 >> (chan->idx * 16);
 172         __raw_writel(val, XOR_INTR_CAUSE(chan));
 173 }
 174
 175 static int mv_can_chain(struct mv_xor_desc_slot *desc)
 176 {
 177         struct mv_xor_desc_slot *chain_old_tail = list_entry(
 178                 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
 179
 180         if (chain_old_tail->type != desc->type)
 181                 return 0;
 182         if (desc->type == DMA_MEMSET)
 183                 return 0;
 184
 185         return 1;
 186 }
 187
 188 static void mv_set_mode(struct mv_xor_chan *chan,
 189                                enum dma_transaction_type type)
 190 {
 191         u32 op_mode;
 192         u32 config = __raw_readl(XOR_CONFIG(chan));
 193
 194         switch (type) {
 195         case DMA_XOR:
 196                 op_mode = XOR_OPERATION_MODE_XOR;
 197                 break;
 198         case DMA_MEMCPY:
 199                 op_mode = XOR_OPERATION_MODE_MEMCPY;
 200                 break;
 201         case DMA_MEMSET:
 202                 op_mode = XOR_OPERATION_MODE_MEMSET;
 203                 break;
 204         default:
 205                 dev_printk(KERN_ERR, chan->device->common.dev,
 206                            "error: unsupported operation %d.\n",
 207                            type);
 208                 BUG();
 209                 return;
 210         }
 211
 212         config &= ~0x7;
 213         config |= op_mode;
 214         __raw_writel(config, XOR_CONFIG(chan));
 215         chan->current_type = type;
 216 }
 217
 218 static void mv_chan_activate(struct mv_xor_chan *chan)
 219 {
 220         u32 activation;
 221
 222         dev_dbg(chan->device->common.dev, " activate chan.\n");
 223         activation = __raw_readl(XOR_ACTIVATION(chan));
 224         activation |= 0x1;
 225         __raw_writel(activation, XOR_ACTIVATION(chan));
 226 }
 227
 228 static char mv_chan_is_busy(struct mv_xor_chan *chan)
 229 {
 230         u32 state = __raw_readl(XOR_ACTIVATION(chan));
 231
 232         state = (state >> 4) & 0x3;
 233
 234         return (state == 1) ? 1 : 0;
 235 }
 236
 237 static int mv_chan_xor_slot_count(size_t len, int src_cnt)
 238 {
 239         return 1;
 240 }
 241
 242 /**
 243  * mv_xor_free_slots - flags descriptor slots for reuse
 244  * @slot: Slot to free
 245  * Caller must hold &mv_chan->lock while calling this function
 246  */
 247 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
 248                               struct mv_xor_desc_slot *slot)
 249 {
 250         dev_dbg(mv_chan->device->common.dev, "%s %d slot %p\n",
 251                 __func__, __LINE__, slot);
 252
 253         slot->slots_per_op = 0;
 254
 255 }
 256
 257 /*
 258  * mv_xor_start_new_chain - program the engine to operate on new chain headed by
 259  * sw_desc
 260  * Caller must hold &mv_chan->lock while calling this function
 261  */
 262 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
 263                                    struct mv_xor_desc_slot *sw_desc)
 264 {
 265         dev_dbg(mv_chan->device->common.dev, "%s %d: sw_desc %p\n",
 266                 __func__, __LINE__, sw_desc);
 267         if (sw_desc->type != mv_chan->current_type)
 268                 mv_set_mode(mv_chan, sw_desc->type);
 269
 270         if (sw_desc->type == DMA_MEMSET) {
 271                 /* for memset requests we need to program the engine, no
 272                  * descriptors used.
 273                  */
 274                 struct mv_xor_desc *hw_desc = sw_desc->hw_desc;
 275                 mv_chan_set_dest_pointer(mv_chan, hw_desc->phy_dest_addr);
 276                 mv_chan_set_block_size(mv_chan, sw_desc->unmap_len);
 277                 mv_chan_set_value(mv_chan, sw_desc->value);
 278         } else {
 279                 /* set the hardware chain */
 280                 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
 281         }
 282         mv_chan->pending += sw_desc->slot_cnt;
 283         mv_xor_issue_pending(&mv_chan->common);
 284 }
 285
 286 static dma_cookie_t
 287 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
 288         struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
 289 {
 290         BUG_ON(desc->async_tx.cookie < 0);
 291
 292         if (desc->async_tx.cookie > 0) {
 293                 cookie = desc->async_tx.cookie;
 294
 295                 /* call the callback (must not sleep or submit new
 296                  * operations to this channel)
 297                  */
 298                 if (desc->async_tx.callback)
 299                         desc->async_tx.callback(
 300                                 desc->async_tx.callback_param);
 301
 302                 /* unmap dma addresses
 303                  * (unmap_single vs unmap_page?)
 304                  */
 305                 if (desc->group_head && desc->unmap_len) {
 306                         struct mv_xor_desc_slot *unmap = desc->group_head;
 307                         struct device *dev =
 308                                 &mv_chan->device->pdev->dev;
 309                         u32 len = unmap->unmap_len;
 310                         enum dma_ctrl_flags flags = desc->async_tx.flags;
 311                         u32 src_cnt;
 312                         dma_addr_t addr;
 313                         dma_addr_t dest;
 314
 315                         src_cnt = unmap->unmap_src_cnt;
 316                         dest = mv_desc_get_dest_addr(unmap);
 317                         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 318                                 enum dma_data_direction dir;
 319
 320                                 if (src_cnt > 1) /* is xor ? */
 321                                         dir = DMA_BIDIRECTIONAL;
 322                                 else
 323                                         dir = DMA_FROM_DEVICE;
 324                                 dma_unmap_page(dev, dest, len, dir);
 325                         }
 326
 327                         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 328                                 while (src_cnt--) {
 329                                         addr = mv_desc_get_src_addr(unmap,
 330                                                                     src_cnt);
 331                                         if (addr == dest)
 332                                                 continue;
 333                                         dma_unmap_page(dev, addr, len,
 334                                                        DMA_TO_DEVICE);
 335                                 }
 336                         }
 337                         desc->group_head = NULL;
 338                 }
 339         }
 340
 341         /* run dependent operations */
 342         dma_run_dependencies(&desc->async_tx);
 343
 344         return cookie;
 345 }
 346
 347 static int
 348 mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
 349 {
 350         struct mv_xor_desc_slot *iter, *_iter;
 351
 352         dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
 353         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 354                                  completed_node) {
 355
 356                 if (async_tx_test_ack(&iter->async_tx)) {
 357                         list_del(&iter->completed_node);
 358                         mv_xor_free_slots(mv_chan, iter);
 359                 }
 360         }
 361         return 0;
 362 }
 363
 364 static int
 365 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
 366         struct mv_xor_chan *mv_chan)
 367 {
 368         dev_dbg(mv_chan->device->common.dev, "%s %d: desc %p flags %d\n",
 369                 __func__, __LINE__, desc, desc->async_tx.flags);
 370         list_del(&desc->chain_node);
 371         /* the client is allowed to attach dependent operations
 372          * until 'ack' is set
 373          */
 374         if (!async_tx_test_ack(&desc->async_tx)) {
 375                 /* move this slot to the completed_slots */
 376                 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
 377                 return 0;
 378         }
 379
 380         mv_xor_free_slots(mv_chan, desc);
 381         return 0;
 382 }
 383
 384 static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 385 {
 386         struct mv_xor_desc_slot *iter, *_iter;
 387         dma_cookie_t cookie = 0;
 388         int busy = mv_chan_is_busy(mv_chan);
 389         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 390         int seen_current = 0;
 391
 392         dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
 393         dev_dbg(mv_chan->device->common.dev, "current_desc %x\n", current_desc);
 394         mv_xor_clean_completed_slots(mv_chan);
 395
 396         /* free completed slots from the chain starting with
 397          * the oldest descriptor
 398          */
 399
 400         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 401                                         chain_node) {
 402                 prefetch(_iter);
 403                 prefetch(&_iter->async_tx);
 404
 405                 /* do not advance past the current descriptor loaded into the
 406                  * hardware channel, subsequent descriptors are either in
 407                  * process or have not been submitted
 408                  */
 409                 if (seen_current)
 410                         break;
 411
 412                 /* stop the search if we reach the current descriptor and the
 413                  * channel is busy
 414                  */
 415                 if (iter->async_tx.phys == current_desc) {
 416                         seen_current = 1;
 417                         if (busy)
 418                                 break;
 419                 }
 420
 421                 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
 422
 423                 if (mv_xor_clean_slot(iter, mv_chan))
 424                         break;
 425         }
 426
 427         if ((busy == 0) && !list_empty(&mv_chan->chain)) {
 428                 struct mv_xor_desc_slot *chain_head;
 429                 chain_head = list_entry(mv_chan->chain.next,
 430                                         struct mv_xor_desc_slot,
 431                                         chain_node);
 432
 433                 mv_xor_start_new_chain(mv_chan, chain_head);
 434         }
 435
 436         if (cookie > 0)
 437                 mv_chan->completed_cookie = cookie;
 438 }
 439
 440 static void
 441 mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 442 {
 443         spin_lock_bh(&mv_chan->lock);
 444         __mv_xor_slot_cleanup(mv_chan);
 445         spin_unlock_bh(&mv_chan->lock);
 446 }
 447
 448 static void mv_xor_tasklet(unsigned long data)
 449 {
 450         struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
 451         __mv_xor_slot_cleanup(chan);
 452 }
 453
 454 static struct mv_xor_desc_slot *
 455 mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
 456                     int slots_per_op)
 457 {
 458         struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
 459         LIST_HEAD(chain);
 460         int slots_found, retry = 0;
 461
 462         /* start search from the last allocated descrtiptor
 463          * if a contiguous allocation can not be found start searching
 464          * from the beginning of the list
 465          */
 466 retry:
 467         slots_found = 0;
 468         if (retry == 0)
 469                 iter = mv_chan->last_used;
 470         else
 471                 iter = list_entry(&mv_chan->all_slots,
 472                         struct mv_xor_desc_slot,
 473                         slot_node);
 474
 475         list_for_each_entry_safe_continue(
 476                 iter, _iter, &mv_chan->all_slots, slot_node) {
 477                 prefetch(_iter);
 478                 prefetch(&_iter->async_tx);
 479                 if (iter->slots_per_op) {
 480                         /* give up after finding the first busy slot
 481                          * on the second pass through the list
 482                          */
 483                         if (retry)
 484                                 break;
 485
 486                         slots_found = 0;
 487                         continue;
 488                 }
 489
 490                 /* start the allocation if the slot is correctly aligned */
 491                 if (!slots_found++)
 492                         alloc_start = iter;
 493
 494                 if (slots_found == num_slots) {
 495                         struct mv_xor_desc_slot *alloc_tail = NULL;
 496                         struct mv_xor_desc_slot *last_used = NULL;
 497                         iter = alloc_start;
 498                         while (num_slots) {
 499                                 int i;
 500
 501                                 /* pre-ack all but the last descriptor */
 502                                 async_tx_ack(&iter->async_tx);
 503
 504                                 list_add_tail(&iter->chain_node, &chain);
 505                                 alloc_tail = iter;
 506                                 iter->async_tx.cookie = 0;
 507                                 iter->slot_cnt = num_slots;
 508                                 iter->xor_check_result = NULL;
 509                                 for (i = 0; i < slots_per_op; i++) {
 510                                         iter->slots_per_op = slots_per_op - i;
 511                                         last_used = iter;
 512                                         iter = list_entry(iter->slot_node.next,
 513                                                 struct mv_xor_desc_slot,
 514                                                 slot_node);
 515                                 }
 516                                 num_slots -= slots_per_op;
 517                         }
 518                         alloc_tail->group_head = alloc_start;
 519                         alloc_tail->async_tx.cookie = -EBUSY;
 520                         list_splice(&chain, &alloc_tail->tx_list);
 521                         mv_chan->last_used = last_used;
 522                         mv_desc_clear_next_desc(alloc_start);
 523                         mv_desc_clear_next_desc(alloc_tail);
 524                         return alloc_tail;
 525                 }
 526         }
 527         if (!retry++)
 528                 goto retry;
 529
 530         /* try to free some slots if the allocation fails */
 531         tasklet_schedule(&mv_chan->irq_tasklet);
 532
 533         return NULL;
 534 }
 535
 536 static dma_cookie_t
 537 mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
 538                       struct mv_xor_desc_slot *desc)
 539 {
 540         dma_cookie_t cookie = mv_chan->common.cookie;
 541
 542         if (++cookie < 0)
 543                 cookie = 1;
 544         mv_chan->common.cookie = desc->async_tx.cookie = cookie;
 545         return cookie;
 546 }
 547
 548 /************************ DMA engine API functions ****************************/
 549 static dma_cookie_t
 550 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 551 {
 552         struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
 553         struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
 554         struct mv_xor_desc_slot *grp_start, *old_chain_tail;
 555         dma_cookie_t cookie;
 556         int new_hw_chain = 1;
 557
 558         dev_dbg(mv_chan->device->common.dev,
 559                 "%s sw_desc %p: async_tx %p\n",
 560                 __func__, sw_desc, &sw_desc->async_tx);
 561
 562         grp_start = sw_desc->group_head;
 563
 564         spin_lock_bh(&mv_chan->lock);
 565         cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
 566
 567         if (list_empty(&mv_chan->chain))
 568                 list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
 569         else {
 570                 new_hw_chain = 0;
 571
 572                 old_chain_tail = list_entry(mv_chan->chain.prev,
 573                                             struct mv_xor_desc_slot,
 574                                             chain_node);
 575                 list_splice_init(&grp_start->tx_list,
 576                                  &old_chain_tail->chain_node);
 577
 578                 if (!mv_can_chain(grp_start))
 579                         goto submit_done;
 580
 581                 dev_dbg(mv_chan->device->common.dev, "Append to last desc %x\n",
 582                         old_chain_tail->async_tx.phys);
 583
 584                 /* fix up the hardware chain */
 585                 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
 586
 587                 /* if the channel is not busy */
 588                 if (!mv_chan_is_busy(mv_chan)) {
 589                         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 590                         /*
 591                          * and the curren desc is the end of the chain before
 592                          * the append, then we need to start the channel
 593                          */
 594                         if (current_desc == old_chain_tail->async_tx.phys)
 595                                 new_hw_chain = 1;
 596                 }
 597         }
 598
 599         if (new_hw_chain)
 600                 mv_xor_start_new_chain(mv_chan, grp_start);
 601
 602 submit_done:
 603         spin_unlock_bh(&mv_chan->lock);
 604
 605         return cookie;
 606 }
 607
 608 /* returns the number of allocated descriptors */
 609 static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
 610 {
 611         char *hw_desc;
 612         int idx;
 613         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 614         struct mv_xor_desc_slot *slot = NULL;
 615         struct mv_xor_platform_data *plat_data =
 616                 mv_chan->device->pdev->dev.platform_data;
 617         int num_descs_in_pool = plat_data->pool_size/MV_XOR_SLOT_SIZE;
 618
 619         /* Allocate descriptor slots */
 620         idx = mv_chan->slots_allocated;
 621         while (idx < num_descs_in_pool) {
 622                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 623                 if (!slot) {
 624                         printk(KERN_INFO "MV XOR Channel only initialized"
 625                                 " %d descriptor slots", idx);
 626                         break;
 627                 }
 628                 hw_desc = (char *) mv_chan->device->dma_desc_pool_virt;
 629                 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 630
 631                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
 632                 slot->async_tx.tx_submit = mv_xor_tx_submit;
 633                 INIT_LIST_HEAD(&slot->chain_node);
 634                 INIT_LIST_HEAD(&slot->slot_node);
 635                 INIT_LIST_HEAD(&slot->tx_list);
 636                 hw_desc = (char *) mv_chan->device->dma_desc_pool;
 637                 slot->async_tx.phys =
 638                         (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 639                 slot->idx = idx++;
 640
 641                 spin_lock_bh(&mv_chan->lock);
 642                 mv_chan->slots_allocated = idx;
 643                 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
 644                 spin_unlock_bh(&mv_chan->lock);
 645         }
 646
 647         if (mv_chan->slots_allocated && !mv_chan->last_used)
 648                 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
 649                                         struct mv_xor_desc_slot,
 650                                         slot_node);
 651
 652         dev_dbg(mv_chan->device->common.dev,
 653                 "allocated %d descriptor slots last_used: %p\n",
 654                 mv_chan->slots_allocated, mv_chan->last_used);
 655
 656         return mv_chan->slots_allocated ? : -ENOMEM;
 657 }
 658
 659 static struct dma_async_tx_descriptor *
 660 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 661                 size_t len, unsigned long flags)
 662 {
 663         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 664         struct mv_xor_desc_slot *sw_desc, *grp_start;
 665         int slot_cnt;
 666
 667         dev_dbg(mv_chan->device->common.dev,
 668                 "%s dest: %x src %x len: %u flags: %ld\n",
 669                 __func__, dest, src, len, flags);
 670         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 671                 return NULL;
 672
 673         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
 674
 675         spin_lock_bh(&mv_chan->lock);
 676         slot_cnt = mv_chan_memcpy_slot_count(len);
 677         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 678         if (sw_desc) {
 679                 sw_desc->type = DMA_MEMCPY;
 680                 sw_desc->async_tx.flags = flags;
 681                 grp_start = sw_desc->group_head;
 682                 mv_desc_init(grp_start, flags);
 683                 mv_desc_set_byte_count(grp_start, len);
 684                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 685                 mv_desc_set_src_addr(grp_start, 0, src);
 686                 sw_desc->unmap_src_cnt = 1;
 687                 sw_desc->unmap_len = len;
 688         }
 689         spin_unlock_bh(&mv_chan->lock);
 690
 691         dev_dbg(mv_chan->device->common.dev,
 692                 "%s sw_desc %p async_tx %p\n",
 693                 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : 0);
 694
 695         return sw_desc ? &sw_desc->async_tx : NULL;
 696 }
 697
 698 static struct dma_async_tx_descriptor *
 699 mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
 700                        size_t len, unsigned long flags)
 701 {
 702         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 703         struct mv_xor_desc_slot *sw_desc, *grp_start;
 704         int slot_cnt;
 705
 706         dev_dbg(mv_chan->device->common.dev,
 707                 "%s dest: %x len: %u flags: %ld\n",
 708                 __func__, dest, len, flags);
 709         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 710                 return NULL;
 711
 712         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
 713
 714         spin_lock_bh(&mv_chan->lock);
 715         slot_cnt = mv_chan_memset_slot_count(len);
 716         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 717         if (sw_desc) {
 718                 sw_desc->type = DMA_MEMSET;
 719                 sw_desc->async_tx.flags = flags;
 720                 grp_start = sw_desc->group_head;
 721                 mv_desc_init(grp_start, flags);
 722                 mv_desc_set_byte_count(grp_start, len);
 723                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 724                 mv_desc_set_block_fill_val(grp_start, value);
 725                 sw_desc->unmap_src_cnt = 1;
 726                 sw_desc->unmap_len = len;
 727         }
 728         spin_unlock_bh(&mv_chan->lock);
 729         dev_dbg(mv_chan->device->common.dev,
 730                 "%s sw_desc %p async_tx %p \n",
 731                 __func__, sw_desc, &sw_desc->async_tx);
 732         return sw_desc ? &sw_desc->async_tx : NULL;
 733 }
 734
 735 static struct dma_async_tx_descriptor *
 736 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 737                     unsigned int src_cnt, size_t len, unsigned long flags)
 738 {
 739         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 740         struct mv_xor_desc_slot *sw_desc, *grp_start;
 741         int slot_cnt;
 742
 743         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 744                 return NULL;
 745
 746         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
 747
 748         dev_dbg(mv_chan->device->common.dev,
 749                 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
 750                 __func__, src_cnt, len, dest, flags);
 751
 752         spin_lock_bh(&mv_chan->lock);
 753         slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
 754         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 755         if (sw_desc) {
 756                 sw_desc->type = DMA_XOR;
 757                 sw_desc->async_tx.flags = flags;
 758                 grp_start = sw_desc->group_head;
 759                 mv_desc_init(grp_start, flags);
 760                 /* the byte count field is the same as in memcpy desc*/
 761                 mv_desc_set_byte_count(grp_start, len);
 762                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 763                 sw_desc->unmap_src_cnt = src_cnt;
 764                 sw_desc->unmap_len = len;
 765                 while (src_cnt--)
 766                         mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
 767         }
 768         spin_unlock_bh(&mv_chan->lock);
 769         dev_dbg(mv_chan->device->common.dev,
 770                 "%s sw_desc %p async_tx %p \n",
 771                 __func__, sw_desc, &sw_desc->async_tx);
 772         return sw_desc ? &sw_desc->async_tx : NULL;
 773 }
 774
 775 static void mv_xor_free_chan_resources(struct dma_chan *chan)
 776 {
 777         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 778         struct mv_xor_desc_slot *iter, *_iter;
 779         int in_use_descs = 0;
 780
 781         mv_xor_slot_cleanup(mv_chan);
 782
 783         spin_lock_bh(&mv_chan->lock);
 784         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 785                                         chain_node) {
 786                 in_use_descs++;
 787                 list_del(&iter->chain_node);
 788         }
 789         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 790                                  completed_node) {
 791                 in_use_descs++;
 792                 list_del(&iter->completed_node);
 793         }
 794         list_for_each_entry_safe_reverse(
 795                 iter, _iter, &mv_chan->all_slots, slot_node) {
 796                 list_del(&iter->slot_node);
 797                 kfree(iter);
 798                 mv_chan->slots_allocated--;
 799         }
 800         mv_chan->last_used = NULL;
 801
 802         dev_dbg(mv_chan->device->common.dev, "%s slots_allocated %d\n",
 803                 __func__, mv_chan->slots_allocated);
 804         spin_unlock_bh(&mv_chan->lock);
 805
 806         if (in_use_descs)
 807                 dev_err(mv_chan->device->common.dev,
 808                         "freeing %d in use descriptors!\n", in_use_descs);
 809 }
 810
 811 /**
 812  * mv_xor_status - poll the status of an XOR transaction
 813  * @chan: XOR channel handle
 814  * @cookie: XOR transaction identifier
 815  * @txstate: XOR transactions state holder (or NULL)
 816  */
 817 static enum dma_status mv_xor_status(struct dma_chan *chan,
 818                                           dma_cookie_t cookie,
 819                                           struct dma_tx_state *txstate)
 820 {
 821         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 822         dma_cookie_t last_used;
 823         dma_cookie_t last_complete;
 824         enum dma_status ret;
 825
 826         last_used = chan->cookie;
 827         last_complete = mv_chan->completed_cookie;
 828         mv_chan->is_complete_cookie = cookie;
 829         if (txstate) {
 830                 txstate->last = last_complete;
 831                 txstate->used = last_used;
 832                 txstate->residue = 0;
 833         }
 834
 835         ret = dma_async_is_complete(cookie, last_complete, last_used);
 836         if (ret == DMA_SUCCESS) {
 837                 mv_xor_clean_completed_slots(mv_chan);
 838                 return ret;
 839         }
 840         mv_xor_slot_cleanup(mv_chan);
 841
 842         last_used = chan->cookie;
 843         last_complete = mv_chan->completed_cookie;
 844
 845         if (txstate) {
 846                 txstate->last = last_complete;
 847                 txstate->used = last_used;
 848                 txstate->residue = 0;
 849         }
 850
 851         return dma_async_is_complete(cookie, last_complete, last_used);
 852 }
 853
 854 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
 855 {
 856         u32 val;
 857
 858         val = __raw_readl(XOR_CONFIG(chan));
 859         dev_printk(KERN_ERR, chan->device->common.dev,
 860                    "config       0x%08x.\n", val);
 861
 862         val = __raw_readl(XOR_ACTIVATION(chan));
 863         dev_printk(KERN_ERR, chan->device->common.dev,
 864                    "activation   0x%08x.\n", val);
 865
 866         val = __raw_readl(XOR_INTR_CAUSE(chan));
 867         dev_printk(KERN_ERR, chan->device->common.dev,
 868                    "intr cause   0x%08x.\n", val);
 869
 870         val = __raw_readl(XOR_INTR_MASK(chan));
 871         dev_printk(KERN_ERR, chan->device->common.dev,
 872                    "intr mask    0x%08x.\n", val);
 873
 874         val = __raw_readl(XOR_ERROR_CAUSE(chan));
 875         dev_printk(KERN_ERR, chan->device->common.dev,
 876                    "error cause  0x%08x.\n", val);
 877
 878         val = __raw_readl(XOR_ERROR_ADDR(chan));
 879         dev_printk(KERN_ERR, chan->device->common.dev,
 880                    "error addr   0x%08x.\n", val);
 881 }
 882
 883 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
 884                                          u32 intr_cause)
 885 {
 886         if (intr_cause & (1 << 4)) {
 887              dev_dbg(chan->device->common.dev,
 888                      "ignore this error\n");
 889              return;
 890         }
 891
 892         dev_printk(KERN_ERR, chan->device->common.dev,
 893                    "error on chan %d. intr cause 0x%08x.\n",
 894                    chan->idx, intr_cause);
 895
 896         mv_dump_xor_regs(chan);
 897         BUG();
 898 }
 899
 900 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
 901 {
 902         struct mv_xor_chan *chan = data;
 903         u32 intr_cause = mv_chan_get_intr_cause(chan);
 904
 905         dev_dbg(chan->device->common.dev, "intr cause %x\n", intr_cause);
 906
 907         if (mv_is_err_intr(intr_cause))
 908                 mv_xor_err_interrupt_handler(chan, intr_cause);
 909
 910         tasklet_schedule(&chan->irq_tasklet);
 911
 912         mv_xor_device_clear_eoc_cause(chan);
 913
 914         return IRQ_HANDLED;
 915 }
 916
 917 static void mv_xor_issue_pending(struct dma_chan *chan)
 918 {
 919         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 920
 921         if (mv_chan->pending >= MV_XOR_THRESHOLD) {
 922                 mv_chan->pending = 0;
 923                 mv_chan_activate(mv_chan);
 924         }
 925 }
 926
 927 /*
 928  * Perform a transaction to verify the HW works.
 929  */
 930 #define MV_XOR_TEST_SIZE 2000
 931
 932 static int __devinit mv_xor_memcpy_self_test(struct mv_xor_device *device)
 933 {
 934         int i;
 935         void *src, *dest;
 936         dma_addr_t src_dma, dest_dma;
 937         struct dma_chan *dma_chan;
 938         dma_cookie_t cookie;
 939         struct dma_async_tx_descriptor *tx;
 940         int err = 0;
 941         struct mv_xor_chan *mv_chan;
 942
 943         src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
 944         if (!src)
 945                 return -ENOMEM;
 946
 947         dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
 948         if (!dest) {
 949                 kfree(src);
 950                 return -ENOMEM;
 951         }
 952
 953         /* Fill in src buffer */
 954         for (i = 0; i < MV_XOR_TEST_SIZE; i++)
 955                 ((u8 *) src)[i] = (u8)i;
 956
 957         /* Start copy, using first DMA channel */
 958         dma_chan = container_of(device->common.channels.next,
 959                                 struct dma_chan,
 960                                 device_node);
 961         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
 962                 err = -ENODEV;
 963                 goto out;
 964         }
 965
 966         dest_dma = dma_map_single(dma_chan->device->dev, dest,
 967                                   MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
 968
 969         src_dma = dma_map_single(dma_chan->device->dev, src,
 970                                  MV_XOR_TEST_SIZE, DMA_TO_DEVICE);
 971
 972         tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
 973                                     MV_XOR_TEST_SIZE, 0);
 974         cookie = mv_xor_tx_submit(tx);
 975         mv_xor_issue_pending(dma_chan);
 976         async_tx_ack(tx);
 977         msleep(1);
 978
 979         if (mv_xor_status(dma_chan, cookie, NULL) !=
 980             DMA_SUCCESS) {
 981                 dev_printk(KERN_ERR, dma_chan->device->dev,
 982                            "Self-test copy timed out, disabling\n");
 983                 err = -ENODEV;
 984                 goto free_resources;
 985         }
 986
 987         mv_chan = to_mv_xor_chan(dma_chan);
 988         dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
 989                                 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
 990         if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
 991                 dev_printk(KERN_ERR, dma_chan->device->dev,
 992                            "Self-test copy failed compare, disabling\n");
 993                 err = -ENODEV;
 994                 goto free_resources;
 995         }
 996
 997 free_resources:
 998         mv_xor_free_chan_resources(dma_chan);
 999 out:
1000         kfree(src);
1001         kfree(dest);
1002         return err;
1003 }
1004
1005 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
1006 static int __devinit
1007 mv_xor_xor_self_test(struct mv_xor_device *device)
1008 {
1009         int i, src_idx;
1010         struct page *dest;
1011         struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
1012         dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
1013         dma_addr_t dest_dma;
1014         struct dma_async_tx_descriptor *tx;
1015         struct dma_chan *dma_chan;
1016         dma_cookie_t cookie;
1017         u8 cmp_byte = 0;
1018         u32 cmp_word;
1019         int err = 0;
1020         struct mv_xor_chan *mv_chan;
1021
1022         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1023                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1024                 if (!xor_srcs[src_idx]) {
1025                         while (src_idx--)
1026                                 __free_page(xor_srcs[src_idx]);
1027                         return -ENOMEM;
1028                 }
1029         }
1030
1031         dest = alloc_page(GFP_KERNEL);
1032         if (!dest) {
1033                 while (src_idx--)
1034                         __free_page(xor_srcs[src_idx]);
1035                 return -ENOMEM;
1036         }
1037
1038         /* Fill in src buffers */
1039         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1040                 u8 *ptr = page_address(xor_srcs[src_idx]);
1041                 for (i = 0; i < PAGE_SIZE; i++)
1042                         ptr[i] = (1 << src_idx);
1043         }
1044
1045         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++)
1046                 cmp_byte ^= (u8) (1 << src_idx);
1047
1048         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1049                 (cmp_byte << 8) | cmp_byte;
1050
1051         memset(page_address(dest), 0, PAGE_SIZE);
1052
1053         dma_chan = container_of(device->common.channels.next,
1054                                 struct dma_chan,
1055                                 device_node);
1056         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
1057                 err = -ENODEV;
1058                 goto out;
1059         }
1060
1061         /* test xor */
1062         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
1063                                 DMA_FROM_DEVICE);
1064
1065         for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++)
1066                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1067                                            0, PAGE_SIZE, DMA_TO_DEVICE);
1068
1069         tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1070                                  MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0);
1071
1072         cookie = mv_xor_tx_submit(tx);
1073         mv_xor_issue_pending(dma_chan);
1074         async_tx_ack(tx);
1075         msleep(8);
1076
1077         if (mv_xor_status(dma_chan, cookie, NULL) !=
1078             DMA_SUCCESS) {
1079                 dev_printk(KERN_ERR, dma_chan->device->dev,
1080                            "Self-test xor timed out, disabling\n");
1081                 err = -ENODEV;
1082                 goto free_resources;
1083         }
1084
1085         mv_chan = to_mv_xor_chan(dma_chan);
1086         dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
1087                                 PAGE_SIZE, DMA_FROM_DEVICE);
1088         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1089                 u32 *ptr = page_address(dest);
1090                 if (ptr[i] != cmp_word) {
1091                         dev_printk(KERN_ERR, dma_chan->device->dev,
1092                                    "Self-test xor failed compare, disabling."
1093                                    " index %d, data %x, expected %x\n", i,
1094                                    ptr[i], cmp_word);
1095                         err = -ENODEV;
1096                         goto free_resources;
1097                 }
1098         }
1099
1100 free_resources:
1101         mv_xor_free_chan_resources(dma_chan);
1102 out:
1103         src_idx = MV_XOR_NUM_SRC_TEST;
1104         while (src_idx--)
1105                 __free_page(xor_srcs[src_idx]);
1106         __free_page(dest);
1107         return err;
1108 }
1109
1110 static int __devexit mv_xor_remove(struct platform_device *dev)
1111 {
1112         struct mv_xor_device *device = platform_get_drvdata(dev);
1113         struct dma_chan *chan, *_chan;
1114         struct mv_xor_chan *mv_chan;
1115         struct mv_xor_platform_data *plat_data = dev->dev.platform_data;
1116
1117         dma_async_device_unregister(&device->common);
1118
1119         dma_free_coherent(&dev->dev, plat_data->pool_size,
1120                         device->dma_desc_pool_virt, device->dma_desc_pool);
1121
1122         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1123                                 device_node) {
1124                 mv_chan = to_mv_xor_chan(chan);
1125                 list_del(&chan->device_node);
1126         }
1127
1128         return 0;
1129 }
1130
1131 static int __devinit mv_xor_probe(struct platform_device *pdev)
1132 {
1133         int ret = 0;
1134         int irq;
1135         struct mv_xor_device *adev;
1136         struct mv_xor_chan *mv_chan;
1137         struct dma_device *dma_dev;
1138         struct mv_xor_platform_data *plat_data = pdev->dev.platform_data;
1139
1140
1141         adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
1142         if (!adev)
1143                 return -ENOMEM;
1144
1145         dma_dev = &adev->common;
1146
1147         /* allocate coherent memory for hardware descriptors
1148          * note: writecombine gives slightly better performance, but
1149          * requires that we explicitly flush the writes
1150          */
1151         adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1152                                                           plat_data->pool_size,
1153                                                           &adev->dma_desc_pool,
1154                                                           GFP_KERNEL);
1155         if (!adev->dma_desc_pool_virt)
1156                 return -ENOMEM;
1157
1158         adev->id = plat_data->hw_id;
1159
1160         /* discover transaction capabilites from the platform data */
1161         dma_dev->cap_mask = plat_data->cap_mask;
1162         adev->pdev = pdev;
1163         platform_set_drvdata(pdev, adev);
1164
1165         adev->shared = platform_get_drvdata(plat_data->shared);
1166
1167         INIT_LIST_HEAD(&dma_dev->channels);
1168
1169         /* set base routines */
1170         dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1171         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1172         dma_dev->device_tx_status = mv_xor_status;
1173         dma_dev->device_issue_pending = mv_xor_issue_pending;
1174         dma_dev->dev = &pdev->dev;
1175
1176         /* set prep routines based on capability */
1177         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1178                 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1179         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1180                 dma_dev->device_prep_dma_memset = mv_xor_prep_dma_memset;
1181         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1182                 dma_dev->max_xor = 8;
1183                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1184         }
1185
1186         mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1187         if (!mv_chan) {
1188                 ret = -ENOMEM;
1189                 goto err_free_dma;
1190         }
1191         mv_chan->device = adev;
1192         mv_chan->idx = plat_data->hw_id;
1193         mv_chan->mmr_base = adev->shared->xor_base;
1194
1195         if (!mv_chan->mmr_base) {
1196                 ret = -ENOMEM;
1197                 goto err_free_dma;
1198         }
1199         tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1200                      mv_chan);
1201
1202         /* clear errors before enabling interrupts */
1203         mv_xor_device_clear_err_status(mv_chan);
1204
1205         irq = platform_get_irq(pdev, 0);
1206         if (irq < 0) {
1207                 ret = irq;
1208                 goto err_free_dma;
1209         }
1210         ret = devm_request_irq(&pdev->dev, irq,
1211                                mv_xor_interrupt_handler,
1212                                0, dev_name(&pdev->dev), mv_chan);
1213         if (ret)
1214                 goto err_free_dma;
1215
1216         mv_chan_unmask_interrupts(mv_chan);
1217
1218         mv_set_mode(mv_chan, DMA_MEMCPY);
1219
1220         spin_lock_init(&mv_chan->lock);
1221         INIT_LIST_HEAD(&mv_chan->chain);
1222         INIT_LIST_HEAD(&mv_chan->completed_slots);
1223         INIT_LIST_HEAD(&mv_chan->all_slots);
1224         mv_chan->common.device = dma_dev;
1225
1226         list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
1227
1228         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1229                 ret = mv_xor_memcpy_self_test(adev);
1230                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1231                 if (ret)
1232                         goto err_free_dma;
1233         }
1234
1235         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1236                 ret = mv_xor_xor_self_test(adev);
1237                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1238                 if (ret)
1239                         goto err_free_dma;
1240         }
1241
1242         dev_printk(KERN_INFO, &pdev->dev, "Marvell XOR: "
1243           "( %s%s%s%s)\n",
1244           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1245           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1246           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1247           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1248
1249         dma_async_device_register(dma_dev);
1250         goto out;
1251
1252  err_free_dma:
1253         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1254                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1255  out:
1256         return ret;
1257 }
1258
1259 static void
1260 mv_xor_conf_mbus_windows(struct mv_xor_shared_private *msp,
1261                          struct mbus_dram_target_info *dram)
1262 {
1263         void __iomem *base = msp->xor_base;
1264         u32 win_enable = 0;
1265         int i;
1266
1267         for (i = 0; i < 8; i++) {
1268                 writel(0, base + WINDOW_BASE(i));
1269                 writel(0, base + WINDOW_SIZE(i));
1270                 if (i < 4)
1271                         writel(0, base + WINDOW_REMAP_HIGH(i));
1272         }
1273
1274         for (i = 0; i < dram->num_cs; i++) {
1275                 struct mbus_dram_window *cs = dram->cs + i;
1276
1277                 writel((cs->base & 0xffff0000) |
1278                        (cs->mbus_attr << 8) |
1279                        dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1280                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1281
1282                 win_enable |= (1 << i);
1283                 win_enable |= 3 << (16 + (2 * i));
1284         }
1285
1286         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1287         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1288 }
1289
1290 static struct platform_driver mv_xor_driver = {
1291         .probe          = mv_xor_probe,
1292         .remove         = __devexit_p(mv_xor_remove),
1293         .driver         = {
1294                 .owner  = THIS_MODULE,
1295                 .name   = MV_XOR_NAME,
1296         },
1297 };
1298
1299 static int mv_xor_shared_probe(struct platform_device *pdev)
1300 {
1301         struct mv_xor_platform_shared_data *msd = pdev->dev.platform_data;
1302         struct mv_xor_shared_private *msp;
1303         struct resource *res;
1304
1305         dev_printk(KERN_NOTICE, &pdev->dev, "Marvell shared XOR driver\n");
1306
1307         msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
1308         if (!msp)
1309                 return -ENOMEM;
1310
1311         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1312         if (!res)
1313                 return -ENODEV;
1314
1315         msp->xor_base = devm_ioremap(&pdev->dev, res->start,
1316                                      res->end - res->start + 1);
1317         if (!msp->xor_base)
1318                 return -EBUSY;
1319
1320         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1321         if (!res)
1322                 return -ENODEV;
1323
1324         msp->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1325                                           res->end - res->start + 1);
1326         if (!msp->xor_high_base)
1327                 return -EBUSY;
1328
1329         platform_set_drvdata(pdev, msp);
1330
1331         /*
1332          * (Re-)program MBUS remapping windows if we are asked to.
1333          */
1334         if (msd != NULL && msd->dram != NULL)
1335                 mv_xor_conf_mbus_windows(msp, msd->dram);
1336
1337         return 0;
1338 }
1339
1340 static int mv_xor_shared_remove(struct platform_device *pdev)
1341 {
1342         return 0;
1343 }
1344
1345 static struct platform_driver mv_xor_shared_driver = {
1346         .probe          = mv_xor_shared_probe,
1347         .remove         = mv_xor_shared_remove,
1348         .driver         = {
1349                 .owner  = THIS_MODULE,
1350                 .name   = MV_XOR_SHARED_NAME,
1351         },
1352 };
1353
1354
1355 static int __init mv_xor_init(void)
1356 {
1357         int rc;
1358
1359         rc = platform_driver_register(&mv_xor_shared_driver);
1360         if (!rc) {
1361                 rc = platform_driver_register(&mv_xor_driver);
1362                 if (rc)
1363                         platform_driver_unregister(&mv_xor_shared_driver);
1364         }
1365         return rc;
1366 }
1367 module_init(mv_xor_init);
1368
1369 /* it's currently unsafe to unload this module */
1370 #if 0
1371 static void __exit mv_xor_exit(void)
1372 {
1373         platform_driver_unregister(&mv_xor_driver);
1374         platform_driver_unregister(&mv_xor_shared_driver);
1375         return;
1376 }
1377
1378 module_exit(mv_xor_exit);
1379 #endif
1380
1381 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1382 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1383 MODULE_LICENSE("GPL");