drivers/dma/coh901318.c

   1 /*
   2  * driver/dma/coh901318.c
   3  *
   4  * Copyright (C) 2007-2009 ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  * DMA driver for COH 901 318
   7  * Author: Per Friden <per.friden@stericsson.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h> /* printk() */
  13 #include <linux/fs.h> /* everything... */
  14 #include <linux/slab.h> /* kmalloc() */
  15 #include <linux/dmaengine.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/device.h>
  18 #include <linux/irqreturn.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/debugfs.h>
  23 #include <mach/coh901318.h>
  24
  25 #include "coh901318_lli.h"
  26
  27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
  28
  29 #ifdef VERBOSE_DEBUG
  30 #define COH_DBG(x) ({ if (1) x; 0; })
  31 #else
  32 #define COH_DBG(x) ({ if (0) x; 0; })
  33 #endif
  34
  35 struct coh901318_desc {
  36         struct dma_async_tx_descriptor desc;
  37         struct list_head node;
  38         struct scatterlist *sg;
  39         unsigned int sg_len;
  40         struct coh901318_lli *lli;
  41         enum dma_data_direction dir;
  42         unsigned long flags;
  43 };
  44
  45 struct coh901318_base {
  46         struct device *dev;
  47         void __iomem *virtbase;
  48         struct coh901318_pool pool;
  49         struct powersave pm;
  50         struct dma_device dma_slave;
  51         struct dma_device dma_memcpy;
  52         struct coh901318_chan *chans;
  53         struct coh901318_platform *platform;
  54 };
  55
  56 struct coh901318_chan {
  57         spinlock_t lock;
  58         int allocated;
  59         int completed;
  60         int id;
  61         int stopped;
  62
  63         struct work_struct free_work;
  64         struct dma_chan chan;
  65
  66         struct tasklet_struct tasklet;
  67
  68         struct list_head active;
  69         struct list_head queue;
  70         struct list_head free;
  71
  72         unsigned long nbr_active_done;
  73         unsigned long busy;
  74
  75         struct coh901318_base *base;
  76 };
  77
  78 static void coh901318_list_print(struct coh901318_chan *cohc,
  79                                  struct coh901318_lli *lli)
  80 {
  81         struct coh901318_lli *l = lli;
  82         int i = 0;
  83
  84         while (l) {
  85                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
  86                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
  87                          i, l, l->control, l->src_addr, l->dst_addr,
  88                          l->link_addr, l->virt_link_addr);
  89                 i++;
  90                 l = l->virt_link_addr;
  91         }
  92 }
  93
  94 #ifdef CONFIG_DEBUG_FS
  95
  96 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
  97
  98 static struct coh901318_base *debugfs_dma_base;
  99 static struct dentry *dma_dentry;
 100
 101 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
 102 {
 103
 104         file->private_data = inode->i_private;
 105         return 0;
 106 }
 107
 108 static int coh901318_debugfs_read(struct file *file, char __user *buf,
 109                                   size_t count, loff_t *f_pos)
 110 {
 111         u64 started_channels = debugfs_dma_base->pm.started_channels;
 112         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
 113         int i;
 114         int ret = 0;
 115         char *dev_buf;
 116         char *tmp;
 117         int dev_size;
 118
 119         dev_buf = kmalloc(4*1024, GFP_KERNEL);
 120         if (dev_buf == NULL)
 121                 goto err_kmalloc;
 122         tmp = dev_buf;
 123
 124         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
 125
 126         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
 127                 if (started_channels & (1 << i))
 128                         tmp += sprintf(tmp, "channel %d\n", i);
 129
 130         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
 131         dev_size = tmp  - dev_buf;
 132
 133         /* No more to read if offset != 0 */
 134         if (*f_pos > dev_size)
 135                 goto out;
 136
 137         if (count > dev_size - *f_pos)
 138                 count = dev_size - *f_pos;
 139
 140         if (copy_to_user(buf, dev_buf + *f_pos, count))
 141                 ret = -EINVAL;
 142         ret = count;
 143         *f_pos += count;
 144
 145  out:
 146         kfree(dev_buf);
 147         return ret;
 148
 149  err_kmalloc:
 150         return 0;
 151 }
 152
 153 static const struct file_operations coh901318_debugfs_status_operations = {
 154         .owner          = THIS_MODULE,
 155         .open           = coh901318_debugfs_open,
 156         .read           = coh901318_debugfs_read,
 157 };
 158
 159
 160 static int __init init_coh901318_debugfs(void)
 161 {
 162
 163         dma_dentry = debugfs_create_dir("dma", NULL);
 164
 165         (void) debugfs_create_file("status",
 166                                    S_IFREG | S_IRUGO,
 167                                    dma_dentry, NULL,
 168                                    &coh901318_debugfs_status_operations);
 169         return 0;
 170 }
 171
 172 static void __exit exit_coh901318_debugfs(void)
 173 {
 174         debugfs_remove_recursive(dma_dentry);
 175 }
 176
 177 module_init(init_coh901318_debugfs);
 178 module_exit(exit_coh901318_debugfs);
 179 #else
 180
 181 #define COH901318_DEBUGFS_ASSIGN(x, y)
 182
 183 #endif /* CONFIG_DEBUG_FS */
 184
 185 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
 186 {
 187         return container_of(chan, struct coh901318_chan, chan);
 188 }
 189
 190 static inline dma_addr_t
 191 cohc_dev_addr(struct coh901318_chan *cohc)
 192 {
 193         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
 194 }
 195
 196 static inline const struct coh901318_params *
 197 cohc_chan_param(struct coh901318_chan *cohc)
 198 {
 199         return &cohc->base->platform->chan_conf[cohc->id].param;
 200 }
 201
 202 static inline const struct coh_dma_channel *
 203 cohc_chan_conf(struct coh901318_chan *cohc)
 204 {
 205         return &cohc->base->platform->chan_conf[cohc->id];
 206 }
 207
 208 static void enable_powersave(struct coh901318_chan *cohc)
 209 {
 210         unsigned long flags;
 211         struct powersave *pm = &cohc->base->pm;
 212
 213         spin_lock_irqsave(&pm->lock, flags);
 214
 215         pm->started_channels &= ~(1ULL << cohc->id);
 216
 217         if (!pm->started_channels) {
 218                 /* DMA no longer intends to access memory */
 219                 cohc->base->platform->access_memory_state(cohc->base->dev,
 220                                                           false);
 221         }
 222
 223         spin_unlock_irqrestore(&pm->lock, flags);
 224 }
 225 static void disable_powersave(struct coh901318_chan *cohc)
 226 {
 227         unsigned long flags;
 228         struct powersave *pm = &cohc->base->pm;
 229
 230         spin_lock_irqsave(&pm->lock, flags);
 231
 232         if (!pm->started_channels) {
 233                 /* DMA intends to access memory */
 234                 cohc->base->platform->access_memory_state(cohc->base->dev,
 235                                                           true);
 236         }
 237
 238         pm->started_channels |= (1ULL << cohc->id);
 239
 240         spin_unlock_irqrestore(&pm->lock, flags);
 241 }
 242
 243 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
 244 {
 245         int channel = cohc->id;
 246         void __iomem *virtbase = cohc->base->virtbase;
 247
 248         writel(control,
 249                virtbase + COH901318_CX_CTRL +
 250                COH901318_CX_CTRL_SPACING * channel);
 251         return 0;
 252 }
 253
 254 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
 255 {
 256         int channel = cohc->id;
 257         void __iomem *virtbase = cohc->base->virtbase;
 258
 259         writel(conf,
 260                virtbase + COH901318_CX_CFG +
 261                COH901318_CX_CFG_SPACING*channel);
 262         return 0;
 263 }
 264
 265
 266 static int coh901318_start(struct coh901318_chan *cohc)
 267 {
 268         u32 val;
 269         int channel = cohc->id;
 270         void __iomem *virtbase = cohc->base->virtbase;
 271
 272         disable_powersave(cohc);
 273
 274         val = readl(virtbase + COH901318_CX_CFG +
 275                     COH901318_CX_CFG_SPACING * channel);
 276
 277         /* Enable channel */
 278         val |= COH901318_CX_CFG_CH_ENABLE;
 279         writel(val, virtbase + COH901318_CX_CFG +
 280                COH901318_CX_CFG_SPACING * channel);
 281
 282         return 0;
 283 }
 284
 285 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 286                                       struct coh901318_lli *lli)
 287 {
 288         int channel = cohc->id;
 289         void __iomem *virtbase = cohc->base->virtbase;
 290
 291         BUG_ON(readl(virtbase + COH901318_CX_STAT +
 292                      COH901318_CX_STAT_SPACING*channel) &
 293                COH901318_CX_STAT_ACTIVE);
 294
 295         writel(lli->src_addr,
 296                virtbase + COH901318_CX_SRC_ADDR +
 297                COH901318_CX_SRC_ADDR_SPACING * channel);
 298
 299         writel(lli->dst_addr, virtbase +
 300                COH901318_CX_DST_ADDR +
 301                COH901318_CX_DST_ADDR_SPACING * channel);
 302
 303         writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
 304                COH901318_CX_LNK_ADDR_SPACING * channel);
 305
 306         writel(lli->control, virtbase + COH901318_CX_CTRL +
 307                COH901318_CX_CTRL_SPACING * channel);
 308
 309         return 0;
 310 }
 311 static dma_cookie_t
 312 coh901318_assign_cookie(struct coh901318_chan *cohc,
 313                         struct coh901318_desc *cohd)
 314 {
 315         dma_cookie_t cookie = cohc->chan.cookie;
 316
 317         if (++cookie < 0)
 318                 cookie = 1;
 319
 320         cohc->chan.cookie = cookie;
 321         cohd->desc.cookie = cookie;
 322
 323         return cookie;
 324 }
 325
 326 static struct coh901318_desc *
 327 coh901318_desc_get(struct coh901318_chan *cohc)
 328 {
 329         struct coh901318_desc *desc;
 330
 331         if (list_empty(&cohc->free)) {
 332                 /* alloc new desc because we're out of used ones
 333                  * TODO: alloc a pile of descs instead of just one,
 334                  * avoid many small allocations.
 335                  */
 336                 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
 337                 if (desc == NULL)
 338                         goto out;
 339                 INIT_LIST_HEAD(&desc->node);
 340                 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
 341         } else {
 342                 /* Reuse an old desc. */
 343                 desc = list_first_entry(&cohc->free,
 344                                         struct coh901318_desc,
 345                                         node);
 346                 list_del(&desc->node);
 347                 /* Initialize it a bit so it's not insane */
 348                 desc->sg = NULL;
 349                 desc->sg_len = 0;
 350                 desc->desc.callback = NULL;
 351                 desc->desc.callback_param = NULL;
 352         }
 353
 354  out:
 355         return desc;
 356 }
 357
 358 static void
 359 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
 360 {
 361         list_add_tail(&cohd->node, &cohc->free);
 362 }
 363
 364 /* call with irq lock held */
 365 static void
 366 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 367 {
 368         list_add_tail(&desc->node, &cohc->active);
 369 }
 370
 371 static struct coh901318_desc *
 372 coh901318_first_active_get(struct coh901318_chan *cohc)
 373 {
 374         struct coh901318_desc *d;
 375
 376         if (list_empty(&cohc->active))
 377                 return NULL;
 378
 379         d = list_first_entry(&cohc->active,
 380                              struct coh901318_desc,
 381                              node);
 382         return d;
 383 }
 384
 385 static void
 386 coh901318_desc_remove(struct coh901318_desc *cohd)
 387 {
 388         list_del(&cohd->node);
 389 }
 390
 391 static void
 392 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 393 {
 394         list_add_tail(&desc->node, &cohc->queue);
 395 }
 396
 397 static struct coh901318_desc *
 398 coh901318_first_queued(struct coh901318_chan *cohc)
 399 {
 400         struct coh901318_desc *d;
 401
 402         if (list_empty(&cohc->queue))
 403                 return NULL;
 404
 405         d = list_first_entry(&cohc->queue,
 406                              struct coh901318_desc,
 407                              node);
 408         return d;
 409 }
 410
 411 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
 412 {
 413         struct coh901318_lli *lli = in_lli;
 414         u32 bytes = 0;
 415
 416         while (lli) {
 417                 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
 418                 lli = lli->virt_link_addr;
 419         }
 420         return bytes;
 421 }
 422
 423 /*
 424  * Get the number of bytes left to transfer on this channel,
 425  * it is unwise to call this before stopping the channel for
 426  * absolute measures, but for a rough guess you can still call
 427  * it.
 428  */
 429 u32 coh901318_get_bytes_left(struct dma_chan *chan)
 430 {
 431         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 432         struct coh901318_desc *cohd;
 433         struct list_head *pos;
 434         unsigned long flags;
 435         u32 left = 0;
 436         int i = 0;
 437
 438         spin_lock_irqsave(&cohc->lock, flags);
 439
 440         /*
 441          * If there are many queued jobs, we iterate and add the
 442          * size of them all. We take a special look on the first
 443          * job though, since it is probably active.
 444          */
 445         list_for_each(pos, &cohc->active) {
 446                 /*
 447                  * The first job in the list will be working on the
 448                  * hardware. The job can be stopped but still active,
 449                  * so that the transfer counter is somewhere inside
 450                  * the buffer.
 451                  */
 452                 cohd = list_entry(pos, struct coh901318_desc, node);
 453
 454                 if (i == 0) {
 455                         struct coh901318_lli *lli;
 456                         dma_addr_t ladd;
 457
 458                         /* Read current transfer count value */
 459                         left = readl(cohc->base->virtbase +
 460                                      COH901318_CX_CTRL +
 461                                      COH901318_CX_CTRL_SPACING * cohc->id) &
 462                                 COH901318_CX_CTRL_TC_VALUE_MASK;
 463
 464                         /* See if the transfer is linked... */
 465                         ladd = readl(cohc->base->virtbase +
 466                                      COH901318_CX_LNK_ADDR +
 467                                      COH901318_CX_LNK_ADDR_SPACING *
 468                                      cohc->id) &
 469                                 ~COH901318_CX_LNK_LINK_IMMEDIATE;
 470                         /* Single transaction */
 471                         if (!ladd)
 472                                 continue;
 473
 474                         /*
 475                          * Linked transaction, follow the lli, find the
 476                          * currently processing lli, and proceed to the next
 477                          */
 478                         lli = cohd->lli;
 479                         while (lli && lli->link_addr != ladd)
 480                                 lli = lli->virt_link_addr;
 481
 482                         if (lli)
 483                                 lli = lli->virt_link_addr;
 484
 485                         /*
 486                          * Follow remaining lli links around to count the total
 487                          * number of bytes left
 488                          */
 489                         left += coh901318_get_bytes_in_lli(lli);
 490                 } else {
 491                         left += coh901318_get_bytes_in_lli(cohd->lli);
 492                 }
 493                 i++;
 494         }
 495
 496         /* Also count bytes in the queued jobs */
 497         list_for_each(pos, &cohc->queue) {
 498                 cohd = list_entry(pos, struct coh901318_desc, node);
 499                 left += coh901318_get_bytes_in_lli(cohd->lli);
 500         }
 501
 502         spin_unlock_irqrestore(&cohc->lock, flags);
 503
 504         return left;
 505 }
 506 EXPORT_SYMBOL(coh901318_get_bytes_left);
 507
 508
 509 /*
 510  * Pauses a transfer without losing data. Enables power save.
 511  * Use this function in conjunction with coh901318_resume.
 512  */
 513 static void coh901318_pause(struct dma_chan *chan)
 514 {
 515         u32 val;
 516         unsigned long flags;
 517         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 518         int channel = cohc->id;
 519         void __iomem *virtbase = cohc->base->virtbase;
 520
 521         spin_lock_irqsave(&cohc->lock, flags);
 522
 523         /* Disable channel in HW */
 524         val = readl(virtbase + COH901318_CX_CFG +
 525                     COH901318_CX_CFG_SPACING * channel);
 526
 527         /* Stopping infinit transfer */
 528         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
 529             (val & COH901318_CX_CFG_CH_ENABLE))
 530                 cohc->stopped = 1;
 531
 532
 533         val &= ~COH901318_CX_CFG_CH_ENABLE;
 534         /* Enable twice, HW bug work around */
 535         writel(val, virtbase + COH901318_CX_CFG +
 536                COH901318_CX_CFG_SPACING * channel);
 537         writel(val, virtbase + COH901318_CX_CFG +
 538                COH901318_CX_CFG_SPACING * channel);
 539
 540         /* Spin-wait for it to actually go inactive */
 541         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
 542                      channel) & COH901318_CX_STAT_ACTIVE)
 543                 cpu_relax();
 544
 545         /* Check if we stopped an active job */
 546         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 547                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
 548                 cohc->stopped = 1;
 549
 550         enable_powersave(cohc);
 551
 552         spin_unlock_irqrestore(&cohc->lock, flags);
 553 }
 554
 555 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
 556    Power save is handled.
 557 */
 558 static void coh901318_resume(struct dma_chan *chan)
 559 {
 560         u32 val;
 561         unsigned long flags;
 562         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 563         int channel = cohc->id;
 564
 565         spin_lock_irqsave(&cohc->lock, flags);
 566
 567         disable_powersave(cohc);
 568
 569         if (cohc->stopped) {
 570                 /* Enable channel in HW */
 571                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
 572                             COH901318_CX_CFG_SPACING * channel);
 573
 574                 val |= COH901318_CX_CFG_CH_ENABLE;
 575
 576                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
 577                        COH901318_CX_CFG_SPACING*channel);
 578
 579                 cohc->stopped = 0;
 580         }
 581
 582         spin_unlock_irqrestore(&cohc->lock, flags);
 583 }
 584
 585 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 586 {
 587         unsigned int ch_nr = (unsigned int) chan_id;
 588
 589         if (ch_nr == to_coh901318_chan(chan)->id)
 590                 return true;
 591
 592         return false;
 593 }
 594 EXPORT_SYMBOL(coh901318_filter_id);
 595
 596 /*
 597  * DMA channel allocation
 598  */
 599 static int coh901318_config(struct coh901318_chan *cohc,
 600                             struct coh901318_params *param)
 601 {
 602         unsigned long flags;
 603         const struct coh901318_params *p;
 604         int channel = cohc->id;
 605         void __iomem *virtbase = cohc->base->virtbase;
 606
 607         spin_lock_irqsave(&cohc->lock, flags);
 608
 609         if (param)
 610                 p = param;
 611         else
 612                 p = &cohc->base->platform->chan_conf[channel].param;
 613
 614         /* Clear any pending BE or TC interrupt */
 615         if (channel < 32) {
 616                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
 617                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
 618         } else {
 619                 writel(1 << (channel - 32), virtbase +
 620                        COH901318_BE_INT_CLEAR2);
 621                 writel(1 << (channel - 32), virtbase +
 622                        COH901318_TC_INT_CLEAR2);
 623         }
 624
 625         coh901318_set_conf(cohc, p->config);
 626         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
 627
 628         spin_unlock_irqrestore(&cohc->lock, flags);
 629
 630         return 0;
 631 }
 632
 633 /* must lock when calling this function
 634  * start queued jobs, if any
 635  * TODO: start all queued jobs in one go
 636  *
 637  * Returns descriptor if queued job is started otherwise NULL.
 638  * If the queue is empty NULL is returned.
 639  */
 640 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
 641 {
 642         struct coh901318_desc *cohd;
 643
 644         /*
 645          * start queued jobs, if any
 646          * TODO: transmit all queued jobs in one go
 647          */
 648         cohd = coh901318_first_queued(cohc);
 649
 650         if (cohd != NULL) {
 651                 /* Remove from queue */
 652                 coh901318_desc_remove(cohd);
 653                 /* initiate DMA job */
 654                 cohc->busy = 1;
 655
 656                 coh901318_desc_submit(cohc, cohd);
 657
 658                 coh901318_prep_linked_list(cohc, cohd->lli);
 659
 660                 /* start dma job on this channel */
 661                 coh901318_start(cohc);
 662
 663         }
 664
 665         return cohd;
 666 }
 667
 668 /*
 669  * This tasklet is called from the interrupt handler to
 670  * handle each descriptor (DMA job) that is sent to a channel.
 671  */
 672 static void dma_tasklet(unsigned long data)
 673 {
 674         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
 675         struct coh901318_desc *cohd_fin;
 676         unsigned long flags;
 677         dma_async_tx_callback callback;
 678         void *callback_param;
 679
 680         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
 681                  " nbr_active_done %ld\n", __func__,
 682                  cohc->id, cohc->nbr_active_done);
 683
 684         spin_lock_irqsave(&cohc->lock, flags);
 685
 686         /* get first active descriptor entry from list */
 687         cohd_fin = coh901318_first_active_get(cohc);
 688
 689         if (cohd_fin == NULL)
 690                 goto err;
 691
 692         /* locate callback to client */
 693         callback = cohd_fin->desc.callback;
 694         callback_param = cohd_fin->desc.callback_param;
 695
 696         /* sign this job as completed on the channel */
 697         cohc->completed = cohd_fin->desc.cookie;
 698
 699         /* release the lli allocation and remove the descriptor */
 700         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
 701
 702         /* return desc to free-list */
 703         coh901318_desc_remove(cohd_fin);
 704         coh901318_desc_free(cohc, cohd_fin);
 705
 706         spin_unlock_irqrestore(&cohc->lock, flags);
 707
 708         /* Call the callback when we're done */
 709         if (callback)
 710                 callback(callback_param);
 711
 712         spin_lock_irqsave(&cohc->lock, flags);
 713
 714         /*
 715          * If another interrupt fired while the tasklet was scheduling,
 716          * we don't get called twice, so we have this number of active
 717          * counter that keep track of the number of IRQs expected to
 718          * be handled for this channel. If there happen to be more than
 719          * one IRQ to be ack:ed, we simply schedule this tasklet again.
 720          */
 721         cohc->nbr_active_done--;
 722         if (cohc->nbr_active_done) {
 723                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
 724                         "came in while we were scheduling this tasklet\n");
 725                 if (cohc_chan_conf(cohc)->priority_high)
 726                         tasklet_hi_schedule(&cohc->tasklet);
 727                 else
 728                         tasklet_schedule(&cohc->tasklet);
 729         }
 730
 731         spin_unlock_irqrestore(&cohc->lock, flags);
 732
 733         return;
 734
 735  err:
 736         spin_unlock_irqrestore(&cohc->lock, flags);
 737         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
 738 }
 739
 740
 741 /* called from interrupt context */
 742 static void dma_tc_handle(struct coh901318_chan *cohc)
 743 {
 744         /*
 745          * If the channel is not allocated, then we shouldn't have
 746          * any TC interrupts on it.
 747          */
 748         if (!cohc->allocated) {
 749                 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
 750                         "unallocated channel\n");
 751                 return;
 752         }
 753
 754         spin_lock(&cohc->lock);
 755
 756         /*
 757          * When we reach this point, at least one queue item
 758          * should have been moved over from cohc->queue to
 759          * cohc->active and run to completion, that is why we're
 760          * getting a terminal count interrupt is it not?
 761          * If you get this BUG() the most probable cause is that
 762          * the individual nodes in the lli chain have IRQ enabled,
 763          * so check your platform config for lli chain ctrl.
 764          */
 765         BUG_ON(list_empty(&cohc->active));
 766
 767         cohc->nbr_active_done++;
 768
 769         /*
 770          * This attempt to take a job from cohc->queue, put it
 771          * into cohc->active and start it.
 772          */
 773         if (coh901318_queue_start(cohc) == NULL)
 774                 cohc->busy = 0;
 775
 776         spin_unlock(&cohc->lock);
 777
 778         /*
 779          * This tasklet will remove items from cohc->active
 780          * and thus terminates them.
 781          */
 782         if (cohc_chan_conf(cohc)->priority_high)
 783                 tasklet_hi_schedule(&cohc->tasklet);
 784         else
 785                 tasklet_schedule(&cohc->tasklet);
 786 }
 787
 788
 789 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 790 {
 791         u32 status1;
 792         u32 status2;
 793         int i;
 794         int ch;
 795         struct coh901318_base *base  = dev_id;
 796         struct coh901318_chan *cohc;
 797         void __iomem *virtbase = base->virtbase;
 798
 799         status1 = readl(virtbase + COH901318_INT_STATUS1);
 800         status2 = readl(virtbase + COH901318_INT_STATUS2);
 801
 802         if (unlikely(status1 == 0 && status2 == 0)) {
 803                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
 804                 return IRQ_HANDLED;
 805         }
 806
 807         /* TODO: consider handle IRQ in tasklet here to
 808          *       minimize interrupt latency */
 809
 810         /* Check the first 32 DMA channels for IRQ */
 811         while (status1) {
 812                 /* Find first bit set, return as a number. */
 813                 i = ffs(status1) - 1;
 814                 ch = i;
 815
 816                 cohc = &base->chans[ch];
 817                 spin_lock(&cohc->lock);
 818
 819                 /* Mask off this bit */
 820                 status1 &= ~(1 << i);
 821                 /* Check the individual channel bits */
 822                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
 823                         dev_crit(COHC_2_DEV(cohc),
 824                                  "DMA bus error on channel %d!\n", ch);
 825                         BUG_ON(1);
 826                         /* Clear BE interrupt */
 827                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
 828                 } else {
 829                         /* Caused by TC, really? */
 830                         if (unlikely(!test_bit(i, virtbase +
 831                                                COH901318_TC_INT_STATUS1))) {
 832                                 dev_warn(COHC_2_DEV(cohc),
 833                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 834                                 /* Clear TC interrupt */
 835                                 BUG_ON(1);
 836                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 837                         } else {
 838                                 /* Enable powersave if transfer has finished */
 839                                 if (!(readl(virtbase + COH901318_CX_STAT +
 840                                             COH901318_CX_STAT_SPACING*ch) &
 841                                       COH901318_CX_STAT_ENABLED)) {
 842                                         enable_powersave(cohc);
 843                                 }
 844
 845                                 /* Must clear TC interrupt before calling
 846                                  * dma_tc_handle
 847                                  * in case tc_handle initate a new dma job
 848                                  */
 849                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 850
 851                                 dma_tc_handle(cohc);
 852                         }
 853                 }
 854                 spin_unlock(&cohc->lock);
 855         }
 856
 857         /* Check the remaining 32 DMA channels for IRQ */
 858         while (status2) {
 859                 /* Find first bit set, return as a number. */
 860                 i = ffs(status2) - 1;
 861                 ch = i + 32;
 862                 cohc = &base->chans[ch];
 863                 spin_lock(&cohc->lock);
 864
 865                 /* Mask off this bit */
 866                 status2 &= ~(1 << i);
 867                 /* Check the individual channel bits */
 868                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
 869                         dev_crit(COHC_2_DEV(cohc),
 870                                  "DMA bus error on channel %d!\n", ch);
 871                         /* Clear BE interrupt */
 872                         BUG_ON(1);
 873                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
 874                 } else {
 875                         /* Caused by TC, really? */
 876                         if (unlikely(!test_bit(i, virtbase +
 877                                                COH901318_TC_INT_STATUS2))) {
 878                                 dev_warn(COHC_2_DEV(cohc),
 879                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 880                                 /* Clear TC interrupt */
 881                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 882                                 BUG_ON(1);
 883                         } else {
 884                                 /* Enable powersave if transfer has finished */
 885                                 if (!(readl(virtbase + COH901318_CX_STAT +
 886                                             COH901318_CX_STAT_SPACING*ch) &
 887                                       COH901318_CX_STAT_ENABLED)) {
 888                                         enable_powersave(cohc);
 889                                 }
 890                                 /* Must clear TC interrupt before calling
 891                                  * dma_tc_handle
 892                                  * in case tc_handle initate a new dma job
 893                                  */
 894                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 895
 896                                 dma_tc_handle(cohc);
 897                         }
 898                 }
 899                 spin_unlock(&cohc->lock);
 900         }
 901
 902         return IRQ_HANDLED;
 903 }
 904
 905 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 906 {
 907         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 908         unsigned long flags;
 909
 910         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
 911                  __func__, cohc->id);
 912
 913         if (chan->client_count > 1)
 914                 return -EBUSY;
 915
 916         spin_lock_irqsave(&cohc->lock, flags);
 917
 918         coh901318_config(cohc, NULL);
 919
 920         cohc->allocated = 1;
 921         cohc->completed = chan->cookie = 1;
 922
 923         spin_unlock_irqrestore(&cohc->lock, flags);
 924
 925         return 1;
 926 }
 927
 928 static void
 929 coh901318_free_chan_resources(struct dma_chan *chan)
 930 {
 931         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 932         int channel = cohc->id;
 933         unsigned long flags;
 934
 935         spin_lock_irqsave(&cohc->lock, flags);
 936
 937         /* Disable HW */
 938         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
 939                COH901318_CX_CFG_SPACING*channel);
 940         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
 941                COH901318_CX_CTRL_SPACING*channel);
 942
 943         cohc->allocated = 0;
 944
 945         spin_unlock_irqrestore(&cohc->lock, flags);
 946
 947         chan->device->device_control(chan, DMA_TERMINATE_ALL);
 948 }
 949
 950
 951 static dma_cookie_t
 952 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 953 {
 954         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
 955                                                    desc);
 956         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 957         unsigned long flags;
 958
 959         spin_lock_irqsave(&cohc->lock, flags);
 960
 961         tx->cookie = coh901318_assign_cookie(cohc, cohd);
 962
 963         coh901318_desc_queue(cohc, cohd);
 964
 965         spin_unlock_irqrestore(&cohc->lock, flags);
 966
 967         return tx->cookie;
 968 }
 969
 970 static struct dma_async_tx_descriptor *
 971 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 972                       size_t size, unsigned long flags)
 973 {
 974         struct coh901318_lli *lli;
 975         struct coh901318_desc *cohd;
 976         unsigned long flg;
 977         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 978         int lli_len;
 979         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 980         int ret;
 981
 982         spin_lock_irqsave(&cohc->lock, flg);
 983
 984         dev_vdbg(COHC_2_DEV(cohc),
 985                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
 986                  __func__, cohc->id, src, dest, size);
 987
 988         if (flags & DMA_PREP_INTERRUPT)
 989                 /* Trigger interrupt after last lli */
 990                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 991
 992         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
 993         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
 994                 lli_len++;
 995
 996         lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
 997
 998         if (lli == NULL)
 999                 goto err;
1000
1001         ret = coh901318_lli_fill_memcpy(
1002                 &cohc->base->pool, lli, src, size, dest,
1003                 cohc_chan_param(cohc)->ctrl_lli_chained,
1004                 ctrl_last);
1005         if (ret)
1006                 goto err;
1007
1008         COH_DBG(coh901318_list_print(cohc, lli));
1009
1010         /* Pick a descriptor to handle this transfer */
1011         cohd = coh901318_desc_get(cohc);
1012         cohd->lli = lli;
1013         cohd->flags = flags;
1014         cohd->desc.tx_submit = coh901318_tx_submit;
1015
1016         spin_unlock_irqrestore(&cohc->lock, flg);
1017
1018         return &cohd->desc;
1019  err:
1020         spin_unlock_irqrestore(&cohc->lock, flg);
1021         return NULL;
1022 }
1023
1024 static struct dma_async_tx_descriptor *
1025 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1026                         unsigned int sg_len, enum dma_data_direction direction,
1027                         unsigned long flags)
1028 {
1029         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1030         struct coh901318_lli *lli;
1031         struct coh901318_desc *cohd;
1032         const struct coh901318_params *params;
1033         struct scatterlist *sg;
1034         int len = 0;
1035         int size;
1036         int i;
1037         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1038         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1039         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1040         u32 config;
1041         unsigned long flg;
1042         int ret;
1043
1044         if (!sgl)
1045                 goto out;
1046         if (sgl->length == 0)
1047                 goto out;
1048
1049         spin_lock_irqsave(&cohc->lock, flg);
1050
1051         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1052                  __func__, sg_len, direction);
1053
1054         if (flags & DMA_PREP_INTERRUPT)
1055                 /* Trigger interrupt after last lli */
1056                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1057
1058         params = cohc_chan_param(cohc);
1059         config = params->config;
1060
1061         if (direction == DMA_TO_DEVICE) {
1062                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1063                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1064
1065                 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1066                 ctrl_chained |= tx_flags;
1067                 ctrl_last |= tx_flags;
1068                 ctrl |= tx_flags;
1069         } else if (direction == DMA_FROM_DEVICE) {
1070                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1071                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1072
1073                 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1074                 ctrl_chained |= rx_flags;
1075                 ctrl_last |= rx_flags;
1076                 ctrl |= rx_flags;
1077         } else
1078                 goto err_direction;
1079
1080         coh901318_set_conf(cohc, config);
1081
1082         /* The dma only supports transmitting packages up to
1083          * MAX_DMA_PACKET_SIZE. Calculate to total number of
1084          * dma elemts required to send the entire sg list
1085          */
1086         for_each_sg(sgl, sg, sg_len, i) {
1087                 unsigned int factor;
1088                 size = sg_dma_len(sg);
1089
1090                 if (size <= MAX_DMA_PACKET_SIZE) {
1091                         len++;
1092                         continue;
1093                 }
1094
1095                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1096                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1097                         factor++;
1098
1099                 len += factor;
1100         }
1101
1102         pr_debug("Allocate %d lli:s for this transfer\n", len);
1103         lli = coh901318_lli_alloc(&cohc->base->pool, len);
1104
1105         if (lli == NULL)
1106                 goto err_dma_alloc;
1107
1108         /* initiate allocated lli list */
1109         ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1110                                     cohc_dev_addr(cohc),
1111                                     ctrl_chained,
1112                                     ctrl,
1113                                     ctrl_last,
1114                                     direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1115         if (ret)
1116                 goto err_lli_fill;
1117
1118         COH_DBG(coh901318_list_print(cohc, lli));
1119
1120         /* Pick a descriptor to handle this transfer */
1121         cohd = coh901318_desc_get(cohc);
1122         cohd->dir = direction;
1123         cohd->flags = flags;
1124         cohd->desc.tx_submit = coh901318_tx_submit;
1125         cohd->lli = lli;
1126
1127         spin_unlock_irqrestore(&cohc->lock, flg);
1128
1129         return &cohd->desc;
1130  err_lli_fill:
1131  err_dma_alloc:
1132  err_direction:
1133         spin_unlock_irqrestore(&cohc->lock, flg);
1134  out:
1135         return NULL;
1136 }
1137
1138 static enum dma_status
1139 coh901318_is_tx_complete(struct dma_chan *chan,
1140                          dma_cookie_t cookie, dma_cookie_t *done,
1141                          dma_cookie_t *used)
1142 {
1143         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1144         dma_cookie_t last_used;
1145         dma_cookie_t last_complete;
1146         int ret;
1147
1148         last_complete = cohc->completed;
1149         last_used = chan->cookie;
1150
1151         ret = dma_async_is_complete(cookie, last_complete, last_used);
1152
1153         if (done)
1154                 *done = last_complete;
1155         if (used)
1156                 *used = last_used;
1157
1158         return ret;
1159 }
1160
1161 static void
1162 coh901318_issue_pending(struct dma_chan *chan)
1163 {
1164         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1165         unsigned long flags;
1166
1167         spin_lock_irqsave(&cohc->lock, flags);
1168
1169         /*
1170          * Busy means that pending jobs are already being processed,
1171          * and then there is no point in starting the queue: the
1172          * terminal count interrupt on the channel will take the next
1173          * job on the queue and execute it anyway.
1174          */
1175         if (!cohc->busy)
1176                 coh901318_queue_start(cohc);
1177
1178         spin_unlock_irqrestore(&cohc->lock, flags);
1179 }
1180
1181 static int
1182 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd)
1183 {
1184         unsigned long flags;
1185         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1186         struct coh901318_desc *cohd;
1187         void __iomem *virtbase = cohc->base->virtbase;
1188
1189         if (cmd == DMA_PAUSE) {
1190                 coh901318_pause(chan);
1191                 return 0;
1192         }
1193
1194         if (cmd == DMA_RESUME) {
1195                 coh901318_resume(chan);
1196                 return 0;
1197         }
1198
1199         if (cmd != DMA_TERMINATE_ALL)
1200                 return -ENXIO;
1201
1202         /* The remainder of this function terminates the transfer */
1203         coh901318_pause(chan);
1204         spin_lock_irqsave(&cohc->lock, flags);
1205
1206         /* Clear any pending BE or TC interrupt */
1207         if (cohc->id < 32) {
1208                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1209                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1210         } else {
1211                 writel(1 << (cohc->id - 32), virtbase +
1212                        COH901318_BE_INT_CLEAR2);
1213                 writel(1 << (cohc->id - 32), virtbase +
1214                        COH901318_TC_INT_CLEAR2);
1215         }
1216
1217         enable_powersave(cohc);
1218
1219         while ((cohd = coh901318_first_active_get(cohc))) {
1220                 /* release the lli allocation*/
1221                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1222
1223                 /* return desc to free-list */
1224                 coh901318_desc_remove(cohd);
1225                 coh901318_desc_free(cohc, cohd);
1226         }
1227
1228         while ((cohd = coh901318_first_queued(cohc))) {
1229                 /* release the lli allocation*/
1230                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1231
1232                 /* return desc to free-list */
1233                 coh901318_desc_remove(cohd);
1234                 coh901318_desc_free(cohc, cohd);
1235         }
1236
1237
1238         cohc->nbr_active_done = 0;
1239         cohc->busy = 0;
1240
1241         spin_unlock_irqrestore(&cohc->lock, flags);
1242
1243         return 0;
1244 }
1245 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1246                          struct coh901318_base *base)
1247 {
1248         int chans_i;
1249         int i = 0;
1250         struct coh901318_chan *cohc;
1251
1252         INIT_LIST_HEAD(&dma->channels);
1253
1254         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1255                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1256                         cohc = &base->chans[i];
1257
1258                         cohc->base = base;
1259                         cohc->chan.device = dma;
1260                         cohc->id = i;
1261
1262                         /* TODO: do we really need this lock if only one
1263                          * client is connected to each channel?
1264                          */
1265
1266                         spin_lock_init(&cohc->lock);
1267
1268                         cohc->nbr_active_done = 0;
1269                         cohc->busy = 0;
1270                         INIT_LIST_HEAD(&cohc->free);
1271                         INIT_LIST_HEAD(&cohc->active);
1272                         INIT_LIST_HEAD(&cohc->queue);
1273
1274                         tasklet_init(&cohc->tasklet, dma_tasklet,
1275                                      (unsigned long) cohc);
1276
1277                         list_add_tail(&cohc->chan.device_node,
1278                                       &dma->channels);
1279                 }
1280         }
1281 }
1282
1283 static int __init coh901318_probe(struct platform_device *pdev)
1284 {
1285         int err = 0;
1286         struct coh901318_platform *pdata;
1287         struct coh901318_base *base;
1288         int irq;
1289         struct resource *io;
1290
1291         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292         if (!io)
1293                 goto err_get_resource;
1294
1295         /* Map DMA controller registers to virtual memory */
1296         if (request_mem_region(io->start,
1297                                resource_size(io),
1298                                pdev->dev.driver->name) == NULL) {
1299                 err = -EBUSY;
1300                 goto err_request_mem;
1301         }
1302
1303         pdata = pdev->dev.platform_data;
1304         if (!pdata)
1305                 goto err_no_platformdata;
1306
1307         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1308                        pdata->max_channels *
1309                        sizeof(struct coh901318_chan),
1310                        GFP_KERNEL);
1311         if (!base)
1312                 goto err_alloc_coh_dma_channels;
1313
1314         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1315
1316         base->virtbase = ioremap(io->start, resource_size(io));
1317         if (!base->virtbase) {
1318                 err = -ENOMEM;
1319                 goto err_no_ioremap;
1320         }
1321
1322         base->dev = &pdev->dev;
1323         base->platform = pdata;
1324         spin_lock_init(&base->pm.lock);
1325         base->pm.started_channels = 0;
1326
1327         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1328
1329         platform_set_drvdata(pdev, base);
1330
1331         irq = platform_get_irq(pdev, 0);
1332         if (irq < 0)
1333                 goto err_no_irq;
1334
1335         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1336                           "coh901318", base);
1337         if (err) {
1338                 dev_crit(&pdev->dev,
1339                          "Cannot allocate IRQ for DMA controller!\n");
1340                 goto err_request_irq;
1341         }
1342
1343         err = coh901318_pool_create(&base->pool, &pdev->dev,
1344                                     sizeof(struct coh901318_lli),
1345                                     32);
1346         if (err)
1347                 goto err_pool_create;
1348
1349         /* init channels for device transfers */
1350         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1351                             base);
1352
1353         dma_cap_zero(base->dma_slave.cap_mask);
1354         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1355
1356         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1357         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1358         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1359         base->dma_slave.device_is_tx_complete = coh901318_is_tx_complete;
1360         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1361         base->dma_slave.device_control = coh901318_control;
1362         base->dma_slave.dev = &pdev->dev;
1363
1364         err = dma_async_device_register(&base->dma_slave);
1365
1366         if (err)
1367                 goto err_register_slave;
1368
1369         /* init channels for memcpy */
1370         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1371                             base);
1372
1373         dma_cap_zero(base->dma_memcpy.cap_mask);
1374         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1375
1376         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1377         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1378         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1379         base->dma_memcpy.device_is_tx_complete = coh901318_is_tx_complete;
1380         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1381         base->dma_memcpy.device_control = coh901318_control;
1382         base->dma_memcpy.dev = &pdev->dev;
1383         /*
1384          * This controller can only access address at even 32bit boundaries,
1385          * i.e. 2^2
1386          */
1387         base->dma_memcpy.copy_align = 2;
1388         err = dma_async_device_register(&base->dma_memcpy);
1389
1390         if (err)
1391                 goto err_register_memcpy;
1392
1393         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1394                 (u32) base->virtbase);
1395
1396         return err;
1397
1398  err_register_memcpy:
1399         dma_async_device_unregister(&base->dma_slave);
1400  err_register_slave:
1401         coh901318_pool_destroy(&base->pool);
1402  err_pool_create:
1403         free_irq(platform_get_irq(pdev, 0), base);
1404  err_request_irq:
1405  err_no_irq:
1406         iounmap(base->virtbase);
1407  err_no_ioremap:
1408         kfree(base);
1409  err_alloc_coh_dma_channels:
1410  err_no_platformdata:
1411         release_mem_region(pdev->resource->start,
1412                            resource_size(pdev->resource));
1413  err_request_mem:
1414  err_get_resource:
1415         return err;
1416 }
1417
1418 static int __exit coh901318_remove(struct platform_device *pdev)
1419 {
1420         struct coh901318_base *base = platform_get_drvdata(pdev);
1421
1422         dma_async_device_unregister(&base->dma_memcpy);
1423         dma_async_device_unregister(&base->dma_slave);
1424         coh901318_pool_destroy(&base->pool);
1425         free_irq(platform_get_irq(pdev, 0), base);
1426         iounmap(base->virtbase);
1427         kfree(base);
1428         release_mem_region(pdev->resource->start,
1429                            resource_size(pdev->resource));
1430         return 0;
1431 }
1432
1433
1434 static struct platform_driver coh901318_driver = {
1435         .remove = __exit_p(coh901318_remove),
1436         .driver = {
1437                 .name   = "coh901318",
1438         },
1439 };
1440
1441 int __init coh901318_init(void)
1442 {
1443         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1444 }
1445 subsys_initcall(coh901318_init);
1446
1447 void __exit coh901318_exit(void)
1448 {
1449         platform_driver_unregister(&coh901318_driver);
1450 }
1451 module_exit(coh901318_exit);
1452
1453 MODULE_LICENSE("GPL");
1454 MODULE_AUTHOR("Per Friden");