drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 /*
  14  * If we have Intel graphics, we're not going to have anything other than
  15  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  16  * on the Intel IOMMU support (CONFIG_DMAR).
  17  * Only newer chipsets need to bother with this, of course.
  18  */
  19 #ifdef CONFIG_DMAR
  20 #define USE_PCI_DMA_API 1
  21 #endif
  22
  23 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  24 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  27 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  28 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  29 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  30 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  31 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  32 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  33 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  34 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  35 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  36 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  37 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  38 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  39 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  40 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  41 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  42 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  43 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  44 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  45 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  46 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  47 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  48 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  49 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  50 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  51 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  52 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  53 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  54 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  55 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  56 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  57 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  58 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  59 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  60 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  61 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  62 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  63
  64 /* cover 915 and 945 variants */
  65 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  66                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  67                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  68                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  69                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  71
  72 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  73                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  74                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  75                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  76                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  77                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  78
  79 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  80                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  81                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  82                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  83                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  84
  85 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  86                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  87
  88 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  89                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  90                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  91                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  92                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB)
  95
  96 extern int agp_memory_reserved;
  97
  98
  99 /* Intel 815 register */
 100 #define INTEL_815_APCONT        0x51
 101 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 102
 103 /* Intel i820 registers */
 104 #define INTEL_I820_RDCR         0x51
 105 #define INTEL_I820_ERRSTS       0xc8
 106
 107 /* Intel i840 registers */
 108 #define INTEL_I840_MCHCFG       0x50
 109 #define INTEL_I840_ERRSTS       0xc8
 110
 111 /* Intel i850 registers */
 112 #define INTEL_I850_MCHCFG       0x50
 113 #define INTEL_I850_ERRSTS       0xc8
 114
 115 /* intel 915G registers */
 116 #define I915_GMADDR     0x18
 117 #define I915_MMADDR     0x10
 118 #define I915_PTEADDR    0x1C
 119 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 120 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 121 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 122 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 123 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 124 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 125 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 126 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 127
 128 #define I915_IFPADDR    0x60
 129
 130 /* Intel 965G registers */
 131 #define I965_MSAC 0x62
 132 #define I965_IFPADDR    0x70
 133
 134 /* Intel 7505 registers */
 135 #define INTEL_I7505_APSIZE      0x74
 136 #define INTEL_I7505_NCAPID      0x60
 137 #define INTEL_I7505_NISTAT      0x6c
 138 #define INTEL_I7505_ATTBASE     0x78
 139 #define INTEL_I7505_ERRSTS      0x42
 140 #define INTEL_I7505_AGPCTRL     0x70
 141 #define INTEL_I7505_MCHCFG      0x50
 142
 143 static const struct aper_size_info_fixed intel_i810_sizes[] =
 144 {
 145         {64, 16384, 4},
 146         /* The 32M mode still requires a 64k gatt */
 147         {32, 8192, 4}
 148 };
 149
 150 #define AGP_DCACHE_MEMORY       1
 151 #define AGP_PHYS_MEMORY         2
 152 #define INTEL_AGP_CACHED_MEMORY 3
 153
 154 static struct gatt_mask intel_i810_masks[] =
 155 {
 156         {.mask = I810_PTE_VALID, .type = 0},
 157         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 158         {.mask = I810_PTE_VALID, .type = 0},
 159         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 160          .type = INTEL_AGP_CACHED_MEMORY}
 161 };
 162
 163 static struct _intel_private {
 164         struct pci_dev *pcidev; /* device one */
 165         u8 __iomem *registers;
 166         u32 __iomem *gtt;               /* I915G */
 167         int num_dcache_entries;
 168         /* gtt_entries is the number of gtt entries that are already mapped
 169          * to stolen memory.  Stolen memory is larger than the memory mapped
 170          * through gtt_entries, as it includes some reserved space for the BIOS
 171          * popup and for the GTT.
 172          */
 173         int gtt_entries;                        /* i830+ */
 174         union {
 175                 void __iomem *i9xx_flush_page;
 176                 void *i8xx_flush_page;
 177         };
 178         struct page *i8xx_page;
 179         struct resource ifp_resource;
 180         int resource_valid;
 181 } intel_private;
 182
 183 #ifdef USE_PCI_DMA_API
 184 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 185 {
 186         *ret = pci_map_page(intel_private.pcidev, page, 0,
 187                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 188         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 189                 return -EINVAL;
 190         return 0;
 191 }
 192
 193 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 194 {
 195         pci_unmap_page(intel_private.pcidev, dma,
 196                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 197 }
 198
 199 static void intel_agp_free_sglist(struct agp_memory *mem)
 200 {
 201         struct sg_table st;
 202
 203         st.sgl = mem->sg_list;
 204         st.orig_nents = st.nents = mem->page_count;
 205
 206         sg_free_table(&st);
 207
 208         mem->sg_list = NULL;
 209         mem->num_sg = 0;
 210 }
 211
 212 static int intel_agp_map_memory(struct agp_memory *mem)
 213 {
 214         struct sg_table st;
 215         struct scatterlist *sg;
 216         int i;
 217
 218         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 219
 220         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 221                 return -ENOMEM;
 222
 223         mem->sg_list = sg = st.sgl;
 224
 225         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 226                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 227
 228         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 229                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 230         if (unlikely(!mem->num_sg)) {
 231                 intel_agp_free_sglist(mem);
 232                 return -ENOMEM;
 233         }
 234         return 0;
 235 }
 236
 237 static void intel_agp_unmap_memory(struct agp_memory *mem)
 238 {
 239         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 240
 241         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 242                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 243         intel_agp_free_sglist(mem);
 244 }
 245
 246 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 247                                         off_t pg_start, int mask_type)
 248 {
 249         struct scatterlist *sg;
 250         int i, j;
 251
 252         j = pg_start;
 253
 254         WARN_ON(!mem->num_sg);
 255
 256         if (mem->num_sg == mem->page_count) {
 257                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 258                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 259                                         sg_dma_address(sg), mask_type),
 260                                         intel_private.gtt+j);
 261                         j++;
 262                 }
 263         } else {
 264                 /* sg may merge pages, but we have to seperate
 265                  * per-page addr for GTT */
 266                 unsigned int len, m;
 267
 268                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 269                         len = sg_dma_len(sg) / PAGE_SIZE;
 270                         for (m = 0; m < len; m++) {
 271                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 272                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 273                                                                        mask_type),
 274                                        intel_private.gtt+j);
 275                                 j++;
 276                         }
 277                 }
 278         }
 279         readl(intel_private.gtt+j-1);
 280 }
 281
 282 #else
 283
 284 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 285                                         off_t pg_start, int mask_type)
 286 {
 287         int i, j;
 288
 289         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 290                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 291                                 page_to_phys(mem->pages[i]), mask_type),
 292                        intel_private.gtt+j);
 293         }
 294
 295         readl(intel_private.gtt+j-1);
 296 }
 297
 298 #endif
 299
 300 static int intel_i810_fetch_size(void)
 301 {
 302         u32 smram_miscc;
 303         struct aper_size_info_fixed *values;
 304
 305         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 306         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 307
 308         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 309                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 310                 return 0;
 311         }
 312         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 313                 agp_bridge->previous_size =
 314                         agp_bridge->current_size = (void *) (values + 1);
 315                 agp_bridge->aperture_size_idx = 1;
 316                 return values[1].size;
 317         } else {
 318                 agp_bridge->previous_size =
 319                         agp_bridge->current_size = (void *) (values);
 320                 agp_bridge->aperture_size_idx = 0;
 321                 return values[0].size;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int intel_i810_configure(void)
 328 {
 329         struct aper_size_info_fixed *current_size;
 330         u32 temp;
 331         int i;
 332
 333         current_size = A_SIZE_FIX(agp_bridge->current_size);
 334
 335         if (!intel_private.registers) {
 336                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 337                 temp &= 0xfff80000;
 338
 339                 intel_private.registers = ioremap(temp, 128 * 4096);
 340                 if (!intel_private.registers) {
 341                         dev_err(&intel_private.pcidev->dev,
 342                                 "can't remap memory\n");
 343                         return -ENOMEM;
 344                 }
 345         }
 346
 347         if ((readl(intel_private.registers+I810_DRAM_CTL)
 348                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 349                 /* This will need to be dynamically assigned */
 350                 dev_info(&intel_private.pcidev->dev,
 351                          "detected 4MB dedicated video ram\n");
 352                 intel_private.num_dcache_entries = 1024;
 353         }
 354         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 355         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 356         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 357         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 358
 359         if (agp_bridge->driver->needs_scratch_page) {
 360                 for (i = 0; i < current_size->num_entries; i++) {
 361                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 362                 }
 363                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 364         }
 365         global_cache_flush();
 366         return 0;
 367 }
 368
 369 static void intel_i810_cleanup(void)
 370 {
 371         writel(0, intel_private.registers+I810_PGETBL_CTL);
 372         readl(intel_private.registers); /* PCI Posting. */
 373         iounmap(intel_private.registers);
 374 }
 375
 376 static void intel_i810_tlbflush(struct agp_memory *mem)
 377 {
 378         return;
 379 }
 380
 381 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 382 {
 383         return;
 384 }
 385
 386 /* Exists to support ARGB cursors */
 387 static struct page *i8xx_alloc_pages(void)
 388 {
 389         struct page *page;
 390
 391         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 392         if (page == NULL)
 393                 return NULL;
 394
 395         if (set_pages_uc(page, 4) < 0) {
 396                 set_pages_wb(page, 4);
 397                 __free_pages(page, 2);
 398                 return NULL;
 399         }
 400         get_page(page);
 401         atomic_inc(&agp_bridge->current_memory_agp);
 402         return page;
 403 }
 404
 405 static void i8xx_destroy_pages(struct page *page)
 406 {
 407         if (page == NULL)
 408                 return;
 409
 410         set_pages_wb(page, 4);
 411         put_page(page);
 412         __free_pages(page, 2);
 413         atomic_dec(&agp_bridge->current_memory_agp);
 414 }
 415
 416 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 417                                         int type)
 418 {
 419         if (type < AGP_USER_TYPES)
 420                 return type;
 421         else if (type == AGP_USER_CACHED_MEMORY)
 422                 return INTEL_AGP_CACHED_MEMORY;
 423         else
 424                 return 0;
 425 }
 426
 427 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 428                                 int type)
 429 {
 430         int i, j, num_entries;
 431         void *temp;
 432         int ret = -EINVAL;
 433         int mask_type;
 434
 435         if (mem->page_count == 0)
 436                 goto out;
 437
 438         temp = agp_bridge->current_size;
 439         num_entries = A_SIZE_FIX(temp)->num_entries;
 440
 441         if ((pg_start + mem->page_count) > num_entries)
 442                 goto out_err;
 443
 444
 445         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 446                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 447                         ret = -EBUSY;
 448                         goto out_err;
 449                 }
 450         }
 451
 452         if (type != mem->type)
 453                 goto out_err;
 454
 455         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 456
 457         switch (mask_type) {
 458         case AGP_DCACHE_MEMORY:
 459                 if (!mem->is_flushed)
 460                         global_cache_flush();
 461                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 462                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 463                                intel_private.registers+I810_PTE_BASE+(i*4));
 464                 }
 465                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 466                 break;
 467         case AGP_PHYS_MEMORY:
 468         case AGP_NORMAL_MEMORY:
 469                 if (!mem->is_flushed)
 470                         global_cache_flush();
 471                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 472                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 473                                         page_to_phys(mem->pages[i]), mask_type),
 474                                intel_private.registers+I810_PTE_BASE+(j*4));
 475                 }
 476                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 477                 break;
 478         default:
 479                 goto out_err;
 480         }
 481
 482         agp_bridge->driver->tlb_flush(mem);
 483 out:
 484         ret = 0;
 485 out_err:
 486         mem->is_flushed = true;
 487         return ret;
 488 }
 489
 490 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 491                                 int type)
 492 {
 493         int i;
 494
 495         if (mem->page_count == 0)
 496                 return 0;
 497
 498         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 499                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 500         }
 501         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 502
 503         agp_bridge->driver->tlb_flush(mem);
 504         return 0;
 505 }
 506
 507 /*
 508  * The i810/i830 requires a physical address to program its mouse
 509  * pointer into hardware.
 510  * However the Xserver still writes to it through the agp aperture.
 511  */
 512 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 513 {
 514         struct agp_memory *new;
 515         struct page *page;
 516
 517         switch (pg_count) {
 518         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 519                 break;
 520         case 4:
 521                 /* kludge to get 4 physical pages for ARGB cursor */
 522                 page = i8xx_alloc_pages();
 523                 break;
 524         default:
 525                 return NULL;
 526         }
 527
 528         if (page == NULL)
 529                 return NULL;
 530
 531         new = agp_create_memory(pg_count);
 532         if (new == NULL)
 533                 return NULL;
 534
 535         new->pages[0] = page;
 536         if (pg_count == 4) {
 537                 /* kludge to get 4 physical pages for ARGB cursor */
 538                 new->pages[1] = new->pages[0] + 1;
 539                 new->pages[2] = new->pages[1] + 1;
 540                 new->pages[3] = new->pages[2] + 1;
 541         }
 542         new->page_count = pg_count;
 543         new->num_scratch_pages = pg_count;
 544         new->type = AGP_PHYS_MEMORY;
 545         new->physical = page_to_phys(new->pages[0]);
 546         return new;
 547 }
 548
 549 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 550 {
 551         struct agp_memory *new;
 552
 553         if (type == AGP_DCACHE_MEMORY) {
 554                 if (pg_count != intel_private.num_dcache_entries)
 555                         return NULL;
 556
 557                 new = agp_create_memory(1);
 558                 if (new == NULL)
 559                         return NULL;
 560
 561                 new->type = AGP_DCACHE_MEMORY;
 562                 new->page_count = pg_count;
 563                 new->num_scratch_pages = 0;
 564                 agp_free_page_array(new);
 565                 return new;
 566         }
 567         if (type == AGP_PHYS_MEMORY)
 568                 return alloc_agpphysmem_i8xx(pg_count, type);
 569         return NULL;
 570 }
 571
 572 static void intel_i810_free_by_type(struct agp_memory *curr)
 573 {
 574         agp_free_key(curr->key);
 575         if (curr->type == AGP_PHYS_MEMORY) {
 576                 if (curr->page_count == 4)
 577                         i8xx_destroy_pages(curr->pages[0]);
 578                 else {
 579                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 580                                                              AGP_PAGE_DESTROY_UNMAP);
 581                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 582                                                              AGP_PAGE_DESTROY_FREE);
 583                 }
 584                 agp_free_page_array(curr);
 585         }
 586         kfree(curr);
 587 }
 588
 589 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 590                                             dma_addr_t addr, int type)
 591 {
 592         /* Type checking must be done elsewhere */
 593         return addr | bridge->driver->masks[type].mask;
 594 }
 595
 596 static struct aper_size_info_fixed intel_i830_sizes[] =
 597 {
 598         {128, 32768, 5},
 599         /* The 64M mode still requires a 128k gatt */
 600         {64, 16384, 5},
 601         {256, 65536, 6},
 602         {512, 131072, 7},
 603 };
 604
 605 static void intel_i830_init_gtt_entries(void)
 606 {
 607         u16 gmch_ctrl;
 608         int gtt_entries;
 609         u8 rdct;
 610         int local = 0;
 611         static const int ddt[4] = { 0, 16, 32, 64 };
 612         int size; /* reserved space (in kb) at the top of stolen memory */
 613
 614         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 615
 616         if (IS_I965) {
 617                 u32 pgetbl_ctl;
 618                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 619
 620                 /* The 965 has a field telling us the size of the GTT,
 621                  * which may be larger than what is necessary to map the
 622                  * aperture.
 623                  */
 624                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 625                 case I965_PGETBL_SIZE_128KB:
 626                         size = 128;
 627                         break;
 628                 case I965_PGETBL_SIZE_256KB:
 629                         size = 256;
 630                         break;
 631                 case I965_PGETBL_SIZE_512KB:
 632                         size = 512;
 633                         break;
 634                 case I965_PGETBL_SIZE_1MB:
 635                         size = 1024;
 636                         break;
 637                 case I965_PGETBL_SIZE_2MB:
 638                         size = 2048;
 639                         break;
 640                 case I965_PGETBL_SIZE_1_5MB:
 641                         size = 1024 + 512;
 642                         break;
 643                 default:
 644                         dev_info(&intel_private.pcidev->dev,
 645                                  "unknown page table size, assuming 512KB\n");
 646                         size = 512;
 647                 }
 648                 size += 4; /* add in BIOS popup space */
 649         } else if (IS_G33 && !IS_IGD) {
 650         /* G33's GTT size defined in gmch_ctrl */
 651                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 652                 case G33_PGETBL_SIZE_1M:
 653                         size = 1024;
 654                         break;
 655                 case G33_PGETBL_SIZE_2M:
 656                         size = 2048;
 657                         break;
 658                 default:
 659                         dev_info(&agp_bridge->dev->dev,
 660                                  "unknown page table size 0x%x, assuming 512KB\n",
 661                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 662                         size = 512;
 663                 }
 664                 size += 4;
 665         } else if (IS_G4X || IS_IGD) {
 666                 /* On 4 series hardware, GTT stolen is separate from graphics
 667                  * stolen, ignore it in stolen gtt entries counting.  However,
 668                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 669                  */
 670                 size = 4;
 671         } else {
 672                 /* On previous hardware, the GTT size was just what was
 673                  * required to map the aperture.
 674                  */
 675                 size = agp_bridge->driver->fetch_size() + 4;
 676         }
 677
 678         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 679             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 680                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 681                 case I830_GMCH_GMS_STOLEN_512:
 682                         gtt_entries = KB(512) - KB(size);
 683                         break;
 684                 case I830_GMCH_GMS_STOLEN_1024:
 685                         gtt_entries = MB(1) - KB(size);
 686                         break;
 687                 case I830_GMCH_GMS_STOLEN_8192:
 688                         gtt_entries = MB(8) - KB(size);
 689                         break;
 690                 case I830_GMCH_GMS_LOCAL:
 691                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 692                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 693                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 694                         local = 1;
 695                         break;
 696                 default:
 697                         gtt_entries = 0;
 698                         break;
 699                 }
 700         } else {
 701                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 702                 case I855_GMCH_GMS_STOLEN_1M:
 703                         gtt_entries = MB(1) - KB(size);
 704                         break;
 705                 case I855_GMCH_GMS_STOLEN_4M:
 706                         gtt_entries = MB(4) - KB(size);
 707                         break;
 708                 case I855_GMCH_GMS_STOLEN_8M:
 709                         gtt_entries = MB(8) - KB(size);
 710                         break;
 711                 case I855_GMCH_GMS_STOLEN_16M:
 712                         gtt_entries = MB(16) - KB(size);
 713                         break;
 714                 case I855_GMCH_GMS_STOLEN_32M:
 715                         gtt_entries = MB(32) - KB(size);
 716                         break;
 717                 case I915_GMCH_GMS_STOLEN_48M:
 718                         /* Check it's really I915G */
 719                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 720                                 gtt_entries = MB(48) - KB(size);
 721                         else
 722                                 gtt_entries = 0;
 723                         break;
 724                 case I915_GMCH_GMS_STOLEN_64M:
 725                         /* Check it's really I915G */
 726                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 727                                 gtt_entries = MB(64) - KB(size);
 728                         else
 729                                 gtt_entries = 0;
 730                         break;
 731                 case G33_GMCH_GMS_STOLEN_128M:
 732                         if (IS_G33 || IS_I965 || IS_G4X)
 733                                 gtt_entries = MB(128) - KB(size);
 734                         else
 735                                 gtt_entries = 0;
 736                         break;
 737                 case G33_GMCH_GMS_STOLEN_256M:
 738                         if (IS_G33 || IS_I965 || IS_G4X)
 739                                 gtt_entries = MB(256) - KB(size);
 740                         else
 741                                 gtt_entries = 0;
 742                         break;
 743                 case INTEL_GMCH_GMS_STOLEN_96M:
 744                         if (IS_I965 || IS_G4X)
 745                                 gtt_entries = MB(96) - KB(size);
 746                         else
 747                                 gtt_entries = 0;
 748                         break;
 749                 case INTEL_GMCH_GMS_STOLEN_160M:
 750                         if (IS_I965 || IS_G4X)
 751                                 gtt_entries = MB(160) - KB(size);
 752                         else
 753                                 gtt_entries = 0;
 754                         break;
 755                 case INTEL_GMCH_GMS_STOLEN_224M:
 756                         if (IS_I965 || IS_G4X)
 757                                 gtt_entries = MB(224) - KB(size);
 758                         else
 759                                 gtt_entries = 0;
 760                         break;
 761                 case INTEL_GMCH_GMS_STOLEN_352M:
 762                         if (IS_I965 || IS_G4X)
 763                                 gtt_entries = MB(352) - KB(size);
 764                         else
 765                                 gtt_entries = 0;
 766                         break;
 767                 default:
 768                         gtt_entries = 0;
 769                         break;
 770                 }
 771         }
 772         if (gtt_entries > 0) {
 773                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 774                        gtt_entries / KB(1), local ? "local" : "stolen");
 775                 gtt_entries /= KB(4);
 776         } else {
 777                 dev_info(&agp_bridge->dev->dev,
 778                        "no pre-allocated video memory detected\n");
 779                 gtt_entries = 0;
 780         }
 781
 782         intel_private.gtt_entries = gtt_entries;
 783 }
 784
 785 static void intel_i830_fini_flush(void)
 786 {
 787         kunmap(intel_private.i8xx_page);
 788         intel_private.i8xx_flush_page = NULL;
 789         unmap_page_from_agp(intel_private.i8xx_page);
 790
 791         __free_page(intel_private.i8xx_page);
 792         intel_private.i8xx_page = NULL;
 793 }
 794
 795 static void intel_i830_setup_flush(void)
 796 {
 797         /* return if we've already set the flush mechanism up */
 798         if (intel_private.i8xx_page)
 799                 return;
 800
 801         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 802         if (!intel_private.i8xx_page)
 803                 return;
 804
 805         /* make page uncached */
 806         map_page_into_agp(intel_private.i8xx_page);
 807
 808         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 809         if (!intel_private.i8xx_flush_page)
 810                 intel_i830_fini_flush();
 811 }
 812
 813 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 814 {
 815         unsigned int *pg = intel_private.i8xx_flush_page;
 816         int i;
 817
 818         for (i = 0; i < 256; i += 2)
 819                 *(pg + i) = i;
 820
 821         wmb();
 822 }
 823
 824 /* The intel i830 automatically initializes the agp aperture during POST.
 825  * Use the memory already set aside for in the GTT.
 826  */
 827 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 828 {
 829         int page_order;
 830         struct aper_size_info_fixed *size;
 831         int num_entries;
 832         u32 temp;
 833
 834         size = agp_bridge->current_size;
 835         page_order = size->page_order;
 836         num_entries = size->num_entries;
 837         agp_bridge->gatt_table_real = NULL;
 838
 839         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 840         temp &= 0xfff80000;
 841
 842         intel_private.registers = ioremap(temp, 128 * 4096);
 843         if (!intel_private.registers)
 844                 return -ENOMEM;
 845
 846         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 847         global_cache_flush();   /* FIXME: ?? */
 848
 849         /* we have to call this as early as possible after the MMIO base address is known */
 850         intel_i830_init_gtt_entries();
 851
 852         agp_bridge->gatt_table = NULL;
 853
 854         agp_bridge->gatt_bus_addr = temp;
 855
 856         return 0;
 857 }
 858
 859 /* Return the gatt table to a sane state. Use the top of stolen
 860  * memory for the GTT.
 861  */
 862 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 863 {
 864         return 0;
 865 }
 866
 867 static int intel_i830_fetch_size(void)
 868 {
 869         u16 gmch_ctrl;
 870         struct aper_size_info_fixed *values;
 871
 872         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 873
 874         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 875             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 876                 /* 855GM/852GM/865G has 128MB aperture size */
 877                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 878                 agp_bridge->aperture_size_idx = 0;
 879                 return values[0].size;
 880         }
 881
 882         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 883
 884         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 885                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 886                 agp_bridge->aperture_size_idx = 0;
 887                 return values[0].size;
 888         } else {
 889                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 890                 agp_bridge->aperture_size_idx = 1;
 891                 return values[1].size;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static int intel_i830_configure(void)
 898 {
 899         struct aper_size_info_fixed *current_size;
 900         u32 temp;
 901         u16 gmch_ctrl;
 902         int i;
 903
 904         current_size = A_SIZE_FIX(agp_bridge->current_size);
 905
 906         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 907         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 908
 909         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 910         gmch_ctrl |= I830_GMCH_ENABLED;
 911         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 912
 913         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 914         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 915
 916         if (agp_bridge->driver->needs_scratch_page) {
 917                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 918                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 919                 }
 920                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 921         }
 922
 923         global_cache_flush();
 924
 925         intel_i830_setup_flush();
 926         return 0;
 927 }
 928
 929 static void intel_i830_cleanup(void)
 930 {
 931         iounmap(intel_private.registers);
 932 }
 933
 934 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 935                                      int type)
 936 {
 937         int i, j, num_entries;
 938         void *temp;
 939         int ret = -EINVAL;
 940         int mask_type;
 941
 942         if (mem->page_count == 0)
 943                 goto out;
 944
 945         temp = agp_bridge->current_size;
 946         num_entries = A_SIZE_FIX(temp)->num_entries;
 947
 948         if (pg_start < intel_private.gtt_entries) {
 949                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 950                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 951                            pg_start, intel_private.gtt_entries);
 952
 953                 dev_info(&intel_private.pcidev->dev,
 954                          "trying to insert into local/stolen memory\n");
 955                 goto out_err;
 956         }
 957
 958         if ((pg_start + mem->page_count) > num_entries)
 959                 goto out_err;
 960
 961         /* The i830 can't check the GTT for entries since its read only,
 962          * depend on the caller to make the correct offset decisions.
 963          */
 964
 965         if (type != mem->type)
 966                 goto out_err;
 967
 968         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 969
 970         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 971             mask_type != INTEL_AGP_CACHED_MEMORY)
 972                 goto out_err;
 973
 974         if (!mem->is_flushed)
 975                 global_cache_flush();
 976
 977         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 978                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 979                                 page_to_phys(mem->pages[i]), mask_type),
 980                        intel_private.registers+I810_PTE_BASE+(j*4));
 981         }
 982         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 983         agp_bridge->driver->tlb_flush(mem);
 984
 985 out:
 986         ret = 0;
 987 out_err:
 988         mem->is_flushed = true;
 989         return ret;
 990 }
 991
 992 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 993                                      int type)
 994 {
 995         int i;
 996
 997         if (mem->page_count == 0)
 998                 return 0;
 999
1000         if (pg_start < intel_private.gtt_entries) {
1001                 dev_info(&intel_private.pcidev->dev,
1002                          "trying to disable local/stolen memory\n");
1003                 return -EINVAL;
1004         }
1005
1006         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1007                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1008         }
1009         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1010
1011         agp_bridge->driver->tlb_flush(mem);
1012         return 0;
1013 }
1014
1015 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1016 {
1017         if (type == AGP_PHYS_MEMORY)
1018                 return alloc_agpphysmem_i8xx(pg_count, type);
1019         /* always return NULL for other allocation types for now */
1020         return NULL;
1021 }
1022
1023 static int intel_alloc_chipset_flush_resource(void)
1024 {
1025         int ret;
1026         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1027                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1028                                      pcibios_align_resource, agp_bridge->dev);
1029
1030         return ret;
1031 }
1032
1033 static void intel_i915_setup_chipset_flush(void)
1034 {
1035         int ret;
1036         u32 temp;
1037
1038         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1039         if (!(temp & 0x1)) {
1040                 intel_alloc_chipset_flush_resource();
1041                 intel_private.resource_valid = 1;
1042                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1043         } else {
1044                 temp &= ~1;
1045
1046                 intel_private.resource_valid = 1;
1047                 intel_private.ifp_resource.start = temp;
1048                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1049                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1050                 /* some BIOSes reserve this area in a pnp some don't */
1051                 if (ret)
1052                         intel_private.resource_valid = 0;
1053         }
1054 }
1055
1056 static void intel_i965_g33_setup_chipset_flush(void)
1057 {
1058         u32 temp_hi, temp_lo;
1059         int ret;
1060
1061         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1062         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1063
1064         if (!(temp_lo & 0x1)) {
1065
1066                 intel_alloc_chipset_flush_resource();
1067
1068                 intel_private.resource_valid = 1;
1069                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1070                         upper_32_bits(intel_private.ifp_resource.start));
1071                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1072         } else {
1073                 u64 l64;
1074
1075                 temp_lo &= ~0x1;
1076                 l64 = ((u64)temp_hi << 32) | temp_lo;
1077
1078                 intel_private.resource_valid = 1;
1079                 intel_private.ifp_resource.start = l64;
1080                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1081                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1082                 /* some BIOSes reserve this area in a pnp some don't */
1083                 if (ret)
1084                         intel_private.resource_valid = 0;
1085         }
1086 }
1087
1088 static void intel_i9xx_setup_flush(void)
1089 {
1090         /* return if already configured */
1091         if (intel_private.ifp_resource.start)
1092                 return;
1093
1094         /* setup a resource for this object */
1095         intel_private.ifp_resource.name = "Intel Flush Page";
1096         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1097
1098         /* Setup chipset flush for 915 */
1099         if (IS_I965 || IS_G33 || IS_G4X) {
1100                 intel_i965_g33_setup_chipset_flush();
1101         } else {
1102                 intel_i915_setup_chipset_flush();
1103         }
1104
1105         if (intel_private.ifp_resource.start) {
1106                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1107                 if (!intel_private.i9xx_flush_page)
1108                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1109         }
1110 }
1111
1112 static int intel_i915_configure(void)
1113 {
1114         struct aper_size_info_fixed *current_size;
1115         u32 temp;
1116         u16 gmch_ctrl;
1117         int i;
1118
1119         current_size = A_SIZE_FIX(agp_bridge->current_size);
1120
1121         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1122
1123         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1124
1125         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1126         gmch_ctrl |= I830_GMCH_ENABLED;
1127         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1128
1129         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1130         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1131
1132         if (agp_bridge->driver->needs_scratch_page) {
1133                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1134                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1135                 }
1136                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1137         }
1138
1139         global_cache_flush();
1140
1141         intel_i9xx_setup_flush();
1142
1143         return 0;
1144 }
1145
1146 static void intel_i915_cleanup(void)
1147 {
1148         if (intel_private.i9xx_flush_page)
1149                 iounmap(intel_private.i9xx_flush_page);
1150         if (intel_private.resource_valid)
1151                 release_resource(&intel_private.ifp_resource);
1152         intel_private.ifp_resource.start = 0;
1153         intel_private.resource_valid = 0;
1154         iounmap(intel_private.gtt);
1155         iounmap(intel_private.registers);
1156 }
1157
1158 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1159 {
1160         if (intel_private.i9xx_flush_page)
1161                 writel(1, intel_private.i9xx_flush_page);
1162 }
1163
1164 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1165                                      int type)
1166 {
1167         int num_entries;
1168         void *temp;
1169         int ret = -EINVAL;
1170         int mask_type;
1171
1172         if (mem->page_count == 0)
1173                 goto out;
1174
1175         temp = agp_bridge->current_size;
1176         num_entries = A_SIZE_FIX(temp)->num_entries;
1177
1178         if (pg_start < intel_private.gtt_entries) {
1179                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1180                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1181                            pg_start, intel_private.gtt_entries);
1182
1183                 dev_info(&intel_private.pcidev->dev,
1184                          "trying to insert into local/stolen memory\n");
1185                 goto out_err;
1186         }
1187
1188         if ((pg_start + mem->page_count) > num_entries)
1189                 goto out_err;
1190
1191         /* The i915 can't check the GTT for entries since it's read only;
1192          * depend on the caller to make the correct offset decisions.
1193          */
1194
1195         if (type != mem->type)
1196                 goto out_err;
1197
1198         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1199
1200         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1201             mask_type != INTEL_AGP_CACHED_MEMORY)
1202                 goto out_err;
1203
1204         if (!mem->is_flushed)
1205                 global_cache_flush();
1206
1207         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1208         agp_bridge->driver->tlb_flush(mem);
1209
1210  out:
1211         ret = 0;
1212  out_err:
1213         mem->is_flushed = true;
1214         return ret;
1215 }
1216
1217 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1218                                      int type)
1219 {
1220         int i;
1221
1222         if (mem->page_count == 0)
1223                 return 0;
1224
1225         if (pg_start < intel_private.gtt_entries) {
1226                 dev_info(&intel_private.pcidev->dev,
1227                          "trying to disable local/stolen memory\n");
1228                 return -EINVAL;
1229         }
1230
1231         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1232                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1233
1234         readl(intel_private.gtt+i-1);
1235
1236         agp_bridge->driver->tlb_flush(mem);
1237         return 0;
1238 }
1239
1240 /* Return the aperture size by just checking the resource length.  The effect
1241  * described in the spec of the MSAC registers is just changing of the
1242  * resource size.
1243  */
1244 static int intel_i9xx_fetch_size(void)
1245 {
1246         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1247         int aper_size; /* size in megabytes */
1248         int i;
1249
1250         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1251
1252         for (i = 0; i < num_sizes; i++) {
1253                 if (aper_size == intel_i830_sizes[i].size) {
1254                         agp_bridge->current_size = intel_i830_sizes + i;
1255                         agp_bridge->previous_size = agp_bridge->current_size;
1256                         return aper_size;
1257                 }
1258         }
1259
1260         return 0;
1261 }
1262
1263 /* The intel i915 automatically initializes the agp aperture during POST.
1264  * Use the memory already set aside for in the GTT.
1265  */
1266 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1267 {
1268         int page_order;
1269         struct aper_size_info_fixed *size;
1270         int num_entries;
1271         u32 temp, temp2;
1272         int gtt_map_size = 256 * 1024;
1273
1274         size = agp_bridge->current_size;
1275         page_order = size->page_order;
1276         num_entries = size->num_entries;
1277         agp_bridge->gatt_table_real = NULL;
1278
1279         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1280         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1281
1282         if (IS_G33)
1283             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1284         intel_private.gtt = ioremap(temp2, gtt_map_size);
1285         if (!intel_private.gtt)
1286                 return -ENOMEM;
1287
1288         temp &= 0xfff80000;
1289
1290         intel_private.registers = ioremap(temp, 128 * 4096);
1291         if (!intel_private.registers) {
1292                 iounmap(intel_private.gtt);
1293                 return -ENOMEM;
1294         }
1295
1296         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1297         global_cache_flush();   /* FIXME: ? */
1298
1299         /* we have to call this as early as possible after the MMIO base address is known */
1300         intel_i830_init_gtt_entries();
1301
1302         agp_bridge->gatt_table = NULL;
1303
1304         agp_bridge->gatt_bus_addr = temp;
1305
1306         return 0;
1307 }
1308
1309 /*
1310  * The i965 supports 36-bit physical addresses, but to keep
1311  * the format of the GTT the same, the bits that don't fit
1312  * in a 32-bit word are shifted down to bits 4..7.
1313  *
1314  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1315  * is always zero on 32-bit architectures, so no need to make
1316  * this conditional.
1317  */
1318 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1319                                             dma_addr_t addr, int type)
1320 {
1321         /* Shift high bits down */
1322         addr |= (addr >> 28) & 0xf0;
1323
1324         /* Type checking must be done elsewhere */
1325         return addr | bridge->driver->masks[type].mask;
1326 }
1327
1328 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1329 {
1330         switch (agp_bridge->dev->device) {
1331         case PCI_DEVICE_ID_INTEL_GM45_HB:
1332         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1333         case PCI_DEVICE_ID_INTEL_Q45_HB:
1334         case PCI_DEVICE_ID_INTEL_G45_HB:
1335         case PCI_DEVICE_ID_INTEL_G41_HB:
1336         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1337         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1338                 *gtt_offset = *gtt_size = MB(2);
1339                 break;
1340         default:
1341                 *gtt_offset = *gtt_size = KB(512);
1342         }
1343 }
1344
1345 /* The intel i965 automatically initializes the agp aperture during POST.
1346  * Use the memory already set aside for in the GTT.
1347  */
1348 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1349 {
1350         int page_order;
1351         struct aper_size_info_fixed *size;
1352         int num_entries;
1353         u32 temp;
1354         int gtt_offset, gtt_size;
1355
1356         size = agp_bridge->current_size;
1357         page_order = size->page_order;
1358         num_entries = size->num_entries;
1359         agp_bridge->gatt_table_real = NULL;
1360
1361         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1362
1363         temp &= 0xfff00000;
1364
1365         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1366
1367         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1368
1369         if (!intel_private.gtt)
1370                 return -ENOMEM;
1371
1372         intel_private.registers = ioremap(temp, 128 * 4096);
1373         if (!intel_private.registers) {
1374                 iounmap(intel_private.gtt);
1375                 return -ENOMEM;
1376         }
1377
1378         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1379         global_cache_flush();   /* FIXME: ? */
1380
1381         /* we have to call this as early as possible after the MMIO base address is known */
1382         intel_i830_init_gtt_entries();
1383
1384         agp_bridge->gatt_table = NULL;
1385
1386         agp_bridge->gatt_bus_addr = temp;
1387
1388         return 0;
1389 }
1390
1391
1392 static int intel_fetch_size(void)
1393 {
1394         int i;
1395         u16 temp;
1396         struct aper_size_info_16 *values;
1397
1398         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1399         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1400
1401         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1402                 if (temp == values[i].size_value) {
1403                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1404                         agp_bridge->aperture_size_idx = i;
1405                         return values[i].size;
1406                 }
1407         }
1408
1409         return 0;
1410 }
1411
1412 static int __intel_8xx_fetch_size(u8 temp)
1413 {
1414         int i;
1415         struct aper_size_info_8 *values;
1416
1417         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1418
1419         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1420                 if (temp == values[i].size_value) {
1421                         agp_bridge->previous_size =
1422                                 agp_bridge->current_size = (void *) (values + i);
1423                         agp_bridge->aperture_size_idx = i;
1424                         return values[i].size;
1425                 }
1426         }
1427         return 0;
1428 }
1429
1430 static int intel_8xx_fetch_size(void)
1431 {
1432         u8 temp;
1433
1434         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1435         return __intel_8xx_fetch_size(temp);
1436 }
1437
1438 static int intel_815_fetch_size(void)
1439 {
1440         u8 temp;
1441
1442         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1443          * one non-reserved bit, so mask the others out ... */
1444         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1445         temp &= (1 << 3);
1446
1447         return __intel_8xx_fetch_size(temp);
1448 }
1449
1450 static void intel_tlbflush(struct agp_memory *mem)
1451 {
1452         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1453         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1454 }
1455
1456
1457 static void intel_8xx_tlbflush(struct agp_memory *mem)
1458 {
1459         u32 temp;
1460         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1461         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1462         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1463         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1464 }
1465
1466
1467 static void intel_cleanup(void)
1468 {
1469         u16 temp;
1470         struct aper_size_info_16 *previous_size;
1471
1472         previous_size = A_SIZE_16(agp_bridge->previous_size);
1473         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1474         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1475         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1476 }
1477
1478
1479 static void intel_8xx_cleanup(void)
1480 {
1481         u16 temp;
1482         struct aper_size_info_8 *previous_size;
1483
1484         previous_size = A_SIZE_8(agp_bridge->previous_size);
1485         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1486         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1487         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1488 }
1489
1490
1491 static int intel_configure(void)
1492 {
1493         u32 temp;
1494         u16 temp2;
1495         struct aper_size_info_16 *current_size;
1496
1497         current_size = A_SIZE_16(agp_bridge->current_size);
1498
1499         /* aperture size */
1500         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1501
1502         /* address to map to */
1503         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1504         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1505
1506         /* attbase - aperture base */
1507         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1508
1509         /* agpctrl */
1510         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1511
1512         /* paccfg/nbxcfg */
1513         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1514         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1515                         (temp2 & ~(1 << 10)) | (1 << 9));
1516         /* clear any possible error conditions */
1517         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1518         return 0;
1519 }
1520
1521 static int intel_815_configure(void)
1522 {
1523         u32 temp, addr;
1524         u8 temp2;
1525         struct aper_size_info_8 *current_size;
1526
1527         /* attbase - aperture base */
1528         /* the Intel 815 chipset spec. says that bits 29-31 in the
1529         * ATTBASE register are reserved -> try not to write them */
1530         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1531                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1532                 return -EINVAL;
1533         }
1534
1535         current_size = A_SIZE_8(agp_bridge->current_size);
1536
1537         /* aperture size */
1538         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1539                         current_size->size_value);
1540
1541         /* address to map to */
1542         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1543         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1544
1545         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1546         addr &= INTEL_815_ATTBASE_MASK;
1547         addr |= agp_bridge->gatt_bus_addr;
1548         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1549
1550         /* agpctrl */
1551         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1552
1553         /* apcont */
1554         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1555         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1556
1557         /* clear any possible error conditions */
1558         /* Oddness : this chipset seems to have no ERRSTS register ! */
1559         return 0;
1560 }
1561
1562 static void intel_820_tlbflush(struct agp_memory *mem)
1563 {
1564         return;
1565 }
1566
1567 static void intel_820_cleanup(void)
1568 {
1569         u8 temp;
1570         struct aper_size_info_8 *previous_size;
1571
1572         previous_size = A_SIZE_8(agp_bridge->previous_size);
1573         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1574         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1575                         temp & ~(1 << 1));
1576         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1577                         previous_size->size_value);
1578 }
1579
1580
1581 static int intel_820_configure(void)
1582 {
1583         u32 temp;
1584         u8 temp2;
1585         struct aper_size_info_8 *current_size;
1586
1587         current_size = A_SIZE_8(agp_bridge->current_size);
1588
1589         /* aperture size */
1590         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1591
1592         /* address to map to */
1593         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1594         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1595
1596         /* attbase - aperture base */
1597         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1598
1599         /* agpctrl */
1600         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1601
1602         /* global enable aperture access */
1603         /* This flag is not accessed through MCHCFG register as in */
1604         /* i850 chipset. */
1605         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1606         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1607         /* clear any possible AGP-related error conditions */
1608         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1609         return 0;
1610 }
1611
1612 static int intel_840_configure(void)
1613 {
1614         u32 temp;
1615         u16 temp2;
1616         struct aper_size_info_8 *current_size;
1617
1618         current_size = A_SIZE_8(agp_bridge->current_size);
1619
1620         /* aperture size */
1621         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1622
1623         /* address to map to */
1624         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1625         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1626
1627         /* attbase - aperture base */
1628         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1629
1630         /* agpctrl */
1631         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1632
1633         /* mcgcfg */
1634         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1635         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1636         /* clear any possible error conditions */
1637         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1638         return 0;
1639 }
1640
1641 static int intel_845_configure(void)
1642 {
1643         u32 temp;
1644         u8 temp2;
1645         struct aper_size_info_8 *current_size;
1646
1647         current_size = A_SIZE_8(agp_bridge->current_size);
1648
1649         /* aperture size */
1650         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1651
1652         if (agp_bridge->apbase_config != 0) {
1653                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1654                                        agp_bridge->apbase_config);
1655         } else {
1656                 /* address to map to */
1657                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1658                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1659                 agp_bridge->apbase_config = temp;
1660         }
1661
1662         /* attbase - aperture base */
1663         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1664
1665         /* agpctrl */
1666         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1667
1668         /* agpm */
1669         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1670         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1671         /* clear any possible error conditions */
1672         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1673
1674         intel_i830_setup_flush();
1675         return 0;
1676 }
1677
1678 static int intel_850_configure(void)
1679 {
1680         u32 temp;
1681         u16 temp2;
1682         struct aper_size_info_8 *current_size;
1683
1684         current_size = A_SIZE_8(agp_bridge->current_size);
1685
1686         /* aperture size */
1687         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1688
1689         /* address to map to */
1690         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1691         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1692
1693         /* attbase - aperture base */
1694         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1695
1696         /* agpctrl */
1697         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1698
1699         /* mcgcfg */
1700         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1701         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1702         /* clear any possible AGP-related error conditions */
1703         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1704         return 0;
1705 }
1706
1707 static int intel_860_configure(void)
1708 {
1709         u32 temp;
1710         u16 temp2;
1711         struct aper_size_info_8 *current_size;
1712
1713         current_size = A_SIZE_8(agp_bridge->current_size);
1714
1715         /* aperture size */
1716         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1717
1718         /* address to map to */
1719         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1720         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1721
1722         /* attbase - aperture base */
1723         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1724
1725         /* agpctrl */
1726         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1727
1728         /* mcgcfg */
1729         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1730         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1731         /* clear any possible AGP-related error conditions */
1732         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1733         return 0;
1734 }
1735
1736 static int intel_830mp_configure(void)
1737 {
1738         u32 temp;
1739         u16 temp2;
1740         struct aper_size_info_8 *current_size;
1741
1742         current_size = A_SIZE_8(agp_bridge->current_size);
1743
1744         /* aperture size */
1745         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1746
1747         /* address to map to */
1748         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1749         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1750
1751         /* attbase - aperture base */
1752         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1753
1754         /* agpctrl */
1755         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1756
1757         /* gmch */
1758         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1759         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1760         /* clear any possible AGP-related error conditions */
1761         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1762         return 0;
1763 }
1764
1765 static int intel_7505_configure(void)
1766 {
1767         u32 temp;
1768         u16 temp2;
1769         struct aper_size_info_8 *current_size;
1770
1771         current_size = A_SIZE_8(agp_bridge->current_size);
1772
1773         /* aperture size */
1774         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1775
1776         /* address to map to */
1777         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1778         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1779
1780         /* attbase - aperture base */
1781         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1782
1783         /* agpctrl */
1784         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1785
1786         /* mchcfg */
1787         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1788         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1789
1790         return 0;
1791 }
1792
1793 /* Setup function */
1794 static const struct gatt_mask intel_generic_masks[] =
1795 {
1796         {.mask = 0x00000017, .type = 0}
1797 };
1798
1799 static const struct aper_size_info_8 intel_815_sizes[2] =
1800 {
1801         {64, 16384, 4, 0},
1802         {32, 8192, 3, 8},
1803 };
1804
1805 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1806 {
1807         {256, 65536, 6, 0},
1808         {128, 32768, 5, 32},
1809         {64, 16384, 4, 48},
1810         {32, 8192, 3, 56},
1811         {16, 4096, 2, 60},
1812         {8, 2048, 1, 62},
1813         {4, 1024, 0, 63}
1814 };
1815
1816 static const struct aper_size_info_16 intel_generic_sizes[7] =
1817 {
1818         {256, 65536, 6, 0},
1819         {128, 32768, 5, 32},
1820         {64, 16384, 4, 48},
1821         {32, 8192, 3, 56},
1822         {16, 4096, 2, 60},
1823         {8, 2048, 1, 62},
1824         {4, 1024, 0, 63}
1825 };
1826
1827 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1828 {
1829         {256, 65536, 6, 0},
1830         {128, 32768, 5, 32},
1831         {64, 16384, 4, 48},
1832         {32, 8192, 3, 56}
1833 };
1834
1835 static const struct agp_bridge_driver intel_generic_driver = {
1836         .owner                  = THIS_MODULE,
1837         .aperture_sizes         = intel_generic_sizes,
1838         .size_type              = U16_APER_SIZE,
1839         .num_aperture_sizes     = 7,
1840         .configure              = intel_configure,
1841         .fetch_size             = intel_fetch_size,
1842         .cleanup                = intel_cleanup,
1843         .tlb_flush              = intel_tlbflush,
1844         .mask_memory            = agp_generic_mask_memory,
1845         .masks                  = intel_generic_masks,
1846         .agp_enable             = agp_generic_enable,
1847         .cache_flush            = global_cache_flush,
1848         .create_gatt_table      = agp_generic_create_gatt_table,
1849         .free_gatt_table        = agp_generic_free_gatt_table,
1850         .insert_memory          = agp_generic_insert_memory,
1851         .remove_memory          = agp_generic_remove_memory,
1852         .alloc_by_type          = agp_generic_alloc_by_type,
1853         .free_by_type           = agp_generic_free_by_type,
1854         .agp_alloc_page         = agp_generic_alloc_page,
1855         .agp_alloc_pages        = agp_generic_alloc_pages,
1856         .agp_destroy_page       = agp_generic_destroy_page,
1857         .agp_destroy_pages      = agp_generic_destroy_pages,
1858         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1859 };
1860
1861 static const struct agp_bridge_driver intel_810_driver = {
1862         .owner                  = THIS_MODULE,
1863         .aperture_sizes         = intel_i810_sizes,
1864         .size_type              = FIXED_APER_SIZE,
1865         .num_aperture_sizes     = 2,
1866         .needs_scratch_page     = true,
1867         .configure              = intel_i810_configure,
1868         .fetch_size             = intel_i810_fetch_size,
1869         .cleanup                = intel_i810_cleanup,
1870         .tlb_flush              = intel_i810_tlbflush,
1871         .mask_memory            = intel_i810_mask_memory,
1872         .masks                  = intel_i810_masks,
1873         .agp_enable             = intel_i810_agp_enable,
1874         .cache_flush            = global_cache_flush,
1875         .create_gatt_table      = agp_generic_create_gatt_table,
1876         .free_gatt_table        = agp_generic_free_gatt_table,
1877         .insert_memory          = intel_i810_insert_entries,
1878         .remove_memory          = intel_i810_remove_entries,
1879         .alloc_by_type          = intel_i810_alloc_by_type,
1880         .free_by_type           = intel_i810_free_by_type,
1881         .agp_alloc_page         = agp_generic_alloc_page,
1882         .agp_alloc_pages        = agp_generic_alloc_pages,
1883         .agp_destroy_page       = agp_generic_destroy_page,
1884         .agp_destroy_pages      = agp_generic_destroy_pages,
1885         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1886 };
1887
1888 static const struct agp_bridge_driver intel_815_driver = {
1889         .owner                  = THIS_MODULE,
1890         .aperture_sizes         = intel_815_sizes,
1891         .size_type              = U8_APER_SIZE,
1892         .num_aperture_sizes     = 2,
1893         .configure              = intel_815_configure,
1894         .fetch_size             = intel_815_fetch_size,
1895         .cleanup                = intel_8xx_cleanup,
1896         .tlb_flush              = intel_8xx_tlbflush,
1897         .mask_memory            = agp_generic_mask_memory,
1898         .masks                  = intel_generic_masks,
1899         .agp_enable             = agp_generic_enable,
1900         .cache_flush            = global_cache_flush,
1901         .create_gatt_table      = agp_generic_create_gatt_table,
1902         .free_gatt_table        = agp_generic_free_gatt_table,
1903         .insert_memory          = agp_generic_insert_memory,
1904         .remove_memory          = agp_generic_remove_memory,
1905         .alloc_by_type          = agp_generic_alloc_by_type,
1906         .free_by_type           = agp_generic_free_by_type,
1907         .agp_alloc_page         = agp_generic_alloc_page,
1908         .agp_alloc_pages        = agp_generic_alloc_pages,
1909         .agp_destroy_page       = agp_generic_destroy_page,
1910         .agp_destroy_pages      = agp_generic_destroy_pages,
1911         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1912 };
1913
1914 static const struct agp_bridge_driver intel_830_driver = {
1915         .owner                  = THIS_MODULE,
1916         .aperture_sizes         = intel_i830_sizes,
1917         .size_type              = FIXED_APER_SIZE,
1918         .num_aperture_sizes     = 4,
1919         .needs_scratch_page     = true,
1920         .configure              = intel_i830_configure,
1921         .fetch_size             = intel_i830_fetch_size,
1922         .cleanup                = intel_i830_cleanup,
1923         .tlb_flush              = intel_i810_tlbflush,
1924         .mask_memory            = intel_i810_mask_memory,
1925         .masks                  = intel_i810_masks,
1926         .agp_enable             = intel_i810_agp_enable,
1927         .cache_flush            = global_cache_flush,
1928         .create_gatt_table      = intel_i830_create_gatt_table,
1929         .free_gatt_table        = intel_i830_free_gatt_table,
1930         .insert_memory          = intel_i830_insert_entries,
1931         .remove_memory          = intel_i830_remove_entries,
1932         .alloc_by_type          = intel_i830_alloc_by_type,
1933         .free_by_type           = intel_i810_free_by_type,
1934         .agp_alloc_page         = agp_generic_alloc_page,
1935         .agp_alloc_pages        = agp_generic_alloc_pages,
1936         .agp_destroy_page       = agp_generic_destroy_page,
1937         .agp_destroy_pages      = agp_generic_destroy_pages,
1938         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1939         .chipset_flush          = intel_i830_chipset_flush,
1940 };
1941
1942 static const struct agp_bridge_driver intel_820_driver = {
1943         .owner                  = THIS_MODULE,
1944         .aperture_sizes         = intel_8xx_sizes,
1945         .size_type              = U8_APER_SIZE,
1946         .num_aperture_sizes     = 7,
1947         .configure              = intel_820_configure,
1948         .fetch_size             = intel_8xx_fetch_size,
1949         .cleanup                = intel_820_cleanup,
1950         .tlb_flush              = intel_820_tlbflush,
1951         .mask_memory            = agp_generic_mask_memory,
1952         .masks                  = intel_generic_masks,
1953         .agp_enable             = agp_generic_enable,
1954         .cache_flush            = global_cache_flush,
1955         .create_gatt_table      = agp_generic_create_gatt_table,
1956         .free_gatt_table        = agp_generic_free_gatt_table,
1957         .insert_memory          = agp_generic_insert_memory,
1958         .remove_memory          = agp_generic_remove_memory,
1959         .alloc_by_type          = agp_generic_alloc_by_type,
1960         .free_by_type           = agp_generic_free_by_type,
1961         .agp_alloc_page         = agp_generic_alloc_page,
1962         .agp_alloc_pages        = agp_generic_alloc_pages,
1963         .agp_destroy_page       = agp_generic_destroy_page,
1964         .agp_destroy_pages      = agp_generic_destroy_pages,
1965         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1966 };
1967
1968 static const struct agp_bridge_driver intel_830mp_driver = {
1969         .owner                  = THIS_MODULE,
1970         .aperture_sizes         = intel_830mp_sizes,
1971         .size_type              = U8_APER_SIZE,
1972         .num_aperture_sizes     = 4,
1973         .configure              = intel_830mp_configure,
1974         .fetch_size             = intel_8xx_fetch_size,
1975         .cleanup                = intel_8xx_cleanup,
1976         .tlb_flush              = intel_8xx_tlbflush,
1977         .mask_memory            = agp_generic_mask_memory,
1978         .masks                  = intel_generic_masks,
1979         .agp_enable             = agp_generic_enable,
1980         .cache_flush            = global_cache_flush,
1981         .create_gatt_table      = agp_generic_create_gatt_table,
1982         .free_gatt_table        = agp_generic_free_gatt_table,
1983         .insert_memory          = agp_generic_insert_memory,
1984         .remove_memory          = agp_generic_remove_memory,
1985         .alloc_by_type          = agp_generic_alloc_by_type,
1986         .free_by_type           = agp_generic_free_by_type,
1987         .agp_alloc_page         = agp_generic_alloc_page,
1988         .agp_alloc_pages        = agp_generic_alloc_pages,
1989         .agp_destroy_page       = agp_generic_destroy_page,
1990         .agp_destroy_pages      = agp_generic_destroy_pages,
1991         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1992 };
1993
1994 static const struct agp_bridge_driver intel_840_driver = {
1995         .owner                  = THIS_MODULE,
1996         .aperture_sizes         = intel_8xx_sizes,
1997         .size_type              = U8_APER_SIZE,
1998         .num_aperture_sizes     = 7,
1999         .configure              = intel_840_configure,
2000         .fetch_size             = intel_8xx_fetch_size,
2001         .cleanup                = intel_8xx_cleanup,
2002         .tlb_flush              = intel_8xx_tlbflush,
2003         .mask_memory            = agp_generic_mask_memory,
2004         .masks                  = intel_generic_masks,
2005         .agp_enable             = agp_generic_enable,
2006         .cache_flush            = global_cache_flush,
2007         .create_gatt_table      = agp_generic_create_gatt_table,
2008         .free_gatt_table        = agp_generic_free_gatt_table,
2009         .insert_memory          = agp_generic_insert_memory,
2010         .remove_memory          = agp_generic_remove_memory,
2011         .alloc_by_type          = agp_generic_alloc_by_type,
2012         .free_by_type           = agp_generic_free_by_type,
2013         .agp_alloc_page         = agp_generic_alloc_page,
2014         .agp_alloc_pages        = agp_generic_alloc_pages,
2015         .agp_destroy_page       = agp_generic_destroy_page,
2016         .agp_destroy_pages      = agp_generic_destroy_pages,
2017         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2018 };
2019
2020 static const struct agp_bridge_driver intel_845_driver = {
2021         .owner                  = THIS_MODULE,
2022         .aperture_sizes         = intel_8xx_sizes,
2023         .size_type              = U8_APER_SIZE,
2024         .num_aperture_sizes     = 7,
2025         .configure              = intel_845_configure,
2026         .fetch_size             = intel_8xx_fetch_size,
2027         .cleanup                = intel_8xx_cleanup,
2028         .tlb_flush              = intel_8xx_tlbflush,
2029         .mask_memory            = agp_generic_mask_memory,
2030         .masks                  = intel_generic_masks,
2031         .agp_enable             = agp_generic_enable,
2032         .cache_flush            = global_cache_flush,
2033         .create_gatt_table      = agp_generic_create_gatt_table,
2034         .free_gatt_table        = agp_generic_free_gatt_table,
2035         .insert_memory          = agp_generic_insert_memory,
2036         .remove_memory          = agp_generic_remove_memory,
2037         .alloc_by_type          = agp_generic_alloc_by_type,
2038         .free_by_type           = agp_generic_free_by_type,
2039         .agp_alloc_page         = agp_generic_alloc_page,
2040         .agp_alloc_pages        = agp_generic_alloc_pages,
2041         .agp_destroy_page       = agp_generic_destroy_page,
2042         .agp_destroy_pages      = agp_generic_destroy_pages,
2043         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2044         .chipset_flush          = intel_i830_chipset_flush,
2045 };
2046
2047 static const struct agp_bridge_driver intel_850_driver = {
2048         .owner                  = THIS_MODULE,
2049         .aperture_sizes         = intel_8xx_sizes,
2050         .size_type              = U8_APER_SIZE,
2051         .num_aperture_sizes     = 7,
2052         .configure              = intel_850_configure,
2053         .fetch_size             = intel_8xx_fetch_size,
2054         .cleanup                = intel_8xx_cleanup,
2055         .tlb_flush              = intel_8xx_tlbflush,
2056         .mask_memory            = agp_generic_mask_memory,
2057         .masks                  = intel_generic_masks,
2058         .agp_enable             = agp_generic_enable,
2059         .cache_flush            = global_cache_flush,
2060         .create_gatt_table      = agp_generic_create_gatt_table,
2061         .free_gatt_table        = agp_generic_free_gatt_table,
2062         .insert_memory          = agp_generic_insert_memory,
2063         .remove_memory          = agp_generic_remove_memory,
2064         .alloc_by_type          = agp_generic_alloc_by_type,
2065         .free_by_type           = agp_generic_free_by_type,
2066         .agp_alloc_page         = agp_generic_alloc_page,
2067         .agp_alloc_pages        = agp_generic_alloc_pages,
2068         .agp_destroy_page       = agp_generic_destroy_page,
2069         .agp_destroy_pages      = agp_generic_destroy_pages,
2070         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2071 };
2072
2073 static const struct agp_bridge_driver intel_860_driver = {
2074         .owner                  = THIS_MODULE,
2075         .aperture_sizes         = intel_8xx_sizes,
2076         .size_type              = U8_APER_SIZE,
2077         .num_aperture_sizes     = 7,
2078         .configure              = intel_860_configure,
2079         .fetch_size             = intel_8xx_fetch_size,
2080         .cleanup                = intel_8xx_cleanup,
2081         .tlb_flush              = intel_8xx_tlbflush,
2082         .mask_memory            = agp_generic_mask_memory,
2083         .masks                  = intel_generic_masks,
2084         .agp_enable             = agp_generic_enable,
2085         .cache_flush            = global_cache_flush,
2086         .create_gatt_table      = agp_generic_create_gatt_table,
2087         .free_gatt_table        = agp_generic_free_gatt_table,
2088         .insert_memory          = agp_generic_insert_memory,
2089         .remove_memory          = agp_generic_remove_memory,
2090         .alloc_by_type          = agp_generic_alloc_by_type,
2091         .free_by_type           = agp_generic_free_by_type,
2092         .agp_alloc_page         = agp_generic_alloc_page,
2093         .agp_alloc_pages        = agp_generic_alloc_pages,
2094         .agp_destroy_page       = agp_generic_destroy_page,
2095         .agp_destroy_pages      = agp_generic_destroy_pages,
2096         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2097 };
2098
2099 static const struct agp_bridge_driver intel_915_driver = {
2100         .owner                  = THIS_MODULE,
2101         .aperture_sizes         = intel_i830_sizes,
2102         .size_type              = FIXED_APER_SIZE,
2103         .num_aperture_sizes     = 4,
2104         .needs_scratch_page     = true,
2105         .configure              = intel_i915_configure,
2106         .fetch_size             = intel_i9xx_fetch_size,
2107         .cleanup                = intel_i915_cleanup,
2108         .tlb_flush              = intel_i810_tlbflush,
2109         .mask_memory            = intel_i810_mask_memory,
2110         .masks                  = intel_i810_masks,
2111         .agp_enable             = intel_i810_agp_enable,
2112         .cache_flush            = global_cache_flush,
2113         .create_gatt_table      = intel_i915_create_gatt_table,
2114         .free_gatt_table        = intel_i830_free_gatt_table,
2115         .insert_memory          = intel_i915_insert_entries,
2116         .remove_memory          = intel_i915_remove_entries,
2117         .alloc_by_type          = intel_i830_alloc_by_type,
2118         .free_by_type           = intel_i810_free_by_type,
2119         .agp_alloc_page         = agp_generic_alloc_page,
2120         .agp_alloc_pages        = agp_generic_alloc_pages,
2121         .agp_destroy_page       = agp_generic_destroy_page,
2122         .agp_destroy_pages      = agp_generic_destroy_pages,
2123         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2124         .chipset_flush          = intel_i915_chipset_flush,
2125 #ifdef USE_PCI_DMA_API
2126         .agp_map_page           = intel_agp_map_page,
2127         .agp_unmap_page         = intel_agp_unmap_page,
2128         .agp_map_memory         = intel_agp_map_memory,
2129         .agp_unmap_memory       = intel_agp_unmap_memory,
2130 #endif
2131 };
2132
2133 static const struct agp_bridge_driver intel_i965_driver = {
2134         .owner                  = THIS_MODULE,
2135         .aperture_sizes         = intel_i830_sizes,
2136         .size_type              = FIXED_APER_SIZE,
2137         .num_aperture_sizes     = 4,
2138         .needs_scratch_page     = true,
2139         .configure              = intel_i915_configure,
2140         .fetch_size             = intel_i9xx_fetch_size,
2141         .cleanup                = intel_i915_cleanup,
2142         .tlb_flush              = intel_i810_tlbflush,
2143         .mask_memory            = intel_i965_mask_memory,
2144         .masks                  = intel_i810_masks,
2145         .agp_enable             = intel_i810_agp_enable,
2146         .cache_flush            = global_cache_flush,
2147         .create_gatt_table      = intel_i965_create_gatt_table,
2148         .free_gatt_table        = intel_i830_free_gatt_table,
2149         .insert_memory          = intel_i915_insert_entries,
2150         .remove_memory          = intel_i915_remove_entries,
2151         .alloc_by_type          = intel_i830_alloc_by_type,
2152         .free_by_type           = intel_i810_free_by_type,
2153         .agp_alloc_page         = agp_generic_alloc_page,
2154         .agp_alloc_pages        = agp_generic_alloc_pages,
2155         .agp_destroy_page       = agp_generic_destroy_page,
2156         .agp_destroy_pages      = agp_generic_destroy_pages,
2157         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2158         .chipset_flush          = intel_i915_chipset_flush,
2159 #ifdef USE_PCI_DMA_API
2160         .agp_map_page           = intel_agp_map_page,
2161         .agp_unmap_page         = intel_agp_unmap_page,
2162         .agp_map_memory         = intel_agp_map_memory,
2163         .agp_unmap_memory       = intel_agp_unmap_memory,
2164 #endif
2165 };
2166
2167 static const struct agp_bridge_driver intel_7505_driver = {
2168         .owner                  = THIS_MODULE,
2169         .aperture_sizes         = intel_8xx_sizes,
2170         .size_type              = U8_APER_SIZE,
2171         .num_aperture_sizes     = 7,
2172         .configure              = intel_7505_configure,
2173         .fetch_size             = intel_8xx_fetch_size,
2174         .cleanup                = intel_8xx_cleanup,
2175         .tlb_flush              = intel_8xx_tlbflush,
2176         .mask_memory            = agp_generic_mask_memory,
2177         .masks                  = intel_generic_masks,
2178         .agp_enable             = agp_generic_enable,
2179         .cache_flush            = global_cache_flush,
2180         .create_gatt_table      = agp_generic_create_gatt_table,
2181         .free_gatt_table        = agp_generic_free_gatt_table,
2182         .insert_memory          = agp_generic_insert_memory,
2183         .remove_memory          = agp_generic_remove_memory,
2184         .alloc_by_type          = agp_generic_alloc_by_type,
2185         .free_by_type           = agp_generic_free_by_type,
2186         .agp_alloc_page         = agp_generic_alloc_page,
2187         .agp_alloc_pages        = agp_generic_alloc_pages,
2188         .agp_destroy_page       = agp_generic_destroy_page,
2189         .agp_destroy_pages      = agp_generic_destroy_pages,
2190         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2191 };
2192
2193 static const struct agp_bridge_driver intel_g33_driver = {
2194         .owner                  = THIS_MODULE,
2195         .aperture_sizes         = intel_i830_sizes,
2196         .size_type              = FIXED_APER_SIZE,
2197         .num_aperture_sizes     = 4,
2198         .needs_scratch_page     = true,
2199         .configure              = intel_i915_configure,
2200         .fetch_size             = intel_i9xx_fetch_size,
2201         .cleanup                = intel_i915_cleanup,
2202         .tlb_flush              = intel_i810_tlbflush,
2203         .mask_memory            = intel_i965_mask_memory,
2204         .masks                  = intel_i810_masks,
2205         .agp_enable             = intel_i810_agp_enable,
2206         .cache_flush            = global_cache_flush,
2207         .create_gatt_table      = intel_i915_create_gatt_table,
2208         .free_gatt_table        = intel_i830_free_gatt_table,
2209         .insert_memory          = intel_i915_insert_entries,
2210         .remove_memory          = intel_i915_remove_entries,
2211         .alloc_by_type          = intel_i830_alloc_by_type,
2212         .free_by_type           = intel_i810_free_by_type,
2213         .agp_alloc_page         = agp_generic_alloc_page,
2214         .agp_alloc_pages        = agp_generic_alloc_pages,
2215         .agp_destroy_page       = agp_generic_destroy_page,
2216         .agp_destroy_pages      = agp_generic_destroy_pages,
2217         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2218         .chipset_flush          = intel_i915_chipset_flush,
2219 #ifdef USE_PCI_DMA_API
2220         .agp_map_page           = intel_agp_map_page,
2221         .agp_unmap_page         = intel_agp_unmap_page,
2222         .agp_map_memory         = intel_agp_map_memory,
2223         .agp_unmap_memory       = intel_agp_unmap_memory,
2224 #endif
2225 };
2226
2227 static int find_gmch(u16 device)
2228 {
2229         struct pci_dev *gmch_device;
2230
2231         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2232         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2233                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2234                                              device, gmch_device);
2235         }
2236
2237         if (!gmch_device)
2238                 return 0;
2239
2240         intel_private.pcidev = gmch_device;
2241         return 1;
2242 }
2243
2244 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2245  * driver and gmch_driver must be non-null, and find_gmch will determine
2246  * which one should be used if a gmch_chip_id is present.
2247  */
2248 static const struct intel_driver_description {
2249         unsigned int chip_id;
2250         unsigned int gmch_chip_id;
2251         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2252         char *name;
2253         const struct agp_bridge_driver *driver;
2254         const struct agp_bridge_driver *gmch_driver;
2255 } intel_agp_chipsets[] = {
2256         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2257         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2258         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2259         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2260                 NULL, &intel_810_driver },
2261         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2262                 NULL, &intel_810_driver },
2263         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2264                 NULL, &intel_810_driver },
2265         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2266                 &intel_815_driver, &intel_810_driver },
2267         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2268         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2269         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2270                 &intel_830mp_driver, &intel_830_driver },
2271         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2272         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2273         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2274                 &intel_845_driver, &intel_830_driver },
2275         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2276         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2277                 &intel_845_driver, &intel_830_driver },
2278         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2279         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2280                 &intel_845_driver, &intel_830_driver },
2281         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2282         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2283                 &intel_845_driver, &intel_830_driver },
2284         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2285         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2286                 NULL, &intel_915_driver },
2287         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2288                 NULL, &intel_915_driver },
2289         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2290                 NULL, &intel_915_driver },
2291         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2292                 NULL, &intel_915_driver },
2293         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2294                 NULL, &intel_915_driver },
2295         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2296                 NULL, &intel_915_driver },
2297         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2298                 NULL, &intel_i965_driver },
2299         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2300                 NULL, &intel_i965_driver },
2301         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2302                 NULL, &intel_i965_driver },
2303         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2304                 NULL, &intel_i965_driver },
2305         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2306                 NULL, &intel_i965_driver },
2307         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2308                 NULL, &intel_i965_driver },
2309         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2310         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2311         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2312                 NULL, &intel_g33_driver },
2313         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2314                 NULL, &intel_g33_driver },
2315         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2316                 NULL, &intel_g33_driver },
2317         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2318                 NULL, &intel_g33_driver },
2319         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2320                 NULL, &intel_g33_driver },
2321         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2322             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2323         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2324             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2325         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2326             "Q45/Q43", NULL, &intel_i965_driver },
2327         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2328             "G45/G43", NULL, &intel_i965_driver },
2329         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2330             "G41", NULL, &intel_i965_driver },
2331         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2332             "IGDNG/D", NULL, &intel_i965_driver },
2333         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2334             "IGDNG/M", NULL, &intel_i965_driver },
2335         { 0, 0, 0, NULL, NULL, NULL }
2336 };
2337
2338 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2339                                      const struct pci_device_id *ent)
2340 {
2341         struct agp_bridge_data *bridge;
2342         u8 cap_ptr = 0;
2343         struct resource *r;
2344         int i;
2345
2346         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2347
2348         bridge = agp_alloc_bridge();
2349         if (!bridge)
2350                 return -ENOMEM;
2351
2352         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2353                 /* In case that multiple models of gfx chip may
2354                    stand on same host bridge type, this can be
2355                    sure we detect the right IGD. */
2356                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2357                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2358                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2359                                 bridge->driver =
2360                                         intel_agp_chipsets[i].gmch_driver;
2361                                 break;
2362                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2363                                 continue;
2364                         } else {
2365                                 bridge->driver = intel_agp_chipsets[i].driver;
2366                                 break;
2367                         }
2368                 }
2369         }
2370
2371         if (intel_agp_chipsets[i].name == NULL) {
2372                 if (cap_ptr)
2373                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2374                                  pdev->vendor, pdev->device);
2375                 agp_put_bridge(bridge);
2376                 return -ENODEV;
2377         }
2378
2379         if (bridge->driver == NULL) {
2380                 /* bridge has no AGP and no IGD detected */
2381                 if (cap_ptr)
2382                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2383                                  intel_agp_chipsets[i].gmch_chip_id);
2384                 agp_put_bridge(bridge);
2385                 return -ENODEV;
2386         }
2387
2388         bridge->dev = pdev;
2389         bridge->capndx = cap_ptr;
2390         bridge->dev_private_data = &intel_private;
2391
2392         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2393
2394         /*
2395         * The following fixes the case where the BIOS has "forgotten" to
2396         * provide an address range for the GART.
2397         * 20030610 - hamish@zot.org
2398         */
2399         r = &pdev->resource[0];
2400         if (!r->start && r->end) {
2401                 if (pci_assign_resource(pdev, 0)) {
2402                         dev_err(&pdev->dev, "can't assign resource 0\n");
2403                         agp_put_bridge(bridge);
2404                         return -ENODEV;
2405                 }
2406         }
2407
2408         /*
2409         * If the device has not been properly setup, the following will catch
2410         * the problem and should stop the system from crashing.
2411         * 20030610 - hamish@zot.org
2412         */
2413         if (pci_enable_device(pdev)) {
2414                 dev_err(&pdev->dev, "can't enable PCI device\n");
2415                 agp_put_bridge(bridge);
2416                 return -ENODEV;
2417         }
2418
2419         /* Fill in the mode register */
2420         if (cap_ptr) {
2421                 pci_read_config_dword(pdev,
2422                                 bridge->capndx+PCI_AGP_STATUS,
2423                                 &bridge->mode);
2424         }
2425
2426         pci_set_drvdata(pdev, bridge);
2427         return agp_add_bridge(bridge);
2428 }
2429
2430 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2431 {
2432         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2433
2434         agp_remove_bridge(bridge);
2435
2436         if (intel_private.pcidev)
2437                 pci_dev_put(intel_private.pcidev);
2438
2439         agp_put_bridge(bridge);
2440 }
2441
2442 #ifdef CONFIG_PM
2443 static int agp_intel_resume(struct pci_dev *pdev)
2444 {
2445         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2446         int ret_val;
2447
2448         pci_restore_state(pdev);
2449
2450         /* We should restore our graphics device's config space,
2451          * as host bridge (00:00) resumes before graphics device (02:00),
2452          * then our access to its pci space can work right.
2453          */
2454         if (intel_private.pcidev)
2455                 pci_restore_state(intel_private.pcidev);
2456
2457         if (bridge->driver == &intel_generic_driver)
2458                 intel_configure();
2459         else if (bridge->driver == &intel_850_driver)
2460                 intel_850_configure();
2461         else if (bridge->driver == &intel_845_driver)
2462                 intel_845_configure();
2463         else if (bridge->driver == &intel_830mp_driver)
2464                 intel_830mp_configure();
2465         else if (bridge->driver == &intel_915_driver)
2466                 intel_i915_configure();
2467         else if (bridge->driver == &intel_830_driver)
2468                 intel_i830_configure();
2469         else if (bridge->driver == &intel_810_driver)
2470                 intel_i810_configure();
2471         else if (bridge->driver == &intel_i965_driver)
2472                 intel_i915_configure();
2473
2474         ret_val = agp_rebind_memory();
2475         if (ret_val != 0)
2476                 return ret_val;
2477
2478         return 0;
2479 }
2480 #endif
2481
2482 static struct pci_device_id agp_intel_pci_table[] = {
2483 #define ID(x)                                           \
2484         {                                               \
2485         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2486         .class_mask     = ~0,                           \
2487         .vendor         = PCI_VENDOR_ID_INTEL,          \
2488         .device         = x,                            \
2489         .subvendor      = PCI_ANY_ID,                   \
2490         .subdevice      = PCI_ANY_ID,                   \
2491         }
2492         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2493         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2494         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2495         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2496         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2497         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2498         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2499         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2500         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2501         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2502         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2503         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2504         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2505         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2506         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2507         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2508         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2509         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2510         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2511         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2512         ID(PCI_DEVICE_ID_INTEL_7505_0),
2513         ID(PCI_DEVICE_ID_INTEL_7205_0),
2514         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2515         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2516         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2517         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2518         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2519         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2520         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2521         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2522         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2523         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2524         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2525         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2526         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2527         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2528         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2529         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2530         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2531         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2532         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2533         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2534         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2535         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2536         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2537         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2538         { }
2539 };
2540
2541 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2542
2543 static struct pci_driver agp_intel_pci_driver = {
2544         .name           = "agpgart-intel",
2545         .id_table       = agp_intel_pci_table,
2546         .probe          = agp_intel_probe,
2547         .remove         = __devexit_p(agp_intel_remove),
2548 #ifdef CONFIG_PM
2549         .resume         = agp_intel_resume,
2550 #endif
2551 };
2552
2553 static int __init agp_intel_init(void)
2554 {
2555         if (agp_off)
2556                 return -EINVAL;
2557         return pci_register_driver(&agp_intel_pci_driver);
2558 }
2559
2560 static void __exit agp_intel_cleanup(void)
2561 {
2562         pci_unregister_driver(&agp_intel_pci_driver);
2563 }
2564
2565 module_init(agp_intel_init);
2566 module_exit(agp_intel_cleanup);
2567
2568 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2569 MODULE_LICENSE("GPL and additional rights");