2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> Develop a low-power-consumption strategy, and implement it.
36 * --> [Experiment, low priority] Investigate interrupt coalescing.
37 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
38 * the overhead reduced by interrupt mitigation is quite often not
39 * worth the latency cost.
41 * --> [Experiment, Marvell value added] Is it possible to use target
42 * mode to cross-connect two Linux boxes with Marvell cards? If so,
43 * creating LibATA target mode support would be very interesting.
45 * Target mode, for those without docs, is the ability to directly
46 * connect two SATA ports.
49 #include <linux/kernel.h>
50 #include <linux/module.h>
51 #include <linux/pci.h>
52 #include <linux/init.h>
53 #include <linux/blkdev.h>
54 #include <linux/delay.h>
55 #include <linux/interrupt.h>
56 #include <linux/dmapool.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/device.h>
59 #include <linux/platform_device.h>
60 #include <linux/ata_platform.h>
61 #include <linux/mbus.h>
62 #include <linux/bitops.h>
63 #include <scsi/scsi_host.h>
64 #include <scsi/scsi_cmnd.h>
65 #include <scsi/scsi_device.h>
66 #include <linux/libata.h>
68 #define DRV_NAME "sata_mv"
69 #define DRV_VERSION "1.26"
72 /* BAR's are enumerated in terms of pci_resource_start() terms */
73 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
74 MV_IO_BAR = 2, /* offset 0x18: IO space */
75 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
77 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
78 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
81 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
82 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
83 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
84 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
85 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
86 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
88 MV_SATAHC0_REG_BASE = 0x20000,
89 MV_FLASH_CTL_OFS = 0x1046c,
90 MV_GPIO_PORT_CTL_OFS = 0x104f0,
91 MV_RESET_CFG_OFS = 0x180d8,
93 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
94 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
95 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
96 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
99 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
101 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
102 * CRPB needs alignment on a 256B boundary. Size == 256B
103 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
105 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
106 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
108 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
110 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
111 MV_PORT_HC_SHIFT = 2,
112 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
113 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
114 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
117 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
118 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
120 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
123 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
125 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
126 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
129 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
131 CRQB_FLAG_READ = (1 << 0),
133 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
134 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
135 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
136 CRQB_CMD_ADDR_SHIFT = 8,
137 CRQB_CMD_CS = (0x2 << 11),
138 CRQB_CMD_LAST = (1 << 15),
140 CRPB_FLAG_STATUS_SHIFT = 8,
141 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
142 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
144 EPRD_FLAG_END_OF_TBL = (1 << 31),
146 /* PCI interface registers */
148 PCI_COMMAND_OFS = 0xc00,
149 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
151 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4),
156 MV_PCI_MODE_OFS = 0xd00,
157 MV_PCI_MODE_MASK = 0x30,
159 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
160 MV_PCI_DISC_TIMER = 0xd04,
161 MV_PCI_MSI_TRIGGER = 0xc38,
162 MV_PCI_SERR_MASK = 0xc28,
163 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
164 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
165 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
166 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
167 MV_PCI_ERR_COMMAND = 0x1d50,
169 PCI_IRQ_CAUSE_OFS = 0x1d58,
170 PCI_IRQ_MASK_OFS = 0x1d5c,
171 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173 PCIE_IRQ_CAUSE_OFS = 0x1900,
174 PCIE_IRQ_MASK_OFS = 0x1910,
175 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
177 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
178 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
179 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
180 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
181 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
182 ERR_IRQ = (1 << 0), /* shift by port # */
183 DONE_IRQ = (1 << 1), /* shift by port # */
184 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
185 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
188 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
189 PORTS_0_3_COAL_DONE = (1 << 8),
190 PORTS_4_7_COAL_DONE = (1 << 17),
191 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
192 GPIO_INT = (1 << 22),
193 SELF_INT = (1 << 23),
194 TWSI_INT = (1 << 24),
195 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
196 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
197 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
199 /* SATAHC registers */
202 HC_IRQ_CAUSE_OFS = 0x14,
203 DMA_IRQ = (1 << 0), /* shift by port # */
204 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
205 DEV_IRQ = (1 << 8), /* shift by port # */
207 /* Shadow block registers */
209 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
212 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
213 SATA_ACTIVE_OFS = 0x350,
214 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
215 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
218 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
222 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
223 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
224 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
225 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
228 SATA_IFCTL_OFS = 0x344,
229 SATA_TESTCTL_OFS = 0x348,
230 SATA_IFSTAT_OFS = 0x34c,
231 VENDOR_UNIQUE_FIS_OFS = 0x35c,
234 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
238 MV5_LTMODE_OFS = 0x30,
239 MV5_PHY_CTL_OFS = 0x0C,
240 SATA_INTERFACE_CFG_OFS = 0x050,
242 MV_M2_PREAMP_MASK = 0x7e0,
246 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
251 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
254 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
255 EDMA_ERR_IRQ_MASK_OFS = 0xc,
256 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV = (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
261 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
262 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
264 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
265 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
266 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
271 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
272 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
277 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
279 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
280 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
286 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
288 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
289 EDMA_ERR_OVERRUN_5 = (1 << 5),
290 EDMA_ERR_UNDERRUN_5 = (1 << 6),
292 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
293 EDMA_ERR_LNK_CTRL_RX_1 |
294 EDMA_ERR_LNK_CTRL_RX_3 |
295 EDMA_ERR_LNK_CTRL_TX,
297 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
307 EDMA_ERR_LNK_CTRL_RX_2 |
308 EDMA_ERR_LNK_DATA_RX |
309 EDMA_ERR_LNK_DATA_TX |
310 EDMA_ERR_TRANS_PROTO,
312 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
317 EDMA_ERR_UNDERRUN_5 |
318 EDMA_ERR_SELF_DIS_5 |
324 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
327 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
328 EDMA_REQ_Q_PTR_SHIFT = 5,
330 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
333 EDMA_RSP_Q_PTR_SHIFT = 3,
335 EDMA_CMD_OFS = 0x28, /* EDMA command register */
336 EDMA_EN = (1 << 0), /* enable EDMA */
337 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
338 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
340 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
344 EDMA_IORDY_TMOUT_OFS = 0x34,
345 EDMA_ARB_CFG_OFS = 0x38,
347 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
350 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
351 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
352 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
353 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
355 /* Host private flags (hp_flags) */
356 MV_HP_FLAG_MSI = (1 << 0),
357 MV_HP_ERRATA_50XXB0 = (1 << 1),
358 MV_HP_ERRATA_50XXB2 = (1 << 2),
359 MV_HP_ERRATA_60X1B2 = (1 << 3),
360 MV_HP_ERRATA_60X1C0 = (1 << 4),
361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
366 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
368 /* Port private flags (pp_flags) */
369 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
370 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
371 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
372 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
375 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
376 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
377 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
378 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
379 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
381 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
382 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
385 /* DMA boundary 0xffff is required by the s/g splitting
386 * we need on /length/ in mv_fill-sg().
388 MV_DMA_BOUNDARY = 0xffffU,
390 /* mask of register bits containing lower 32 bits
391 * of EDMA request queue DMA address
393 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
395 /* ditto, for response queue */
396 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
410 /* Command ReQuest Block: 32B */
426 /* Command ResPonse Block: 8B */
433 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
441 struct mv_port_priv {
442 struct mv_crqb *crqb;
444 struct mv_crpb *crpb;
446 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
447 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
449 unsigned int req_idx;
450 unsigned int resp_idx;
453 unsigned int delayed_eh_pmp_map;
456 struct mv_port_signal {
461 struct mv_host_priv {
464 struct mv_port_signal signal[8];
465 const struct mv_hw_ops *ops;
468 void __iomem *main_irq_cause_addr;
469 void __iomem *main_irq_mask_addr;
474 * These consistent DMA memory pools give us guaranteed
475 * alignment for hardware-accessed data structures,
476 * and less memory waste in accomplishing the alignment.
478 struct dma_pool *crqb_pool;
479 struct dma_pool *crpb_pool;
480 struct dma_pool *sg_tbl_pool;
484 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
486 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
487 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
489 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
491 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
492 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
495 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
496 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
497 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
498 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
499 static int mv_port_start(struct ata_port *ap);
500 static void mv_port_stop(struct ata_port *ap);
501 static int mv_qc_defer(struct ata_queued_cmd *qc);
502 static void mv_qc_prep(struct ata_queued_cmd *qc);
503 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
504 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
505 static int mv_hardreset(struct ata_link *link, unsigned int *class,
506 unsigned long deadline);
507 static void mv_eh_freeze(struct ata_port *ap);
508 static void mv_eh_thaw(struct ata_port *ap);
509 static void mv6_dev_config(struct ata_device *dev);
511 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
513 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
514 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
516 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
518 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
519 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
521 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
523 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
524 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
526 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
528 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
529 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
531 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
533 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
534 void __iomem *mmio, unsigned int n_hc);
535 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
537 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
538 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
539 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
540 unsigned int port_no);
541 static int mv_stop_edma(struct ata_port *ap);
542 static int mv_stop_edma_engine(void __iomem *port_mmio);
543 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
545 static void mv_pmp_select(struct ata_port *ap, int pmp);
546 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline);
548 static int mv_softreset(struct ata_link *link, unsigned int *class,
549 unsigned long deadline);
550 static void mv_pmp_error_handler(struct ata_port *ap);
551 static void mv_process_crpb_entries(struct ata_port *ap,
552 struct mv_port_priv *pp);
554 static unsigned long mv_mode_filter(struct ata_device *dev,
555 unsigned long xfer_mask);
556 static void mv_sff_irq_clear(struct ata_port *ap);
557 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
558 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
559 static void mv_bmdma_start(struct ata_queued_cmd *qc);
560 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
561 static u8 mv_bmdma_status(struct ata_port *ap);
563 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
564 * because we have to allow room for worst case splitting of
565 * PRDs for 64K boundaries in mv_fill_sg().
567 static struct scsi_host_template mv5_sht = {
568 ATA_BASE_SHT(DRV_NAME),
569 .sg_tablesize = MV_MAX_SG_CT / 2,
570 .dma_boundary = MV_DMA_BOUNDARY,
573 static struct scsi_host_template mv6_sht = {
574 ATA_NCQ_SHT(DRV_NAME),
575 .can_queue = MV_MAX_Q_DEPTH - 1,
576 .sg_tablesize = MV_MAX_SG_CT / 2,
577 .dma_boundary = MV_DMA_BOUNDARY,
580 static struct ata_port_operations mv5_ops = {
581 .inherits = &ata_sff_port_ops,
583 .qc_defer = mv_qc_defer,
584 .qc_prep = mv_qc_prep,
585 .qc_issue = mv_qc_issue,
587 .freeze = mv_eh_freeze,
589 .hardreset = mv_hardreset,
590 .error_handler = ata_std_error_handler, /* avoid SFF EH */
591 .post_internal_cmd = ATA_OP_NULL,
593 .scr_read = mv5_scr_read,
594 .scr_write = mv5_scr_write,
596 .port_start = mv_port_start,
597 .port_stop = mv_port_stop,
600 static struct ata_port_operations mv6_ops = {
601 .inherits = &mv5_ops,
602 .dev_config = mv6_dev_config,
603 .scr_read = mv_scr_read,
604 .scr_write = mv_scr_write,
606 .pmp_hardreset = mv_pmp_hardreset,
607 .pmp_softreset = mv_softreset,
608 .softreset = mv_softreset,
609 .error_handler = mv_pmp_error_handler,
611 .sff_irq_clear = mv_sff_irq_clear,
612 .check_atapi_dma = mv_check_atapi_dma,
613 .bmdma_setup = mv_bmdma_setup,
614 .bmdma_start = mv_bmdma_start,
615 .bmdma_stop = mv_bmdma_stop,
616 .bmdma_status = mv_bmdma_status,
617 .mode_filter = mv_mode_filter,
620 static struct ata_port_operations mv_iie_ops = {
621 .inherits = &mv6_ops,
622 .dev_config = ATA_OP_NULL,
623 .qc_prep = mv_qc_prep_iie,
626 static const struct ata_port_info mv_port_info[] = {
628 .flags = MV_GEN_I_FLAGS,
629 .pio_mask = 0x1f, /* pio0-4 */
630 .udma_mask = ATA_UDMA6,
631 .port_ops = &mv5_ops,
634 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
635 .pio_mask = 0x1f, /* pio0-4 */
636 .udma_mask = ATA_UDMA6,
637 .port_ops = &mv5_ops,
640 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
641 .pio_mask = 0x1f, /* pio0-4 */
642 .udma_mask = ATA_UDMA6,
643 .port_ops = &mv5_ops,
646 .flags = MV_GEN_II_FLAGS,
647 .pio_mask = 0x1f, /* pio0-4 */
648 .udma_mask = ATA_UDMA6,
649 .port_ops = &mv6_ops,
652 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
653 .pio_mask = 0x1f, /* pio0-4 */
654 .udma_mask = ATA_UDMA6,
655 .port_ops = &mv6_ops,
658 .flags = MV_GEN_IIE_FLAGS,
659 .pio_mask = 0x1f, /* pio0-4 */
660 .udma_mask = ATA_UDMA6,
661 .port_ops = &mv_iie_ops,
664 .flags = MV_GEN_IIE_FLAGS,
665 .pio_mask = 0x1f, /* pio0-4 */
666 .udma_mask = ATA_UDMA6,
667 .port_ops = &mv_iie_ops,
670 .flags = MV_GEN_IIE_FLAGS,
671 .pio_mask = 0x1f, /* pio0-4 */
672 .udma_mask = ATA_UDMA6,
673 .port_ops = &mv_iie_ops,
677 static const struct pci_device_id mv_pci_tbl[] = {
678 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
679 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
680 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
681 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
682 /* RocketRAID 1720/174x have different identifiers */
683 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
684 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
685 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
687 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
688 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
689 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
690 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
691 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
693 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
696 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
698 /* Marvell 7042 support */
699 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
701 /* Highpoint RocketRAID PCIe series */
702 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
703 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
705 { } /* terminate list */
708 static const struct mv_hw_ops mv5xxx_ops = {
709 .phy_errata = mv5_phy_errata,
710 .enable_leds = mv5_enable_leds,
711 .read_preamp = mv5_read_preamp,
712 .reset_hc = mv5_reset_hc,
713 .reset_flash = mv5_reset_flash,
714 .reset_bus = mv5_reset_bus,
717 static const struct mv_hw_ops mv6xxx_ops = {
718 .phy_errata = mv6_phy_errata,
719 .enable_leds = mv6_enable_leds,
720 .read_preamp = mv6_read_preamp,
721 .reset_hc = mv6_reset_hc,
722 .reset_flash = mv6_reset_flash,
723 .reset_bus = mv_reset_pci_bus,
726 static const struct mv_hw_ops mv_soc_ops = {
727 .phy_errata = mv6_phy_errata,
728 .enable_leds = mv_soc_enable_leds,
729 .read_preamp = mv_soc_read_preamp,
730 .reset_hc = mv_soc_reset_hc,
731 .reset_flash = mv_soc_reset_flash,
732 .reset_bus = mv_soc_reset_bus,
739 static inline void writelfl(unsigned long data, void __iomem *addr)
742 (void) readl(addr); /* flush to avoid PCI posted write */
745 static inline unsigned int mv_hc_from_port(unsigned int port)
747 return port >> MV_PORT_HC_SHIFT;
750 static inline unsigned int mv_hardport_from_port(unsigned int port)
752 return port & MV_PORT_MASK;
756 * Consolidate some rather tricky bit shift calculations.
757 * This is hot-path stuff, so not a function.
758 * Simple code, with two return values, so macro rather than inline.
760 * port is the sole input, in range 0..7.
761 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
762 * hardport is the other output, in range 0..3.
764 * Note that port and hardport may be the same variable in some cases.
766 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
768 shift = mv_hc_from_port(port) * HC_SHIFT; \
769 hardport = mv_hardport_from_port(port); \
770 shift += hardport * 2; \
773 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
775 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
778 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
781 return mv_hc_base(base, mv_hc_from_port(port));
784 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
786 return mv_hc_base_from_port(base, port) +
787 MV_SATAHC_ARBTR_REG_SZ +
788 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
791 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
793 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
794 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
796 return hc_mmio + ofs;
799 static inline void __iomem *mv_host_base(struct ata_host *host)
801 struct mv_host_priv *hpriv = host->private_data;
805 static inline void __iomem *mv_ap_base(struct ata_port *ap)
807 return mv_port_base(mv_host_base(ap->host), ap->port_no);
810 static inline int mv_get_hc_count(unsigned long port_flags)
812 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
815 static void mv_set_edma_ptrs(void __iomem *port_mmio,
816 struct mv_host_priv *hpriv,
817 struct mv_port_priv *pp)
822 * initialize request queue
824 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
827 WARN_ON(pp->crqb_dma & 0x3ff);
828 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
829 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
830 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
831 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
834 * initialize response queue
836 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
837 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
839 WARN_ON(pp->crpb_dma & 0xff);
840 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
841 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
842 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
843 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
846 static void mv_set_main_irq_mask(struct ata_host *host,
847 u32 disable_bits, u32 enable_bits)
849 struct mv_host_priv *hpriv = host->private_data;
850 u32 old_mask, new_mask;
852 old_mask = hpriv->main_irq_mask;
853 new_mask = (old_mask & ~disable_bits) | enable_bits;
854 if (new_mask != old_mask) {
855 hpriv->main_irq_mask = new_mask;
856 writelfl(new_mask, hpriv->main_irq_mask_addr);
860 static void mv_enable_port_irqs(struct ata_port *ap,
861 unsigned int port_bits)
863 unsigned int shift, hardport, port = ap->port_no;
864 u32 disable_bits, enable_bits;
866 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
868 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
869 enable_bits = port_bits << shift;
870 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
873 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
874 void __iomem *port_mmio,
875 unsigned int port_irqs)
877 struct mv_host_priv *hpriv = ap->host->private_data;
878 int hardport = mv_hardport_from_port(ap->port_no);
879 void __iomem *hc_mmio = mv_hc_base_from_port(
880 mv_host_base(ap->host), ap->port_no);
883 /* clear EDMA event indicators, if any */
884 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
886 /* clear pending irq events */
887 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
888 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
890 /* clear FIS IRQ Cause */
891 if (IS_GEN_IIE(hpriv))
892 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
894 mv_enable_port_irqs(ap, port_irqs);
898 * mv_start_edma - Enable eDMA engine
899 * @base: port base address
900 * @pp: port private data
902 * Verify the local cache of the eDMA state is accurate with a
906 * Inherited from caller.
908 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
909 struct mv_port_priv *pp, u8 protocol)
911 int want_ncq = (protocol == ATA_PROT_NCQ);
913 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
914 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
915 if (want_ncq != using_ncq)
918 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
919 struct mv_host_priv *hpriv = ap->host->private_data;
921 mv_edma_cfg(ap, want_ncq, 1);
923 mv_set_edma_ptrs(port_mmio, hpriv, pp);
924 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
926 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
927 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
931 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
933 void __iomem *port_mmio = mv_ap_base(ap);
934 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
935 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
939 * Wait for the EDMA engine to finish transactions in progress.
940 * No idea what a good "timeout" value might be, but measurements
941 * indicate that it often requires hundreds of microseconds
942 * with two drives in-use. So we use the 15msec value above
943 * as a rough guess at what even more drives might require.
945 for (i = 0; i < timeout; ++i) {
946 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
947 if ((edma_stat & empty_idle) == empty_idle)
951 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
955 * mv_stop_edma_engine - Disable eDMA engine
956 * @port_mmio: io base address
959 * Inherited from caller.
961 static int mv_stop_edma_engine(void __iomem *port_mmio)
965 /* Disable eDMA. The disable bit auto clears. */
966 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
968 /* Wait for the chip to confirm eDMA is off. */
969 for (i = 10000; i > 0; i--) {
970 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
971 if (!(reg & EDMA_EN))
978 static int mv_stop_edma(struct ata_port *ap)
980 void __iomem *port_mmio = mv_ap_base(ap);
981 struct mv_port_priv *pp = ap->private_data;
984 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
986 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
987 mv_wait_for_edma_empty_idle(ap);
988 if (mv_stop_edma_engine(port_mmio)) {
989 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
992 mv_edma_cfg(ap, 0, 0);
997 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1000 for (b = 0; b < bytes; ) {
1001 DPRINTK("%p: ", start + b);
1002 for (w = 0; b < bytes && w < 4; w++) {
1003 printk("%08x ", readl(start + b));
1011 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1016 for (b = 0; b < bytes; ) {
1017 DPRINTK("%02x: ", b);
1018 for (w = 0; b < bytes && w < 4; w++) {
1019 (void) pci_read_config_dword(pdev, b, &dw);
1020 printk("%08x ", dw);
1027 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1028 struct pci_dev *pdev)
1031 void __iomem *hc_base = mv_hc_base(mmio_base,
1032 port >> MV_PORT_HC_SHIFT);
1033 void __iomem *port_base;
1034 int start_port, num_ports, p, start_hc, num_hcs, hc;
1037 start_hc = start_port = 0;
1038 num_ports = 8; /* shld be benign for 4 port devs */
1041 start_hc = port >> MV_PORT_HC_SHIFT;
1043 num_ports = num_hcs = 1;
1045 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1046 num_ports > 1 ? num_ports - 1 : start_port);
1049 DPRINTK("PCI config space regs:\n");
1050 mv_dump_pci_cfg(pdev, 0x68);
1052 DPRINTK("PCI regs:\n");
1053 mv_dump_mem(mmio_base+0xc00, 0x3c);
1054 mv_dump_mem(mmio_base+0xd00, 0x34);
1055 mv_dump_mem(mmio_base+0xf00, 0x4);
1056 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1057 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1058 hc_base = mv_hc_base(mmio_base, hc);
1059 DPRINTK("HC regs (HC %i):\n", hc);
1060 mv_dump_mem(hc_base, 0x1c);
1062 for (p = start_port; p < start_port + num_ports; p++) {
1063 port_base = mv_port_base(mmio_base, p);
1064 DPRINTK("EDMA regs (port %i):\n", p);
1065 mv_dump_mem(port_base, 0x54);
1066 DPRINTK("SATA regs (port %i):\n", p);
1067 mv_dump_mem(port_base+0x300, 0x60);
1072 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1076 switch (sc_reg_in) {
1080 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1083 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1092 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1094 unsigned int ofs = mv_scr_offset(sc_reg_in);
1096 if (ofs != 0xffffffffU) {
1097 *val = readl(mv_ap_base(link->ap) + ofs);
1103 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1105 unsigned int ofs = mv_scr_offset(sc_reg_in);
1107 if (ofs != 0xffffffffU) {
1108 writelfl(val, mv_ap_base(link->ap) + ofs);
1114 static void mv6_dev_config(struct ata_device *adev)
1117 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1119 * Gen-II does not support NCQ over a port multiplier
1120 * (no FIS-based switching).
1122 if (adev->flags & ATA_DFLAG_NCQ) {
1123 if (sata_pmp_attached(adev->link->ap)) {
1124 adev->flags &= ~ATA_DFLAG_NCQ;
1125 ata_dev_printk(adev, KERN_INFO,
1126 "NCQ disabled for command-based switching\n");
1131 static int mv_qc_defer(struct ata_queued_cmd *qc)
1133 struct ata_link *link = qc->dev->link;
1134 struct ata_port *ap = link->ap;
1135 struct mv_port_priv *pp = ap->private_data;
1138 * Don't allow new commands if we're in a delayed EH state
1139 * for NCQ and/or FIS-based switching.
1141 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1142 return ATA_DEFER_PORT;
1144 * If the port is completely idle, then allow the new qc.
1146 if (ap->nr_active_links == 0)
1150 * The port is operating in host queuing mode (EDMA) with NCQ
1151 * enabled, allow multiple NCQ commands. EDMA also allows
1152 * queueing multiple DMA commands but libata core currently
1155 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1156 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1159 return ATA_DEFER_PORT;
1162 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1164 u32 new_fiscfg, old_fiscfg;
1165 u32 new_ltmode, old_ltmode;
1166 u32 new_haltcond, old_haltcond;
1168 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1169 old_ltmode = readl(port_mmio + LTMODE_OFS);
1170 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1172 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1173 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1174 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1177 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1178 new_ltmode = old_ltmode | LTMODE_BIT8;
1180 new_haltcond &= ~EDMA_ERR_DEV;
1182 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1185 if (new_fiscfg != old_fiscfg)
1186 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1187 if (new_ltmode != old_ltmode)
1188 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1189 if (new_haltcond != old_haltcond)
1190 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1193 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1195 struct mv_host_priv *hpriv = ap->host->private_data;
1198 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1199 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1201 new = old | (1 << 22);
1203 new = old & ~(1 << 22);
1205 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1208 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1211 struct mv_port_priv *pp = ap->private_data;
1212 struct mv_host_priv *hpriv = ap->host->private_data;
1213 void __iomem *port_mmio = mv_ap_base(ap);
1215 /* set up non-NCQ EDMA configuration */
1216 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1217 pp->pp_flags &= ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN);
1219 if (IS_GEN_I(hpriv))
1220 cfg |= (1 << 8); /* enab config burst size mask */
1222 else if (IS_GEN_II(hpriv)) {
1223 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1224 mv_60x1_errata_sata25(ap, want_ncq);
1226 } else if (IS_GEN_IIE(hpriv)) {
1227 int want_fbs = sata_pmp_attached(ap);
1229 * Possible future enhancement:
1231 * The chip can use FBS with non-NCQ, if we allow it,
1232 * But first we need to have the error handling in place
1233 * for this mode (datasheet section 7.3.15.4.2.3).
1234 * So disallow non-NCQ FBS for now.
1236 want_fbs &= want_ncq;
1238 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1241 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1242 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1245 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1247 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1249 cfg |= (1 << 18); /* enab early completion */
1251 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1252 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1256 cfg |= EDMA_CFG_NCQ;
1257 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1260 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1263 static void mv_port_free_dma_mem(struct ata_port *ap)
1265 struct mv_host_priv *hpriv = ap->host->private_data;
1266 struct mv_port_priv *pp = ap->private_data;
1270 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1274 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1278 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1279 * For later hardware, we have one unique sg_tbl per NCQ tag.
1281 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1282 if (pp->sg_tbl[tag]) {
1283 if (tag == 0 || !IS_GEN_I(hpriv))
1284 dma_pool_free(hpriv->sg_tbl_pool,
1286 pp->sg_tbl_dma[tag]);
1287 pp->sg_tbl[tag] = NULL;
1293 * mv_port_start - Port specific init/start routine.
1294 * @ap: ATA channel to manipulate
1296 * Allocate and point to DMA memory, init port private memory,
1300 * Inherited from caller.
1302 static int mv_port_start(struct ata_port *ap)
1304 struct device *dev = ap->host->dev;
1305 struct mv_host_priv *hpriv = ap->host->private_data;
1306 struct mv_port_priv *pp;
1309 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1312 ap->private_data = pp;
1314 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1317 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1319 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1321 goto out_port_free_dma_mem;
1322 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1324 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1325 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1326 ap->flags |= ATA_FLAG_AN;
1328 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1329 * For later hardware, we need one unique sg_tbl per NCQ tag.
1331 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1332 if (tag == 0 || !IS_GEN_I(hpriv)) {
1333 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1334 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1335 if (!pp->sg_tbl[tag])
1336 goto out_port_free_dma_mem;
1338 pp->sg_tbl[tag] = pp->sg_tbl[0];
1339 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1342 mv_edma_cfg(ap, 0, 0);
1345 out_port_free_dma_mem:
1346 mv_port_free_dma_mem(ap);
1351 * mv_port_stop - Port specific cleanup/stop routine.
1352 * @ap: ATA channel to manipulate
1354 * Stop DMA, cleanup port memory.
1357 * This routine uses the host lock to protect the DMA stop.
1359 static void mv_port_stop(struct ata_port *ap)
1362 mv_enable_port_irqs(ap, 0);
1363 mv_port_free_dma_mem(ap);
1367 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1368 * @qc: queued command whose SG list to source from
1370 * Populate the SG list and mark the last entry.
1373 * Inherited from caller.
1375 static void mv_fill_sg(struct ata_queued_cmd *qc)
1377 struct mv_port_priv *pp = qc->ap->private_data;
1378 struct scatterlist *sg;
1379 struct mv_sg *mv_sg, *last_sg = NULL;
1382 mv_sg = pp->sg_tbl[qc->tag];
1383 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1384 dma_addr_t addr = sg_dma_address(sg);
1385 u32 sg_len = sg_dma_len(sg);
1388 u32 offset = addr & 0xffff;
1391 if (offset + len > 0x10000)
1392 len = 0x10000 - offset;
1394 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1395 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1396 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1397 mv_sg->reserved = 0;
1407 if (likely(last_sg))
1408 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1409 mb(); /* ensure data structure is visible to the chipset */
1412 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1414 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1415 (last ? CRQB_CMD_LAST : 0);
1416 *cmdw = cpu_to_le16(tmp);
1420 * mv_mode_filter - Allow ATAPI DMA only on GenII chips.
1421 * @dev: device whose xfer modes are being configured.
1423 * Only the GenII hardware can use DMA with ATAPI drives.
1425 static unsigned long mv_mode_filter(struct ata_device *adev,
1426 unsigned long xfer_mask)
1428 if (adev->class == ATA_DEV_ATAPI) {
1429 struct mv_host_priv *hpriv = adev->link->ap->host->private_data;
1430 if (!IS_GEN_II(hpriv)) {
1431 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
1432 ata_dev_printk(adev, KERN_INFO,
1433 "ATAPI DMA not supported on this chipset\n");
1440 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1441 * @ap: Port associated with this ATA transaction.
1443 * We need this only for ATAPI bmdma transactions,
1444 * as otherwise we experience spurious interrupts
1445 * after libata-sff handles the bmdma interrupts.
1447 static void mv_sff_irq_clear(struct ata_port *ap)
1449 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1453 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1454 * @qc: queued command to check for chipset/DMA compatibility.
1456 * The bmdma engines cannot handle speculative data sizes
1457 * (bytecount under/over flow). So only allow DMA for
1458 * data transfer commands with known data sizes.
1461 * Inherited from caller.
1463 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1465 struct scsi_cmnd *scmd = qc->scsicmd;
1468 switch (scmd->cmnd[0]) {
1476 case GPCMD_SEND_DVD_STRUCTURE:
1477 case GPCMD_SEND_CUE_SHEET:
1478 return 0; /* DMA is safe */
1481 return -EOPNOTSUPP; /* use PIO instead */
1485 * mv_bmdma_setup - Set up BMDMA transaction
1486 * @qc: queued command to prepare DMA for.
1489 * Inherited from caller.
1491 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1493 struct ata_port *ap = qc->ap;
1494 void __iomem *port_mmio = mv_ap_base(ap);
1495 struct mv_port_priv *pp = ap->private_data;
1499 /* clear all DMA cmd bits */
1500 writel(0, port_mmio + BMDMA_CMD_OFS);
1502 /* load PRD table addr. */
1503 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1504 port_mmio + BMDMA_PRD_HIGH_OFS);
1505 writelfl(pp->sg_tbl_dma[qc->tag],
1506 port_mmio + BMDMA_PRD_LOW_OFS);
1508 /* issue r/w command */
1509 ap->ops->sff_exec_command(ap, &qc->tf);
1513 * mv_bmdma_start - Start a BMDMA transaction
1514 * @qc: queued command to start DMA on.
1517 * Inherited from caller.
1519 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1521 struct ata_port *ap = qc->ap;
1522 void __iomem *port_mmio = mv_ap_base(ap);
1523 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1524 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1526 /* start host DMA transaction */
1527 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1531 * mv_bmdma_stop - Stop BMDMA transfer
1532 * @qc: queued command to stop DMA on.
1534 * Clears the ATA_DMA_START flag in the bmdma control register
1537 * Inherited from caller.
1539 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1541 struct ata_port *ap = qc->ap;
1542 void __iomem *port_mmio = mv_ap_base(ap);
1545 /* clear start/stop bit */
1546 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1547 cmd &= ~ATA_DMA_START;
1548 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1550 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1551 ata_sff_dma_pause(ap);
1555 * mv_bmdma_status - Read BMDMA status
1556 * @ap: port for which to retrieve DMA status.
1558 * Read and return equivalent of the sff BMDMA status register.
1561 * Inherited from caller.
1563 static u8 mv_bmdma_status(struct ata_port *ap)
1565 void __iomem *port_mmio = mv_ap_base(ap);
1569 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1570 * and the ATA_DMA_INTR bit doesn't exist.
1572 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1573 if (reg & ATA_DMA_ACTIVE)
1574 status = ATA_DMA_ACTIVE;
1576 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1581 * mv_qc_prep - Host specific command preparation.
1582 * @qc: queued command to prepare
1584 * This routine simply redirects to the general purpose routine
1585 * if command is not DMA. Else, it handles prep of the CRQB
1586 * (command request block), does some sanity checking, and calls
1587 * the SG load routine.
1590 * Inherited from caller.
1592 static void mv_qc_prep(struct ata_queued_cmd *qc)
1594 struct ata_port *ap = qc->ap;
1595 struct mv_port_priv *pp = ap->private_data;
1597 struct ata_taskfile *tf;
1601 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1602 (qc->tf.protocol != ATA_PROT_NCQ))
1605 /* Fill in command request block
1607 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1608 flags |= CRQB_FLAG_READ;
1609 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1610 flags |= qc->tag << CRQB_TAG_SHIFT;
1611 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1613 /* get current queue index from software */
1614 in_index = pp->req_idx;
1616 pp->crqb[in_index].sg_addr =
1617 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1618 pp->crqb[in_index].sg_addr_hi =
1619 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1620 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1622 cw = &pp->crqb[in_index].ata_cmd[0];
1625 /* Sadly, the CRQB cannot accomodate all registers--there are
1626 * only 11 bytes...so we must pick and choose required
1627 * registers based on the command. So, we drop feature and
1628 * hob_feature for [RW] DMA commands, but they are needed for
1629 * NCQ. NCQ will drop hob_nsect, which is not needed there
1630 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1632 switch (tf->command) {
1634 case ATA_CMD_READ_EXT:
1636 case ATA_CMD_WRITE_EXT:
1637 case ATA_CMD_WRITE_FUA_EXT:
1638 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1640 case ATA_CMD_FPDMA_READ:
1641 case ATA_CMD_FPDMA_WRITE:
1642 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1643 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1646 /* The only other commands EDMA supports in non-queued and
1647 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1648 * of which are defined/used by Linux. If we get here, this
1649 * driver needs work.
1651 * FIXME: modify libata to give qc_prep a return value and
1652 * return error here.
1654 BUG_ON(tf->command);
1657 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1658 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1659 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1660 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1661 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1662 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1663 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1664 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1665 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1667 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1673 * mv_qc_prep_iie - Host specific command preparation.
1674 * @qc: queued command to prepare
1676 * This routine simply redirects to the general purpose routine
1677 * if command is not DMA. Else, it handles prep of the CRQB
1678 * (command request block), does some sanity checking, and calls
1679 * the SG load routine.
1682 * Inherited from caller.
1684 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1686 struct ata_port *ap = qc->ap;
1687 struct mv_port_priv *pp = ap->private_data;
1688 struct mv_crqb_iie *crqb;
1689 struct ata_taskfile *tf;
1693 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1694 (qc->tf.protocol != ATA_PROT_NCQ))
1697 /* Fill in Gen IIE command request block */
1698 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1699 flags |= CRQB_FLAG_READ;
1701 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1702 flags |= qc->tag << CRQB_TAG_SHIFT;
1703 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1704 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1706 /* get current queue index from software */
1707 in_index = pp->req_idx;
1709 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1710 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1711 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1712 crqb->flags = cpu_to_le32(flags);
1715 crqb->ata_cmd[0] = cpu_to_le32(
1716 (tf->command << 16) |
1719 crqb->ata_cmd[1] = cpu_to_le32(
1725 crqb->ata_cmd[2] = cpu_to_le32(
1726 (tf->hob_lbal << 0) |
1727 (tf->hob_lbam << 8) |
1728 (tf->hob_lbah << 16) |
1729 (tf->hob_feature << 24)
1731 crqb->ata_cmd[3] = cpu_to_le32(
1733 (tf->hob_nsect << 8)
1736 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1742 * mv_qc_issue - Initiate a command to the host
1743 * @qc: queued command to start
1745 * This routine simply redirects to the general purpose routine
1746 * if command is not DMA. Else, it sanity checks our local
1747 * caches of the request producer/consumer indices then enables
1748 * DMA and bumps the request producer index.
1751 * Inherited from caller.
1753 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1755 static int limit_warnings = 10;
1756 struct ata_port *ap = qc->ap;
1757 void __iomem *port_mmio = mv_ap_base(ap);
1758 struct mv_port_priv *pp = ap->private_data;
1760 unsigned int port_irqs = DONE_IRQ | ERR_IRQ;
1762 switch (qc->tf.protocol) {
1765 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
1766 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1767 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1769 /* Write the request in pointer to kick the EDMA to life */
1770 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1771 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1776 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1778 * Someday, we might implement special polling workarounds
1779 * for these, but it all seems rather unnecessary since we
1780 * normally use only DMA for commands which transfer more
1781 * than a single block of data.
1783 * Much of the time, this could just work regardless.
1784 * So for now, just log the incident, and allow the attempt.
1786 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
1788 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1789 ": attempting PIO w/multiple DRQ: "
1790 "this may fail due to h/w errata\n");
1793 case ATAPI_PROT_PIO:
1794 port_irqs = ERR_IRQ; /* leave DONE_IRQ masked for PIO */
1798 * We're about to send a non-EDMA capable command to the
1799 * port. Turn off EDMA so there won't be problems accessing
1800 * shadow block, etc registers.
1803 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
1804 mv_pmp_select(ap, qc->dev->link->pmp);
1805 return ata_sff_qc_issue(qc);
1809 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1811 struct mv_port_priv *pp = ap->private_data;
1812 struct ata_queued_cmd *qc;
1814 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1816 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1818 if (qc->tf.flags & ATA_TFLAG_POLLING)
1820 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
1823 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1828 static void mv_pmp_error_handler(struct ata_port *ap)
1830 unsigned int pmp, pmp_map;
1831 struct mv_port_priv *pp = ap->private_data;
1833 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1835 * Perform NCQ error analysis on failed PMPs
1836 * before we freeze the port entirely.
1838 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1840 pmp_map = pp->delayed_eh_pmp_map;
1841 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1842 for (pmp = 0; pmp_map != 0; pmp++) {
1843 unsigned int this_pmp = (1 << pmp);
1844 if (pmp_map & this_pmp) {
1845 struct ata_link *link = &ap->pmp_link[pmp];
1846 pmp_map &= ~this_pmp;
1847 ata_eh_analyze_ncq_error(link);
1850 ata_port_freeze(ap);
1852 sata_pmp_error_handler(ap);
1855 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1857 void __iomem *port_mmio = mv_ap_base(ap);
1859 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1862 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1864 struct ata_eh_info *ehi;
1868 * Initialize EH info for PMPs which saw device errors
1870 ehi = &ap->link.eh_info;
1871 for (pmp = 0; pmp_map != 0; pmp++) {
1872 unsigned int this_pmp = (1 << pmp);
1873 if (pmp_map & this_pmp) {
1874 struct ata_link *link = &ap->pmp_link[pmp];
1876 pmp_map &= ~this_pmp;
1877 ehi = &link->eh_info;
1878 ata_ehi_clear_desc(ehi);
1879 ata_ehi_push_desc(ehi, "dev err");
1880 ehi->err_mask |= AC_ERR_DEV;
1881 ehi->action |= ATA_EH_RESET;
1882 ata_link_abort(link);
1887 static int mv_req_q_empty(struct ata_port *ap)
1889 void __iomem *port_mmio = mv_ap_base(ap);
1890 u32 in_ptr, out_ptr;
1892 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1893 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1894 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1895 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1896 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1899 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1901 struct mv_port_priv *pp = ap->private_data;
1903 unsigned int old_map, new_map;
1906 * Device error during FBS+NCQ operation:
1908 * Set a port flag to prevent further I/O being enqueued.
1909 * Leave the EDMA running to drain outstanding commands from this port.
1910 * Perform the post-mortem/EH only when all responses are complete.
1911 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1913 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1914 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1915 pp->delayed_eh_pmp_map = 0;
1917 old_map = pp->delayed_eh_pmp_map;
1918 new_map = old_map | mv_get_err_pmp_map(ap);
1920 if (old_map != new_map) {
1921 pp->delayed_eh_pmp_map = new_map;
1922 mv_pmp_eh_prep(ap, new_map & ~old_map);
1924 failed_links = hweight16(new_map);
1926 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1927 "failed_links=%d nr_active_links=%d\n",
1928 __func__, pp->delayed_eh_pmp_map,
1929 ap->qc_active, failed_links,
1930 ap->nr_active_links);
1932 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
1933 mv_process_crpb_entries(ap, pp);
1936 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1937 return 1; /* handled */
1939 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1940 return 1; /* handled */
1943 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1946 * Possible future enhancement:
1948 * FBS+non-NCQ operation is not yet implemented.
1949 * See related notes in mv_edma_cfg().
1951 * Device error during FBS+non-NCQ operation:
1953 * We need to snapshot the shadow registers for each failed command.
1954 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1956 return 0; /* not handled */
1959 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1961 struct mv_port_priv *pp = ap->private_data;
1963 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1964 return 0; /* EDMA was not active: not handled */
1965 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1966 return 0; /* FBS was not active: not handled */
1968 if (!(edma_err_cause & EDMA_ERR_DEV))
1969 return 0; /* non DEV error: not handled */
1970 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1971 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1972 return 0; /* other problems: not handled */
1974 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1976 * EDMA should NOT have self-disabled for this case.
1977 * If it did, then something is wrong elsewhere,
1978 * and we cannot handle it here.
1980 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1981 ata_port_printk(ap, KERN_WARNING,
1982 "%s: err_cause=0x%x pp_flags=0x%x\n",
1983 __func__, edma_err_cause, pp->pp_flags);
1984 return 0; /* not handled */
1986 return mv_handle_fbs_ncq_dev_err(ap);
1989 * EDMA should have self-disabled for this case.
1990 * If it did not, then something is wrong elsewhere,
1991 * and we cannot handle it here.
1993 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1994 ata_port_printk(ap, KERN_WARNING,
1995 "%s: err_cause=0x%x pp_flags=0x%x\n",
1996 __func__, edma_err_cause, pp->pp_flags);
1997 return 0; /* not handled */
1999 return mv_handle_fbs_non_ncq_dev_err(ap);
2001 return 0; /* not handled */
2004 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2006 struct ata_eh_info *ehi = &ap->link.eh_info;
2007 char *when = "idle";
2009 ata_ehi_clear_desc(ehi);
2010 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2012 } else if (edma_was_enabled) {
2013 when = "EDMA enabled";
2015 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2016 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2019 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2020 ehi->err_mask |= AC_ERR_OTHER;
2021 ehi->action |= ATA_EH_RESET;
2022 ata_port_freeze(ap);
2026 * mv_err_intr - Handle error interrupts on the port
2027 * @ap: ATA channel to manipulate
2029 * Most cases require a full reset of the chip's state machine,
2030 * which also performs a COMRESET.
2031 * Also, if the port disabled DMA, update our cached copy to match.
2034 * Inherited from caller.
2036 static void mv_err_intr(struct ata_port *ap)
2038 void __iomem *port_mmio = mv_ap_base(ap);
2039 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2041 struct mv_port_priv *pp = ap->private_data;
2042 struct mv_host_priv *hpriv = ap->host->private_data;
2043 unsigned int action = 0, err_mask = 0;
2044 struct ata_eh_info *ehi = &ap->link.eh_info;
2045 struct ata_queued_cmd *qc;
2049 * Read and clear the SError and err_cause bits.
2050 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2051 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2053 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2054 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2056 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2057 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2058 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2059 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2061 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2063 if (edma_err_cause & EDMA_ERR_DEV) {
2065 * Device errors during FIS-based switching operation
2066 * require special handling.
2068 if (mv_handle_dev_err(ap, edma_err_cause))
2072 qc = mv_get_active_qc(ap);
2073 ata_ehi_clear_desc(ehi);
2074 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2075 edma_err_cause, pp->pp_flags);
2077 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2078 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2079 if (fis_cause & SATA_FIS_IRQ_AN) {
2080 u32 ec = edma_err_cause &
2081 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2082 sata_async_notification(ap);
2084 return; /* Just an AN; no need for the nukes */
2085 ata_ehi_push_desc(ehi, "SDB notify");
2089 * All generations share these EDMA error cause bits:
2091 if (edma_err_cause & EDMA_ERR_DEV) {
2092 err_mask |= AC_ERR_DEV;
2093 action |= ATA_EH_RESET;
2094 ata_ehi_push_desc(ehi, "dev error");
2096 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2097 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2098 EDMA_ERR_INTRL_PAR)) {
2099 err_mask |= AC_ERR_ATA_BUS;
2100 action |= ATA_EH_RESET;
2101 ata_ehi_push_desc(ehi, "parity error");
2103 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2104 ata_ehi_hotplugged(ehi);
2105 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2106 "dev disconnect" : "dev connect");
2107 action |= ATA_EH_RESET;
2111 * Gen-I has a different SELF_DIS bit,
2112 * different FREEZE bits, and no SERR bit:
2114 if (IS_GEN_I(hpriv)) {
2115 eh_freeze_mask = EDMA_EH_FREEZE_5;
2116 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2117 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2118 ata_ehi_push_desc(ehi, "EDMA self-disable");
2121 eh_freeze_mask = EDMA_EH_FREEZE;
2122 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2123 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2124 ata_ehi_push_desc(ehi, "EDMA self-disable");
2126 if (edma_err_cause & EDMA_ERR_SERR) {
2127 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2128 err_mask |= AC_ERR_ATA_BUS;
2129 action |= ATA_EH_RESET;
2134 err_mask = AC_ERR_OTHER;
2135 action |= ATA_EH_RESET;
2138 ehi->serror |= serr;
2139 ehi->action |= action;
2142 qc->err_mask |= err_mask;
2144 ehi->err_mask |= err_mask;
2146 if (err_mask == AC_ERR_DEV) {
2148 * Cannot do ata_port_freeze() here,
2149 * because it would kill PIO access,
2150 * which is needed for further diagnosis.
2154 } else if (edma_err_cause & eh_freeze_mask) {
2156 * Note to self: ata_port_freeze() calls ata_port_abort()
2158 ata_port_freeze(ap);
2165 ata_link_abort(qc->dev->link);
2171 static void mv_process_crpb_response(struct ata_port *ap,
2172 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2174 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2178 u16 edma_status = le16_to_cpu(response->flags);
2180 * edma_status from a response queue entry:
2181 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2182 * MSB is saved ATA status from command completion.
2185 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2188 * Error will be seen/handled by mv_err_intr().
2189 * So do nothing at all here.
2194 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2195 if (!ac_err_mask(ata_status))
2196 ata_qc_complete(qc);
2197 /* else: leave it for mv_err_intr() */
2199 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2204 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2206 void __iomem *port_mmio = mv_ap_base(ap);
2207 struct mv_host_priv *hpriv = ap->host->private_data;
2209 bool work_done = false;
2210 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2212 /* Get the hardware queue position index */
2213 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2214 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2216 /* Process new responses from since the last time we looked */
2217 while (in_index != pp->resp_idx) {
2219 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2221 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2223 if (IS_GEN_I(hpriv)) {
2224 /* 50xx: no NCQ, only one command active at a time */
2225 tag = ap->link.active_tag;
2227 /* Gen II/IIE: get command tag from CRPB entry */
2228 tag = le16_to_cpu(response->id) & 0x1f;
2230 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2234 /* Update the software queue position index in hardware */
2236 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2237 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2238 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2241 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2243 struct mv_port_priv *pp;
2244 int edma_was_enabled;
2246 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2247 mv_unexpected_intr(ap, 0);
2251 * Grab a snapshot of the EDMA_EN flag setting,
2252 * so that we have a consistent view for this port,
2253 * even if something we call of our routines changes it.
2255 pp = ap->private_data;
2256 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2258 * Process completed CRPB response(s) before other events.
2260 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2261 mv_process_crpb_entries(ap, pp);
2262 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2263 mv_handle_fbs_ncq_dev_err(ap);
2266 * Handle chip-reported errors, or continue on to handle PIO.
2268 if (unlikely(port_cause & ERR_IRQ)) {
2270 } else if (!edma_was_enabled) {
2271 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2273 ata_sff_host_intr(ap, qc);
2275 mv_unexpected_intr(ap, edma_was_enabled);
2280 * mv_host_intr - Handle all interrupts on the given host controller
2281 * @host: host specific structure
2282 * @main_irq_cause: Main interrupt cause register for the chip.
2285 * Inherited from caller.
2287 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2289 struct mv_host_priv *hpriv = host->private_data;
2290 void __iomem *mmio = hpriv->base, *hc_mmio;
2291 unsigned int handled = 0, port;
2293 for (port = 0; port < hpriv->n_ports; port++) {
2294 struct ata_port *ap = host->ports[port];
2295 unsigned int p, shift, hardport, port_cause;
2297 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2299 * Each hc within the host has its own hc_irq_cause register,
2300 * where the interrupting ports bits get ack'd.
2302 if (hardport == 0) { /* first port on this hc ? */
2303 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2304 u32 port_mask, ack_irqs;
2306 * Skip this entire hc if nothing pending for any ports
2309 port += MV_PORTS_PER_HC - 1;
2313 * We don't need/want to read the hc_irq_cause register,
2314 * because doing so hurts performance, and
2315 * main_irq_cause already gives us everything we need.
2317 * But we do have to *write* to the hc_irq_cause to ack
2318 * the ports that we are handling this time through.
2320 * This requires that we create a bitmap for those
2321 * ports which interrupted us, and use that bitmap
2322 * to ack (only) those ports via hc_irq_cause.
2325 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2326 if ((port + p) >= hpriv->n_ports)
2328 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2329 if (hc_cause & port_mask)
2330 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2332 hc_mmio = mv_hc_base_from_port(mmio, port);
2333 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2337 * Handle interrupts signalled for this port:
2339 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2341 mv_port_intr(ap, port_cause);
2346 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2348 struct mv_host_priv *hpriv = host->private_data;
2349 struct ata_port *ap;
2350 struct ata_queued_cmd *qc;
2351 struct ata_eh_info *ehi;
2352 unsigned int i, err_mask, printed = 0;
2355 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2357 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2360 DPRINTK("All regs @ PCI error\n");
2361 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2363 writelfl(0, mmio + hpriv->irq_cause_ofs);
2365 for (i = 0; i < host->n_ports; i++) {
2366 ap = host->ports[i];
2367 if (!ata_link_offline(&ap->link)) {
2368 ehi = &ap->link.eh_info;
2369 ata_ehi_clear_desc(ehi);
2371 ata_ehi_push_desc(ehi,
2372 "PCI err cause 0x%08x", err_cause);
2373 err_mask = AC_ERR_HOST_BUS;
2374 ehi->action = ATA_EH_RESET;
2375 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2377 qc->err_mask |= err_mask;
2379 ehi->err_mask |= err_mask;
2381 ata_port_freeze(ap);
2384 return 1; /* handled */
2388 * mv_interrupt - Main interrupt event handler
2390 * @dev_instance: private data; in this case the host structure
2392 * Read the read only register to determine if any host
2393 * controllers have pending interrupts. If so, call lower level
2394 * routine to handle. Also check for PCI errors which are only
2398 * This routine holds the host lock while processing pending
2401 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2403 struct ata_host *host = dev_instance;
2404 struct mv_host_priv *hpriv = host->private_data;
2405 unsigned int handled = 0;
2406 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2407 u32 main_irq_cause, pending_irqs;
2409 spin_lock(&host->lock);
2411 /* for MSI: block new interrupts while in here */
2413 writel(0, hpriv->main_irq_mask_addr);
2415 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2416 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2418 * Deal with cases where we either have nothing pending, or have read
2419 * a bogus register value which can indicate HW removal or PCI fault.
2421 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2422 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2423 handled = mv_pci_error(host, hpriv->base);
2425 handled = mv_host_intr(host, pending_irqs);
2428 /* for MSI: unmask; interrupt cause bits will retrigger now */
2430 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2432 spin_unlock(&host->lock);
2434 return IRQ_RETVAL(handled);
2437 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2441 switch (sc_reg_in) {
2445 ofs = sc_reg_in * sizeof(u32);
2454 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2456 struct mv_host_priv *hpriv = link->ap->host->private_data;
2457 void __iomem *mmio = hpriv->base;
2458 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2459 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2461 if (ofs != 0xffffffffU) {
2462 *val = readl(addr + ofs);
2468 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2470 struct mv_host_priv *hpriv = link->ap->host->private_data;
2471 void __iomem *mmio = hpriv->base;
2472 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2473 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2475 if (ofs != 0xffffffffU) {
2476 writelfl(val, addr + ofs);
2482 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2484 struct pci_dev *pdev = to_pci_dev(host->dev);
2487 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2490 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2492 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2495 mv_reset_pci_bus(host, mmio);
2498 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2500 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2503 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2506 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2509 tmp = readl(phy_mmio + MV5_PHY_MODE);
2511 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2512 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2515 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2519 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2521 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2523 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2525 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2528 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2531 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2532 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2534 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2537 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2539 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2541 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2544 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2547 tmp = readl(phy_mmio + MV5_PHY_MODE);
2549 tmp |= hpriv->signal[port].pre;
2550 tmp |= hpriv->signal[port].amps;
2551 writel(tmp, phy_mmio + MV5_PHY_MODE);
2556 #define ZERO(reg) writel(0, port_mmio + (reg))
2557 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2560 void __iomem *port_mmio = mv_port_base(mmio, port);
2562 mv_reset_channel(hpriv, mmio, port);
2564 ZERO(0x028); /* command */
2565 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2566 ZERO(0x004); /* timer */
2567 ZERO(0x008); /* irq err cause */
2568 ZERO(0x00c); /* irq err mask */
2569 ZERO(0x010); /* rq bah */
2570 ZERO(0x014); /* rq inp */
2571 ZERO(0x018); /* rq outp */
2572 ZERO(0x01c); /* respq bah */
2573 ZERO(0x024); /* respq outp */
2574 ZERO(0x020); /* respq inp */
2575 ZERO(0x02c); /* test control */
2576 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2580 #define ZERO(reg) writel(0, hc_mmio + (reg))
2581 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2584 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2592 tmp = readl(hc_mmio + 0x20);
2595 writel(tmp, hc_mmio + 0x20);
2599 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2602 unsigned int hc, port;
2604 for (hc = 0; hc < n_hc; hc++) {
2605 for (port = 0; port < MV_PORTS_PER_HC; port++)
2606 mv5_reset_hc_port(hpriv, mmio,
2607 (hc * MV_PORTS_PER_HC) + port);
2609 mv5_reset_one_hc(hpriv, mmio, hc);
2616 #define ZERO(reg) writel(0, mmio + (reg))
2617 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2619 struct mv_host_priv *hpriv = host->private_data;
2622 tmp = readl(mmio + MV_PCI_MODE_OFS);
2624 writel(tmp, mmio + MV_PCI_MODE_OFS);
2626 ZERO(MV_PCI_DISC_TIMER);
2627 ZERO(MV_PCI_MSI_TRIGGER);
2628 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2629 ZERO(MV_PCI_SERR_MASK);
2630 ZERO(hpriv->irq_cause_ofs);
2631 ZERO(hpriv->irq_mask_ofs);
2632 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2633 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2634 ZERO(MV_PCI_ERR_ATTRIBUTE);
2635 ZERO(MV_PCI_ERR_COMMAND);
2639 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2643 mv5_reset_flash(hpriv, mmio);
2645 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2647 tmp |= (1 << 5) | (1 << 6);
2648 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2652 * mv6_reset_hc - Perform the 6xxx global soft reset
2653 * @mmio: base address of the HBA
2655 * This routine only applies to 6xxx parts.
2658 * Inherited from caller.
2660 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2663 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2667 /* Following procedure defined in PCI "main command and status
2671 writel(t | STOP_PCI_MASTER, reg);
2673 for (i = 0; i < 1000; i++) {
2676 if (PCI_MASTER_EMPTY & t)
2679 if (!(PCI_MASTER_EMPTY & t)) {
2680 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2688 writel(t | GLOB_SFT_RST, reg);
2691 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2693 if (!(GLOB_SFT_RST & t)) {
2694 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2699 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2702 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2705 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2707 if (GLOB_SFT_RST & t) {
2708 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2715 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2718 void __iomem *port_mmio;
2721 tmp = readl(mmio + MV_RESET_CFG_OFS);
2722 if ((tmp & (1 << 0)) == 0) {
2723 hpriv->signal[idx].amps = 0x7 << 8;
2724 hpriv->signal[idx].pre = 0x1 << 5;
2728 port_mmio = mv_port_base(mmio, idx);
2729 tmp = readl(port_mmio + PHY_MODE2);
2731 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2732 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2735 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2737 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2740 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2743 void __iomem *port_mmio = mv_port_base(mmio, port);
2745 u32 hp_flags = hpriv->hp_flags;
2747 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2749 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2752 if (fix_phy_mode2) {
2753 m2 = readl(port_mmio + PHY_MODE2);
2756 writel(m2, port_mmio + PHY_MODE2);
2760 m2 = readl(port_mmio + PHY_MODE2);
2761 m2 &= ~((1 << 16) | (1 << 31));
2762 writel(m2, port_mmio + PHY_MODE2);
2768 * Gen-II/IIe PHY_MODE3 errata RM#2:
2769 * Achieves better receiver noise performance than the h/w default:
2771 m3 = readl(port_mmio + PHY_MODE3);
2772 m3 = (m3 & 0x1f) | (0x5555601 << 5);
2774 /* Guideline 88F5182 (GL# SATA-S11) */
2778 if (fix_phy_mode4) {
2779 u32 m4 = readl(port_mmio + PHY_MODE4);
2781 * Enforce reserved-bit restrictions on GenIIe devices only.
2782 * For earlier chipsets, force only the internal config field
2783 * (workaround for errata FEr SATA#10 part 1).
2785 if (IS_GEN_IIE(hpriv))
2786 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2788 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
2789 writel(m4, port_mmio + PHY_MODE4);
2792 * Workaround for 60x1-B2 errata SATA#13:
2793 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2794 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2796 writel(m3, port_mmio + PHY_MODE3);
2798 /* Revert values of pre-emphasis and signal amps to the saved ones */
2799 m2 = readl(port_mmio + PHY_MODE2);
2801 m2 &= ~MV_M2_PREAMP_MASK;
2802 m2 |= hpriv->signal[port].amps;
2803 m2 |= hpriv->signal[port].pre;
2806 /* according to mvSata 3.6.1, some IIE values are fixed */
2807 if (IS_GEN_IIE(hpriv)) {
2812 writel(m2, port_mmio + PHY_MODE2);
2815 /* TODO: use the generic LED interface to configure the SATA Presence */
2816 /* & Acitivy LEDs on the board */
2817 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2823 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2826 void __iomem *port_mmio;
2829 port_mmio = mv_port_base(mmio, idx);
2830 tmp = readl(port_mmio + PHY_MODE2);
2832 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2833 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2837 #define ZERO(reg) writel(0, port_mmio + (reg))
2838 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2839 void __iomem *mmio, unsigned int port)
2841 void __iomem *port_mmio = mv_port_base(mmio, port);
2843 mv_reset_channel(hpriv, mmio, port);
2845 ZERO(0x028); /* command */
2846 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2847 ZERO(0x004); /* timer */
2848 ZERO(0x008); /* irq err cause */
2849 ZERO(0x00c); /* irq err mask */
2850 ZERO(0x010); /* rq bah */
2851 ZERO(0x014); /* rq inp */
2852 ZERO(0x018); /* rq outp */
2853 ZERO(0x01c); /* respq bah */
2854 ZERO(0x024); /* respq outp */
2855 ZERO(0x020); /* respq inp */
2856 ZERO(0x02c); /* test control */
2857 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2862 #define ZERO(reg) writel(0, hc_mmio + (reg))
2863 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2866 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2876 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2877 void __iomem *mmio, unsigned int n_hc)
2881 for (port = 0; port < hpriv->n_ports; port++)
2882 mv_soc_reset_hc_port(hpriv, mmio, port);
2884 mv_soc_reset_one_hc(hpriv, mmio);
2889 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2895 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2900 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2902 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2904 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2906 ifcfg |= (1 << 7); /* enable gen2i speed */
2907 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2910 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2911 unsigned int port_no)
2913 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2916 * The datasheet warns against setting EDMA_RESET when EDMA is active
2917 * (but doesn't say what the problem might be). So we first try
2918 * to disable the EDMA engine before doing the EDMA_RESET operation.
2920 mv_stop_edma_engine(port_mmio);
2921 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2923 if (!IS_GEN_I(hpriv)) {
2924 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2925 mv_setup_ifcfg(port_mmio, 1);
2928 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2929 * link, and physical layers. It resets all SATA interface registers
2930 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2932 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2933 udelay(25); /* allow reset propagation */
2934 writelfl(0, port_mmio + EDMA_CMD_OFS);
2936 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2938 if (IS_GEN_I(hpriv))
2942 static void mv_pmp_select(struct ata_port *ap, int pmp)
2944 if (sata_pmp_supported(ap)) {
2945 void __iomem *port_mmio = mv_ap_base(ap);
2946 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2947 int old = reg & 0xf;
2950 reg = (reg & ~0xf) | pmp;
2951 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2956 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2957 unsigned long deadline)
2959 mv_pmp_select(link->ap, sata_srst_pmp(link));
2960 return sata_std_hardreset(link, class, deadline);
2963 static int mv_softreset(struct ata_link *link, unsigned int *class,
2964 unsigned long deadline)
2966 mv_pmp_select(link->ap, sata_srst_pmp(link));
2967 return ata_sff_softreset(link, class, deadline);
2970 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2971 unsigned long deadline)
2973 struct ata_port *ap = link->ap;
2974 struct mv_host_priv *hpriv = ap->host->private_data;
2975 struct mv_port_priv *pp = ap->private_data;
2976 void __iomem *mmio = hpriv->base;
2977 int rc, attempts = 0, extra = 0;
2981 mv_reset_channel(hpriv, mmio, ap->port_no);
2982 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2984 /* Workaround for errata FEr SATA#10 (part 2) */
2986 const unsigned long *timing =
2987 sata_ehc_deb_timing(&link->eh_context);
2989 rc = sata_link_hardreset(link, timing, deadline + extra,
2991 rc = online ? -EAGAIN : rc;
2994 sata_scr_read(link, SCR_STATUS, &sstatus);
2995 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2996 /* Force 1.5gb/s link speed and try again */
2997 mv_setup_ifcfg(mv_ap_base(ap), 0);
2998 if (time_after(jiffies + HZ, deadline))
2999 extra = HZ; /* only extend it once, max */
3001 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3002 mv_edma_cfg(ap, 0, 0);
3007 static void mv_eh_freeze(struct ata_port *ap)
3010 mv_enable_port_irqs(ap, 0);
3013 static void mv_eh_thaw(struct ata_port *ap)
3015 struct mv_host_priv *hpriv = ap->host->private_data;
3016 unsigned int port = ap->port_no;
3017 unsigned int hardport = mv_hardport_from_port(port);
3018 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3019 void __iomem *port_mmio = mv_ap_base(ap);
3022 /* clear EDMA errors on this port */
3023 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3025 /* clear pending irq events */
3026 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3027 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
3029 mv_enable_port_irqs(ap, ERR_IRQ);
3033 * mv_port_init - Perform some early initialization on a single port.
3034 * @port: libata data structure storing shadow register addresses
3035 * @port_mmio: base address of the port
3037 * Initialize shadow register mmio addresses, clear outstanding
3038 * interrupts on the port, and unmask interrupts for the future
3039 * start of the port.
3042 * Inherited from caller.
3044 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3046 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
3049 /* PIO related setup
3051 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3053 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3054 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3055 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3056 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3057 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3058 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3060 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3061 /* special case: control/altstatus doesn't have ATA_REG_ address */
3062 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3065 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3067 /* Clear any currently outstanding port interrupt conditions */
3068 serr_ofs = mv_scr_offset(SCR_ERROR);
3069 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3070 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3072 /* unmask all non-transient EDMA error interrupts */
3073 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
3075 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3076 readl(port_mmio + EDMA_CFG_OFS),
3077 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3078 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
3081 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3083 struct mv_host_priv *hpriv = host->private_data;
3084 void __iomem *mmio = hpriv->base;
3087 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3088 return 0; /* not PCI-X capable */
3089 reg = readl(mmio + MV_PCI_MODE_OFS);
3090 if ((reg & MV_PCI_MODE_MASK) == 0)
3091 return 0; /* conventional PCI mode */
3092 return 1; /* chip is in PCI-X mode */
3095 static int mv_pci_cut_through_okay(struct ata_host *host)
3097 struct mv_host_priv *hpriv = host->private_data;
3098 void __iomem *mmio = hpriv->base;
3101 if (!mv_in_pcix_mode(host)) {
3102 reg = readl(mmio + PCI_COMMAND_OFS);
3103 if (reg & PCI_COMMAND_MRDTRIG)
3104 return 0; /* not okay */
3106 return 1; /* okay */
3109 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3111 struct pci_dev *pdev = to_pci_dev(host->dev);
3112 struct mv_host_priv *hpriv = host->private_data;
3113 u32 hp_flags = hpriv->hp_flags;
3115 switch (board_idx) {
3117 hpriv->ops = &mv5xxx_ops;
3118 hp_flags |= MV_HP_GEN_I;
3120 switch (pdev->revision) {
3122 hp_flags |= MV_HP_ERRATA_50XXB0;
3125 hp_flags |= MV_HP_ERRATA_50XXB2;
3128 dev_printk(KERN_WARNING, &pdev->dev,
3129 "Applying 50XXB2 workarounds to unknown rev\n");
3130 hp_flags |= MV_HP_ERRATA_50XXB2;
3137 hpriv->ops = &mv5xxx_ops;
3138 hp_flags |= MV_HP_GEN_I;
3140 switch (pdev->revision) {
3142 hp_flags |= MV_HP_ERRATA_50XXB0;
3145 hp_flags |= MV_HP_ERRATA_50XXB2;
3148 dev_printk(KERN_WARNING, &pdev->dev,
3149 "Applying B2 workarounds to unknown rev\n");
3150 hp_flags |= MV_HP_ERRATA_50XXB2;
3157 hpriv->ops = &mv6xxx_ops;
3158 hp_flags |= MV_HP_GEN_II;
3160 switch (pdev->revision) {
3162 hp_flags |= MV_HP_ERRATA_60X1B2;
3165 hp_flags |= MV_HP_ERRATA_60X1C0;
3168 dev_printk(KERN_WARNING, &pdev->dev,
3169 "Applying B2 workarounds to unknown rev\n");
3170 hp_flags |= MV_HP_ERRATA_60X1B2;
3176 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3177 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3178 (pdev->device == 0x2300 || pdev->device == 0x2310))
3181 * Highpoint RocketRAID PCIe 23xx series cards:
3183 * Unconfigured drives are treated as "Legacy"
3184 * by the BIOS, and it overwrites sector 8 with
3185 * a "Lgcy" metadata block prior to Linux boot.
3187 * Configured drives (RAID or JBOD) leave sector 8
3188 * alone, but instead overwrite a high numbered
3189 * sector for the RAID metadata. This sector can
3190 * be determined exactly, by truncating the physical
3191 * drive capacity to a nice even GB value.
3193 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3195 * Warn the user, lest they think we're just buggy.
3197 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3198 " BIOS CORRUPTS DATA on all attached drives,"
3199 " regardless of if/how they are configured."
3201 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3202 " use sectors 8-9 on \"Legacy\" drives,"
3203 " and avoid the final two gigabytes on"
3204 " all RocketRAID BIOS initialized drives.\n");
3208 hpriv->ops = &mv6xxx_ops;
3209 hp_flags |= MV_HP_GEN_IIE;
3210 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3211 hp_flags |= MV_HP_CUT_THROUGH;
3213 switch (pdev->revision) {
3214 case 0x2: /* Rev.B0: the first/only public release */
3215 hp_flags |= MV_HP_ERRATA_60X1C0;
3218 dev_printk(KERN_WARNING, &pdev->dev,
3219 "Applying 60X1C0 workarounds to unknown rev\n");
3220 hp_flags |= MV_HP_ERRATA_60X1C0;
3225 hpriv->ops = &mv_soc_ops;
3226 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3227 MV_HP_ERRATA_60X1C0;
3231 dev_printk(KERN_ERR, host->dev,
3232 "BUG: invalid board index %u\n", board_idx);
3236 hpriv->hp_flags = hp_flags;
3237 if (hp_flags & MV_HP_PCIE) {
3238 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3239 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3240 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3242 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3243 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3244 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3251 * mv_init_host - Perform some early initialization of the host.
3252 * @host: ATA host to initialize
3253 * @board_idx: controller index
3255 * If possible, do an early global reset of the host. Then do
3256 * our port init and clear/unmask all/relevant host interrupts.
3259 * Inherited from caller.
3261 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3263 int rc = 0, n_hc, port, hc;
3264 struct mv_host_priv *hpriv = host->private_data;
3265 void __iomem *mmio = hpriv->base;
3267 rc = mv_chip_id(host, board_idx);
3271 if (IS_SOC(hpriv)) {
3272 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3273 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3275 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3276 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3279 /* initialize shadow irq mask with register's value */
3280 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3282 /* global interrupt mask: 0 == mask everything */
3283 mv_set_main_irq_mask(host, ~0, 0);
3285 n_hc = mv_get_hc_count(host->ports[0]->flags);
3287 for (port = 0; port < host->n_ports; port++)
3288 hpriv->ops->read_preamp(hpriv, port, mmio);
3290 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3294 hpriv->ops->reset_flash(hpriv, mmio);
3295 hpriv->ops->reset_bus(host, mmio);
3296 hpriv->ops->enable_leds(hpriv, mmio);
3298 for (port = 0; port < host->n_ports; port++) {
3299 struct ata_port *ap = host->ports[port];
3300 void __iomem *port_mmio = mv_port_base(mmio, port);
3302 mv_port_init(&ap->ioaddr, port_mmio);
3305 if (!IS_SOC(hpriv)) {
3306 unsigned int offset = port_mmio - mmio;
3307 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3308 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3313 for (hc = 0; hc < n_hc; hc++) {
3314 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3316 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3317 "(before clear)=0x%08x\n", hc,
3318 readl(hc_mmio + HC_CFG_OFS),
3319 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3321 /* Clear any currently outstanding hc interrupt conditions */
3322 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3325 /* Clear any currently outstanding host interrupt conditions */
3326 writelfl(0, mmio + hpriv->irq_cause_ofs);
3328 /* and unmask interrupt generation for host regs */
3329 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3332 * enable only global host interrupts for now.
3333 * The per-port interrupts get done later as ports are set up.
3335 mv_set_main_irq_mask(host, 0, PCI_ERR);
3340 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3342 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3344 if (!hpriv->crqb_pool)
3347 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3349 if (!hpriv->crpb_pool)
3352 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3354 if (!hpriv->sg_tbl_pool)
3360 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3361 struct mbus_dram_target_info *dram)
3365 for (i = 0; i < 4; i++) {
3366 writel(0, hpriv->base + WINDOW_CTRL(i));
3367 writel(0, hpriv->base + WINDOW_BASE(i));
3370 for (i = 0; i < dram->num_cs; i++) {
3371 struct mbus_dram_window *cs = dram->cs + i;
3373 writel(((cs->size - 1) & 0xffff0000) |
3374 (cs->mbus_attr << 8) |
3375 (dram->mbus_dram_target_id << 4) | 1,
3376 hpriv->base + WINDOW_CTRL(i));
3377 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3382 * mv_platform_probe - handle a positive probe of an soc Marvell
3384 * @pdev: platform device found
3387 * Inherited from caller.
3389 static int mv_platform_probe(struct platform_device *pdev)
3391 static int printed_version;
3392 const struct mv_sata_platform_data *mv_platform_data;
3393 const struct ata_port_info *ppi[] =
3394 { &mv_port_info[chip_soc], NULL };
3395 struct ata_host *host;
3396 struct mv_host_priv *hpriv;
3397 struct resource *res;
3400 if (!printed_version++)
3401 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3404 * Simple resource validation ..
3406 if (unlikely(pdev->num_resources != 2)) {
3407 dev_err(&pdev->dev, "invalid number of resources\n");
3412 * Get the register base first
3414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3419 mv_platform_data = pdev->dev.platform_data;
3420 n_ports = mv_platform_data->n_ports;
3422 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3423 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3425 if (!host || !hpriv)
3427 host->private_data = hpriv;
3428 hpriv->n_ports = n_ports;
3431 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3432 res->end - res->start + 1);
3433 hpriv->base -= MV_SATAHC0_REG_BASE;
3436 * (Re-)program MBUS remapping windows if we are asked to.
3438 if (mv_platform_data->dram != NULL)
3439 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3441 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3445 /* initialize adapter */
3446 rc = mv_init_host(host, chip_soc);
3450 dev_printk(KERN_INFO, &pdev->dev,
3451 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3454 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3455 IRQF_SHARED, &mv6_sht);
3460 * mv_platform_remove - unplug a platform interface
3461 * @pdev: platform device
3463 * A platform bus SATA device has been unplugged. Perform the needed
3464 * cleanup. Also called on module unload for any active devices.
3466 static int __devexit mv_platform_remove(struct platform_device *pdev)
3468 struct device *dev = &pdev->dev;
3469 struct ata_host *host = dev_get_drvdata(dev);
3471 ata_host_detach(host);
3475 static struct platform_driver mv_platform_driver = {
3476 .probe = mv_platform_probe,
3477 .remove = __devexit_p(mv_platform_remove),
3480 .owner = THIS_MODULE,
3486 static int mv_pci_init_one(struct pci_dev *pdev,
3487 const struct pci_device_id *ent);
3490 static struct pci_driver mv_pci_driver = {
3492 .id_table = mv_pci_tbl,
3493 .probe = mv_pci_init_one,
3494 .remove = ata_pci_remove_one,
3500 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3503 /* move to PCI layer or libata core? */
3504 static int pci_go_64(struct pci_dev *pdev)
3508 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3509 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3511 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3513 dev_printk(KERN_ERR, &pdev->dev,
3514 "64-bit DMA enable failed\n");
3519 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3521 dev_printk(KERN_ERR, &pdev->dev,
3522 "32-bit DMA enable failed\n");
3525 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3527 dev_printk(KERN_ERR, &pdev->dev,
3528 "32-bit consistent DMA enable failed\n");
3537 * mv_print_info - Dump key info to kernel log for perusal.
3538 * @host: ATA host to print info about
3540 * FIXME: complete this.
3543 * Inherited from caller.
3545 static void mv_print_info(struct ata_host *host)
3547 struct pci_dev *pdev = to_pci_dev(host->dev);
3548 struct mv_host_priv *hpriv = host->private_data;
3550 const char *scc_s, *gen;
3552 /* Use this to determine the HW stepping of the chip so we know
3553 * what errata to workaround
3555 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3558 else if (scc == 0x01)
3563 if (IS_GEN_I(hpriv))
3565 else if (IS_GEN_II(hpriv))
3567 else if (IS_GEN_IIE(hpriv))
3572 dev_printk(KERN_INFO, &pdev->dev,
3573 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3574 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3575 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3579 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3580 * @pdev: PCI device found
3581 * @ent: PCI device ID entry for the matched host
3584 * Inherited from caller.
3586 static int mv_pci_init_one(struct pci_dev *pdev,
3587 const struct pci_device_id *ent)
3589 static int printed_version;
3590 unsigned int board_idx = (unsigned int)ent->driver_data;
3591 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3592 struct ata_host *host;
3593 struct mv_host_priv *hpriv;
3596 if (!printed_version++)
3597 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3600 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3602 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3603 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3604 if (!host || !hpriv)
3606 host->private_data = hpriv;
3607 hpriv->n_ports = n_ports;
3609 /* acquire resources */
3610 rc = pcim_enable_device(pdev);
3614 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3616 pcim_pin_device(pdev);
3619 host->iomap = pcim_iomap_table(pdev);
3620 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3622 rc = pci_go_64(pdev);
3626 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3630 /* initialize adapter */
3631 rc = mv_init_host(host, board_idx);
3635 /* Enable message-switched interrupts, if requested */
3636 if (msi && pci_enable_msi(pdev) == 0)
3637 hpriv->hp_flags |= MV_HP_FLAG_MSI;
3639 mv_dump_pci_cfg(pdev, 0x68);
3640 mv_print_info(host);
3642 pci_set_master(pdev);
3643 pci_try_set_mwi(pdev);
3644 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3645 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3649 static int mv_platform_probe(struct platform_device *pdev);
3650 static int __devexit mv_platform_remove(struct platform_device *pdev);
3652 static int __init mv_init(void)
3656 rc = pci_register_driver(&mv_pci_driver);
3660 rc = platform_driver_register(&mv_platform_driver);
3664 pci_unregister_driver(&mv_pci_driver);
3669 static void __exit mv_exit(void)
3672 pci_unregister_driver(&mv_pci_driver);
3674 platform_driver_unregister(&mv_platform_driver);
3677 MODULE_AUTHOR("Brett Russ");
3678 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3679 MODULE_LICENSE("GPL");
3680 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3681 MODULE_VERSION(DRV_VERSION);
3682 MODULE_ALIAS("platform:" DRV_NAME);
3685 module_param(msi, int, 0444);
3686 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3689 module_init(mv_init);
3690 module_exit(mv_exit);