2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/pci.h>
38 #include <linux/libata.h>
39 #include <linux/highmem.h>
43 const struct ata_port_operations ata_sff_port_ops = {
44 .inherits = &ata_base_port_ops,
46 .qc_prep = ata_sff_qc_prep,
47 .qc_issue = ata_sff_qc_issue,
48 .qc_fill_rtf = ata_sff_qc_fill_rtf,
50 .freeze = ata_sff_freeze,
52 .prereset = ata_sff_prereset,
53 .softreset = ata_sff_softreset,
54 .hardreset = sata_sff_hardreset,
55 .postreset = ata_sff_postreset,
56 .drain_fifo = ata_sff_drain_fifo,
57 .error_handler = ata_sff_error_handler,
58 .post_internal_cmd = ata_sff_post_internal_cmd,
60 .sff_dev_select = ata_sff_dev_select,
61 .sff_check_status = ata_sff_check_status,
62 .sff_tf_load = ata_sff_tf_load,
63 .sff_tf_read = ata_sff_tf_read,
64 .sff_exec_command = ata_sff_exec_command,
65 .sff_data_xfer = ata_sff_data_xfer,
66 .sff_irq_on = ata_sff_irq_on,
67 .sff_irq_clear = ata_sff_irq_clear,
69 .lost_interrupt = ata_sff_lost_interrupt,
71 .port_start = ata_sff_port_start,
73 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
75 const struct ata_port_operations ata_bmdma_port_ops = {
76 .inherits = &ata_sff_port_ops,
78 .mode_filter = ata_bmdma_mode_filter,
80 .bmdma_setup = ata_bmdma_setup,
81 .bmdma_start = ata_bmdma_start,
82 .bmdma_stop = ata_bmdma_stop,
83 .bmdma_status = ata_bmdma_status,
85 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
87 const struct ata_port_operations ata_bmdma32_port_ops = {
88 .inherits = &ata_bmdma_port_ops,
90 .sff_data_xfer = ata_sff_data_xfer32,
91 .port_start = ata_sff_port_start32,
93 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
96 * ata_fill_sg - Fill PCI IDE PRD table
97 * @qc: Metadata associated with taskfile to be transferred
99 * Fill PCI IDE PRD (scatter-gather) table with segments
100 * associated with the current disk command.
103 * spin_lock_irqsave(host lock)
106 static void ata_fill_sg(struct ata_queued_cmd *qc)
108 struct ata_port *ap = qc->ap;
109 struct scatterlist *sg;
113 for_each_sg(qc->sg, sg, qc->n_elem, si) {
117 /* determine if physical DMA addr spans 64K boundary.
118 * Note h/w doesn't support 64-bit, so we unconditionally
119 * truncate dma_addr_t to u32.
121 addr = (u32) sg_dma_address(sg);
122 sg_len = sg_dma_len(sg);
125 offset = addr & 0xffff;
127 if ((offset + sg_len) > 0x10000)
128 len = 0x10000 - offset;
130 ap->prd[pi].addr = cpu_to_le32(addr);
131 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
132 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
140 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
144 * ata_fill_sg_dumb - Fill PCI IDE PRD table
145 * @qc: Metadata associated with taskfile to be transferred
147 * Fill PCI IDE PRD (scatter-gather) table with segments
148 * associated with the current disk command. Perform the fill
149 * so that we avoid writing any length 64K records for
150 * controllers that don't follow the spec.
153 * spin_lock_irqsave(host lock)
156 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
158 struct ata_port *ap = qc->ap;
159 struct scatterlist *sg;
163 for_each_sg(qc->sg, sg, qc->n_elem, si) {
165 u32 sg_len, len, blen;
167 /* determine if physical DMA addr spans 64K boundary.
168 * Note h/w doesn't support 64-bit, so we unconditionally
169 * truncate dma_addr_t to u32.
171 addr = (u32) sg_dma_address(sg);
172 sg_len = sg_dma_len(sg);
175 offset = addr & 0xffff;
177 if ((offset + sg_len) > 0x10000)
178 len = 0x10000 - offset;
181 ap->prd[pi].addr = cpu_to_le32(addr);
183 /* Some PATA chipsets like the CS5530 can't
184 cope with 0x0000 meaning 64K as the spec
186 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
188 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
190 ap->prd[pi].flags_len = cpu_to_le32(blen);
191 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
199 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
203 * ata_sff_qc_prep - Prepare taskfile for submission
204 * @qc: Metadata associated with taskfile to be prepared
206 * Prepare ATA taskfile for submission.
209 * spin_lock_irqsave(host lock)
211 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
213 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
218 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
221 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
222 * @qc: Metadata associated with taskfile to be prepared
224 * Prepare ATA taskfile for submission.
227 * spin_lock_irqsave(host lock)
229 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
231 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
234 ata_fill_sg_dumb(qc);
236 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
239 * ata_sff_check_status - Read device status reg & clear interrupt
240 * @ap: port where the device is
242 * Reads ATA taskfile status register for currently-selected device
243 * and return its value. This also clears pending interrupts
247 * Inherited from caller.
249 u8 ata_sff_check_status(struct ata_port *ap)
251 return ioread8(ap->ioaddr.status_addr);
253 EXPORT_SYMBOL_GPL(ata_sff_check_status);
256 * ata_sff_altstatus - Read device alternate status reg
257 * @ap: port where the device is
259 * Reads ATA taskfile alternate status register for
260 * currently-selected device and return its value.
262 * Note: may NOT be used as the check_altstatus() entry in
263 * ata_port_operations.
266 * Inherited from caller.
268 static u8 ata_sff_altstatus(struct ata_port *ap)
270 if (ap->ops->sff_check_altstatus)
271 return ap->ops->sff_check_altstatus(ap);
273 return ioread8(ap->ioaddr.altstatus_addr);
277 * ata_sff_irq_status - Check if the device is busy
278 * @ap: port where the device is
280 * Determine if the port is currently busy. Uses altstatus
281 * if available in order to avoid clearing shared IRQ status
282 * when finding an IRQ source. Non ctl capable devices don't
283 * share interrupt lines fortunately for us.
286 * Inherited from caller.
288 static u8 ata_sff_irq_status(struct ata_port *ap)
292 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
293 status = ata_sff_altstatus(ap);
294 /* Not us: We are busy */
295 if (status & ATA_BUSY)
298 /* Clear INTRQ latch */
299 status = ap->ops->sff_check_status(ap);
304 * ata_sff_sync - Flush writes
305 * @ap: Port to wait for.
308 * If we have an mmio device with no ctl and no altstatus
309 * method this will fail. No such devices are known to exist.
312 * Inherited from caller.
315 static void ata_sff_sync(struct ata_port *ap)
317 if (ap->ops->sff_check_altstatus)
318 ap->ops->sff_check_altstatus(ap);
319 else if (ap->ioaddr.altstatus_addr)
320 ioread8(ap->ioaddr.altstatus_addr);
324 * ata_sff_pause - Flush writes and wait 400nS
325 * @ap: Port to pause for.
328 * If we have an mmio device with no ctl and no altstatus
329 * method this will fail. No such devices are known to exist.
332 * Inherited from caller.
335 void ata_sff_pause(struct ata_port *ap)
340 EXPORT_SYMBOL_GPL(ata_sff_pause);
343 * ata_sff_dma_pause - Pause before commencing DMA
344 * @ap: Port to pause for.
346 * Perform I/O fencing and ensure sufficient cycle delays occur
347 * for the HDMA1:0 transition
350 void ata_sff_dma_pause(struct ata_port *ap)
352 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
353 /* An altstatus read will cause the needed delay without
354 messing up the IRQ status */
355 ata_sff_altstatus(ap);
358 /* There are no DMA controllers without ctl. BUG here to ensure
359 we never violate the HDMA1:0 transition timing and risk
363 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
366 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
367 * @ap: port containing status register to be polled
368 * @tmout_pat: impatience timeout in msecs
369 * @tmout: overall timeout in msecs
371 * Sleep until ATA Status register bit BSY clears,
372 * or a timeout occurs.
375 * Kernel thread context (may sleep).
378 * 0 on success, -errno otherwise.
380 int ata_sff_busy_sleep(struct ata_port *ap,
381 unsigned long tmout_pat, unsigned long tmout)
383 unsigned long timer_start, timeout;
386 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
387 timer_start = jiffies;
388 timeout = ata_deadline(timer_start, tmout_pat);
389 while (status != 0xff && (status & ATA_BUSY) &&
390 time_before(jiffies, timeout)) {
392 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
395 if (status != 0xff && (status & ATA_BUSY))
396 ata_port_printk(ap, KERN_WARNING,
397 "port is slow to respond, please be patient "
398 "(Status 0x%x)\n", status);
400 timeout = ata_deadline(timer_start, tmout);
401 while (status != 0xff && (status & ATA_BUSY) &&
402 time_before(jiffies, timeout)) {
404 status = ap->ops->sff_check_status(ap);
410 if (status & ATA_BUSY) {
411 ata_port_printk(ap, KERN_ERR, "port failed to respond "
412 "(%lu secs, Status 0x%x)\n",
413 DIV_ROUND_UP(tmout, 1000), status);
419 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
421 static int ata_sff_check_ready(struct ata_link *link)
423 u8 status = link->ap->ops->sff_check_status(link->ap);
425 return ata_check_ready(status);
429 * ata_sff_wait_ready - sleep until BSY clears, or timeout
430 * @link: SFF link to wait ready status for
431 * @deadline: deadline jiffies for the operation
433 * Sleep until ATA Status register bit BSY clears, or timeout
437 * Kernel thread context (may sleep).
440 * 0 on success, -errno otherwise.
442 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
444 return ata_wait_ready(link, deadline, ata_sff_check_ready);
446 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
449 * ata_sff_set_devctl - Write device control reg
450 * @ap: port where the device is
451 * @ctl: value to write
453 * Writes ATA taskfile device control register.
455 * Note: may NOT be used as the sff_set_devctl() entry in
456 * ata_port_operations.
459 * Inherited from caller.
461 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
463 if (ap->ops->sff_set_devctl)
464 ap->ops->sff_set_devctl(ap, ctl);
466 iowrite8(ctl, ap->ioaddr.ctl_addr);
470 * ata_sff_dev_select - Select device 0/1 on ATA bus
471 * @ap: ATA channel to manipulate
472 * @device: ATA device (numbered from zero) to select
474 * Use the method defined in the ATA specification to
475 * make either device 0, or device 1, active on the
476 * ATA channel. Works with both PIO and MMIO.
478 * May be used as the dev_select() entry in ata_port_operations.
483 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
488 tmp = ATA_DEVICE_OBS;
490 tmp = ATA_DEVICE_OBS | ATA_DEV1;
492 iowrite8(tmp, ap->ioaddr.device_addr);
493 ata_sff_pause(ap); /* needed; also flushes, for mmio */
495 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
498 * ata_dev_select - Select device 0/1 on ATA bus
499 * @ap: ATA channel to manipulate
500 * @device: ATA device (numbered from zero) to select
501 * @wait: non-zero to wait for Status register BSY bit to clear
502 * @can_sleep: non-zero if context allows sleeping
504 * Use the method defined in the ATA specification to
505 * make either device 0, or device 1, active on the
508 * This is a high-level version of ata_sff_dev_select(), which
509 * additionally provides the services of inserting the proper
510 * pauses and status polling, where needed.
515 void ata_dev_select(struct ata_port *ap, unsigned int device,
516 unsigned int wait, unsigned int can_sleep)
518 if (ata_msg_probe(ap))
519 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
520 "device %u, wait %u\n", device, wait);
525 ap->ops->sff_dev_select(ap, device);
528 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
535 * ata_sff_irq_on - Enable interrupts on a port.
536 * @ap: Port on which interrupts are enabled.
538 * Enable interrupts on a legacy IDE device using MMIO or PIO,
539 * wait for idle, clear any pending interrupts.
542 * Inherited from caller.
544 u8 ata_sff_irq_on(struct ata_port *ap)
546 struct ata_ioports *ioaddr = &ap->ioaddr;
549 ap->ctl &= ~ATA_NIEN;
550 ap->last_ctl = ap->ctl;
552 if (ioaddr->ctl_addr)
553 iowrite8(ap->ctl, ioaddr->ctl_addr);
554 tmp = ata_wait_idle(ap);
556 ap->ops->sff_irq_clear(ap);
560 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
563 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
564 * @ap: Port associated with this ATA transaction.
566 * Clear interrupt and error flags in DMA status register.
568 * May be used as the irq_clear() entry in ata_port_operations.
571 * spin_lock_irqsave(host lock)
573 void ata_sff_irq_clear(struct ata_port *ap)
575 void __iomem *mmio = ap->ioaddr.bmdma_addr;
580 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
582 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
585 * ata_sff_tf_load - send taskfile registers to host controller
586 * @ap: Port to which output is sent
587 * @tf: ATA taskfile register set
589 * Outputs ATA taskfile to standard ATA host controller.
592 * Inherited from caller.
594 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
596 struct ata_ioports *ioaddr = &ap->ioaddr;
597 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
599 if (tf->ctl != ap->last_ctl) {
600 if (ioaddr->ctl_addr)
601 iowrite8(tf->ctl, ioaddr->ctl_addr);
602 ap->last_ctl = tf->ctl;
606 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
607 WARN_ON_ONCE(!ioaddr->ctl_addr);
608 iowrite8(tf->hob_feature, ioaddr->feature_addr);
609 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
610 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
611 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
612 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
613 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
622 iowrite8(tf->feature, ioaddr->feature_addr);
623 iowrite8(tf->nsect, ioaddr->nsect_addr);
624 iowrite8(tf->lbal, ioaddr->lbal_addr);
625 iowrite8(tf->lbam, ioaddr->lbam_addr);
626 iowrite8(tf->lbah, ioaddr->lbah_addr);
627 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
635 if (tf->flags & ATA_TFLAG_DEVICE) {
636 iowrite8(tf->device, ioaddr->device_addr);
637 VPRINTK("device 0x%X\n", tf->device);
642 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
645 * ata_sff_tf_read - input device's ATA taskfile shadow registers
646 * @ap: Port from which input is read
647 * @tf: ATA taskfile register set for storing input
649 * Reads ATA taskfile registers for currently-selected device
650 * into @tf. Assumes the device has a fully SFF compliant task file
651 * layout and behaviour. If you device does not (eg has a different
652 * status method) then you will need to provide a replacement tf_read
655 * Inherited from caller.
657 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
659 struct ata_ioports *ioaddr = &ap->ioaddr;
661 tf->command = ata_sff_check_status(ap);
662 tf->feature = ioread8(ioaddr->error_addr);
663 tf->nsect = ioread8(ioaddr->nsect_addr);
664 tf->lbal = ioread8(ioaddr->lbal_addr);
665 tf->lbam = ioread8(ioaddr->lbam_addr);
666 tf->lbah = ioread8(ioaddr->lbah_addr);
667 tf->device = ioread8(ioaddr->device_addr);
669 if (tf->flags & ATA_TFLAG_LBA48) {
670 if (likely(ioaddr->ctl_addr)) {
671 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
672 tf->hob_feature = ioread8(ioaddr->error_addr);
673 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
674 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
675 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
676 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
677 iowrite8(tf->ctl, ioaddr->ctl_addr);
678 ap->last_ctl = tf->ctl;
683 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
686 * ata_sff_exec_command - issue ATA command to host controller
687 * @ap: port to which command is being issued
688 * @tf: ATA taskfile register set
690 * Issues ATA command, with proper synchronization with interrupt
691 * handler / other threads.
694 * spin_lock_irqsave(host lock)
696 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
698 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
700 iowrite8(tf->command, ap->ioaddr.command_addr);
703 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
706 * ata_tf_to_host - issue ATA taskfile to host controller
707 * @ap: port to which command is being issued
708 * @tf: ATA taskfile register set
710 * Issues ATA taskfile register set to ATA host controller,
711 * with proper synchronization with interrupt handler and
715 * spin_lock_irqsave(host lock)
717 static inline void ata_tf_to_host(struct ata_port *ap,
718 const struct ata_taskfile *tf)
720 ap->ops->sff_tf_load(ap, tf);
721 ap->ops->sff_exec_command(ap, tf);
725 * ata_sff_data_xfer - Transfer data by PIO
726 * @dev: device to target
728 * @buflen: buffer length
731 * Transfer data from/to the device data register by PIO.
734 * Inherited from caller.
739 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
740 unsigned int buflen, int rw)
742 struct ata_port *ap = dev->link->ap;
743 void __iomem *data_addr = ap->ioaddr.data_addr;
744 unsigned int words = buflen >> 1;
746 /* Transfer multiple of 2 bytes */
748 ioread16_rep(data_addr, buf, words);
750 iowrite16_rep(data_addr, buf, words);
752 /* Transfer trailing byte, if any. */
753 if (unlikely(buflen & 0x01)) {
754 unsigned char pad[2];
756 /* Point buf to the tail of buffer */
760 * Use io*16_rep() accessors here as well to avoid pointlessly
761 * swapping bytes to and from on the big endian machines...
764 ioread16_rep(data_addr, pad, 1);
768 iowrite16_rep(data_addr, pad, 1);
775 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
778 * ata_sff_data_xfer32 - Transfer data by PIO
779 * @dev: device to target
781 * @buflen: buffer length
784 * Transfer data from/to the device data register by PIO using 32bit
788 * Inherited from caller.
794 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
795 unsigned int buflen, int rw)
797 struct ata_port *ap = dev->link->ap;
798 void __iomem *data_addr = ap->ioaddr.data_addr;
799 unsigned int words = buflen >> 2;
800 int slop = buflen & 3;
802 if (!(ap->pflags & ATA_PFLAG_PIO32))
803 return ata_sff_data_xfer(dev, buf, buflen, rw);
805 /* Transfer multiple of 4 bytes */
807 ioread32_rep(data_addr, buf, words);
809 iowrite32_rep(data_addr, buf, words);
811 /* Transfer trailing bytes, if any */
812 if (unlikely(slop)) {
813 unsigned char pad[4];
815 /* Point buf to the tail of buffer */
816 buf += buflen - slop;
819 * Use io*_rep() accessors here as well to avoid pointlessly
820 * swapping bytes to and from on the big endian machines...
824 ioread16_rep(data_addr, pad, 1);
826 ioread32_rep(data_addr, pad, 1);
827 memcpy(buf, pad, slop);
829 memcpy(pad, buf, slop);
831 iowrite16_rep(data_addr, pad, 1);
833 iowrite32_rep(data_addr, pad, 1);
836 return (buflen + 1) & ~1;
838 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
841 * ata_sff_data_xfer_noirq - Transfer data by PIO
842 * @dev: device to target
844 * @buflen: buffer length
847 * Transfer data from/to the device data register by PIO. Do the
848 * transfer with interrupts disabled.
851 * Inherited from caller.
856 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
857 unsigned int buflen, int rw)
860 unsigned int consumed;
862 local_irq_save(flags);
863 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
864 local_irq_restore(flags);
868 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
871 * ata_pio_sector - Transfer a sector of data.
872 * @qc: Command on going
874 * Transfer qc->sect_size bytes of data from/to the ATA device.
877 * Inherited from caller.
879 static void ata_pio_sector(struct ata_queued_cmd *qc)
881 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
882 struct ata_port *ap = qc->ap;
887 if (qc->curbytes == qc->nbytes - qc->sect_size)
888 ap->hsm_task_state = HSM_ST_LAST;
890 page = sg_page(qc->cursg);
891 offset = qc->cursg->offset + qc->cursg_ofs;
893 /* get the current page and offset */
894 page = nth_page(page, (offset >> PAGE_SHIFT));
897 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
899 if (PageHighMem(page)) {
902 /* FIXME: use a bounce buffer */
903 local_irq_save(flags);
904 buf = kmap_atomic(page, KM_IRQ0);
906 /* do the actual data transfer */
907 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
910 kunmap_atomic(buf, KM_IRQ0);
911 local_irq_restore(flags);
913 buf = page_address(page);
914 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
919 flush_dcache_page(page);
921 qc->curbytes += qc->sect_size;
922 qc->cursg_ofs += qc->sect_size;
924 if (qc->cursg_ofs == qc->cursg->length) {
925 qc->cursg = sg_next(qc->cursg);
931 * ata_pio_sectors - Transfer one or many sectors.
932 * @qc: Command on going
934 * Transfer one or many sectors of data from/to the
935 * ATA device for the DRQ request.
938 * Inherited from caller.
940 static void ata_pio_sectors(struct ata_queued_cmd *qc)
942 if (is_multi_taskfile(&qc->tf)) {
943 /* READ/WRITE MULTIPLE */
946 WARN_ON_ONCE(qc->dev->multi_count == 0);
948 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
949 qc->dev->multi_count);
955 ata_sff_sync(qc->ap); /* flush */
959 * atapi_send_cdb - Write CDB bytes to hardware
960 * @ap: Port to which ATAPI device is attached.
961 * @qc: Taskfile currently active
963 * When device has indicated its readiness to accept
964 * a CDB, this function is called. Send the CDB.
969 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
972 DPRINTK("send cdb\n");
973 WARN_ON_ONCE(qc->dev->cdb_len < 12);
975 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
977 /* FIXME: If the CDB is for DMA do we need to do the transition delay
978 or is bmdma_start guaranteed to do it ? */
979 switch (qc->tf.protocol) {
981 ap->hsm_task_state = HSM_ST;
983 case ATAPI_PROT_NODATA:
984 ap->hsm_task_state = HSM_ST_LAST;
987 ap->hsm_task_state = HSM_ST_LAST;
989 ap->ops->bmdma_start(qc);
995 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
996 * @qc: Command on going
997 * @bytes: number of bytes
999 * Transfer Transfer data from/to the ATAPI device.
1002 * Inherited from caller.
1005 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
1007 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
1008 struct ata_port *ap = qc->ap;
1009 struct ata_device *dev = qc->dev;
1010 struct ata_eh_info *ehi = &dev->link->eh_info;
1011 struct scatterlist *sg;
1014 unsigned int offset, count, consumed;
1018 if (unlikely(!sg)) {
1019 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
1020 "buf=%u cur=%u bytes=%u",
1021 qc->nbytes, qc->curbytes, bytes);
1026 offset = sg->offset + qc->cursg_ofs;
1028 /* get the current page and offset */
1029 page = nth_page(page, (offset >> PAGE_SHIFT));
1030 offset %= PAGE_SIZE;
1032 /* don't overrun current sg */
1033 count = min(sg->length - qc->cursg_ofs, bytes);
1035 /* don't cross page boundaries */
1036 count = min(count, (unsigned int)PAGE_SIZE - offset);
1038 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
1040 if (PageHighMem(page)) {
1041 unsigned long flags;
1043 /* FIXME: use bounce buffer */
1044 local_irq_save(flags);
1045 buf = kmap_atomic(page, KM_IRQ0);
1047 /* do the actual data transfer */
1048 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
1051 kunmap_atomic(buf, KM_IRQ0);
1052 local_irq_restore(flags);
1054 buf = page_address(page);
1055 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
1059 bytes -= min(bytes, consumed);
1060 qc->curbytes += count;
1061 qc->cursg_ofs += count;
1063 if (qc->cursg_ofs == sg->length) {
1064 qc->cursg = sg_next(qc->cursg);
1069 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
1070 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
1071 * check correctly as it doesn't know if it is the last request being
1072 * made. Somebody should implement a proper sanity check.
1080 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
1081 * @qc: Command on going
1083 * Transfer Transfer data from/to the ATAPI device.
1086 * Inherited from caller.
1088 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
1090 struct ata_port *ap = qc->ap;
1091 struct ata_device *dev = qc->dev;
1092 struct ata_eh_info *ehi = &dev->link->eh_info;
1093 unsigned int ireason, bc_lo, bc_hi, bytes;
1094 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
1096 /* Abuse qc->result_tf for temp storage of intermediate TF
1097 * here to save some kernel stack usage.
1098 * For normal completion, qc->result_tf is not relevant. For
1099 * error, qc->result_tf is later overwritten by ata_qc_complete().
1100 * So, the correctness of qc->result_tf is not affected.
1102 ap->ops->sff_tf_read(ap, &qc->result_tf);
1103 ireason = qc->result_tf.nsect;
1104 bc_lo = qc->result_tf.lbam;
1105 bc_hi = qc->result_tf.lbah;
1106 bytes = (bc_hi << 8) | bc_lo;
1108 /* shall be cleared to zero, indicating xfer of data */
1109 if (unlikely(ireason & (1 << 0)))
1112 /* make sure transfer direction matches expected */
1113 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
1114 if (unlikely(do_write != i_write))
1117 if (unlikely(!bytes))
1120 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
1122 if (unlikely(__atapi_pio_bytes(qc, bytes)))
1124 ata_sff_sync(ap); /* flush */
1129 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
1132 qc->err_mask |= AC_ERR_HSM;
1133 ap->hsm_task_state = HSM_ST_ERR;
1137 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
1138 * @ap: the target ata_port
1142 * 1 if ok in workqueue, 0 otherwise.
1144 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
1145 struct ata_queued_cmd *qc)
1147 if (qc->tf.flags & ATA_TFLAG_POLLING)
1150 if (ap->hsm_task_state == HSM_ST_FIRST) {
1151 if (qc->tf.protocol == ATA_PROT_PIO &&
1152 (qc->tf.flags & ATA_TFLAG_WRITE))
1155 if (ata_is_atapi(qc->tf.protocol) &&
1156 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1164 * ata_hsm_qc_complete - finish a qc running on standard HSM
1165 * @qc: Command to complete
1166 * @in_wq: 1 if called from workqueue, 0 otherwise
1168 * Finish @qc which is running on standard HSM.
1171 * If @in_wq is zero, spin_lock_irqsave(host lock).
1172 * Otherwise, none on entry and grabs host lock.
1174 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1176 struct ata_port *ap = qc->ap;
1177 unsigned long flags;
1179 if (ap->ops->error_handler) {
1181 spin_lock_irqsave(ap->lock, flags);
1183 /* EH might have kicked in while host lock is
1186 qc = ata_qc_from_tag(ap, qc->tag);
1188 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1189 ap->ops->sff_irq_on(ap);
1190 ata_qc_complete(qc);
1192 ata_port_freeze(ap);
1195 spin_unlock_irqrestore(ap->lock, flags);
1197 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1198 ata_qc_complete(qc);
1200 ata_port_freeze(ap);
1204 spin_lock_irqsave(ap->lock, flags);
1205 ap->ops->sff_irq_on(ap);
1206 ata_qc_complete(qc);
1207 spin_unlock_irqrestore(ap->lock, flags);
1209 ata_qc_complete(qc);
1214 * ata_sff_hsm_move - move the HSM to the next state.
1215 * @ap: the target ata_port
1217 * @status: current device status
1218 * @in_wq: 1 if called from workqueue, 0 otherwise
1221 * 1 when poll next status needed, 0 otherwise.
1223 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1224 u8 status, int in_wq)
1226 struct ata_eh_info *ehi = &ap->link.eh_info;
1227 unsigned long flags = 0;
1230 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1232 /* Make sure ata_sff_qc_issue() does not throw things
1233 * like DMA polling into the workqueue. Notice that
1234 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1236 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1239 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1240 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1242 switch (ap->hsm_task_state) {
1244 /* Send first data block or PACKET CDB */
1246 /* If polling, we will stay in the work queue after
1247 * sending the data. Otherwise, interrupt handler
1248 * takes over after sending the data.
1250 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1252 /* check device status */
1253 if (unlikely((status & ATA_DRQ) == 0)) {
1254 /* handle BSY=0, DRQ=0 as error */
1255 if (likely(status & (ATA_ERR | ATA_DF)))
1256 /* device stops HSM for abort/error */
1257 qc->err_mask |= AC_ERR_DEV;
1259 /* HSM violation. Let EH handle this */
1260 ata_ehi_push_desc(ehi,
1261 "ST_FIRST: !(DRQ|ERR|DF)");
1262 qc->err_mask |= AC_ERR_HSM;
1265 ap->hsm_task_state = HSM_ST_ERR;
1269 /* Device should not ask for data transfer (DRQ=1)
1270 * when it finds something wrong.
1271 * We ignore DRQ here and stop the HSM by
1272 * changing hsm_task_state to HSM_ST_ERR and
1273 * let the EH abort the command or reset the device.
1275 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1276 /* Some ATAPI tape drives forget to clear the ERR bit
1277 * when doing the next command (mostly request sense).
1278 * We ignore ERR here to workaround and proceed sending
1281 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1282 ata_ehi_push_desc(ehi, "ST_FIRST: "
1283 "DRQ=1 with device error, "
1284 "dev_stat 0x%X", status);
1285 qc->err_mask |= AC_ERR_HSM;
1286 ap->hsm_task_state = HSM_ST_ERR;
1291 /* Send the CDB (atapi) or the first data block (ata pio out).
1292 * During the state transition, interrupt handler shouldn't
1293 * be invoked before the data transfer is complete and
1294 * hsm_task_state is changed. Hence, the following locking.
1297 spin_lock_irqsave(ap->lock, flags);
1299 if (qc->tf.protocol == ATA_PROT_PIO) {
1300 /* PIO data out protocol.
1301 * send first data block.
1304 /* ata_pio_sectors() might change the state
1305 * to HSM_ST_LAST. so, the state is changed here
1306 * before ata_pio_sectors().
1308 ap->hsm_task_state = HSM_ST;
1309 ata_pio_sectors(qc);
1312 atapi_send_cdb(ap, qc);
1315 spin_unlock_irqrestore(ap->lock, flags);
1317 /* if polling, ata_pio_task() handles the rest.
1318 * otherwise, interrupt handler takes over from here.
1323 /* complete command or read/write the data register */
1324 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1325 /* ATAPI PIO protocol */
1326 if ((status & ATA_DRQ) == 0) {
1327 /* No more data to transfer or device error.
1328 * Device error will be tagged in HSM_ST_LAST.
1330 ap->hsm_task_state = HSM_ST_LAST;
1334 /* Device should not ask for data transfer (DRQ=1)
1335 * when it finds something wrong.
1336 * We ignore DRQ here and stop the HSM by
1337 * changing hsm_task_state to HSM_ST_ERR and
1338 * let the EH abort the command or reset the device.
1340 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1341 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1342 "DRQ=1 with device error, "
1343 "dev_stat 0x%X", status);
1344 qc->err_mask |= AC_ERR_HSM;
1345 ap->hsm_task_state = HSM_ST_ERR;
1349 atapi_pio_bytes(qc);
1351 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1352 /* bad ireason reported by device */
1356 /* ATA PIO protocol */
1357 if (unlikely((status & ATA_DRQ) == 0)) {
1358 /* handle BSY=0, DRQ=0 as error */
1359 if (likely(status & (ATA_ERR | ATA_DF))) {
1360 /* device stops HSM for abort/error */
1361 qc->err_mask |= AC_ERR_DEV;
1363 /* If diagnostic failed and this is
1364 * IDENTIFY, it's likely a phantom
1365 * device. Mark hint.
1367 if (qc->dev->horkage &
1368 ATA_HORKAGE_DIAGNOSTIC)
1372 /* HSM violation. Let EH handle this.
1373 * Phantom devices also trigger this
1374 * condition. Mark hint.
1376 ata_ehi_push_desc(ehi, "ST-ATA: "
1377 "DRQ=0 without device error, "
1378 "dev_stat 0x%X", status);
1379 qc->err_mask |= AC_ERR_HSM |
1383 ap->hsm_task_state = HSM_ST_ERR;
1387 /* For PIO reads, some devices may ask for
1388 * data transfer (DRQ=1) alone with ERR=1.
1389 * We respect DRQ here and transfer one
1390 * block of junk data before changing the
1391 * hsm_task_state to HSM_ST_ERR.
1393 * For PIO writes, ERR=1 DRQ=1 doesn't make
1394 * sense since the data block has been
1395 * transferred to the device.
1397 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1398 /* data might be corrputed */
1399 qc->err_mask |= AC_ERR_DEV;
1401 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1402 ata_pio_sectors(qc);
1403 status = ata_wait_idle(ap);
1406 if (status & (ATA_BUSY | ATA_DRQ)) {
1407 ata_ehi_push_desc(ehi, "ST-ATA: "
1408 "BUSY|DRQ persists on ERR|DF, "
1409 "dev_stat 0x%X", status);
1410 qc->err_mask |= AC_ERR_HSM;
1413 /* There are oddball controllers with
1414 * status register stuck at 0x7f and
1415 * lbal/m/h at zero which makes it
1416 * pass all other presence detection
1417 * mechanisms we have. Set NODEV_HINT
1418 * for it. Kernel bz#7241.
1421 qc->err_mask |= AC_ERR_NODEV_HINT;
1423 /* ata_pio_sectors() might change the
1424 * state to HSM_ST_LAST. so, the state
1425 * is changed after ata_pio_sectors().
1427 ap->hsm_task_state = HSM_ST_ERR;
1431 ata_pio_sectors(qc);
1433 if (ap->hsm_task_state == HSM_ST_LAST &&
1434 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1436 status = ata_wait_idle(ap);
1445 if (unlikely(!ata_ok(status))) {
1446 qc->err_mask |= __ac_err_mask(status);
1447 ap->hsm_task_state = HSM_ST_ERR;
1451 /* no more data to transfer */
1452 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1453 ap->print_id, qc->dev->devno, status);
1455 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1457 ap->hsm_task_state = HSM_ST_IDLE;
1459 /* complete taskfile transaction */
1460 ata_hsm_qc_complete(qc, in_wq);
1466 ap->hsm_task_state = HSM_ST_IDLE;
1468 /* complete taskfile transaction */
1469 ata_hsm_qc_complete(qc, in_wq);
1480 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1482 void ata_pio_task(struct work_struct *work)
1484 struct ata_port *ap =
1485 container_of(work, struct ata_port, port_task.work);
1486 struct ata_queued_cmd *qc = ap->port_task_data;
1491 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1494 * This is purely heuristic. This is a fast path.
1495 * Sometimes when we enter, BSY will be cleared in
1496 * a chk-status or two. If not, the drive is probably seeking
1497 * or something. Snooze for a couple msecs, then
1498 * chk-status again. If still busy, queue delayed work.
1500 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1501 if (status & ATA_BUSY) {
1503 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1504 if (status & ATA_BUSY) {
1505 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1511 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1513 /* another command or interrupt handler
1514 * may be running at this point.
1521 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1522 * @qc: command to issue to device
1524 * Using various libata functions and hooks, this function
1525 * starts an ATA command. ATA commands are grouped into
1526 * classes called "protocols", and issuing each type of protocol
1527 * is slightly different.
1529 * May be used as the qc_issue() entry in ata_port_operations.
1532 * spin_lock_irqsave(host lock)
1535 * Zero on success, AC_ERR_* mask on failure
1537 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1539 struct ata_port *ap = qc->ap;
1541 /* Use polling pio if the LLD doesn't handle
1542 * interrupt driven pio and atapi CDB interrupt.
1544 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1545 switch (qc->tf.protocol) {
1547 case ATA_PROT_NODATA:
1548 case ATAPI_PROT_PIO:
1549 case ATAPI_PROT_NODATA:
1550 qc->tf.flags |= ATA_TFLAG_POLLING;
1552 case ATAPI_PROT_DMA:
1553 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1554 /* see ata_dma_blacklisted() */
1562 /* select the device */
1563 ata_dev_select(ap, qc->dev->devno, 1, 0);
1565 /* start the command */
1566 switch (qc->tf.protocol) {
1567 case ATA_PROT_NODATA:
1568 if (qc->tf.flags & ATA_TFLAG_POLLING)
1569 ata_qc_set_polling(qc);
1571 ata_tf_to_host(ap, &qc->tf);
1572 ap->hsm_task_state = HSM_ST_LAST;
1574 if (qc->tf.flags & ATA_TFLAG_POLLING)
1575 ata_pio_queue_task(ap, qc, 0);
1580 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
1582 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1583 ap->ops->bmdma_setup(qc); /* set up bmdma */
1584 ap->ops->bmdma_start(qc); /* initiate bmdma */
1585 ap->hsm_task_state = HSM_ST_LAST;
1589 if (qc->tf.flags & ATA_TFLAG_POLLING)
1590 ata_qc_set_polling(qc);
1592 ata_tf_to_host(ap, &qc->tf);
1594 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1595 /* PIO data out protocol */
1596 ap->hsm_task_state = HSM_ST_FIRST;
1597 ata_pio_queue_task(ap, qc, 0);
1599 /* always send first data block using
1600 * the ata_pio_task() codepath.
1603 /* PIO data in protocol */
1604 ap->hsm_task_state = HSM_ST;
1606 if (qc->tf.flags & ATA_TFLAG_POLLING)
1607 ata_pio_queue_task(ap, qc, 0);
1609 /* if polling, ata_pio_task() handles the rest.
1610 * otherwise, interrupt handler takes over from here.
1616 case ATAPI_PROT_PIO:
1617 case ATAPI_PROT_NODATA:
1618 if (qc->tf.flags & ATA_TFLAG_POLLING)
1619 ata_qc_set_polling(qc);
1621 ata_tf_to_host(ap, &qc->tf);
1623 ap->hsm_task_state = HSM_ST_FIRST;
1625 /* send cdb by polling if no cdb interrupt */
1626 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1627 (qc->tf.flags & ATA_TFLAG_POLLING))
1628 ata_pio_queue_task(ap, qc, 0);
1631 case ATAPI_PROT_DMA:
1632 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
1634 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1635 ap->ops->bmdma_setup(qc); /* set up bmdma */
1636 ap->hsm_task_state = HSM_ST_FIRST;
1638 /* send cdb by polling if no cdb interrupt */
1639 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1640 ata_pio_queue_task(ap, qc, 0);
1645 return AC_ERR_SYSTEM;
1650 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1653 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1654 * @qc: qc to fill result TF for
1656 * @qc is finished and result TF needs to be filled. Fill it
1657 * using ->sff_tf_read.
1660 * spin_lock_irqsave(host lock)
1663 * true indicating that result TF is successfully filled.
1665 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1667 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1670 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1673 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1674 * @ap: Port on which interrupt arrived (possibly...)
1675 * @qc: Taskfile currently active in engine
1677 * Handle host interrupt for given queued command. Currently,
1678 * only DMA interrupts are handled. All other commands are
1679 * handled via polling with interrupts disabled (nIEN bit).
1682 * spin_lock_irqsave(host lock)
1685 * One if interrupt was handled, zero if not (shared irq).
1687 unsigned int ata_sff_host_intr(struct ata_port *ap,
1688 struct ata_queued_cmd *qc)
1690 struct ata_eh_info *ehi = &ap->link.eh_info;
1691 u8 status, host_stat = 0;
1692 bool bmdma_stopped = false;
1694 VPRINTK("ata%u: protocol %d task_state %d\n",
1695 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1697 /* Check whether we are expecting interrupt in this state */
1698 switch (ap->hsm_task_state) {
1700 /* Some pre-ATAPI-4 devices assert INTRQ
1701 * at this state when ready to receive CDB.
1704 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1705 * The flag was turned on only for atapi devices. No
1706 * need to check ata_is_atapi(qc->tf.protocol) again.
1708 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1712 if (qc->tf.protocol == ATA_PROT_DMA ||
1713 qc->tf.protocol == ATAPI_PROT_DMA) {
1714 /* check status of DMA engine */
1715 host_stat = ap->ops->bmdma_status(ap);
1716 VPRINTK("ata%u: host_stat 0x%X\n",
1717 ap->print_id, host_stat);
1719 /* if it's not our irq... */
1720 if (!(host_stat & ATA_DMA_INTR))
1723 /* before we do anything else, clear DMA-Start bit */
1724 ap->ops->bmdma_stop(qc);
1725 bmdma_stopped = true;
1727 if (unlikely(host_stat & ATA_DMA_ERR)) {
1728 /* error when transfering data to/from memory */
1729 qc->err_mask |= AC_ERR_HOST_BUS;
1730 ap->hsm_task_state = HSM_ST_ERR;
1741 /* check main status, clearing INTRQ if needed */
1742 status = ata_sff_irq_status(ap);
1743 if (status & ATA_BUSY) {
1744 if (bmdma_stopped) {
1745 /* BMDMA engine is already stopped, we're screwed */
1746 qc->err_mask |= AC_ERR_HSM;
1747 ap->hsm_task_state = HSM_ST_ERR;
1752 /* ack bmdma irq events */
1753 ap->ops->sff_irq_clear(ap);
1755 ata_sff_hsm_move(ap, qc, status, 0);
1757 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1758 qc->tf.protocol == ATAPI_PROT_DMA))
1759 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1761 return 1; /* irq handled */
1764 ap->stats.idle_irq++;
1767 if ((ap->stats.idle_irq % 1000) == 0) {
1768 ap->ops->sff_check_status(ap);
1769 ap->ops->sff_irq_clear(ap);
1770 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1774 return 0; /* irq not handled */
1776 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
1779 * ata_sff_interrupt - Default ATA host interrupt handler
1780 * @irq: irq line (unused)
1781 * @dev_instance: pointer to our ata_host information structure
1783 * Default interrupt handler for PCI IDE devices. Calls
1784 * ata_sff_host_intr() for each port that is not disabled.
1787 * Obtains host lock during operation.
1790 * IRQ_NONE or IRQ_HANDLED.
1792 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1794 struct ata_host *host = dev_instance;
1795 bool retried = false;
1797 unsigned int handled, idle, polling;
1798 unsigned long flags;
1800 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1801 spin_lock_irqsave(&host->lock, flags);
1804 handled = idle = polling = 0;
1805 for (i = 0; i < host->n_ports; i++) {
1806 struct ata_port *ap = host->ports[i];
1807 struct ata_queued_cmd *qc;
1809 if (unlikely(ap->flags & ATA_FLAG_DISABLED))
1812 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1814 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1815 handled |= ata_sff_host_intr(ap, qc);
1823 * If no port was expecting IRQ but the controller is actually
1824 * asserting IRQ line, nobody cared will ensue. Check IRQ
1825 * pending status if available and clear spurious IRQ.
1827 if (!handled && !retried) {
1830 for (i = 0; i < host->n_ports; i++) {
1831 struct ata_port *ap = host->ports[i];
1833 if (polling & (1 << i))
1836 if (!ap->ops->sff_irq_check ||
1837 !ap->ops->sff_irq_check(ap))
1840 if (idle & (1 << i)) {
1841 ap->ops->sff_check_status(ap);
1842 ap->ops->sff_irq_clear(ap);
1844 /* clear INTRQ and check if BUSY cleared */
1845 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1848 * With command in flight, we can't do
1849 * sff_irq_clear() w/o racing with completion.
1860 spin_unlock_irqrestore(&host->lock, flags);
1862 return IRQ_RETVAL(handled);
1864 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1867 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1868 * @ap: port that appears to have timed out
1870 * Called from the libata error handlers when the core code suspects
1871 * an interrupt has been lost. If it has complete anything we can and
1872 * then return. Interface must support altstatus for this faster
1873 * recovery to occur.
1876 * Caller holds host lock
1879 void ata_sff_lost_interrupt(struct ata_port *ap)
1882 struct ata_queued_cmd *qc;
1884 /* Only one outstanding command per SFF channel */
1885 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1886 /* Check we have a live one.. */
1887 if (qc == NULL || !(qc->flags & ATA_QCFLAG_ACTIVE))
1889 /* We cannot lose an interrupt on a polled command */
1890 if (qc->tf.flags & ATA_TFLAG_POLLING)
1892 /* See if the controller thinks it is still busy - if so the command
1893 isn't a lost IRQ but is still in progress */
1894 status = ata_sff_altstatus(ap);
1895 if (status & ATA_BUSY)
1898 /* There was a command running, we are no longer busy and we have
1900 ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n",
1902 /* Run the host interrupt logic as if the interrupt had not been
1904 ata_sff_host_intr(ap, qc);
1906 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1909 * ata_sff_freeze - Freeze SFF controller port
1910 * @ap: port to freeze
1912 * Freeze BMDMA controller port.
1915 * Inherited from caller.
1917 void ata_sff_freeze(struct ata_port *ap)
1919 ap->ctl |= ATA_NIEN;
1920 ap->last_ctl = ap->ctl;
1922 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1923 ata_sff_set_devctl(ap, ap->ctl);
1925 /* Under certain circumstances, some controllers raise IRQ on
1926 * ATA_NIEN manipulation. Also, many controllers fail to mask
1927 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1929 ap->ops->sff_check_status(ap);
1931 ap->ops->sff_irq_clear(ap);
1933 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1936 * ata_sff_thaw - Thaw SFF controller port
1939 * Thaw SFF controller port.
1942 * Inherited from caller.
1944 void ata_sff_thaw(struct ata_port *ap)
1946 /* clear & re-enable interrupts */
1947 ap->ops->sff_check_status(ap);
1948 ap->ops->sff_irq_clear(ap);
1949 ap->ops->sff_irq_on(ap);
1951 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1954 * ata_sff_prereset - prepare SFF link for reset
1955 * @link: SFF link to be reset
1956 * @deadline: deadline jiffies for the operation
1958 * SFF link @link is about to be reset. Initialize it. It first
1959 * calls ata_std_prereset() and wait for !BSY if the port is
1963 * Kernel thread context (may sleep)
1966 * 0 on success, -errno otherwise.
1968 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1970 struct ata_eh_context *ehc = &link->eh_context;
1973 rc = ata_std_prereset(link, deadline);
1977 /* if we're about to do hardreset, nothing more to do */
1978 if (ehc->i.action & ATA_EH_HARDRESET)
1981 /* wait for !BSY if we don't know that no device is attached */
1982 if (!ata_link_offline(link)) {
1983 rc = ata_sff_wait_ready(link, deadline);
1984 if (rc && rc != -ENODEV) {
1985 ata_link_printk(link, KERN_WARNING, "device not ready "
1986 "(errno=%d), forcing hardreset\n", rc);
1987 ehc->i.action |= ATA_EH_HARDRESET;
1993 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1996 * ata_devchk - PATA device presence detection
1997 * @ap: ATA channel to examine
1998 * @device: Device to examine (starting at zero)
2000 * This technique was originally described in
2001 * Hale Landis's ATADRVR (www.ata-atapi.com), and
2002 * later found its way into the ATA/ATAPI spec.
2004 * Write a pattern to the ATA shadow registers,
2005 * and if a device is present, it will respond by
2006 * correctly storing and echoing back the
2007 * ATA shadow register contents.
2012 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
2014 struct ata_ioports *ioaddr = &ap->ioaddr;
2017 ap->ops->sff_dev_select(ap, device);
2019 iowrite8(0x55, ioaddr->nsect_addr);
2020 iowrite8(0xaa, ioaddr->lbal_addr);
2022 iowrite8(0xaa, ioaddr->nsect_addr);
2023 iowrite8(0x55, ioaddr->lbal_addr);
2025 iowrite8(0x55, ioaddr->nsect_addr);
2026 iowrite8(0xaa, ioaddr->lbal_addr);
2028 nsect = ioread8(ioaddr->nsect_addr);
2029 lbal = ioread8(ioaddr->lbal_addr);
2031 if ((nsect == 0x55) && (lbal == 0xaa))
2032 return 1; /* we found a device */
2034 return 0; /* nothing found */
2038 * ata_sff_dev_classify - Parse returned ATA device signature
2039 * @dev: ATA device to classify (starting at zero)
2040 * @present: device seems present
2041 * @r_err: Value of error register on completion
2043 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
2044 * an ATA/ATAPI-defined set of values is placed in the ATA
2045 * shadow registers, indicating the results of device detection
2048 * Select the ATA device, and read the values from the ATA shadow
2049 * registers. Then parse according to the Error register value,
2050 * and the spec-defined values examined by ata_dev_classify().
2056 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
2058 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
2061 struct ata_port *ap = dev->link->ap;
2062 struct ata_taskfile tf;
2066 ap->ops->sff_dev_select(ap, dev->devno);
2068 memset(&tf, 0, sizeof(tf));
2070 ap->ops->sff_tf_read(ap, &tf);
2075 /* see if device passed diags: continue and warn later */
2077 /* diagnostic fail : do nothing _YET_ */
2078 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
2081 else if ((dev->devno == 0) && (err == 0x81))
2084 return ATA_DEV_NONE;
2086 /* determine if device is ATA or ATAPI */
2087 class = ata_dev_classify(&tf);
2089 if (class == ATA_DEV_UNKNOWN) {
2090 /* If the device failed diagnostic, it's likely to
2091 * have reported incorrect device signature too.
2092 * Assume ATA device if the device seems present but
2093 * device signature is invalid with diagnostic
2096 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
2097 class = ATA_DEV_ATA;
2099 class = ATA_DEV_NONE;
2100 } else if ((class == ATA_DEV_ATA) &&
2101 (ap->ops->sff_check_status(ap) == 0))
2102 class = ATA_DEV_NONE;
2106 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2109 * ata_sff_wait_after_reset - wait for devices to become ready after reset
2110 * @link: SFF link which is just reset
2111 * @devmask: mask of present devices
2112 * @deadline: deadline jiffies for the operation
2114 * Wait devices attached to SFF @link to become ready after
2115 * reset. It contains preceding 150ms wait to avoid accessing TF
2116 * status register too early.
2119 * Kernel thread context (may sleep).
2122 * 0 on success, -ENODEV if some or all of devices in @devmask
2123 * don't seem to exist. -errno on other errors.
2125 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
2126 unsigned long deadline)
2128 struct ata_port *ap = link->ap;
2129 struct ata_ioports *ioaddr = &ap->ioaddr;
2130 unsigned int dev0 = devmask & (1 << 0);
2131 unsigned int dev1 = devmask & (1 << 1);
2134 msleep(ATA_WAIT_AFTER_RESET);
2136 /* always check readiness of the master device */
2137 rc = ata_sff_wait_ready(link, deadline);
2138 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
2139 * and TF status is 0xff, bail out on it too.
2144 /* if device 1 was found in ata_devchk, wait for register
2145 * access briefly, then wait for BSY to clear.
2150 ap->ops->sff_dev_select(ap, 1);
2152 /* Wait for register access. Some ATAPI devices fail
2153 * to set nsect/lbal after reset, so don't waste too
2154 * much time on it. We're gonna wait for !BSY anyway.
2156 for (i = 0; i < 2; i++) {
2159 nsect = ioread8(ioaddr->nsect_addr);
2160 lbal = ioread8(ioaddr->lbal_addr);
2161 if ((nsect == 1) && (lbal == 1))
2163 msleep(50); /* give drive a breather */
2166 rc = ata_sff_wait_ready(link, deadline);
2174 /* is all this really necessary? */
2175 ap->ops->sff_dev_select(ap, 0);
2177 ap->ops->sff_dev_select(ap, 1);
2179 ap->ops->sff_dev_select(ap, 0);
2183 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2185 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2186 unsigned long deadline)
2188 struct ata_ioports *ioaddr = &ap->ioaddr;
2190 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2192 /* software reset. causes dev0 to be selected */
2193 iowrite8(ap->ctl, ioaddr->ctl_addr);
2194 udelay(20); /* FIXME: flush */
2195 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2196 udelay(20); /* FIXME: flush */
2197 iowrite8(ap->ctl, ioaddr->ctl_addr);
2198 ap->last_ctl = ap->ctl;
2200 /* wait the port to become ready */
2201 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2205 * ata_sff_softreset - reset host port via ATA SRST
2206 * @link: ATA link to reset
2207 * @classes: resulting classes of attached devices
2208 * @deadline: deadline jiffies for the operation
2210 * Reset host port using ATA SRST.
2213 * Kernel thread context (may sleep)
2216 * 0 on success, -errno otherwise.
2218 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2219 unsigned long deadline)
2221 struct ata_port *ap = link->ap;
2222 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2223 unsigned int devmask = 0;
2229 /* determine if device 0/1 are present */
2230 if (ata_devchk(ap, 0))
2231 devmask |= (1 << 0);
2232 if (slave_possible && ata_devchk(ap, 1))
2233 devmask |= (1 << 1);
2235 /* select device 0 again */
2236 ap->ops->sff_dev_select(ap, 0);
2238 /* issue bus reset */
2239 DPRINTK("about to softreset, devmask=%x\n", devmask);
2240 rc = ata_bus_softreset(ap, devmask, deadline);
2241 /* if link is occupied, -ENODEV too is an error */
2242 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2243 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2247 /* determine by signature whether we have ATA or ATAPI devices */
2248 classes[0] = ata_sff_dev_classify(&link->device[0],
2249 devmask & (1 << 0), &err);
2250 if (slave_possible && err != 0x81)
2251 classes[1] = ata_sff_dev_classify(&link->device[1],
2252 devmask & (1 << 1), &err);
2254 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2257 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2260 * sata_sff_hardreset - reset host port via SATA phy reset
2261 * @link: link to reset
2262 * @class: resulting class of attached device
2263 * @deadline: deadline jiffies for the operation
2265 * SATA phy-reset host port using DET bits of SControl register,
2266 * wait for !BSY and classify the attached device.
2269 * Kernel thread context (may sleep)
2272 * 0 on success, -errno otherwise.
2274 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2275 unsigned long deadline)
2277 struct ata_eh_context *ehc = &link->eh_context;
2278 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2282 rc = sata_link_hardreset(link, timing, deadline, &online,
2283 ata_sff_check_ready);
2285 *class = ata_sff_dev_classify(link->device, 1, NULL);
2287 DPRINTK("EXIT, class=%u\n", *class);
2290 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2293 * ata_sff_postreset - SFF postreset callback
2294 * @link: the target SFF ata_link
2295 * @classes: classes of attached devices
2297 * This function is invoked after a successful reset. It first
2298 * calls ata_std_postreset() and performs SFF specific postreset
2302 * Kernel thread context (may sleep)
2304 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2306 struct ata_port *ap = link->ap;
2308 ata_std_postreset(link, classes);
2310 /* is double-select really necessary? */
2311 if (classes[0] != ATA_DEV_NONE)
2312 ap->ops->sff_dev_select(ap, 1);
2313 if (classes[1] != ATA_DEV_NONE)
2314 ap->ops->sff_dev_select(ap, 0);
2316 /* bail out if no device is present */
2317 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2318 DPRINTK("EXIT, no device\n");
2322 /* set up device control */
2323 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2324 ata_sff_set_devctl(ap, ap->ctl);
2325 ap->last_ctl = ap->ctl;
2328 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2331 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2334 * Drain the FIFO and device of any stuck data following a command
2335 * failing to complete. In some cases this is necessary before a
2336 * reset will recover the device.
2340 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2343 struct ata_port *ap;
2345 /* We only need to flush incoming data when a command was running */
2346 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2350 /* Drain up to 64K of data before we give up this recovery method */
2351 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2352 && count < 65536; count += 2)
2353 ioread16(ap->ioaddr.data_addr);
2355 /* Can become DEBUG later */
2357 ata_port_printk(ap, KERN_DEBUG,
2358 "drained %d bytes to clear DRQ.\n", count);
2361 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2364 * ata_sff_error_handler - Stock error handler for BMDMA controller
2365 * @ap: port to handle error for
2367 * Stock error handler for SFF controller. It can handle both
2368 * PATA and SATA controllers. Many controllers should be able to
2369 * use this EH as-is or with some added handling before and
2373 * Kernel thread context (may sleep)
2375 void ata_sff_error_handler(struct ata_port *ap)
2377 ata_reset_fn_t softreset = ap->ops->softreset;
2378 ata_reset_fn_t hardreset = ap->ops->hardreset;
2379 struct ata_queued_cmd *qc;
2380 unsigned long flags;
2383 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2384 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2387 /* reset PIO HSM and stop DMA engine */
2388 spin_lock_irqsave(ap->lock, flags);
2390 ap->hsm_task_state = HSM_ST_IDLE;
2392 if (ap->ioaddr.bmdma_addr &&
2393 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2394 qc->tf.protocol == ATAPI_PROT_DMA)) {
2397 host_stat = ap->ops->bmdma_status(ap);
2399 /* BMDMA controllers indicate host bus error by
2400 * setting DMA_ERR bit and timing out. As it wasn't
2401 * really a timeout event, adjust error mask and
2402 * cancel frozen state.
2404 if (qc->err_mask == AC_ERR_TIMEOUT
2405 && (host_stat & ATA_DMA_ERR)) {
2406 qc->err_mask = AC_ERR_HOST_BUS;
2410 ap->ops->bmdma_stop(qc);
2413 ata_sff_sync(ap); /* FIXME: We don't need this */
2414 ap->ops->sff_check_status(ap);
2415 ap->ops->sff_irq_clear(ap);
2416 /* We *MUST* do FIFO draining before we issue a reset as several
2417 * devices helpfully clear their internal state and will lock solid
2418 * if we touch the data port post reset. Pass qc in case anyone wants
2419 * to do different PIO/DMA recovery or has per command fixups
2421 if (ap->ops->drain_fifo)
2422 ap->ops->drain_fifo(qc);
2424 spin_unlock_irqrestore(ap->lock, flags);
2427 ata_eh_thaw_port(ap);
2429 /* PIO and DMA engines have been stopped, perform recovery */
2431 /* Ignore ata_sff_softreset if ctl isn't accessible and
2432 * built-in hardresets if SCR access isn't available.
2434 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2436 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2439 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2440 ap->ops->postreset);
2442 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2445 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2446 * @qc: internal command to clean up
2449 * Kernel thread context (may sleep)
2451 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2453 struct ata_port *ap = qc->ap;
2454 unsigned long flags;
2456 spin_lock_irqsave(ap->lock, flags);
2458 ap->hsm_task_state = HSM_ST_IDLE;
2460 if (ap->ioaddr.bmdma_addr)
2461 ap->ops->bmdma_stop(qc);
2463 spin_unlock_irqrestore(ap->lock, flags);
2465 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2468 * ata_sff_port_start - Set port up for dma.
2469 * @ap: Port to initialize
2471 * Called just after data structures for each port are
2472 * initialized. Allocates space for PRD table if the device
2473 * is DMA capable SFF.
2475 * May be used as the port_start() entry in ata_port_operations.
2478 * Inherited from caller.
2480 int ata_sff_port_start(struct ata_port *ap)
2482 if (ap->ioaddr.bmdma_addr)
2483 return ata_port_start(ap);
2486 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2489 * ata_sff_port_start32 - Set port up for dma.
2490 * @ap: Port to initialize
2492 * Called just after data structures for each port are
2493 * initialized. Allocates space for PRD table if the device
2494 * is DMA capable SFF.
2496 * May be used as the port_start() entry in ata_port_operations for
2497 * devices that are capable of 32bit PIO.
2500 * Inherited from caller.
2502 int ata_sff_port_start32(struct ata_port *ap)
2504 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
2505 if (ap->ioaddr.bmdma_addr)
2506 return ata_port_start(ap);
2509 EXPORT_SYMBOL_GPL(ata_sff_port_start32);
2512 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2513 * @ioaddr: IO address structure to be initialized
2515 * Utility function which initializes data_addr, error_addr,
2516 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2517 * device_addr, status_addr, and command_addr to standard offsets
2518 * relative to cmd_addr.
2520 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2522 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2524 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2525 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2526 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2527 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2528 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2529 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2530 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2531 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2532 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2533 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2535 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2537 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2538 unsigned long xfer_mask)
2540 /* Filter out DMA modes if the device has been configured by
2541 the BIOS as PIO only */
2543 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2544 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2547 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2550 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2551 * @qc: Info associated with this ATA transaction.
2554 * spin_lock_irqsave(host lock)
2556 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2558 struct ata_port *ap = qc->ap;
2559 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2562 /* load PRD table addr. */
2563 mb(); /* make sure PRD table writes are visible to controller */
2564 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2566 /* specify data direction, triple-check start bit is clear */
2567 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2568 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2570 dmactl |= ATA_DMA_WR;
2571 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2573 /* issue r/w command */
2574 ap->ops->sff_exec_command(ap, &qc->tf);
2576 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2579 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2580 * @qc: Info associated with this ATA transaction.
2583 * spin_lock_irqsave(host lock)
2585 void ata_bmdma_start(struct ata_queued_cmd *qc)
2587 struct ata_port *ap = qc->ap;
2590 /* start host DMA transaction */
2591 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2592 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2594 /* Strictly, one may wish to issue an ioread8() here, to
2595 * flush the mmio write. However, control also passes
2596 * to the hardware at this point, and it will interrupt
2597 * us when we are to resume control. So, in effect,
2598 * we don't care when the mmio write flushes.
2599 * Further, a read of the DMA status register _immediately_
2600 * following the write may not be what certain flaky hardware
2601 * is expected, so I think it is best to not add a readb()
2602 * without first all the MMIO ATA cards/mobos.
2603 * Or maybe I'm just being paranoid.
2605 * FIXME: The posting of this write means I/O starts are
2606 * unneccessarily delayed for MMIO
2609 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2612 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2613 * @qc: Command we are ending DMA for
2615 * Clears the ATA_DMA_START flag in the dma control register
2617 * May be used as the bmdma_stop() entry in ata_port_operations.
2620 * spin_lock_irqsave(host lock)
2622 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2624 struct ata_port *ap = qc->ap;
2625 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2627 /* clear start/stop bit */
2628 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2629 mmio + ATA_DMA_CMD);
2631 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2632 ata_sff_dma_pause(ap);
2634 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2637 * ata_bmdma_status - Read PCI IDE BMDMA status
2638 * @ap: Port associated with this ATA transaction.
2640 * Read and return BMDMA status register.
2642 * May be used as the bmdma_status() entry in ata_port_operations.
2645 * spin_lock_irqsave(host lock)
2647 u8 ata_bmdma_status(struct ata_port *ap)
2649 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2651 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2656 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2659 * Some PCI ATA devices report simplex mode but in fact can be told to
2660 * enter non simplex mode. This implements the necessary logic to
2661 * perform the task on such devices. Calling it on other devices will
2662 * have -undefined- behaviour.
2664 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2666 unsigned long bmdma = pci_resource_start(pdev, 4);
2672 simplex = inb(bmdma + 0x02);
2673 outb(simplex & 0x60, bmdma + 0x02);
2674 simplex = inb(bmdma + 0x02);
2679 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2682 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2683 * @host: target ATA host
2685 * Acquire PCI BMDMA resources and initialize @host accordingly.
2688 * Inherited from calling layer (may sleep).
2691 * 0 on success, -errno otherwise.
2693 int ata_pci_bmdma_init(struct ata_host *host)
2695 struct device *gdev = host->dev;
2696 struct pci_dev *pdev = to_pci_dev(gdev);
2699 /* No BAR4 allocation: No DMA */
2700 if (pci_resource_start(pdev, 4) == 0)
2703 /* TODO: If we get no DMA mask we should fall back to PIO */
2704 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2707 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2711 /* request and iomap DMA region */
2712 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2714 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2717 host->iomap = pcim_iomap_table(pdev);
2719 for (i = 0; i < 2; i++) {
2720 struct ata_port *ap = host->ports[i];
2721 void __iomem *bmdma = host->iomap[4] + 8 * i;
2723 if (ata_port_is_dummy(ap))
2726 ap->ioaddr.bmdma_addr = bmdma;
2727 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2728 (ioread8(bmdma + 2) & 0x80))
2729 host->flags |= ATA_HOST_SIMPLEX;
2731 ata_port_desc(ap, "bmdma 0x%llx",
2732 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2737 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2739 static int ata_resources_present(struct pci_dev *pdev, int port)
2743 /* Check the PCI resources for this channel are enabled */
2745 for (i = 0; i < 2; i++) {
2746 if (pci_resource_start(pdev, port + i) == 0 ||
2747 pci_resource_len(pdev, port + i) == 0)
2754 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2755 * @host: target ATA host
2757 * Acquire native PCI ATA resources for @host and initialize the
2758 * first two ports of @host accordingly. Ports marked dummy are
2759 * skipped and allocation failure makes the port dummy.
2761 * Note that native PCI resources are valid even for legacy hosts
2762 * as we fix up pdev resources array early in boot, so this
2763 * function can be used for both native and legacy SFF hosts.
2766 * Inherited from calling layer (may sleep).
2769 * 0 if at least one port is initialized, -ENODEV if no port is
2772 int ata_pci_sff_init_host(struct ata_host *host)
2774 struct device *gdev = host->dev;
2775 struct pci_dev *pdev = to_pci_dev(gdev);
2776 unsigned int mask = 0;
2779 /* request, iomap BARs and init port addresses accordingly */
2780 for (i = 0; i < 2; i++) {
2781 struct ata_port *ap = host->ports[i];
2783 void __iomem * const *iomap;
2785 if (ata_port_is_dummy(ap))
2788 /* Discard disabled ports. Some controllers show
2789 * their unused channels this way. Disabled ports are
2792 if (!ata_resources_present(pdev, i)) {
2793 ap->ops = &ata_dummy_port_ops;
2797 rc = pcim_iomap_regions(pdev, 0x3 << base,
2798 dev_driver_string(gdev));
2800 dev_printk(KERN_WARNING, gdev,
2801 "failed to request/iomap BARs for port %d "
2802 "(errno=%d)\n", i, rc);
2804 pcim_pin_device(pdev);
2805 ap->ops = &ata_dummy_port_ops;
2808 host->iomap = iomap = pcim_iomap_table(pdev);
2810 ap->ioaddr.cmd_addr = iomap[base];
2811 ap->ioaddr.altstatus_addr =
2812 ap->ioaddr.ctl_addr = (void __iomem *)
2813 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2814 ata_sff_std_ports(&ap->ioaddr);
2816 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2817 (unsigned long long)pci_resource_start(pdev, base),
2818 (unsigned long long)pci_resource_start(pdev, base + 1));
2824 dev_printk(KERN_ERR, gdev, "no available native port\n");
2830 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2833 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2834 * @pdev: target PCI device
2835 * @ppi: array of port_info, must be enough for two ports
2836 * @r_host: out argument for the initialized ATA host
2838 * Helper to allocate ATA host for @pdev, acquire all native PCI
2839 * resources and initialize it accordingly in one go.
2842 * Inherited from calling layer (may sleep).
2845 * 0 on success, -errno otherwise.
2847 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2848 const struct ata_port_info * const *ppi,
2849 struct ata_host **r_host)
2851 struct ata_host *host;
2854 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2857 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2859 dev_printk(KERN_ERR, &pdev->dev,
2860 "failed to allocate ATA host\n");
2865 rc = ata_pci_sff_init_host(host);
2869 /* init DMA related stuff */
2870 rc = ata_pci_bmdma_init(host);
2874 devres_remove_group(&pdev->dev, NULL);
2879 /* This is necessary because PCI and iomap resources are
2880 * merged and releasing the top group won't release the
2881 * acquired resources if some of those have been acquired
2882 * before entering this function.
2884 pcim_iounmap_regions(pdev, 0xf);
2886 devres_release_group(&pdev->dev, NULL);
2889 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2892 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2893 * @host: target SFF ATA host
2894 * @irq_handler: irq_handler used when requesting IRQ(s)
2895 * @sht: scsi_host_template to use when registering the host
2897 * This is the counterpart of ata_host_activate() for SFF ATA
2898 * hosts. This separate helper is necessary because SFF hosts
2899 * use two separate interrupts in legacy mode.
2902 * Inherited from calling layer (may sleep).
2905 * 0 on success, -errno otherwise.
2907 int ata_pci_sff_activate_host(struct ata_host *host,
2908 irq_handler_t irq_handler,
2909 struct scsi_host_template *sht)
2911 struct device *dev = host->dev;
2912 struct pci_dev *pdev = to_pci_dev(dev);
2913 const char *drv_name = dev_driver_string(host->dev);
2914 int legacy_mode = 0, rc;
2916 rc = ata_host_start(host);
2920 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2923 /* TODO: What if one channel is in native mode ... */
2924 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2925 mask = (1 << 2) | (1 << 0);
2926 if ((tmp8 & mask) != mask)
2928 #if defined(CONFIG_NO_ATA_LEGACY)
2929 /* Some platforms with PCI limits cannot address compat
2930 port space. In that case we punt if their firmware has
2931 left a device in compatibility mode */
2933 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2939 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2942 if (!legacy_mode && pdev->irq) {
2943 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2944 IRQF_SHARED, drv_name, host);
2948 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2949 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2950 } else if (legacy_mode) {
2951 if (!ata_port_is_dummy(host->ports[0])) {
2952 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2953 irq_handler, IRQF_SHARED,
2958 ata_port_desc(host->ports[0], "irq %d",
2959 ATA_PRIMARY_IRQ(pdev));
2962 if (!ata_port_is_dummy(host->ports[1])) {
2963 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2964 irq_handler, IRQF_SHARED,
2969 ata_port_desc(host->ports[1], "irq %d",
2970 ATA_SECONDARY_IRQ(pdev));
2974 rc = ata_host_register(host, sht);
2977 devres_remove_group(dev, NULL);
2979 devres_release_group(dev, NULL);
2983 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2986 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
2987 * @pdev: Controller to be initialized
2988 * @ppi: array of port_info, must be enough for two ports
2989 * @sht: scsi_host_template to use when registering the host
2990 * @host_priv: host private_data
2991 * @hflag: host flags
2993 * This is a helper function which can be called from a driver's
2994 * xxx_init_one() probe function if the hardware uses traditional
2995 * IDE taskfile registers.
2997 * This function calls pci_enable_device(), reserves its register
2998 * regions, sets the dma mask, enables bus master mode, and calls
3002 * Nobody makes a single channel controller that appears solely as
3003 * the secondary legacy port on PCI.
3006 * Inherited from PCI layer (may sleep).
3009 * Zero on success, negative on errno-based value on error.
3011 int ata_pci_sff_init_one(struct pci_dev *pdev,
3012 const struct ata_port_info * const *ppi,
3013 struct scsi_host_template *sht, void *host_priv, int hflag)
3015 struct device *dev = &pdev->dev;
3016 const struct ata_port_info *pi = NULL;
3017 struct ata_host *host = NULL;
3022 /* look up the first valid port_info */
3023 for (i = 0; i < 2 && ppi[i]; i++) {
3024 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
3031 dev_printk(KERN_ERR, &pdev->dev,
3032 "no valid port_info specified\n");
3036 if (!devres_open_group(dev, NULL, GFP_KERNEL))
3039 rc = pcim_enable_device(pdev);
3043 /* prepare and activate SFF host */
3044 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
3047 host->private_data = host_priv;
3048 host->flags |= hflag;
3050 pci_set_master(pdev);
3051 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
3054 devres_remove_group(&pdev->dev, NULL);
3056 devres_release_group(&pdev->dev, NULL);
3060 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
3062 #endif /* CONFIG_PCI */