arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  65         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  66 #define KVM_GUEST_CR0_MASK                                              \
  67         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  69         (X86_CR0_WP | X86_CR0_NE)
  70 #define KVM_VM_CR0_ALWAYS_ON                                            \
  71         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  72 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  73         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  74          | X86_CR4_OSXMMEXCPT)
  75
  76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  78
  79 /*
  80  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  81  * ple_gap:    upper bound on the amount of time between two successive
  82  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  83  *             According to test, this time is usually small than 41 cycles.
  84  * ple_window: upper bound on the amount of time a guest is allowed to execute
  85  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  86  *             less than 2^12 cycles
  87  * Time is measured based on a counter that runs at the same rate as the TSC,
  88  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  89  */
  90 #define KVM_VMX_DEFAULT_PLE_GAP    41
  91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  93 module_param(ple_gap, int, S_IRUGO);
  94
  95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  96 module_param(ple_window, int, S_IRUGO);
  97
  98 struct vmcs {
  99         u32 revision_id;
 100         u32 abort;
 101         char data[0];
 102 };
 103
 104 struct shared_msr_entry {
 105         unsigned index;
 106         u64 data;
 107         u64 mask;
 108 };
 109
 110 struct vcpu_vmx {
 111         struct kvm_vcpu       vcpu;
 112         struct list_head      local_vcpus_link;
 113         unsigned long         host_rsp;
 114         int                   launched;
 115         u8                    fail;
 116         u32                   idt_vectoring_info;
 117         struct shared_msr_entry *guest_msrs;
 118         int                   nmsrs;
 119         int                   save_nmsrs;
 120 #ifdef CONFIG_X86_64
 121         u64                   msr_host_kernel_gs_base;
 122         u64                   msr_guest_kernel_gs_base;
 123 #endif
 124         struct vmcs          *vmcs;
 125         struct {
 126                 int           loaded;
 127                 u16           fs_sel, gs_sel, ldt_sel;
 128                 int           gs_ldt_reload_needed;
 129                 int           fs_reload_needed;
 130         } host_state;
 131         struct {
 132                 int vm86_active;
 133                 u8 save_iopl;
 134                 struct kvm_save_segment {
 135                         u16 selector;
 136                         unsigned long base;
 137                         u32 limit;
 138                         u32 ar;
 139                 } tr, es, ds, fs, gs;
 140                 struct {
 141                         bool pending;
 142                         u8 vector;
 143                         unsigned rip;
 144                 } irq;
 145         } rmode;
 146         int vpid;
 147         bool emulation_required;
 148
 149         /* Support for vnmi-less CPUs */
 150         int soft_vnmi_blocked;
 151         ktime_t entry_time;
 152         s64 vnmi_blocked_time;
 153         u32 exit_reason;
 154
 155         bool rdtscp_enabled;
 156 };
 157
 158 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 159 {
 160         return container_of(vcpu, struct vcpu_vmx, vcpu);
 161 }
 162
 163 static int init_rmode(struct kvm *kvm);
 164 static u64 construct_eptp(unsigned long root_hpa);
 165
 166 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 167 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 168 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 169
 170 static unsigned long *vmx_io_bitmap_a;
 171 static unsigned long *vmx_io_bitmap_b;
 172 static unsigned long *vmx_msr_bitmap_legacy;
 173 static unsigned long *vmx_msr_bitmap_longmode;
 174
 175 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 176 static DEFINE_SPINLOCK(vmx_vpid_lock);
 177
 178 static struct vmcs_config {
 179         int size;
 180         int order;
 181         u32 revision_id;
 182         u32 pin_based_exec_ctrl;
 183         u32 cpu_based_exec_ctrl;
 184         u32 cpu_based_2nd_exec_ctrl;
 185         u32 vmexit_ctrl;
 186         u32 vmentry_ctrl;
 187 } vmcs_config;
 188
 189 static struct vmx_capability {
 190         u32 ept;
 191         u32 vpid;
 192 } vmx_capability;
 193
 194 #define VMX_SEGMENT_FIELD(seg)                                  \
 195         [VCPU_SREG_##seg] = {                                   \
 196                 .selector = GUEST_##seg##_SELECTOR,             \
 197                 .base = GUEST_##seg##_BASE,                     \
 198                 .limit = GUEST_##seg##_LIMIT,                   \
 199                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 200         }
 201
 202 static struct kvm_vmx_segment_field {
 203         unsigned selector;
 204         unsigned base;
 205         unsigned limit;
 206         unsigned ar_bytes;
 207 } kvm_vmx_segment_fields[] = {
 208         VMX_SEGMENT_FIELD(CS),
 209         VMX_SEGMENT_FIELD(DS),
 210         VMX_SEGMENT_FIELD(ES),
 211         VMX_SEGMENT_FIELD(FS),
 212         VMX_SEGMENT_FIELD(GS),
 213         VMX_SEGMENT_FIELD(SS),
 214         VMX_SEGMENT_FIELD(TR),
 215         VMX_SEGMENT_FIELD(LDTR),
 216 };
 217
 218 static u64 host_efer;
 219
 220 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 221
 222 /*
 223  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 224  * away by decrementing the array size.
 225  */
 226 static const u32 vmx_msr_index[] = {
 227 #ifdef CONFIG_X86_64
 228         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 229 #endif
 230         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 231 };
 232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 233
 234 static inline int is_page_fault(u32 intr_info)
 235 {
 236         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 237                              INTR_INFO_VALID_MASK)) ==
 238                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 239 }
 240
 241 static inline int is_no_device(u32 intr_info)
 242 {
 243         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 244                              INTR_INFO_VALID_MASK)) ==
 245                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 246 }
 247
 248 static inline int is_invalid_opcode(u32 intr_info)
 249 {
 250         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 251                              INTR_INFO_VALID_MASK)) ==
 252                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 253 }
 254
 255 static inline int is_external_interrupt(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 258                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline int is_machine_check(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline int cpu_has_vmx_msr_bitmap(void)
 269 {
 270         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 271 }
 272
 273 static inline int cpu_has_vmx_tpr_shadow(void)
 274 {
 275         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 276 }
 277
 278 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 279 {
 280         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 281 }
 282
 283 static inline int cpu_has_secondary_exec_ctrls(void)
 284 {
 285         return vmcs_config.cpu_based_exec_ctrl &
 286                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 287 }
 288
 289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 290 {
 291         return vmcs_config.cpu_based_2nd_exec_ctrl &
 292                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 293 }
 294
 295 static inline bool cpu_has_vmx_flexpriority(void)
 296 {
 297         return cpu_has_vmx_tpr_shadow() &&
 298                 cpu_has_vmx_virtualize_apic_accesses();
 299 }
 300
 301 static inline bool cpu_has_vmx_ept_execute_only(void)
 302 {
 303         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 304 }
 305
 306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 307 {
 308         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 309 }
 310
 311 static inline bool cpu_has_vmx_eptp_writeback(void)
 312 {
 313         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 314 }
 315
 316 static inline bool cpu_has_vmx_ept_2m_page(void)
 317 {
 318         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_1g_page(void)
 322 {
 323         return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
 324 }
 325
 326 static inline int cpu_has_vmx_invept_individual_addr(void)
 327 {
 328         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 329 }
 330
 331 static inline int cpu_has_vmx_invept_context(void)
 332 {
 333         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 334 }
 335
 336 static inline int cpu_has_vmx_invept_global(void)
 337 {
 338         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 339 }
 340
 341 static inline int cpu_has_vmx_ept(void)
 342 {
 343         return vmcs_config.cpu_based_2nd_exec_ctrl &
 344                 SECONDARY_EXEC_ENABLE_EPT;
 345 }
 346
 347 static inline int cpu_has_vmx_unrestricted_guest(void)
 348 {
 349         return vmcs_config.cpu_based_2nd_exec_ctrl &
 350                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 351 }
 352
 353 static inline int cpu_has_vmx_ple(void)
 354 {
 355         return vmcs_config.cpu_based_2nd_exec_ctrl &
 356                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 357 }
 358
 359 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 360 {
 361         return flexpriority_enabled && irqchip_in_kernel(kvm);
 362 }
 363
 364 static inline int cpu_has_vmx_vpid(void)
 365 {
 366         return vmcs_config.cpu_based_2nd_exec_ctrl &
 367                 SECONDARY_EXEC_ENABLE_VPID;
 368 }
 369
 370 static inline int cpu_has_vmx_rdtscp(void)
 371 {
 372         return vmcs_config.cpu_based_2nd_exec_ctrl &
 373                 SECONDARY_EXEC_RDTSCP;
 374 }
 375
 376 static inline int cpu_has_virtual_nmis(void)
 377 {
 378         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 379 }
 380
 381 static inline bool report_flexpriority(void)
 382 {
 383         return flexpriority_enabled;
 384 }
 385
 386 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 387 {
 388         int i;
 389
 390         for (i = 0; i < vmx->nmsrs; ++i)
 391                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 392                         return i;
 393         return -1;
 394 }
 395
 396 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 397 {
 398     struct {
 399         u64 vpid : 16;
 400         u64 rsvd : 48;
 401         u64 gva;
 402     } operand = { vpid, 0, gva };
 403
 404     asm volatile (__ex(ASM_VMX_INVVPID)
 405                   /* CF==1 or ZF==1 --> rc = -1 */
 406                   "; ja 1f ; ud2 ; 1:"
 407                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 408 }
 409
 410 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 411 {
 412         struct {
 413                 u64 eptp, gpa;
 414         } operand = {eptp, gpa};
 415
 416         asm volatile (__ex(ASM_VMX_INVEPT)
 417                         /* CF==1 or ZF==1 --> rc = -1 */
 418                         "; ja 1f ; ud2 ; 1:\n"
 419                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 420 }
 421
 422 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 423 {
 424         int i;
 425
 426         i = __find_msr_index(vmx, msr);
 427         if (i >= 0)
 428                 return &vmx->guest_msrs[i];
 429         return NULL;
 430 }
 431
 432 static void vmcs_clear(struct vmcs *vmcs)
 433 {
 434         u64 phys_addr = __pa(vmcs);
 435         u8 error;
 436
 437         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 438                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 439                       : "cc", "memory");
 440         if (error)
 441                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 442                        vmcs, phys_addr);
 443 }
 444
 445 static void __vcpu_clear(void *arg)
 446 {
 447         struct vcpu_vmx *vmx = arg;
 448         int cpu = raw_smp_processor_id();
 449
 450         if (vmx->vcpu.cpu == cpu)
 451                 vmcs_clear(vmx->vmcs);
 452         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 453                 per_cpu(current_vmcs, cpu) = NULL;
 454         rdtscll(vmx->vcpu.arch.host_tsc);
 455         list_del(&vmx->local_vcpus_link);
 456         vmx->vcpu.cpu = -1;
 457         vmx->launched = 0;
 458 }
 459
 460 static void vcpu_clear(struct vcpu_vmx *vmx)
 461 {
 462         if (vmx->vcpu.cpu == -1)
 463                 return;
 464         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 465 }
 466
 467 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 468 {
 469         if (vmx->vpid == 0)
 470                 return;
 471
 472         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 473 }
 474
 475 static inline void ept_sync_global(void)
 476 {
 477         if (cpu_has_vmx_invept_global())
 478                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 479 }
 480
 481 static inline void ept_sync_context(u64 eptp)
 482 {
 483         if (enable_ept) {
 484                 if (cpu_has_vmx_invept_context())
 485                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 486                 else
 487                         ept_sync_global();
 488         }
 489 }
 490
 491 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 492 {
 493         if (enable_ept) {
 494                 if (cpu_has_vmx_invept_individual_addr())
 495                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 496                                         eptp, gpa);
 497                 else
 498                         ept_sync_context(eptp);
 499         }
 500 }
 501
 502 static unsigned long vmcs_readl(unsigned long field)
 503 {
 504         unsigned long value;
 505
 506         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 507                       : "=a"(value) : "d"(field) : "cc");
 508         return value;
 509 }
 510
 511 static u16 vmcs_read16(unsigned long field)
 512 {
 513         return vmcs_readl(field);
 514 }
 515
 516 static u32 vmcs_read32(unsigned long field)
 517 {
 518         return vmcs_readl(field);
 519 }
 520
 521 static u64 vmcs_read64(unsigned long field)
 522 {
 523 #ifdef CONFIG_X86_64
 524         return vmcs_readl(field);
 525 #else
 526         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 527 #endif
 528 }
 529
 530 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 531 {
 532         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 533                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 534         dump_stack();
 535 }
 536
 537 static void vmcs_writel(unsigned long field, unsigned long value)
 538 {
 539         u8 error;
 540
 541         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 542                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 543         if (unlikely(error))
 544                 vmwrite_error(field, value);
 545 }
 546
 547 static void vmcs_write16(unsigned long field, u16 value)
 548 {
 549         vmcs_writel(field, value);
 550 }
 551
 552 static void vmcs_write32(unsigned long field, u32 value)
 553 {
 554         vmcs_writel(field, value);
 555 }
 556
 557 static void vmcs_write64(unsigned long field, u64 value)
 558 {
 559         vmcs_writel(field, value);
 560 #ifndef CONFIG_X86_64
 561         asm volatile ("");
 562         vmcs_writel(field+1, value >> 32);
 563 #endif
 564 }
 565
 566 static void vmcs_clear_bits(unsigned long field, u32 mask)
 567 {
 568         vmcs_writel(field, vmcs_readl(field) & ~mask);
 569 }
 570
 571 static void vmcs_set_bits(unsigned long field, u32 mask)
 572 {
 573         vmcs_writel(field, vmcs_readl(field) | mask);
 574 }
 575
 576 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 577 {
 578         u32 eb;
 579
 580         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 581              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 582         if ((vcpu->guest_debug &
 583              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 584             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 585                 eb |= 1u << BP_VECTOR;
 586         if (to_vmx(vcpu)->rmode.vm86_active)
 587                 eb = ~0;
 588         if (enable_ept)
 589                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 590         if (vcpu->fpu_active)
 591                 eb &= ~(1u << NM_VECTOR);
 592         vmcs_write32(EXCEPTION_BITMAP, eb);
 593 }
 594
 595 static void reload_tss(void)
 596 {
 597         /*
 598          * VT restores TR but not its size.  Useless.
 599          */
 600         struct descriptor_table gdt;
 601         struct desc_struct *descs;
 602
 603         kvm_get_gdt(&gdt);
 604         descs = (void *)gdt.base;
 605         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 606         load_TR_desc();
 607 }
 608
 609 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 610 {
 611         u64 guest_efer;
 612         u64 ignore_bits;
 613
 614         guest_efer = vmx->vcpu.arch.efer;
 615
 616         /*
 617          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 618          * outside long mode
 619          */
 620         ignore_bits = EFER_NX | EFER_SCE;
 621 #ifdef CONFIG_X86_64
 622         ignore_bits |= EFER_LMA | EFER_LME;
 623         /* SCE is meaningful only in long mode on Intel */
 624         if (guest_efer & EFER_LMA)
 625                 ignore_bits &= ~(u64)EFER_SCE;
 626 #endif
 627         guest_efer &= ~ignore_bits;
 628         guest_efer |= host_efer & ignore_bits;
 629         vmx->guest_msrs[efer_offset].data = guest_efer;
 630         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 631         return true;
 632 }
 633
 634 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 635 {
 636         struct vcpu_vmx *vmx = to_vmx(vcpu);
 637         int i;
 638
 639         if (vmx->host_state.loaded)
 640                 return;
 641
 642         vmx->host_state.loaded = 1;
 643         /*
 644          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 645          * allow segment selectors with cpl > 0 or ti == 1.
 646          */
 647         vmx->host_state.ldt_sel = kvm_read_ldt();
 648         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 649         vmx->host_state.fs_sel = kvm_read_fs();
 650         if (!(vmx->host_state.fs_sel & 7)) {
 651                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 652                 vmx->host_state.fs_reload_needed = 0;
 653         } else {
 654                 vmcs_write16(HOST_FS_SELECTOR, 0);
 655                 vmx->host_state.fs_reload_needed = 1;
 656         }
 657         vmx->host_state.gs_sel = kvm_read_gs();
 658         if (!(vmx->host_state.gs_sel & 7))
 659                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 660         else {
 661                 vmcs_write16(HOST_GS_SELECTOR, 0);
 662                 vmx->host_state.gs_ldt_reload_needed = 1;
 663         }
 664
 665 #ifdef CONFIG_X86_64
 666         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 667         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 668 #else
 669         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 670         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 671 #endif
 672
 673 #ifdef CONFIG_X86_64
 674         if (is_long_mode(&vmx->vcpu)) {
 675                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 676                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 677         }
 678 #endif
 679         for (i = 0; i < vmx->save_nmsrs; ++i)
 680                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 681                                    vmx->guest_msrs[i].data,
 682                                    vmx->guest_msrs[i].mask);
 683 }
 684
 685 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 686 {
 687         unsigned long flags;
 688
 689         if (!vmx->host_state.loaded)
 690                 return;
 691
 692         ++vmx->vcpu.stat.host_state_reload;
 693         vmx->host_state.loaded = 0;
 694         if (vmx->host_state.fs_reload_needed)
 695                 kvm_load_fs(vmx->host_state.fs_sel);
 696         if (vmx->host_state.gs_ldt_reload_needed) {
 697                 kvm_load_ldt(vmx->host_state.ldt_sel);
 698                 /*
 699                  * If we have to reload gs, we must take care to
 700                  * preserve our gs base.
 701                  */
 702                 local_irq_save(flags);
 703                 kvm_load_gs(vmx->host_state.gs_sel);
 704 #ifdef CONFIG_X86_64
 705                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 706 #endif
 707                 local_irq_restore(flags);
 708         }
 709         reload_tss();
 710 #ifdef CONFIG_X86_64
 711         if (is_long_mode(&vmx->vcpu)) {
 712                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 713                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 714         }
 715 #endif
 716 }
 717
 718 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 719 {
 720         preempt_disable();
 721         __vmx_load_host_state(vmx);
 722         preempt_enable();
 723 }
 724
 725 /*
 726  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 727  * vcpu mutex is already taken.
 728  */
 729 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 730 {
 731         struct vcpu_vmx *vmx = to_vmx(vcpu);
 732         u64 phys_addr = __pa(vmx->vmcs);
 733         u64 tsc_this, delta, new_offset;
 734
 735         if (vcpu->cpu != cpu) {
 736                 vcpu_clear(vmx);
 737                 kvm_migrate_timers(vcpu);
 738                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 739                 local_irq_disable();
 740                 list_add(&vmx->local_vcpus_link,
 741                          &per_cpu(vcpus_on_cpu, cpu));
 742                 local_irq_enable();
 743         }
 744
 745         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 746                 u8 error;
 747
 748                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 749                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 750                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 751                               : "cc");
 752                 if (error)
 753                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 754                                vmx->vmcs, phys_addr);
 755         }
 756
 757         if (vcpu->cpu != cpu) {
 758                 struct descriptor_table dt;
 759                 unsigned long sysenter_esp;
 760
 761                 vcpu->cpu = cpu;
 762                 /*
 763                  * Linux uses per-cpu TSS and GDT, so set these when switching
 764                  * processors.
 765                  */
 766                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 767                 kvm_get_gdt(&dt);
 768                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 769
 770                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 771                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 772
 773                 /*
 774                  * Make sure the time stamp counter is monotonous.
 775                  */
 776                 rdtscll(tsc_this);
 777                 if (tsc_this < vcpu->arch.host_tsc) {
 778                         delta = vcpu->arch.host_tsc - tsc_this;
 779                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 780                         vmcs_write64(TSC_OFFSET, new_offset);
 781                 }
 782         }
 783 }
 784
 785 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 786 {
 787         __vmx_load_host_state(to_vmx(vcpu));
 788 }
 789
 790 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 791 {
 792         ulong cr0;
 793
 794         if (vcpu->fpu_active)
 795                 return;
 796         vcpu->fpu_active = 1;
 797         cr0 = vmcs_readl(GUEST_CR0);
 798         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 799         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 800         vmcs_writel(GUEST_CR0, cr0);
 801         update_exception_bitmap(vcpu);
 802         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 803         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 804 }
 805
 806 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 807
 808 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 809 {
 810         vmx_decache_cr0_guest_bits(vcpu);
 811         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 812         update_exception_bitmap(vcpu);
 813         vcpu->arch.cr0_guest_owned_bits = 0;
 814         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 815         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 816 }
 817
 818 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 819 {
 820         unsigned long rflags;
 821
 822         rflags = vmcs_readl(GUEST_RFLAGS);
 823         if (to_vmx(vcpu)->rmode.vm86_active)
 824                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 825         return rflags;
 826 }
 827
 828 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 829 {
 830         if (to_vmx(vcpu)->rmode.vm86_active)
 831                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 832         vmcs_writel(GUEST_RFLAGS, rflags);
 833 }
 834
 835 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 836 {
 837         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 838         int ret = 0;
 839
 840         if (interruptibility & GUEST_INTR_STATE_STI)
 841                 ret |= X86_SHADOW_INT_STI;
 842         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 843                 ret |= X86_SHADOW_INT_MOV_SS;
 844
 845         return ret & mask;
 846 }
 847
 848 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 849 {
 850         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 851         u32 interruptibility = interruptibility_old;
 852
 853         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 854
 855         if (mask & X86_SHADOW_INT_MOV_SS)
 856                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 857         if (mask & X86_SHADOW_INT_STI)
 858                 interruptibility |= GUEST_INTR_STATE_STI;
 859
 860         if ((interruptibility != interruptibility_old))
 861                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 862 }
 863
 864 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 865 {
 866         unsigned long rip;
 867
 868         rip = kvm_rip_read(vcpu);
 869         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 870         kvm_rip_write(vcpu, rip);
 871
 872         /* skipping an emulated instruction also counts */
 873         vmx_set_interrupt_shadow(vcpu, 0);
 874 }
 875
 876 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 877                                 bool has_error_code, u32 error_code)
 878 {
 879         struct vcpu_vmx *vmx = to_vmx(vcpu);
 880         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 881
 882         if (has_error_code) {
 883                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 884                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 885         }
 886
 887         if (vmx->rmode.vm86_active) {
 888                 vmx->rmode.irq.pending = true;
 889                 vmx->rmode.irq.vector = nr;
 890                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 891                 if (kvm_exception_is_soft(nr))
 892                         vmx->rmode.irq.rip +=
 893                                 vmx->vcpu.arch.event_exit_inst_len;
 894                 intr_info |= INTR_TYPE_SOFT_INTR;
 895                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 896                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 897                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 898                 return;
 899         }
 900
 901         if (kvm_exception_is_soft(nr)) {
 902                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 903                              vmx->vcpu.arch.event_exit_inst_len);
 904                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 905         } else
 906                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 907
 908         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 909 }
 910
 911 static bool vmx_rdtscp_supported(void)
 912 {
 913         return cpu_has_vmx_rdtscp();
 914 }
 915
 916 /*
 917  * Swap MSR entry in host/guest MSR entry array.
 918  */
 919 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 920 {
 921         struct shared_msr_entry tmp;
 922
 923         tmp = vmx->guest_msrs[to];
 924         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 925         vmx->guest_msrs[from] = tmp;
 926 }
 927
 928 /*
 929  * Set up the vmcs to automatically save and restore system
 930  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 931  * mode, as fiddling with msrs is very expensive.
 932  */
 933 static void setup_msrs(struct vcpu_vmx *vmx)
 934 {
 935         int save_nmsrs, index;
 936         unsigned long *msr_bitmap;
 937
 938         vmx_load_host_state(vmx);
 939         save_nmsrs = 0;
 940 #ifdef CONFIG_X86_64
 941         if (is_long_mode(&vmx->vcpu)) {
 942                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 943                 if (index >= 0)
 944                         move_msr_up(vmx, index, save_nmsrs++);
 945                 index = __find_msr_index(vmx, MSR_LSTAR);
 946                 if (index >= 0)
 947                         move_msr_up(vmx, index, save_nmsrs++);
 948                 index = __find_msr_index(vmx, MSR_CSTAR);
 949                 if (index >= 0)
 950                         move_msr_up(vmx, index, save_nmsrs++);
 951                 index = __find_msr_index(vmx, MSR_TSC_AUX);
 952                 if (index >= 0 && vmx->rdtscp_enabled)
 953                         move_msr_up(vmx, index, save_nmsrs++);
 954                 /*
 955                  * MSR_K6_STAR is only needed on long mode guests, and only
 956                  * if efer.sce is enabled.
 957                  */
 958                 index = __find_msr_index(vmx, MSR_K6_STAR);
 959                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
 960                         move_msr_up(vmx, index, save_nmsrs++);
 961         }
 962 #endif
 963         index = __find_msr_index(vmx, MSR_EFER);
 964         if (index >= 0 && update_transition_efer(vmx, index))
 965                 move_msr_up(vmx, index, save_nmsrs++);
 966
 967         vmx->save_nmsrs = save_nmsrs;
 968
 969         if (cpu_has_vmx_msr_bitmap()) {
 970                 if (is_long_mode(&vmx->vcpu))
 971                         msr_bitmap = vmx_msr_bitmap_longmode;
 972                 else
 973                         msr_bitmap = vmx_msr_bitmap_legacy;
 974
 975                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 976         }
 977 }
 978
 979 /*
 980  * reads and returns guest's timestamp counter "register"
 981  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 982  */
 983 static u64 guest_read_tsc(void)
 984 {
 985         u64 host_tsc, tsc_offset;
 986
 987         rdtscll(host_tsc);
 988         tsc_offset = vmcs_read64(TSC_OFFSET);
 989         return host_tsc + tsc_offset;
 990 }
 991
 992 /*
 993  * writes 'guest_tsc' into guest's timestamp counter "register"
 994  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 995  */
 996 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 997 {
 998         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 999 }
1000
1001 /*
1002  * Reads an msr value (of 'msr_index') into 'pdata'.
1003  * Returns 0 on success, non-0 otherwise.
1004  * Assumes vcpu_load() was already called.
1005  */
1006 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1007 {
1008         u64 data;
1009         struct shared_msr_entry *msr;
1010
1011         if (!pdata) {
1012                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1013                 return -EINVAL;
1014         }
1015
1016         switch (msr_index) {
1017 #ifdef CONFIG_X86_64
1018         case MSR_FS_BASE:
1019                 data = vmcs_readl(GUEST_FS_BASE);
1020                 break;
1021         case MSR_GS_BASE:
1022                 data = vmcs_readl(GUEST_GS_BASE);
1023                 break;
1024         case MSR_KERNEL_GS_BASE:
1025                 vmx_load_host_state(to_vmx(vcpu));
1026                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1027                 break;
1028 #endif
1029         case MSR_EFER:
1030                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1031         case MSR_IA32_TSC:
1032                 data = guest_read_tsc();
1033                 break;
1034         case MSR_IA32_SYSENTER_CS:
1035                 data = vmcs_read32(GUEST_SYSENTER_CS);
1036                 break;
1037         case MSR_IA32_SYSENTER_EIP:
1038                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1039                 break;
1040         case MSR_IA32_SYSENTER_ESP:
1041                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1042                 break;
1043         case MSR_TSC_AUX:
1044                 if (!to_vmx(vcpu)->rdtscp_enabled)
1045                         return 1;
1046                 /* Otherwise falls through */
1047         default:
1048                 vmx_load_host_state(to_vmx(vcpu));
1049                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1050                 if (msr) {
1051                         vmx_load_host_state(to_vmx(vcpu));
1052                         data = msr->data;
1053                         break;
1054                 }
1055                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1056         }
1057
1058         *pdata = data;
1059         return 0;
1060 }
1061
1062 /*
1063  * Writes msr value into into the appropriate "register".
1064  * Returns 0 on success, non-0 otherwise.
1065  * Assumes vcpu_load() was already called.
1066  */
1067 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1068 {
1069         struct vcpu_vmx *vmx = to_vmx(vcpu);
1070         struct shared_msr_entry *msr;
1071         u64 host_tsc;
1072         int ret = 0;
1073
1074         switch (msr_index) {
1075         case MSR_EFER:
1076                 vmx_load_host_state(vmx);
1077                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1078                 break;
1079 #ifdef CONFIG_X86_64
1080         case MSR_FS_BASE:
1081                 vmcs_writel(GUEST_FS_BASE, data);
1082                 break;
1083         case MSR_GS_BASE:
1084                 vmcs_writel(GUEST_GS_BASE, data);
1085                 break;
1086         case MSR_KERNEL_GS_BASE:
1087                 vmx_load_host_state(vmx);
1088                 vmx->msr_guest_kernel_gs_base = data;
1089                 break;
1090 #endif
1091         case MSR_IA32_SYSENTER_CS:
1092                 vmcs_write32(GUEST_SYSENTER_CS, data);
1093                 break;
1094         case MSR_IA32_SYSENTER_EIP:
1095                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1096                 break;
1097         case MSR_IA32_SYSENTER_ESP:
1098                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1099                 break;
1100         case MSR_IA32_TSC:
1101                 rdtscll(host_tsc);
1102                 guest_write_tsc(data, host_tsc);
1103                 break;
1104         case MSR_IA32_CR_PAT:
1105                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1106                         vmcs_write64(GUEST_IA32_PAT, data);
1107                         vcpu->arch.pat = data;
1108                         break;
1109                 }
1110                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1111                 break;
1112         case MSR_TSC_AUX:
1113                 if (!vmx->rdtscp_enabled)
1114                         return 1;
1115                 /* Check reserved bit, higher 32 bits should be zero */
1116                 if ((data >> 32) != 0)
1117                         return 1;
1118                 /* Otherwise falls through */
1119         default:
1120                 msr = find_msr_entry(vmx, msr_index);
1121                 if (msr) {
1122                         vmx_load_host_state(vmx);
1123                         msr->data = data;
1124                         break;
1125                 }
1126                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1127         }
1128
1129         return ret;
1130 }
1131
1132 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1133 {
1134         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1135         switch (reg) {
1136         case VCPU_REGS_RSP:
1137                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1138                 break;
1139         case VCPU_REGS_RIP:
1140                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1141                 break;
1142         case VCPU_EXREG_PDPTR:
1143                 if (enable_ept)
1144                         ept_save_pdptrs(vcpu);
1145                 break;
1146         default:
1147                 break;
1148         }
1149 }
1150
1151 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1152 {
1153         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1154                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1155         else
1156                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1157
1158         update_exception_bitmap(vcpu);
1159 }
1160
1161 static __init int cpu_has_kvm_support(void)
1162 {
1163         return cpu_has_vmx();
1164 }
1165
1166 static __init int vmx_disabled_by_bios(void)
1167 {
1168         u64 msr;
1169
1170         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1171         return (msr & (FEATURE_CONTROL_LOCKED |
1172                        FEATURE_CONTROL_VMXON_ENABLED))
1173             == FEATURE_CONTROL_LOCKED;
1174         /* locked but not enabled */
1175 }
1176
1177 static int hardware_enable(void *garbage)
1178 {
1179         int cpu = raw_smp_processor_id();
1180         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1181         u64 old;
1182
1183         if (read_cr4() & X86_CR4_VMXE)
1184                 return -EBUSY;
1185
1186         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1187         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1188         if ((old & (FEATURE_CONTROL_LOCKED |
1189                     FEATURE_CONTROL_VMXON_ENABLED))
1190             != (FEATURE_CONTROL_LOCKED |
1191                 FEATURE_CONTROL_VMXON_ENABLED))
1192                 /* enable and lock */
1193                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1194                        FEATURE_CONTROL_LOCKED |
1195                        FEATURE_CONTROL_VMXON_ENABLED);
1196         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1197         asm volatile (ASM_VMX_VMXON_RAX
1198                       : : "a"(&phys_addr), "m"(phys_addr)
1199                       : "memory", "cc");
1200
1201         ept_sync_global();
1202
1203         return 0;
1204 }
1205
1206 static void vmclear_local_vcpus(void)
1207 {
1208         int cpu = raw_smp_processor_id();
1209         struct vcpu_vmx *vmx, *n;
1210
1211         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1212                                  local_vcpus_link)
1213                 __vcpu_clear(vmx);
1214 }
1215
1216
1217 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1218  * tricks.
1219  */
1220 static void kvm_cpu_vmxoff(void)
1221 {
1222         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1223         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1224 }
1225
1226 static void hardware_disable(void *garbage)
1227 {
1228         vmclear_local_vcpus();
1229         kvm_cpu_vmxoff();
1230 }
1231
1232 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1233                                       u32 msr, u32 *result)
1234 {
1235         u32 vmx_msr_low, vmx_msr_high;
1236         u32 ctl = ctl_min | ctl_opt;
1237
1238         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1239
1240         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1241         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1242
1243         /* Ensure minimum (required) set of control bits are supported. */
1244         if (ctl_min & ~ctl)
1245                 return -EIO;
1246
1247         *result = ctl;
1248         return 0;
1249 }
1250
1251 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1252 {
1253         u32 vmx_msr_low, vmx_msr_high;
1254         u32 min, opt, min2, opt2;
1255         u32 _pin_based_exec_control = 0;
1256         u32 _cpu_based_exec_control = 0;
1257         u32 _cpu_based_2nd_exec_control = 0;
1258         u32 _vmexit_control = 0;
1259         u32 _vmentry_control = 0;
1260
1261         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1262         opt = PIN_BASED_VIRTUAL_NMIS;
1263         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1264                                 &_pin_based_exec_control) < 0)
1265                 return -EIO;
1266
1267         min = CPU_BASED_HLT_EXITING |
1268 #ifdef CONFIG_X86_64
1269               CPU_BASED_CR8_LOAD_EXITING |
1270               CPU_BASED_CR8_STORE_EXITING |
1271 #endif
1272               CPU_BASED_CR3_LOAD_EXITING |
1273               CPU_BASED_CR3_STORE_EXITING |
1274               CPU_BASED_USE_IO_BITMAPS |
1275               CPU_BASED_MOV_DR_EXITING |
1276               CPU_BASED_USE_TSC_OFFSETING |
1277               CPU_BASED_MWAIT_EXITING |
1278               CPU_BASED_MONITOR_EXITING |
1279               CPU_BASED_INVLPG_EXITING;
1280         opt = CPU_BASED_TPR_SHADOW |
1281               CPU_BASED_USE_MSR_BITMAPS |
1282               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1283         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1284                                 &_cpu_based_exec_control) < 0)
1285                 return -EIO;
1286 #ifdef CONFIG_X86_64
1287         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1288                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1289                                            ~CPU_BASED_CR8_STORE_EXITING;
1290 #endif
1291         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1292                 min2 = 0;
1293                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1294                         SECONDARY_EXEC_WBINVD_EXITING |
1295                         SECONDARY_EXEC_ENABLE_VPID |
1296                         SECONDARY_EXEC_ENABLE_EPT |
1297                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1298                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1299                         SECONDARY_EXEC_RDTSCP;
1300                 if (adjust_vmx_controls(min2, opt2,
1301                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1302                                         &_cpu_based_2nd_exec_control) < 0)
1303                         return -EIO;
1304         }
1305 #ifndef CONFIG_X86_64
1306         if (!(_cpu_based_2nd_exec_control &
1307                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1308                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1309 #endif
1310         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1311                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1312                    enabled */
1313                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1314                                              CPU_BASED_CR3_STORE_EXITING |
1315                                              CPU_BASED_INVLPG_EXITING);
1316                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1317                       vmx_capability.ept, vmx_capability.vpid);
1318         }
1319
1320         min = 0;
1321 #ifdef CONFIG_X86_64
1322         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1323 #endif
1324         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1325         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1326                                 &_vmexit_control) < 0)
1327                 return -EIO;
1328
1329         min = 0;
1330         opt = VM_ENTRY_LOAD_IA32_PAT;
1331         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1332                                 &_vmentry_control) < 0)
1333                 return -EIO;
1334
1335         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1336
1337         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1338         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1339                 return -EIO;
1340
1341 #ifdef CONFIG_X86_64
1342         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1343         if (vmx_msr_high & (1u<<16))
1344                 return -EIO;
1345 #endif
1346
1347         /* Require Write-Back (WB) memory type for VMCS accesses. */
1348         if (((vmx_msr_high >> 18) & 15) != 6)
1349                 return -EIO;
1350
1351         vmcs_conf->size = vmx_msr_high & 0x1fff;
1352         vmcs_conf->order = get_order(vmcs_config.size);
1353         vmcs_conf->revision_id = vmx_msr_low;
1354
1355         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1356         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1357         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1358         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1359         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1360
1361         return 0;
1362 }
1363
1364 static struct vmcs *alloc_vmcs_cpu(int cpu)
1365 {
1366         int node = cpu_to_node(cpu);
1367         struct page *pages;
1368         struct vmcs *vmcs;
1369
1370         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1371         if (!pages)
1372                 return NULL;
1373         vmcs = page_address(pages);
1374         memset(vmcs, 0, vmcs_config.size);
1375         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1376         return vmcs;
1377 }
1378
1379 static struct vmcs *alloc_vmcs(void)
1380 {
1381         return alloc_vmcs_cpu(raw_smp_processor_id());
1382 }
1383
1384 static void free_vmcs(struct vmcs *vmcs)
1385 {
1386         free_pages((unsigned long)vmcs, vmcs_config.order);
1387 }
1388
1389 static void free_kvm_area(void)
1390 {
1391         int cpu;
1392
1393         for_each_possible_cpu(cpu) {
1394                 free_vmcs(per_cpu(vmxarea, cpu));
1395                 per_cpu(vmxarea, cpu) = NULL;
1396         }
1397 }
1398
1399 static __init int alloc_kvm_area(void)
1400 {
1401         int cpu;
1402
1403         for_each_possible_cpu(cpu) {
1404                 struct vmcs *vmcs;
1405
1406                 vmcs = alloc_vmcs_cpu(cpu);
1407                 if (!vmcs) {
1408                         free_kvm_area();
1409                         return -ENOMEM;
1410                 }
1411
1412                 per_cpu(vmxarea, cpu) = vmcs;
1413         }
1414         return 0;
1415 }
1416
1417 static __init int hardware_setup(void)
1418 {
1419         if (setup_vmcs_config(&vmcs_config) < 0)
1420                 return -EIO;
1421
1422         if (boot_cpu_has(X86_FEATURE_NX))
1423                 kvm_enable_efer_bits(EFER_NX);
1424
1425         if (!cpu_has_vmx_vpid())
1426                 enable_vpid = 0;
1427
1428         if (!cpu_has_vmx_ept()) {
1429                 enable_ept = 0;
1430                 enable_unrestricted_guest = 0;
1431         }
1432
1433         if (!cpu_has_vmx_unrestricted_guest())
1434                 enable_unrestricted_guest = 0;
1435
1436         if (!cpu_has_vmx_flexpriority())
1437                 flexpriority_enabled = 0;
1438
1439         if (!cpu_has_vmx_tpr_shadow())
1440                 kvm_x86_ops->update_cr8_intercept = NULL;
1441
1442         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1443                 kvm_disable_largepages();
1444
1445         if (!cpu_has_vmx_ple())
1446                 ple_gap = 0;
1447
1448         return alloc_kvm_area();
1449 }
1450
1451 static __exit void hardware_unsetup(void)
1452 {
1453         free_kvm_area();
1454 }
1455
1456 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1457 {
1458         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1459
1460         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1461                 vmcs_write16(sf->selector, save->selector);
1462                 vmcs_writel(sf->base, save->base);
1463                 vmcs_write32(sf->limit, save->limit);
1464                 vmcs_write32(sf->ar_bytes, save->ar);
1465         } else {
1466                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1467                         << AR_DPL_SHIFT;
1468                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1469         }
1470 }
1471
1472 static void enter_pmode(struct kvm_vcpu *vcpu)
1473 {
1474         unsigned long flags;
1475         struct vcpu_vmx *vmx = to_vmx(vcpu);
1476
1477         vmx->emulation_required = 1;
1478         vmx->rmode.vm86_active = 0;
1479
1480         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1481         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1482         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1483
1484         flags = vmcs_readl(GUEST_RFLAGS);
1485         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1486         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1487         vmcs_writel(GUEST_RFLAGS, flags);
1488
1489         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1490                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1491
1492         update_exception_bitmap(vcpu);
1493
1494         if (emulate_invalid_guest_state)
1495                 return;
1496
1497         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1498         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1499         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1500         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1501
1502         vmcs_write16(GUEST_SS_SELECTOR, 0);
1503         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1504
1505         vmcs_write16(GUEST_CS_SELECTOR,
1506                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1507         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1508 }
1509
1510 static gva_t rmode_tss_base(struct kvm *kvm)
1511 {
1512         if (!kvm->arch.tss_addr) {
1513                 struct kvm_memslots *slots;
1514                 gfn_t base_gfn;
1515
1516                 slots = rcu_dereference(kvm->memslots);
1517                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1518                                  kvm->memslots->memslots[0].npages - 3;
1519                 return base_gfn << PAGE_SHIFT;
1520         }
1521         return kvm->arch.tss_addr;
1522 }
1523
1524 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1525 {
1526         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1527
1528         save->selector = vmcs_read16(sf->selector);
1529         save->base = vmcs_readl(sf->base);
1530         save->limit = vmcs_read32(sf->limit);
1531         save->ar = vmcs_read32(sf->ar_bytes);
1532         vmcs_write16(sf->selector, save->base >> 4);
1533         vmcs_write32(sf->base, save->base & 0xfffff);
1534         vmcs_write32(sf->limit, 0xffff);
1535         vmcs_write32(sf->ar_bytes, 0xf3);
1536 }
1537
1538 static void enter_rmode(struct kvm_vcpu *vcpu)
1539 {
1540         unsigned long flags;
1541         struct vcpu_vmx *vmx = to_vmx(vcpu);
1542
1543         if (enable_unrestricted_guest)
1544                 return;
1545
1546         vmx->emulation_required = 1;
1547         vmx->rmode.vm86_active = 1;
1548
1549         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1550         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1551
1552         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1553         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1554
1555         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1556         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1557
1558         flags = vmcs_readl(GUEST_RFLAGS);
1559         vmx->rmode.save_iopl
1560                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1561
1562         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1563
1564         vmcs_writel(GUEST_RFLAGS, flags);
1565         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1566         update_exception_bitmap(vcpu);
1567
1568         if (emulate_invalid_guest_state)
1569                 goto continue_rmode;
1570
1571         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1572         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1573         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1574
1575         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1576         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1577         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1578                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1579         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1580
1581         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1582         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1583         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1584         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1585
1586 continue_rmode:
1587         kvm_mmu_reset_context(vcpu);
1588         init_rmode(vcpu->kvm);
1589 }
1590
1591 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1592 {
1593         struct vcpu_vmx *vmx = to_vmx(vcpu);
1594         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1595
1596         if (!msr)
1597                 return;
1598
1599         /*
1600          * Force kernel_gs_base reloading before EFER changes, as control
1601          * of this msr depends on is_long_mode().
1602          */
1603         vmx_load_host_state(to_vmx(vcpu));
1604         vcpu->arch.efer = efer;
1605         if (!msr)
1606                 return;
1607         if (efer & EFER_LMA) {
1608                 vmcs_write32(VM_ENTRY_CONTROLS,
1609                              vmcs_read32(VM_ENTRY_CONTROLS) |
1610                              VM_ENTRY_IA32E_MODE);
1611                 msr->data = efer;
1612         } else {
1613                 vmcs_write32(VM_ENTRY_CONTROLS,
1614                              vmcs_read32(VM_ENTRY_CONTROLS) &
1615                              ~VM_ENTRY_IA32E_MODE);
1616
1617                 msr->data = efer & ~EFER_LME;
1618         }
1619         setup_msrs(vmx);
1620 }
1621
1622 #ifdef CONFIG_X86_64
1623
1624 static void enter_lmode(struct kvm_vcpu *vcpu)
1625 {
1626         u32 guest_tr_ar;
1627
1628         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1629         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1630                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1631                        __func__);
1632                 vmcs_write32(GUEST_TR_AR_BYTES,
1633                              (guest_tr_ar & ~AR_TYPE_MASK)
1634                              | AR_TYPE_BUSY_64_TSS);
1635         }
1636         vcpu->arch.efer |= EFER_LMA;
1637         vmx_set_efer(vcpu, vcpu->arch.efer);
1638 }
1639
1640 static void exit_lmode(struct kvm_vcpu *vcpu)
1641 {
1642         vcpu->arch.efer &= ~EFER_LMA;
1643
1644         vmcs_write32(VM_ENTRY_CONTROLS,
1645                      vmcs_read32(VM_ENTRY_CONTROLS)
1646                      & ~VM_ENTRY_IA32E_MODE);
1647 }
1648
1649 #endif
1650
1651 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1652 {
1653         vpid_sync_vcpu_all(to_vmx(vcpu));
1654         if (enable_ept)
1655                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1656 }
1657
1658 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1659 {
1660         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1661
1662         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1663         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1664 }
1665
1666 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1667 {
1668         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1669
1670         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1671         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1672 }
1673
1674 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1675 {
1676         if (!test_bit(VCPU_EXREG_PDPTR,
1677                       (unsigned long *)&vcpu->arch.regs_dirty))
1678                 return;
1679
1680         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1681                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1682                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1683                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1684                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1685         }
1686 }
1687
1688 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1689 {
1690         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1691                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1692                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1693                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1694                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1695         }
1696
1697         __set_bit(VCPU_EXREG_PDPTR,
1698                   (unsigned long *)&vcpu->arch.regs_avail);
1699         __set_bit(VCPU_EXREG_PDPTR,
1700                   (unsigned long *)&vcpu->arch.regs_dirty);
1701 }
1702
1703 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1704
1705 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1706                                         unsigned long cr0,
1707                                         struct kvm_vcpu *vcpu)
1708 {
1709         if (!(cr0 & X86_CR0_PG)) {
1710                 /* From paging/starting to nonpaging */
1711                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1712                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1713                              (CPU_BASED_CR3_LOAD_EXITING |
1714                               CPU_BASED_CR3_STORE_EXITING));
1715                 vcpu->arch.cr0 = cr0;
1716                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1717         } else if (!is_paging(vcpu)) {
1718                 /* From nonpaging to paging */
1719                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1720                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1721                              ~(CPU_BASED_CR3_LOAD_EXITING |
1722                                CPU_BASED_CR3_STORE_EXITING));
1723                 vcpu->arch.cr0 = cr0;
1724                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1725         }
1726
1727         if (!(cr0 & X86_CR0_WP))
1728                 *hw_cr0 &= ~X86_CR0_WP;
1729 }
1730
1731 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1732 {
1733         struct vcpu_vmx *vmx = to_vmx(vcpu);
1734         unsigned long hw_cr0;
1735
1736         if (enable_unrestricted_guest)
1737                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1738                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1739         else
1740                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1741
1742         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1743                 enter_pmode(vcpu);
1744
1745         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1746                 enter_rmode(vcpu);
1747
1748 #ifdef CONFIG_X86_64
1749         if (vcpu->arch.efer & EFER_LME) {
1750                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1751                         enter_lmode(vcpu);
1752                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1753                         exit_lmode(vcpu);
1754         }
1755 #endif
1756
1757         if (enable_ept)
1758                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1759
1760         if (!vcpu->fpu_active)
1761                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1762
1763         vmcs_writel(CR0_READ_SHADOW, cr0);
1764         vmcs_writel(GUEST_CR0, hw_cr0);
1765         vcpu->arch.cr0 = cr0;
1766 }
1767
1768 static u64 construct_eptp(unsigned long root_hpa)
1769 {
1770         u64 eptp;
1771
1772         /* TODO write the value reading from MSR */
1773         eptp = VMX_EPT_DEFAULT_MT |
1774                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1775         eptp |= (root_hpa & PAGE_MASK);
1776
1777         return eptp;
1778 }
1779
1780 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1781 {
1782         unsigned long guest_cr3;
1783         u64 eptp;
1784
1785         guest_cr3 = cr3;
1786         if (enable_ept) {
1787                 eptp = construct_eptp(cr3);
1788                 vmcs_write64(EPT_POINTER, eptp);
1789                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1790                         vcpu->kvm->arch.ept_identity_map_addr;
1791                 ept_load_pdptrs(vcpu);
1792         }
1793
1794         vmx_flush_tlb(vcpu);
1795         vmcs_writel(GUEST_CR3, guest_cr3);
1796 }
1797
1798 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1799 {
1800         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1801                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1802
1803         vcpu->arch.cr4 = cr4;
1804         if (enable_ept) {
1805                 if (!is_paging(vcpu)) {
1806                         hw_cr4 &= ~X86_CR4_PAE;
1807                         hw_cr4 |= X86_CR4_PSE;
1808                 } else if (!(cr4 & X86_CR4_PAE)) {
1809                         hw_cr4 &= ~X86_CR4_PAE;
1810                 }
1811         }
1812
1813         vmcs_writel(CR4_READ_SHADOW, cr4);
1814         vmcs_writel(GUEST_CR4, hw_cr4);
1815 }
1816
1817 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1818 {
1819         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1820
1821         return vmcs_readl(sf->base);
1822 }
1823
1824 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1825                             struct kvm_segment *var, int seg)
1826 {
1827         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1828         u32 ar;
1829
1830         var->base = vmcs_readl(sf->base);
1831         var->limit = vmcs_read32(sf->limit);
1832         var->selector = vmcs_read16(sf->selector);
1833         ar = vmcs_read32(sf->ar_bytes);
1834         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1835                 ar = 0;
1836         var->type = ar & 15;
1837         var->s = (ar >> 4) & 1;
1838         var->dpl = (ar >> 5) & 3;
1839         var->present = (ar >> 7) & 1;
1840         var->avl = (ar >> 12) & 1;
1841         var->l = (ar >> 13) & 1;
1842         var->db = (ar >> 14) & 1;
1843         var->g = (ar >> 15) & 1;
1844         var->unusable = (ar >> 16) & 1;
1845 }
1846
1847 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1848 {
1849         if (!is_protmode(vcpu))
1850                 return 0;
1851
1852         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1853                 return 3;
1854
1855         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1856 }
1857
1858 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1859 {
1860         u32 ar;
1861
1862         if (var->unusable)
1863                 ar = 1 << 16;
1864         else {
1865                 ar = var->type & 15;
1866                 ar |= (var->s & 1) << 4;
1867                 ar |= (var->dpl & 3) << 5;
1868                 ar |= (var->present & 1) << 7;
1869                 ar |= (var->avl & 1) << 12;
1870                 ar |= (var->l & 1) << 13;
1871                 ar |= (var->db & 1) << 14;
1872                 ar |= (var->g & 1) << 15;
1873         }
1874         if (ar == 0) /* a 0 value means unusable */
1875                 ar = AR_UNUSABLE_MASK;
1876
1877         return ar;
1878 }
1879
1880 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1881                             struct kvm_segment *var, int seg)
1882 {
1883         struct vcpu_vmx *vmx = to_vmx(vcpu);
1884         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1885         u32 ar;
1886
1887         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1888                 vmx->rmode.tr.selector = var->selector;
1889                 vmx->rmode.tr.base = var->base;
1890                 vmx->rmode.tr.limit = var->limit;
1891                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1892                 return;
1893         }
1894         vmcs_writel(sf->base, var->base);
1895         vmcs_write32(sf->limit, var->limit);
1896         vmcs_write16(sf->selector, var->selector);
1897         if (vmx->rmode.vm86_active && var->s) {
1898                 /*
1899                  * Hack real-mode segments into vm86 compatibility.
1900                  */
1901                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1902                         vmcs_writel(sf->base, 0xf0000);
1903                 ar = 0xf3;
1904         } else
1905                 ar = vmx_segment_access_rights(var);
1906
1907         /*
1908          *   Fix the "Accessed" bit in AR field of segment registers for older
1909          * qemu binaries.
1910          *   IA32 arch specifies that at the time of processor reset the
1911          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1912          * is setting it to 0 in the usedland code. This causes invalid guest
1913          * state vmexit when "unrestricted guest" mode is turned on.
1914          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1915          * tree. Newer qemu binaries with that qemu fix would not need this
1916          * kvm hack.
1917          */
1918         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1919                 ar |= 0x1; /* Accessed */
1920
1921         vmcs_write32(sf->ar_bytes, ar);
1922 }
1923
1924 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1925 {
1926         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1927
1928         *db = (ar >> 14) & 1;
1929         *l = (ar >> 13) & 1;
1930 }
1931
1932 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1933 {
1934         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1935         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1936 }
1937
1938 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1939 {
1940         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1941         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1942 }
1943
1944 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1945 {
1946         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1947         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1948 }
1949
1950 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1951 {
1952         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1953         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1954 }
1955
1956 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1957 {
1958         struct kvm_segment var;
1959         u32 ar;
1960
1961         vmx_get_segment(vcpu, &var, seg);
1962         ar = vmx_segment_access_rights(&var);
1963
1964         if (var.base != (var.selector << 4))
1965                 return false;
1966         if (var.limit != 0xffff)
1967                 return false;
1968         if (ar != 0xf3)
1969                 return false;
1970
1971         return true;
1972 }
1973
1974 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1975 {
1976         struct kvm_segment cs;
1977         unsigned int cs_rpl;
1978
1979         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1980         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1981
1982         if (cs.unusable)
1983                 return false;
1984         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1985                 return false;
1986         if (!cs.s)
1987                 return false;
1988         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1989                 if (cs.dpl > cs_rpl)
1990                         return false;
1991         } else {
1992                 if (cs.dpl != cs_rpl)
1993                         return false;
1994         }
1995         if (!cs.present)
1996                 return false;
1997
1998         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1999         return true;
2000 }
2001
2002 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2003 {
2004         struct kvm_segment ss;
2005         unsigned int ss_rpl;
2006
2007         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2008         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2009
2010         if (ss.unusable)
2011                 return true;
2012         if (ss.type != 3 && ss.type != 7)
2013                 return false;
2014         if (!ss.s)
2015                 return false;
2016         if (ss.dpl != ss_rpl) /* DPL != RPL */
2017                 return false;
2018         if (!ss.present)
2019                 return false;
2020
2021         return true;
2022 }
2023
2024 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2025 {
2026         struct kvm_segment var;
2027         unsigned int rpl;
2028
2029         vmx_get_segment(vcpu, &var, seg);
2030         rpl = var.selector & SELECTOR_RPL_MASK;
2031
2032         if (var.unusable)
2033                 return true;
2034         if (!var.s)
2035                 return false;
2036         if (!var.present)
2037                 return false;
2038         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2039                 if (var.dpl < rpl) /* DPL < RPL */
2040                         return false;
2041         }
2042
2043         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2044          * rights flags
2045          */
2046         return true;
2047 }
2048
2049 static bool tr_valid(struct kvm_vcpu *vcpu)
2050 {
2051         struct kvm_segment tr;
2052
2053         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2054
2055         if (tr.unusable)
2056                 return false;
2057         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2058                 return false;
2059         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2060                 return false;
2061         if (!tr.present)
2062                 return false;
2063
2064         return true;
2065 }
2066
2067 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2068 {
2069         struct kvm_segment ldtr;
2070
2071         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2072
2073         if (ldtr.unusable)
2074                 return true;
2075         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2076                 return false;
2077         if (ldtr.type != 2)
2078                 return false;
2079         if (!ldtr.present)
2080                 return false;
2081
2082         return true;
2083 }
2084
2085 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2086 {
2087         struct kvm_segment cs, ss;
2088
2089         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2090         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2091
2092         return ((cs.selector & SELECTOR_RPL_MASK) ==
2093                  (ss.selector & SELECTOR_RPL_MASK));
2094 }
2095
2096 /*
2097  * Check if guest state is valid. Returns true if valid, false if
2098  * not.
2099  * We assume that registers are always usable
2100  */
2101 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2102 {
2103         /* real mode guest state checks */
2104         if (!is_protmode(vcpu)) {
2105                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2106                         return false;
2107                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2108                         return false;
2109                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2110                         return false;
2111                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2112                         return false;
2113                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2114                         return false;
2115                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2116                         return false;
2117         } else {
2118         /* protected mode guest state checks */
2119                 if (!cs_ss_rpl_check(vcpu))
2120                         return false;
2121                 if (!code_segment_valid(vcpu))
2122                         return false;
2123                 if (!stack_segment_valid(vcpu))
2124                         return false;
2125                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2126                         return false;
2127                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2128                         return false;
2129                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2130                         return false;
2131                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2132                         return false;
2133                 if (!tr_valid(vcpu))
2134                         return false;
2135                 if (!ldtr_valid(vcpu))
2136                         return false;
2137         }
2138         /* TODO:
2139          * - Add checks on RIP
2140          * - Add checks on RFLAGS
2141          */
2142
2143         return true;
2144 }
2145
2146 static int init_rmode_tss(struct kvm *kvm)
2147 {
2148         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2149         u16 data = 0;
2150         int ret = 0;
2151         int r;
2152
2153         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2154         if (r < 0)
2155                 goto out;
2156         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2157         r = kvm_write_guest_page(kvm, fn++, &data,
2158                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2159         if (r < 0)
2160                 goto out;
2161         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2162         if (r < 0)
2163                 goto out;
2164         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2165         if (r < 0)
2166                 goto out;
2167         data = ~0;
2168         r = kvm_write_guest_page(kvm, fn, &data,
2169                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2170                                  sizeof(u8));
2171         if (r < 0)
2172                 goto out;
2173
2174         ret = 1;
2175 out:
2176         return ret;
2177 }
2178
2179 static int init_rmode_identity_map(struct kvm *kvm)
2180 {
2181         int i, r, ret;
2182         pfn_t identity_map_pfn;
2183         u32 tmp;
2184
2185         if (!enable_ept)
2186                 return 1;
2187         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2188                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2189                         "haven't been allocated!\n");
2190                 return 0;
2191         }
2192         if (likely(kvm->arch.ept_identity_pagetable_done))
2193                 return 1;
2194         ret = 0;
2195         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2196         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2197         if (r < 0)
2198                 goto out;
2199         /* Set up identity-mapping pagetable for EPT in real mode */
2200         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2201                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2202                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2203                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2204                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2205                 if (r < 0)
2206                         goto out;
2207         }
2208         kvm->arch.ept_identity_pagetable_done = true;
2209         ret = 1;
2210 out:
2211         return ret;
2212 }
2213
2214 static void seg_setup(int seg)
2215 {
2216         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2217         unsigned int ar;
2218
2219         vmcs_write16(sf->selector, 0);
2220         vmcs_writel(sf->base, 0);
2221         vmcs_write32(sf->limit, 0xffff);
2222         if (enable_unrestricted_guest) {
2223                 ar = 0x93;
2224                 if (seg == VCPU_SREG_CS)
2225                         ar |= 0x08; /* code segment */
2226         } else
2227                 ar = 0xf3;
2228
2229         vmcs_write32(sf->ar_bytes, ar);
2230 }
2231
2232 static int alloc_apic_access_page(struct kvm *kvm)
2233 {
2234         struct kvm_userspace_memory_region kvm_userspace_mem;
2235         int r = 0;
2236
2237         mutex_lock(&kvm->slots_lock);
2238         if (kvm->arch.apic_access_page)
2239                 goto out;
2240         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2241         kvm_userspace_mem.flags = 0;
2242         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2243         kvm_userspace_mem.memory_size = PAGE_SIZE;
2244         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2245         if (r)
2246                 goto out;
2247
2248         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2249 out:
2250         mutex_unlock(&kvm->slots_lock);
2251         return r;
2252 }
2253
2254 static int alloc_identity_pagetable(struct kvm *kvm)
2255 {
2256         struct kvm_userspace_memory_region kvm_userspace_mem;
2257         int r = 0;
2258
2259         mutex_lock(&kvm->slots_lock);
2260         if (kvm->arch.ept_identity_pagetable)
2261                 goto out;
2262         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2263         kvm_userspace_mem.flags = 0;
2264         kvm_userspace_mem.guest_phys_addr =
2265                 kvm->arch.ept_identity_map_addr;
2266         kvm_userspace_mem.memory_size = PAGE_SIZE;
2267         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2268         if (r)
2269                 goto out;
2270
2271         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2272                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2273 out:
2274         mutex_unlock(&kvm->slots_lock);
2275         return r;
2276 }
2277
2278 static void allocate_vpid(struct vcpu_vmx *vmx)
2279 {
2280         int vpid;
2281
2282         vmx->vpid = 0;
2283         if (!enable_vpid)
2284                 return;
2285         spin_lock(&vmx_vpid_lock);
2286         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2287         if (vpid < VMX_NR_VPIDS) {
2288                 vmx->vpid = vpid;
2289                 __set_bit(vpid, vmx_vpid_bitmap);
2290         }
2291         spin_unlock(&vmx_vpid_lock);
2292 }
2293
2294 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2295 {
2296         int f = sizeof(unsigned long);
2297
2298         if (!cpu_has_vmx_msr_bitmap())
2299                 return;
2300
2301         /*
2302          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2303          * have the write-low and read-high bitmap offsets the wrong way round.
2304          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2305          */
2306         if (msr <= 0x1fff) {
2307                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2308                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2309         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2310                 msr &= 0x1fff;
2311                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2312                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2313         }
2314 }
2315
2316 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2317 {
2318         if (!longmode_only)
2319                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2320         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2321 }
2322
2323 /*
2324  * Sets up the vmcs for emulated real mode.
2325  */
2326 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2327 {
2328         u32 host_sysenter_cs, msr_low, msr_high;
2329         u32 junk;
2330         u64 host_pat, tsc_this, tsc_base;
2331         unsigned long a;
2332         struct descriptor_table dt;
2333         int i;
2334         unsigned long kvm_vmx_return;
2335         u32 exec_control;
2336
2337         /* I/O */
2338         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2339         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2340
2341         if (cpu_has_vmx_msr_bitmap())
2342                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2343
2344         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2345
2346         /* Control */
2347         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2348                 vmcs_config.pin_based_exec_ctrl);
2349
2350         exec_control = vmcs_config.cpu_based_exec_ctrl;
2351         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2352                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2353 #ifdef CONFIG_X86_64
2354                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2355                                 CPU_BASED_CR8_LOAD_EXITING;
2356 #endif
2357         }
2358         if (!enable_ept)
2359                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2360                                 CPU_BASED_CR3_LOAD_EXITING  |
2361                                 CPU_BASED_INVLPG_EXITING;
2362         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2363
2364         if (cpu_has_secondary_exec_ctrls()) {
2365                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2366                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2367                         exec_control &=
2368                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2369                 if (vmx->vpid == 0)
2370                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2371                 if (!enable_ept) {
2372                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2373                         enable_unrestricted_guest = 0;
2374                 }
2375                 if (!enable_unrestricted_guest)
2376                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2377                 if (!ple_gap)
2378                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2379                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2380         }
2381
2382         if (ple_gap) {
2383                 vmcs_write32(PLE_GAP, ple_gap);
2384                 vmcs_write32(PLE_WINDOW, ple_window);
2385         }
2386
2387         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2388         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2389         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2390
2391         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2392         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2393         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2394
2395         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2396         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2397         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2398         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2399         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2400         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2401 #ifdef CONFIG_X86_64
2402         rdmsrl(MSR_FS_BASE, a);
2403         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2404         rdmsrl(MSR_GS_BASE, a);
2405         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2406 #else
2407         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2408         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2409 #endif
2410
2411         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2412
2413         kvm_get_idt(&dt);
2414         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2415
2416         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2417         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2418         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2419         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2420         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2421
2422         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2423         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2424         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2425         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2426         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2427         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2428
2429         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2430                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2431                 host_pat = msr_low | ((u64) msr_high << 32);
2432                 vmcs_write64(HOST_IA32_PAT, host_pat);
2433         }
2434         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2435                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2436                 host_pat = msr_low | ((u64) msr_high << 32);
2437                 /* Write the default value follow host pat */
2438                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2439                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2440                 vmx->vcpu.arch.pat = host_pat;
2441         }
2442
2443         for (i = 0; i < NR_VMX_MSR; ++i) {
2444                 u32 index = vmx_msr_index[i];
2445                 u32 data_low, data_high;
2446                 int j = vmx->nmsrs;
2447
2448                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2449                         continue;
2450                 if (wrmsr_safe(index, data_low, data_high) < 0)
2451                         continue;
2452                 vmx->guest_msrs[j].index = i;
2453                 vmx->guest_msrs[j].data = 0;
2454                 vmx->guest_msrs[j].mask = -1ull;
2455                 ++vmx->nmsrs;
2456         }
2457
2458         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2459
2460         /* 22.2.1, 20.8.1 */
2461         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2462
2463         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2464         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2465         if (enable_ept)
2466                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2467         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2468
2469         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2470         rdtscll(tsc_this);
2471         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2472                 tsc_base = tsc_this;
2473
2474         guest_write_tsc(0, tsc_base);
2475
2476         return 0;
2477 }
2478
2479 static int init_rmode(struct kvm *kvm)
2480 {
2481         if (!init_rmode_tss(kvm))
2482                 return 0;
2483         if (!init_rmode_identity_map(kvm))
2484                 return 0;
2485         return 1;
2486 }
2487
2488 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2489 {
2490         struct vcpu_vmx *vmx = to_vmx(vcpu);
2491         u64 msr;
2492         int ret, idx;
2493
2494         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2495         idx = srcu_read_lock(&vcpu->kvm->srcu);
2496         if (!init_rmode(vmx->vcpu.kvm)) {
2497                 ret = -ENOMEM;
2498                 goto out;
2499         }
2500
2501         vmx->rmode.vm86_active = 0;
2502
2503         vmx->soft_vnmi_blocked = 0;
2504
2505         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2506         kvm_set_cr8(&vmx->vcpu, 0);
2507         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2508         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2509                 msr |= MSR_IA32_APICBASE_BSP;
2510         kvm_set_apic_base(&vmx->vcpu, msr);
2511
2512         fx_init(&vmx->vcpu);
2513
2514         seg_setup(VCPU_SREG_CS);
2515         /*
2516          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2517          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2518          */
2519         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2520                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2521                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2522         } else {
2523                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2524                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2525         }
2526
2527         seg_setup(VCPU_SREG_DS);
2528         seg_setup(VCPU_SREG_ES);
2529         seg_setup(VCPU_SREG_FS);
2530         seg_setup(VCPU_SREG_GS);
2531         seg_setup(VCPU_SREG_SS);
2532
2533         vmcs_write16(GUEST_TR_SELECTOR, 0);
2534         vmcs_writel(GUEST_TR_BASE, 0);
2535         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2536         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2537
2538         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2539         vmcs_writel(GUEST_LDTR_BASE, 0);
2540         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2541         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2542
2543         vmcs_write32(GUEST_SYSENTER_CS, 0);
2544         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2545         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2546
2547         vmcs_writel(GUEST_RFLAGS, 0x02);
2548         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2549                 kvm_rip_write(vcpu, 0xfff0);
2550         else
2551                 kvm_rip_write(vcpu, 0);
2552         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2553
2554         vmcs_writel(GUEST_DR7, 0x400);
2555
2556         vmcs_writel(GUEST_GDTR_BASE, 0);
2557         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2558
2559         vmcs_writel(GUEST_IDTR_BASE, 0);
2560         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2561
2562         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2563         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2564         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2565
2566         /* Special registers */
2567         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2568
2569         setup_msrs(vmx);
2570
2571         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2572
2573         if (cpu_has_vmx_tpr_shadow()) {
2574                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2575                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2576                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2577                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2578                 vmcs_write32(TPR_THRESHOLD, 0);
2579         }
2580
2581         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2582                 vmcs_write64(APIC_ACCESS_ADDR,
2583                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2584
2585         if (vmx->vpid != 0)
2586                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2587
2588         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2589         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2590         vmx_set_cr4(&vmx->vcpu, 0);
2591         vmx_set_efer(&vmx->vcpu, 0);
2592         vmx_fpu_activate(&vmx->vcpu);
2593         update_exception_bitmap(&vmx->vcpu);
2594
2595         vpid_sync_vcpu_all(vmx);
2596
2597         ret = 0;
2598
2599         /* HACK: Don't enable emulation on guest boot/reset */
2600         vmx->emulation_required = 0;
2601
2602 out:
2603         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2604         return ret;
2605 }
2606
2607 static void enable_irq_window(struct kvm_vcpu *vcpu)
2608 {
2609         u32 cpu_based_vm_exec_control;
2610
2611         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2612         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2613         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2614 }
2615
2616 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2617 {
2618         u32 cpu_based_vm_exec_control;
2619
2620         if (!cpu_has_virtual_nmis()) {
2621                 enable_irq_window(vcpu);
2622                 return;
2623         }
2624
2625         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2626         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2627         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2628 }
2629
2630 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2631 {
2632         struct vcpu_vmx *vmx = to_vmx(vcpu);
2633         uint32_t intr;
2634         int irq = vcpu->arch.interrupt.nr;
2635
2636         trace_kvm_inj_virq(irq);
2637
2638         ++vcpu->stat.irq_injections;
2639         if (vmx->rmode.vm86_active) {
2640                 vmx->rmode.irq.pending = true;
2641                 vmx->rmode.irq.vector = irq;
2642                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2643                 if (vcpu->arch.interrupt.soft)
2644                         vmx->rmode.irq.rip +=
2645                                 vmx->vcpu.arch.event_exit_inst_len;
2646                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2647                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2648                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2649                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2650                 return;
2651         }
2652         intr = irq | INTR_INFO_VALID_MASK;
2653         if (vcpu->arch.interrupt.soft) {
2654                 intr |= INTR_TYPE_SOFT_INTR;
2655                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2656                              vmx->vcpu.arch.event_exit_inst_len);
2657         } else
2658                 intr |= INTR_TYPE_EXT_INTR;
2659         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2660 }
2661
2662 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2663 {
2664         struct vcpu_vmx *vmx = to_vmx(vcpu);
2665
2666         if (!cpu_has_virtual_nmis()) {
2667                 /*
2668                  * Tracking the NMI-blocked state in software is built upon
2669                  * finding the next open IRQ window. This, in turn, depends on
2670                  * well-behaving guests: They have to keep IRQs disabled at
2671                  * least as long as the NMI handler runs. Otherwise we may
2672                  * cause NMI nesting, maybe breaking the guest. But as this is
2673                  * highly unlikely, we can live with the residual risk.
2674                  */
2675                 vmx->soft_vnmi_blocked = 1;
2676                 vmx->vnmi_blocked_time = 0;
2677         }
2678
2679         ++vcpu->stat.nmi_injections;
2680         if (vmx->rmode.vm86_active) {
2681                 vmx->rmode.irq.pending = true;
2682                 vmx->rmode.irq.vector = NMI_VECTOR;
2683                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2684                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2685                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2686                              INTR_INFO_VALID_MASK);
2687                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2688                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2689                 return;
2690         }
2691         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2692                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2693 }
2694
2695 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2696 {
2697         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2698                 return 0;
2699
2700         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2701                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2702                                 GUEST_INTR_STATE_NMI));
2703 }
2704
2705 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2706 {
2707         if (!cpu_has_virtual_nmis())
2708                 return to_vmx(vcpu)->soft_vnmi_blocked;
2709         else
2710                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2711                           GUEST_INTR_STATE_NMI);
2712 }
2713
2714 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2715 {
2716         struct vcpu_vmx *vmx = to_vmx(vcpu);
2717
2718         if (!cpu_has_virtual_nmis()) {
2719                 if (vmx->soft_vnmi_blocked != masked) {
2720                         vmx->soft_vnmi_blocked = masked;
2721                         vmx->vnmi_blocked_time = 0;
2722                 }
2723         } else {
2724                 if (masked)
2725                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2726                                       GUEST_INTR_STATE_NMI);
2727                 else
2728                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2729                                         GUEST_INTR_STATE_NMI);
2730         }
2731 }
2732
2733 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2734 {
2735         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2736                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2737                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2738 }
2739
2740 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2741 {
2742         int ret;
2743         struct kvm_userspace_memory_region tss_mem = {
2744                 .slot = TSS_PRIVATE_MEMSLOT,
2745                 .guest_phys_addr = addr,
2746                 .memory_size = PAGE_SIZE * 3,
2747                 .flags = 0,
2748         };
2749
2750         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2751         if (ret)
2752                 return ret;
2753         kvm->arch.tss_addr = addr;
2754         return 0;
2755 }
2756
2757 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2758                                   int vec, u32 err_code)
2759 {
2760         /*
2761          * Instruction with address size override prefix opcode 0x67
2762          * Cause the #SS fault with 0 error code in VM86 mode.
2763          */
2764         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2765                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2766                         return 1;
2767         /*
2768          * Forward all other exceptions that are valid in real mode.
2769          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2770          *        the required debugging infrastructure rework.
2771          */
2772         switch (vec) {
2773         case DB_VECTOR:
2774                 if (vcpu->guest_debug &
2775                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2776                         return 0;
2777                 kvm_queue_exception(vcpu, vec);
2778                 return 1;
2779         case BP_VECTOR:
2780                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2781                         return 0;
2782                 /* fall through */
2783         case DE_VECTOR:
2784         case OF_VECTOR:
2785         case BR_VECTOR:
2786         case UD_VECTOR:
2787         case DF_VECTOR:
2788         case SS_VECTOR:
2789         case GP_VECTOR:
2790         case MF_VECTOR:
2791                 kvm_queue_exception(vcpu, vec);
2792                 return 1;
2793         }
2794         return 0;
2795 }
2796
2797 /*
2798  * Trigger machine check on the host. We assume all the MSRs are already set up
2799  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2800  * We pass a fake environment to the machine check handler because we want
2801  * the guest to be always treated like user space, no matter what context
2802  * it used internally.
2803  */
2804 static void kvm_machine_check(void)
2805 {
2806 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2807         struct pt_regs regs = {
2808                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2809                 .flags = X86_EFLAGS_IF,
2810         };
2811
2812         do_machine_check(&regs, 0);
2813 #endif
2814 }
2815
2816 static int handle_machine_check(struct kvm_vcpu *vcpu)
2817 {
2818         /* already handled by vcpu_run */
2819         return 1;
2820 }
2821
2822 static int handle_exception(struct kvm_vcpu *vcpu)
2823 {
2824         struct vcpu_vmx *vmx = to_vmx(vcpu);
2825         struct kvm_run *kvm_run = vcpu->run;
2826         u32 intr_info, ex_no, error_code;
2827         unsigned long cr2, rip, dr6;
2828         u32 vect_info;
2829         enum emulation_result er;
2830
2831         vect_info = vmx->idt_vectoring_info;
2832         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2833
2834         if (is_machine_check(intr_info))
2835                 return handle_machine_check(vcpu);
2836
2837         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2838             !is_page_fault(intr_info)) {
2839                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2840                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2841                 vcpu->run->internal.ndata = 2;
2842                 vcpu->run->internal.data[0] = vect_info;
2843                 vcpu->run->internal.data[1] = intr_info;
2844                 return 0;
2845         }
2846
2847         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2848                 return 1;  /* already handled by vmx_vcpu_run() */
2849
2850         if (is_no_device(intr_info)) {
2851                 vmx_fpu_activate(vcpu);
2852                 return 1;
2853         }
2854
2855         if (is_invalid_opcode(intr_info)) {
2856                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2857                 if (er != EMULATE_DONE)
2858                         kvm_queue_exception(vcpu, UD_VECTOR);
2859                 return 1;
2860         }
2861
2862         error_code = 0;
2863         rip = kvm_rip_read(vcpu);
2864         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2865                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2866         if (is_page_fault(intr_info)) {
2867                 /* EPT won't cause page fault directly */
2868                 if (enable_ept)
2869                         BUG();
2870                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2871                 trace_kvm_page_fault(cr2, error_code);
2872
2873                 if (kvm_event_needs_reinjection(vcpu))
2874                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2875                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2876         }
2877
2878         if (vmx->rmode.vm86_active &&
2879             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2880                                                                 error_code)) {
2881                 if (vcpu->arch.halt_request) {
2882                         vcpu->arch.halt_request = 0;
2883                         return kvm_emulate_halt(vcpu);
2884                 }
2885                 return 1;
2886         }
2887
2888         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2889         switch (ex_no) {
2890         case DB_VECTOR:
2891                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2892                 if (!(vcpu->guest_debug &
2893                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2894                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2895                         kvm_queue_exception(vcpu, DB_VECTOR);
2896                         return 1;
2897                 }
2898                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2899                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2900                 /* fall through */
2901         case BP_VECTOR:
2902                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2903                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2904                 kvm_run->debug.arch.exception = ex_no;
2905                 break;
2906         default:
2907                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2908                 kvm_run->ex.exception = ex_no;
2909                 kvm_run->ex.error_code = error_code;
2910                 break;
2911         }
2912         return 0;
2913 }
2914
2915 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2916 {
2917         ++vcpu->stat.irq_exits;
2918         return 1;
2919 }
2920
2921 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2922 {
2923         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2924         return 0;
2925 }
2926
2927 static int handle_io(struct kvm_vcpu *vcpu)
2928 {
2929         unsigned long exit_qualification;
2930         int size, in, string;
2931         unsigned port;
2932
2933         ++vcpu->stat.io_exits;
2934         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2935         string = (exit_qualification & 16) != 0;
2936
2937         if (string) {
2938                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2939                         return 0;
2940                 return 1;
2941         }
2942
2943         size = (exit_qualification & 7) + 1;
2944         in = (exit_qualification & 8) != 0;
2945         port = exit_qualification >> 16;
2946
2947         skip_emulated_instruction(vcpu);
2948         return kvm_emulate_pio(vcpu, in, size, port);
2949 }
2950
2951 static void
2952 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2953 {
2954         /*
2955          * Patch in the VMCALL instruction:
2956          */
2957         hypercall[0] = 0x0f;
2958         hypercall[1] = 0x01;
2959         hypercall[2] = 0xc1;
2960 }
2961
2962 static int handle_cr(struct kvm_vcpu *vcpu)
2963 {
2964         unsigned long exit_qualification, val;
2965         int cr;
2966         int reg;
2967
2968         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2969         cr = exit_qualification & 15;
2970         reg = (exit_qualification >> 8) & 15;
2971         switch ((exit_qualification >> 4) & 3) {
2972         case 0: /* mov to cr */
2973                 val = kvm_register_read(vcpu, reg);
2974                 trace_kvm_cr_write(cr, val);
2975                 switch (cr) {
2976                 case 0:
2977                         kvm_set_cr0(vcpu, val);
2978                         skip_emulated_instruction(vcpu);
2979                         return 1;
2980                 case 3:
2981                         kvm_set_cr3(vcpu, val);
2982                         skip_emulated_instruction(vcpu);
2983                         return 1;
2984                 case 4:
2985                         kvm_set_cr4(vcpu, val);
2986                         skip_emulated_instruction(vcpu);
2987                         return 1;
2988                 case 8: {
2989                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2990                                 u8 cr8 = kvm_register_read(vcpu, reg);
2991                                 kvm_set_cr8(vcpu, cr8);
2992                                 skip_emulated_instruction(vcpu);
2993                                 if (irqchip_in_kernel(vcpu->kvm))
2994                                         return 1;
2995                                 if (cr8_prev <= cr8)
2996                                         return 1;
2997                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2998                                 return 0;
2999                         }
3000                 };
3001                 break;
3002         case 2: /* clts */
3003                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3004                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3005                 skip_emulated_instruction(vcpu);
3006                 vmx_fpu_activate(vcpu);
3007                 return 1;
3008         case 1: /*mov from cr*/
3009                 switch (cr) {
3010                 case 3:
3011                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3012                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3013                         skip_emulated_instruction(vcpu);
3014                         return 1;
3015                 case 8:
3016                         val = kvm_get_cr8(vcpu);
3017                         kvm_register_write(vcpu, reg, val);
3018                         trace_kvm_cr_read(cr, val);
3019                         skip_emulated_instruction(vcpu);
3020                         return 1;
3021                 }
3022                 break;
3023         case 3: /* lmsw */
3024                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3025                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3026                 kvm_lmsw(vcpu, val);
3027
3028                 skip_emulated_instruction(vcpu);
3029                 return 1;
3030         default:
3031                 break;
3032         }
3033         vcpu->run->exit_reason = 0;
3034         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3035                (int)(exit_qualification >> 4) & 3, cr);
3036         return 0;
3037 }
3038
3039 static int check_dr_alias(struct kvm_vcpu *vcpu)
3040 {
3041         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3042                 kvm_queue_exception(vcpu, UD_VECTOR);
3043                 return -1;
3044         }
3045         return 0;
3046 }
3047
3048 static int handle_dr(struct kvm_vcpu *vcpu)
3049 {
3050         unsigned long exit_qualification;
3051         unsigned long val;
3052         int dr, reg;
3053
3054         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3055         if (!kvm_require_cpl(vcpu, 0))
3056                 return 1;
3057         dr = vmcs_readl(GUEST_DR7);
3058         if (dr & DR7_GD) {
3059                 /*
3060                  * As the vm-exit takes precedence over the debug trap, we
3061                  * need to emulate the latter, either for the host or the
3062                  * guest debugging itself.
3063                  */
3064                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3065                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3066                         vcpu->run->debug.arch.dr7 = dr;
3067                         vcpu->run->debug.arch.pc =
3068                                 vmcs_readl(GUEST_CS_BASE) +
3069                                 vmcs_readl(GUEST_RIP);
3070                         vcpu->run->debug.arch.exception = DB_VECTOR;
3071                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3072                         return 0;
3073                 } else {
3074                         vcpu->arch.dr7 &= ~DR7_GD;
3075                         vcpu->arch.dr6 |= DR6_BD;
3076                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3077                         kvm_queue_exception(vcpu, DB_VECTOR);
3078                         return 1;
3079                 }
3080         }
3081
3082         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3083         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3084         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3085         if (exit_qualification & TYPE_MOV_FROM_DR) {
3086                 switch (dr) {
3087                 case 0 ... 3:
3088                         val = vcpu->arch.db[dr];
3089                         break;
3090                 case 4:
3091                         if (check_dr_alias(vcpu) < 0)
3092                                 return 1;
3093                         /* fall through */
3094                 case 6:
3095                         val = vcpu->arch.dr6;
3096                         break;
3097                 case 5:
3098                         if (check_dr_alias(vcpu) < 0)
3099                                 return 1;
3100                         /* fall through */
3101                 default: /* 7 */
3102                         val = vcpu->arch.dr7;
3103                         break;
3104                 }
3105                 kvm_register_write(vcpu, reg, val);
3106         } else {
3107                 val = vcpu->arch.regs[reg];
3108                 switch (dr) {
3109                 case 0 ... 3:
3110                         vcpu->arch.db[dr] = val;
3111                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3112                                 vcpu->arch.eff_db[dr] = val;
3113                         break;
3114                 case 4:
3115                         if (check_dr_alias(vcpu) < 0)
3116                                 return 1;
3117                         /* fall through */
3118                 case 6:
3119                         if (val & 0xffffffff00000000ULL) {
3120                                 kvm_inject_gp(vcpu, 0);
3121                                 return 1;
3122                         }
3123                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3124                         break;
3125                 case 5:
3126                         if (check_dr_alias(vcpu) < 0)
3127                                 return 1;
3128                         /* fall through */
3129                 default: /* 7 */
3130                         if (val & 0xffffffff00000000ULL) {
3131                                 kvm_inject_gp(vcpu, 0);
3132                                 return 1;
3133                         }
3134                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3135                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3136                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3137                                 vcpu->arch.switch_db_regs =
3138                                         (val & DR7_BP_EN_MASK);
3139                         }
3140                         break;
3141                 }
3142         }
3143         skip_emulated_instruction(vcpu);
3144         return 1;
3145 }
3146
3147 static int handle_cpuid(struct kvm_vcpu *vcpu)
3148 {
3149         kvm_emulate_cpuid(vcpu);
3150         return 1;
3151 }
3152
3153 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3154 {
3155         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3156         u64 data;
3157
3158         if (vmx_get_msr(vcpu, ecx, &data)) {
3159                 trace_kvm_msr_read_ex(ecx);
3160                 kvm_inject_gp(vcpu, 0);
3161                 return 1;
3162         }
3163
3164         trace_kvm_msr_read(ecx, data);
3165
3166         /* FIXME: handling of bits 32:63 of rax, rdx */
3167         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3168         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3169         skip_emulated_instruction(vcpu);
3170         return 1;
3171 }
3172
3173 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3174 {
3175         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3176         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3177                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3178
3179         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3180                 trace_kvm_msr_write_ex(ecx, data);
3181                 kvm_inject_gp(vcpu, 0);
3182                 return 1;
3183         }
3184
3185         trace_kvm_msr_write(ecx, data);
3186         skip_emulated_instruction(vcpu);
3187         return 1;
3188 }
3189
3190 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3191 {
3192         return 1;
3193 }
3194
3195 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3196 {
3197         u32 cpu_based_vm_exec_control;
3198
3199         /* clear pending irq */
3200         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3201         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3202         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3203
3204         ++vcpu->stat.irq_window_exits;
3205
3206         /*
3207          * If the user space waits to inject interrupts, exit as soon as
3208          * possible
3209          */
3210         if (!irqchip_in_kernel(vcpu->kvm) &&
3211             vcpu->run->request_interrupt_window &&
3212             !kvm_cpu_has_interrupt(vcpu)) {
3213                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3214                 return 0;
3215         }
3216         return 1;
3217 }
3218
3219 static int handle_halt(struct kvm_vcpu *vcpu)
3220 {
3221         skip_emulated_instruction(vcpu);
3222         return kvm_emulate_halt(vcpu);
3223 }
3224
3225 static int handle_vmcall(struct kvm_vcpu *vcpu)
3226 {
3227         skip_emulated_instruction(vcpu);
3228         kvm_emulate_hypercall(vcpu);
3229         return 1;
3230 }
3231
3232 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3233 {
3234         kvm_queue_exception(vcpu, UD_VECTOR);
3235         return 1;
3236 }
3237
3238 static int handle_invlpg(struct kvm_vcpu *vcpu)
3239 {
3240         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3241
3242         kvm_mmu_invlpg(vcpu, exit_qualification);
3243         skip_emulated_instruction(vcpu);
3244         return 1;
3245 }
3246
3247 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3248 {
3249         skip_emulated_instruction(vcpu);
3250         /* TODO: Add support for VT-d/pass-through device */
3251         return 1;
3252 }
3253
3254 static int handle_apic_access(struct kvm_vcpu *vcpu)
3255 {
3256         unsigned long exit_qualification;
3257         enum emulation_result er;
3258         unsigned long offset;
3259
3260         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3261         offset = exit_qualification & 0xffful;
3262
3263         er = emulate_instruction(vcpu, 0, 0, 0);
3264
3265         if (er !=  EMULATE_DONE) {
3266                 printk(KERN_ERR
3267                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3268                        offset);
3269                 return -ENOEXEC;
3270         }
3271         return 1;
3272 }
3273
3274 static int handle_task_switch(struct kvm_vcpu *vcpu)
3275 {
3276         struct vcpu_vmx *vmx = to_vmx(vcpu);
3277         unsigned long exit_qualification;
3278         u16 tss_selector;
3279         int reason, type, idt_v;
3280
3281         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3282         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3283
3284         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3285
3286         reason = (u32)exit_qualification >> 30;
3287         if (reason == TASK_SWITCH_GATE && idt_v) {
3288                 switch (type) {
3289                 case INTR_TYPE_NMI_INTR:
3290                         vcpu->arch.nmi_injected = false;
3291                         if (cpu_has_virtual_nmis())
3292                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3293                                               GUEST_INTR_STATE_NMI);
3294                         break;
3295                 case INTR_TYPE_EXT_INTR:
3296                 case INTR_TYPE_SOFT_INTR:
3297                         kvm_clear_interrupt_queue(vcpu);
3298                         break;
3299                 case INTR_TYPE_HARD_EXCEPTION:
3300                 case INTR_TYPE_SOFT_EXCEPTION:
3301                         kvm_clear_exception_queue(vcpu);
3302                         break;
3303                 default:
3304                         break;
3305                 }
3306         }
3307         tss_selector = exit_qualification;
3308
3309         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3310                        type != INTR_TYPE_EXT_INTR &&
3311                        type != INTR_TYPE_NMI_INTR))
3312                 skip_emulated_instruction(vcpu);
3313
3314         if (!kvm_task_switch(vcpu, tss_selector, reason))
3315                 return 0;
3316
3317         /* clear all local breakpoint enable flags */
3318         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3319
3320         /*
3321          * TODO: What about debug traps on tss switch?
3322          *       Are we supposed to inject them and update dr6?
3323          */
3324
3325         return 1;
3326 }
3327
3328 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3329 {
3330         unsigned long exit_qualification;
3331         gpa_t gpa;
3332         int gla_validity;
3333
3334         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3335
3336         if (exit_qualification & (1 << 6)) {
3337                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3338                 return -EINVAL;
3339         }
3340
3341         gla_validity = (exit_qualification >> 7) & 0x3;
3342         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3343                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3344                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3345                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3346                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3347                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3348                         (long unsigned int)exit_qualification);
3349                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3350                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3351                 return 0;
3352         }
3353
3354         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3355         trace_kvm_page_fault(gpa, exit_qualification);
3356         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3357 }
3358
3359 static u64 ept_rsvd_mask(u64 spte, int level)
3360 {
3361         int i;
3362         u64 mask = 0;
3363
3364         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3365                 mask |= (1ULL << i);
3366
3367         if (level > 2)
3368                 /* bits 7:3 reserved */
3369                 mask |= 0xf8;
3370         else if (level == 2) {
3371                 if (spte & (1ULL << 7))
3372                         /* 2MB ref, bits 20:12 reserved */
3373                         mask |= 0x1ff000;
3374                 else
3375                         /* bits 6:3 reserved */
3376                         mask |= 0x78;
3377         }
3378
3379         return mask;
3380 }
3381
3382 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3383                                        int level)
3384 {
3385         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3386
3387         /* 010b (write-only) */
3388         WARN_ON((spte & 0x7) == 0x2);
3389
3390         /* 110b (write/execute) */
3391         WARN_ON((spte & 0x7) == 0x6);
3392
3393         /* 100b (execute-only) and value not supported by logical processor */
3394         if (!cpu_has_vmx_ept_execute_only())
3395                 WARN_ON((spte & 0x7) == 0x4);
3396
3397         /* not 000b */
3398         if ((spte & 0x7)) {
3399                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3400
3401                 if (rsvd_bits != 0) {
3402                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3403                                          __func__, rsvd_bits);
3404                         WARN_ON(1);
3405                 }
3406
3407                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3408                         u64 ept_mem_type = (spte & 0x38) >> 3;
3409
3410                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3411                             ept_mem_type == 7) {
3412                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3413                                                 __func__, ept_mem_type);
3414                                 WARN_ON(1);
3415                         }
3416                 }
3417         }
3418 }
3419
3420 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3421 {
3422         u64 sptes[4];
3423         int nr_sptes, i;
3424         gpa_t gpa;
3425
3426         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3427
3428         printk(KERN_ERR "EPT: Misconfiguration.\n");
3429         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3430
3431         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3432
3433         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3434                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3435
3436         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3437         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3438
3439         return 0;
3440 }
3441
3442 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3443 {
3444         u32 cpu_based_vm_exec_control;
3445
3446         /* clear pending NMI */
3447         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3448         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3449         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3450         ++vcpu->stat.nmi_window_exits;
3451
3452         return 1;
3453 }
3454
3455 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3456 {
3457         struct vcpu_vmx *vmx = to_vmx(vcpu);
3458         enum emulation_result err = EMULATE_DONE;
3459         int ret = 1;
3460
3461         while (!guest_state_valid(vcpu)) {
3462                 err = emulate_instruction(vcpu, 0, 0, 0);
3463
3464                 if (err == EMULATE_DO_MMIO) {
3465                         ret = 0;
3466                         goto out;
3467                 }
3468
3469                 if (err != EMULATE_DONE) {
3470                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3471                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3472                         vcpu->run->internal.ndata = 0;
3473                         ret = 0;
3474                         goto out;
3475                 }
3476
3477                 if (signal_pending(current))
3478                         goto out;
3479                 if (need_resched())
3480                         schedule();
3481         }
3482
3483         vmx->emulation_required = 0;
3484 out:
3485         return ret;
3486 }
3487
3488 /*
3489  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3490  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3491  */
3492 static int handle_pause(struct kvm_vcpu *vcpu)
3493 {
3494         skip_emulated_instruction(vcpu);
3495         kvm_vcpu_on_spin(vcpu);
3496
3497         return 1;
3498 }
3499
3500 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3501 {
3502         kvm_queue_exception(vcpu, UD_VECTOR);
3503         return 1;
3504 }
3505
3506 /*
3507  * The exit handlers return 1 if the exit was handled fully and guest execution
3508  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3509  * to be done to userspace and return 0.
3510  */
3511 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3512         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3513         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3514         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3515         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3516         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3517         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3518         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3519         [EXIT_REASON_CPUID]                   = handle_cpuid,
3520         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3521         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3522         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3523         [EXIT_REASON_HLT]                     = handle_halt,
3524         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3525         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3526         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3527         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3528         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3529         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3530         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3531         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3532         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3533         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3534         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3535         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3536         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3537         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3538         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3539         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3540         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3541         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3542         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3543         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3544         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3545 };
3546
3547 static const int kvm_vmx_max_exit_handlers =
3548         ARRAY_SIZE(kvm_vmx_exit_handlers);
3549
3550 /*
3551  * The guest has exited.  See if we can fix it or if we need userspace
3552  * assistance.
3553  */
3554 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3555 {
3556         struct vcpu_vmx *vmx = to_vmx(vcpu);
3557         u32 exit_reason = vmx->exit_reason;
3558         u32 vectoring_info = vmx->idt_vectoring_info;
3559
3560         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3561
3562         /* If guest state is invalid, start emulating */
3563         if (vmx->emulation_required && emulate_invalid_guest_state)
3564                 return handle_invalid_guest_state(vcpu);
3565
3566         /* Access CR3 don't cause VMExit in paging mode, so we need
3567          * to sync with guest real CR3. */
3568         if (enable_ept && is_paging(vcpu))
3569                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3570
3571         if (unlikely(vmx->fail)) {
3572                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3573                 vcpu->run->fail_entry.hardware_entry_failure_reason
3574                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3575                 return 0;
3576         }
3577
3578         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3579                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3580                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3581                         exit_reason != EXIT_REASON_TASK_SWITCH))
3582                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3583                        "(0x%x) and exit reason is 0x%x\n",
3584                        __func__, vectoring_info, exit_reason);
3585
3586         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3587                 if (vmx_interrupt_allowed(vcpu)) {
3588                         vmx->soft_vnmi_blocked = 0;
3589                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3590                            vcpu->arch.nmi_pending) {
3591                         /*
3592                          * This CPU don't support us in finding the end of an
3593                          * NMI-blocked window if the guest runs with IRQs
3594                          * disabled. So we pull the trigger after 1 s of
3595                          * futile waiting, but inform the user about this.
3596                          */
3597                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3598                                "state on VCPU %d after 1 s timeout\n",
3599                                __func__, vcpu->vcpu_id);
3600                         vmx->soft_vnmi_blocked = 0;
3601                 }
3602         }
3603
3604         if (exit_reason < kvm_vmx_max_exit_handlers
3605             && kvm_vmx_exit_handlers[exit_reason])
3606                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3607         else {
3608                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3609                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3610         }
3611         return 0;
3612 }
3613
3614 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3615 {
3616         if (irr == -1 || tpr < irr) {
3617                 vmcs_write32(TPR_THRESHOLD, 0);
3618                 return;
3619         }
3620
3621         vmcs_write32(TPR_THRESHOLD, irr);
3622 }
3623
3624 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3625 {
3626         u32 exit_intr_info;
3627         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3628         bool unblock_nmi;
3629         u8 vector;
3630         int type;
3631         bool idtv_info_valid;
3632
3633         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3634
3635         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3636
3637         /* Handle machine checks before interrupts are enabled */
3638         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3639             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3640                 && is_machine_check(exit_intr_info)))
3641                 kvm_machine_check();
3642
3643         /* We need to handle NMIs before interrupts are enabled */
3644         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3645             (exit_intr_info & INTR_INFO_VALID_MASK))
3646                 asm("int $2");
3647
3648         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3649
3650         if (cpu_has_virtual_nmis()) {
3651                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3652                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3653                 /*
3654                  * SDM 3: 27.7.1.2 (September 2008)
3655                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3656                  * a guest IRET fault.
3657                  * SDM 3: 23.2.2 (September 2008)
3658                  * Bit 12 is undefined in any of the following cases:
3659                  *  If the VM exit sets the valid bit in the IDT-vectoring
3660                  *   information field.
3661                  *  If the VM exit is due to a double fault.
3662                  */
3663                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3664                     vector != DF_VECTOR && !idtv_info_valid)
3665                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3666                                       GUEST_INTR_STATE_NMI);
3667         } else if (unlikely(vmx->soft_vnmi_blocked))
3668                 vmx->vnmi_blocked_time +=
3669                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3670
3671         vmx->vcpu.arch.nmi_injected = false;
3672         kvm_clear_exception_queue(&vmx->vcpu);
3673         kvm_clear_interrupt_queue(&vmx->vcpu);
3674
3675         if (!idtv_info_valid)
3676                 return;
3677
3678         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3679         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3680
3681         switch (type) {
3682         case INTR_TYPE_NMI_INTR:
3683                 vmx->vcpu.arch.nmi_injected = true;
3684                 /*
3685                  * SDM 3: 27.7.1.2 (September 2008)
3686                  * Clear bit "block by NMI" before VM entry if a NMI
3687                  * delivery faulted.
3688                  */
3689                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3690                                 GUEST_INTR_STATE_NMI);
3691                 break;
3692         case INTR_TYPE_SOFT_EXCEPTION:
3693                 vmx->vcpu.arch.event_exit_inst_len =
3694                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3695                 /* fall through */
3696         case INTR_TYPE_HARD_EXCEPTION:
3697                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3698                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3699                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3700                 } else
3701                         kvm_queue_exception(&vmx->vcpu, vector);
3702                 break;
3703         case INTR_TYPE_SOFT_INTR:
3704                 vmx->vcpu.arch.event_exit_inst_len =
3705                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3706                 /* fall through */
3707         case INTR_TYPE_EXT_INTR:
3708                 kvm_queue_interrupt(&vmx->vcpu, vector,
3709                         type == INTR_TYPE_SOFT_INTR);
3710                 break;
3711         default:
3712                 break;
3713         }
3714 }
3715
3716 /*
3717  * Failure to inject an interrupt should give us the information
3718  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3719  * when fetching the interrupt redirection bitmap in the real-mode
3720  * tss, this doesn't happen.  So we do it ourselves.
3721  */
3722 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3723 {
3724         vmx->rmode.irq.pending = 0;
3725         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3726                 return;
3727         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3728         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3729                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3730                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3731                 return;
3732         }
3733         vmx->idt_vectoring_info =
3734                 VECTORING_INFO_VALID_MASK
3735                 | INTR_TYPE_EXT_INTR
3736                 | vmx->rmode.irq.vector;
3737 }
3738
3739 #ifdef CONFIG_X86_64
3740 #define R "r"
3741 #define Q "q"
3742 #else
3743 #define R "e"
3744 #define Q "l"
3745 #endif
3746
3747 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3748 {
3749         struct vcpu_vmx *vmx = to_vmx(vcpu);
3750
3751         /* Record the guest's net vcpu time for enforced NMI injections. */
3752         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3753                 vmx->entry_time = ktime_get();
3754
3755         /* Don't enter VMX if guest state is invalid, let the exit handler
3756            start emulation until we arrive back to a valid state */
3757         if (vmx->emulation_required && emulate_invalid_guest_state)
3758                 return;
3759
3760         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3761                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3762         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3763                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3764
3765         /* When single-stepping over STI and MOV SS, we must clear the
3766          * corresponding interruptibility bits in the guest state. Otherwise
3767          * vmentry fails as it then expects bit 14 (BS) in pending debug
3768          * exceptions being set, but that's not correct for the guest debugging
3769          * case. */
3770         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3771                 vmx_set_interrupt_shadow(vcpu, 0);
3772
3773         /*
3774          * Loading guest fpu may have cleared host cr0.ts
3775          */
3776         vmcs_writel(HOST_CR0, read_cr0());
3777
3778         asm(
3779                 /* Store host registers */
3780                 "push %%"R"dx; push %%"R"bp;"
3781                 "push %%"R"cx \n\t"
3782                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3783                 "je 1f \n\t"
3784                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3785                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3786                 "1: \n\t"
3787                 /* Reload cr2 if changed */
3788                 "mov %c[cr2](%0), %%"R"ax \n\t"
3789                 "mov %%cr2, %%"R"dx \n\t"
3790                 "cmp %%"R"ax, %%"R"dx \n\t"
3791                 "je 2f \n\t"
3792                 "mov %%"R"ax, %%cr2 \n\t"
3793                 "2: \n\t"
3794                 /* Check if vmlaunch of vmresume is needed */
3795                 "cmpl $0, %c[launched](%0) \n\t"
3796                 /* Load guest registers.  Don't clobber flags. */
3797                 "mov %c[rax](%0), %%"R"ax \n\t"
3798                 "mov %c[rbx](%0), %%"R"bx \n\t"
3799                 "mov %c[rdx](%0), %%"R"dx \n\t"
3800                 "mov %c[rsi](%0), %%"R"si \n\t"
3801                 "mov %c[rdi](%0), %%"R"di \n\t"
3802                 "mov %c[rbp](%0), %%"R"bp \n\t"
3803 #ifdef CONFIG_X86_64
3804                 "mov %c[r8](%0),  %%r8  \n\t"
3805                 "mov %c[r9](%0),  %%r9  \n\t"
3806                 "mov %c[r10](%0), %%r10 \n\t"
3807                 "mov %c[r11](%0), %%r11 \n\t"
3808                 "mov %c[r12](%0), %%r12 \n\t"
3809                 "mov %c[r13](%0), %%r13 \n\t"
3810                 "mov %c[r14](%0), %%r14 \n\t"
3811                 "mov %c[r15](%0), %%r15 \n\t"
3812 #endif
3813                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3814
3815                 /* Enter guest mode */
3816                 "jne .Llaunched \n\t"
3817                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3818                 "jmp .Lkvm_vmx_return \n\t"
3819                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3820                 ".Lkvm_vmx_return: "
3821                 /* Save guest registers, load host registers, keep flags */
3822                 "xchg %0,     (%%"R"sp) \n\t"
3823                 "mov %%"R"ax, %c[rax](%0) \n\t"
3824                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3825                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3826                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3827                 "mov %%"R"si, %c[rsi](%0) \n\t"
3828                 "mov %%"R"di, %c[rdi](%0) \n\t"
3829                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3830 #ifdef CONFIG_X86_64
3831                 "mov %%r8,  %c[r8](%0) \n\t"
3832                 "mov %%r9,  %c[r9](%0) \n\t"
3833                 "mov %%r10, %c[r10](%0) \n\t"
3834                 "mov %%r11, %c[r11](%0) \n\t"
3835                 "mov %%r12, %c[r12](%0) \n\t"
3836                 "mov %%r13, %c[r13](%0) \n\t"
3837                 "mov %%r14, %c[r14](%0) \n\t"
3838                 "mov %%r15, %c[r15](%0) \n\t"
3839 #endif
3840                 "mov %%cr2, %%"R"ax   \n\t"
3841                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3842
3843                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3844                 "setbe %c[fail](%0) \n\t"
3845               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3846                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3847                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3848                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3849                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3850                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3851                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3852                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3853                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3854                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3855                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3856 #ifdef CONFIG_X86_64
3857                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3858                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3859                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3860                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3861                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3862                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3863                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3864                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3865 #endif
3866                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3867               : "cc", "memory"
3868                 , R"bx", R"di", R"si"
3869 #ifdef CONFIG_X86_64
3870                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3871 #endif
3872               );
3873
3874         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3875                                   | (1 << VCPU_EXREG_PDPTR));
3876         vcpu->arch.regs_dirty = 0;
3877
3878         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3879         if (vmx->rmode.irq.pending)
3880                 fixup_rmode_irq(vmx);
3881
3882         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3883         vmx->launched = 1;
3884
3885         vmx_complete_interrupts(vmx);
3886 }
3887
3888 #undef R
3889 #undef Q
3890
3891 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3892 {
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894
3895         if (vmx->vmcs) {
3896                 vcpu_clear(vmx);
3897                 free_vmcs(vmx->vmcs);
3898                 vmx->vmcs = NULL;
3899         }
3900 }
3901
3902 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3903 {
3904         struct vcpu_vmx *vmx = to_vmx(vcpu);
3905
3906         spin_lock(&vmx_vpid_lock);
3907         if (vmx->vpid != 0)
3908                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3909         spin_unlock(&vmx_vpid_lock);
3910         vmx_free_vmcs(vcpu);
3911         kfree(vmx->guest_msrs);
3912         kvm_vcpu_uninit(vcpu);
3913         kmem_cache_free(kvm_vcpu_cache, vmx);
3914 }
3915
3916 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3917 {
3918         int err;
3919         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3920         int cpu;
3921
3922         if (!vmx)
3923                 return ERR_PTR(-ENOMEM);
3924
3925         allocate_vpid(vmx);
3926
3927         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3928         if (err)
3929                 goto free_vcpu;
3930
3931         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3932         if (!vmx->guest_msrs) {
3933                 err = -ENOMEM;
3934                 goto uninit_vcpu;
3935         }
3936
3937         vmx->vmcs = alloc_vmcs();
3938         if (!vmx->vmcs)
3939                 goto free_msrs;
3940
3941         vmcs_clear(vmx->vmcs);
3942
3943         cpu = get_cpu();
3944         vmx_vcpu_load(&vmx->vcpu, cpu);
3945         err = vmx_vcpu_setup(vmx);
3946         vmx_vcpu_put(&vmx->vcpu);
3947         put_cpu();
3948         if (err)
3949                 goto free_vmcs;
3950         if (vm_need_virtualize_apic_accesses(kvm))
3951                 if (alloc_apic_access_page(kvm) != 0)
3952                         goto free_vmcs;
3953
3954         if (enable_ept) {
3955                 if (!kvm->arch.ept_identity_map_addr)
3956                         kvm->arch.ept_identity_map_addr =
3957                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3958                 if (alloc_identity_pagetable(kvm) != 0)
3959                         goto free_vmcs;
3960         }
3961
3962         return &vmx->vcpu;
3963
3964 free_vmcs:
3965         free_vmcs(vmx->vmcs);
3966 free_msrs:
3967         kfree(vmx->guest_msrs);
3968 uninit_vcpu:
3969         kvm_vcpu_uninit(&vmx->vcpu);
3970 free_vcpu:
3971         kmem_cache_free(kvm_vcpu_cache, vmx);
3972         return ERR_PTR(err);
3973 }
3974
3975 static void __init vmx_check_processor_compat(void *rtn)
3976 {
3977         struct vmcs_config vmcs_conf;
3978
3979         *(int *)rtn = 0;
3980         if (setup_vmcs_config(&vmcs_conf) < 0)
3981                 *(int *)rtn = -EIO;
3982         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3983                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3984                                 smp_processor_id());
3985                 *(int *)rtn = -EIO;
3986         }
3987 }
3988
3989 static int get_ept_level(void)
3990 {
3991         return VMX_EPT_DEFAULT_GAW + 1;
3992 }
3993
3994 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3995 {
3996         u64 ret;
3997
3998         /* For VT-d and EPT combination
3999          * 1. MMIO: always map as UC
4000          * 2. EPT with VT-d:
4001          *   a. VT-d without snooping control feature: can't guarantee the
4002          *      result, try to trust guest.
4003          *   b. VT-d with snooping control feature: snooping control feature of
4004          *      VT-d engine can guarantee the cache correctness. Just set it
4005          *      to WB to keep consistent with host. So the same as item 3.
4006          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
4007          *    consistent with host MTRR
4008          */
4009         if (is_mmio)
4010                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4011         else if (vcpu->kvm->arch.iommu_domain &&
4012                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4013                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4014                       VMX_EPT_MT_EPTE_SHIFT;
4015         else
4016                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4017                         | VMX_EPT_IGMT_BIT;
4018
4019         return ret;
4020 }
4021
4022 #define _ER(x) { EXIT_REASON_##x, #x }
4023
4024 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4025         _ER(EXCEPTION_NMI),
4026         _ER(EXTERNAL_INTERRUPT),
4027         _ER(TRIPLE_FAULT),
4028         _ER(PENDING_INTERRUPT),
4029         _ER(NMI_WINDOW),
4030         _ER(TASK_SWITCH),
4031         _ER(CPUID),
4032         _ER(HLT),
4033         _ER(INVLPG),
4034         _ER(RDPMC),
4035         _ER(RDTSC),
4036         _ER(VMCALL),
4037         _ER(VMCLEAR),
4038         _ER(VMLAUNCH),
4039         _ER(VMPTRLD),
4040         _ER(VMPTRST),
4041         _ER(VMREAD),
4042         _ER(VMRESUME),
4043         _ER(VMWRITE),
4044         _ER(VMOFF),
4045         _ER(VMON),
4046         _ER(CR_ACCESS),
4047         _ER(DR_ACCESS),
4048         _ER(IO_INSTRUCTION),
4049         _ER(MSR_READ),
4050         _ER(MSR_WRITE),
4051         _ER(MWAIT_INSTRUCTION),
4052         _ER(MONITOR_INSTRUCTION),
4053         _ER(PAUSE_INSTRUCTION),
4054         _ER(MCE_DURING_VMENTRY),
4055         _ER(TPR_BELOW_THRESHOLD),
4056         _ER(APIC_ACCESS),
4057         _ER(EPT_VIOLATION),
4058         _ER(EPT_MISCONFIG),
4059         _ER(WBINVD),
4060         { -1, NULL }
4061 };
4062
4063 #undef _ER
4064
4065 static int vmx_get_lpage_level(void)
4066 {
4067         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4068                 return PT_DIRECTORY_LEVEL;
4069         else
4070                 /* For shadow and EPT supported 1GB page */
4071                 return PT_PDPE_LEVEL;
4072 }
4073
4074 static inline u32 bit(int bitno)
4075 {
4076         return 1 << (bitno & 31);
4077 }
4078
4079 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4080 {
4081         struct kvm_cpuid_entry2 *best;
4082         struct vcpu_vmx *vmx = to_vmx(vcpu);
4083         u32 exec_control;
4084
4085         vmx->rdtscp_enabled = false;
4086         if (vmx_rdtscp_supported()) {
4087                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4088                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4089                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4090                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4091                                 vmx->rdtscp_enabled = true;
4092                         else {
4093                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4094                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4095                                                 exec_control);
4096                         }
4097                 }
4098         }
4099 }
4100
4101 static struct kvm_x86_ops vmx_x86_ops = {
4102         .cpu_has_kvm_support = cpu_has_kvm_support,
4103         .disabled_by_bios = vmx_disabled_by_bios,
4104         .hardware_setup = hardware_setup,
4105         .hardware_unsetup = hardware_unsetup,
4106         .check_processor_compatibility = vmx_check_processor_compat,
4107         .hardware_enable = hardware_enable,
4108         .hardware_disable = hardware_disable,
4109         .cpu_has_accelerated_tpr = report_flexpriority,
4110
4111         .vcpu_create = vmx_create_vcpu,
4112         .vcpu_free = vmx_free_vcpu,
4113         .vcpu_reset = vmx_vcpu_reset,
4114
4115         .prepare_guest_switch = vmx_save_host_state,
4116         .vcpu_load = vmx_vcpu_load,
4117         .vcpu_put = vmx_vcpu_put,
4118
4119         .set_guest_debug = set_guest_debug,
4120         .get_msr = vmx_get_msr,
4121         .set_msr = vmx_set_msr,
4122         .get_segment_base = vmx_get_segment_base,
4123         .get_segment = vmx_get_segment,
4124         .set_segment = vmx_set_segment,
4125         .get_cpl = vmx_get_cpl,
4126         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4127         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4128         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4129         .set_cr0 = vmx_set_cr0,
4130         .set_cr3 = vmx_set_cr3,
4131         .set_cr4 = vmx_set_cr4,
4132         .set_efer = vmx_set_efer,
4133         .get_idt = vmx_get_idt,
4134         .set_idt = vmx_set_idt,
4135         .get_gdt = vmx_get_gdt,
4136         .set_gdt = vmx_set_gdt,
4137         .cache_reg = vmx_cache_reg,
4138         .get_rflags = vmx_get_rflags,
4139         .set_rflags = vmx_set_rflags,
4140         .fpu_deactivate = vmx_fpu_deactivate,
4141
4142         .tlb_flush = vmx_flush_tlb,
4143
4144         .run = vmx_vcpu_run,
4145         .handle_exit = vmx_handle_exit,
4146         .skip_emulated_instruction = skip_emulated_instruction,
4147         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4148         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4149         .patch_hypercall = vmx_patch_hypercall,
4150         .set_irq = vmx_inject_irq,
4151         .set_nmi = vmx_inject_nmi,
4152         .queue_exception = vmx_queue_exception,
4153         .interrupt_allowed = vmx_interrupt_allowed,
4154         .nmi_allowed = vmx_nmi_allowed,
4155         .get_nmi_mask = vmx_get_nmi_mask,
4156         .set_nmi_mask = vmx_set_nmi_mask,
4157         .enable_nmi_window = enable_nmi_window,
4158         .enable_irq_window = enable_irq_window,
4159         .update_cr8_intercept = update_cr8_intercept,
4160
4161         .set_tss_addr = vmx_set_tss_addr,
4162         .get_tdp_level = get_ept_level,
4163         .get_mt_mask = vmx_get_mt_mask,
4164
4165         .exit_reasons_str = vmx_exit_reasons_str,
4166         .get_lpage_level = vmx_get_lpage_level,
4167
4168         .cpuid_update = vmx_cpuid_update,
4169
4170         .rdtscp_supported = vmx_rdtscp_supported,
4171 };
4172
4173 static int __init vmx_init(void)
4174 {
4175         int r, i;
4176
4177         rdmsrl_safe(MSR_EFER, &host_efer);
4178
4179         for (i = 0; i < NR_VMX_MSR; ++i)
4180                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4181
4182         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4183         if (!vmx_io_bitmap_a)
4184                 return -ENOMEM;
4185
4186         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4187         if (!vmx_io_bitmap_b) {
4188                 r = -ENOMEM;
4189                 goto out;
4190         }
4191
4192         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4193         if (!vmx_msr_bitmap_legacy) {
4194                 r = -ENOMEM;
4195                 goto out1;
4196         }
4197
4198         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4199         if (!vmx_msr_bitmap_longmode) {
4200                 r = -ENOMEM;
4201                 goto out2;
4202         }
4203
4204         /*
4205          * Allow direct access to the PC debug port (it is often used for I/O
4206          * delays, but the vmexits simply slow things down).
4207          */
4208         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4209         clear_bit(0x80, vmx_io_bitmap_a);
4210
4211         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4212
4213         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4214         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4215
4216         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4217
4218         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4219         if (r)
4220                 goto out3;
4221
4222         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4223         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4224         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4225         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4226         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4227         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4228
4229         if (enable_ept) {
4230                 bypass_guest_pf = 0;
4231                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4232                         VMX_EPT_WRITABLE_MASK);
4233                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4234                                 VMX_EPT_EXECUTABLE_MASK);
4235                 kvm_enable_tdp();
4236         } else
4237                 kvm_disable_tdp();
4238
4239         if (bypass_guest_pf)
4240                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4241
4242         return 0;
4243
4244 out3:
4245         free_page((unsigned long)vmx_msr_bitmap_longmode);
4246 out2:
4247         free_page((unsigned long)vmx_msr_bitmap_legacy);
4248 out1:
4249         free_page((unsigned long)vmx_io_bitmap_b);
4250 out:
4251         free_page((unsigned long)vmx_io_bitmap_a);
4252         return r;
4253 }
4254
4255 static void __exit vmx_exit(void)
4256 {
4257         free_page((unsigned long)vmx_msr_bitmap_legacy);
4258         free_page((unsigned long)vmx_msr_bitmap_longmode);
4259         free_page((unsigned long)vmx_io_bitmap_b);
4260         free_page((unsigned long)vmx_io_bitmap_a);
4261
4262         kvm_exit();
4263 }
4264
4265 module_init(vmx_init)
4266 module_exit(vmx_exit)