arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #include <asm/hpet.h>
   8
   9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  10
  11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  12 {
  13         u8 config, rev;
  14         u16 word;
  15
  16         /* BIOS may enable hardware IRQ balancing for
  17          * E7520/E7320/E7525(revision ID 0x9 and below)
  18          * based platforms.
  19          * Disable SW irqbalance/affinity on those platforms.
  20          */
  21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  22         if (rev > 0x9)
  23                 return;
  24
  25         /* enable access to config space*/
  26         pci_read_config_byte(dev, 0xf4, &config);
  27         pci_write_config_byte(dev, 0xf4, config|0x2);
  28
  29         /*
  30          * read xTPR register.  We may not have a pci_dev for device 8
  31          * because it might be hidden until the above write.
  32          */
  33         pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
  34
  35         if (!(word & (1 << 13))) {
  36                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
  37                         "disabling irq balancing and affinity\n");
  38                 noirqdebug_setup("");
  39 #ifdef CONFIG_PROC_FS
  40                 no_irq_affinity = 1;
  41 #endif
  42         }
  43
  44         /* put back the original value for config space*/
  45         if (!(config & 0x2))
  46                 pci_write_config_byte(dev, 0xf4, config);
  47 }
  48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  49                         quirk_intel_irqbalance);
  50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  51                         quirk_intel_irqbalance);
  52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  53                         quirk_intel_irqbalance);
  54 #endif
  55
  56 #if defined(CONFIG_HPET_TIMER)
  57 unsigned long force_hpet_address;
  58
  59 static enum {
  60         NONE_FORCE_HPET_RESUME,
  61         OLD_ICH_FORCE_HPET_RESUME,
  62         ICH_FORCE_HPET_RESUME,
  63         VT8237_FORCE_HPET_RESUME,
  64         NVIDIA_FORCE_HPET_RESUME,
  65         ATI_FORCE_HPET_RESUME,
  66 } force_hpet_resume_type;
  67
  68 static void __iomem *rcba_base;
  69
  70 static void ich_force_hpet_resume(void)
  71 {
  72         u32 val;
  73
  74         if (!force_hpet_address)
  75                 return;
  76
  77         if (rcba_base == NULL)
  78                 BUG();
  79
  80         /* read the Function Disable register, dword mode only */
  81         val = readl(rcba_base + 0x3404);
  82         if (!(val & 0x80)) {
  83                 /* HPET disabled in HPTC. Trying to enable */
  84                 writel(val | 0x80, rcba_base + 0x3404);
  85         }
  86
  87         val = readl(rcba_base + 0x3404);
  88         if (!(val & 0x80))
  89                 BUG();
  90         else
  91                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
  92
  93         return;
  94 }
  95
  96 static void ich_force_enable_hpet(struct pci_dev *dev)
  97 {
  98         u32 val;
  99         u32 uninitialized_var(rcba);
 100         int err = 0;
 101
 102         if (hpet_address || force_hpet_address)
 103                 return;
 104
 105         pci_read_config_dword(dev, 0xF0, &rcba);
 106         rcba &= 0xFFFFC000;
 107         if (rcba == 0) {
 108                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
 109                         "cannot force enable HPET\n");
 110                 return;
 111         }
 112
 113         /* use bits 31:14, 16 kB aligned */
 114         rcba_base = ioremap_nocache(rcba, 0x4000);
 115         if (rcba_base == NULL) {
 116                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
 117                         "cannot force enable HPET\n");
 118                 return;
 119         }
 120
 121         /* read the Function Disable register, dword mode only */
 122         val = readl(rcba_base + 0x3404);
 123
 124         if (val & 0x80) {
 125                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 126                 val = val & 0x3;
 127                 force_hpet_address = 0xFED00000 | (val << 12);
 128                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 129                         "0x%lx\n", force_hpet_address);
 130                 iounmap(rcba_base);
 131                 return;
 132         }
 133
 134         /* HPET disabled in HPTC. Trying to enable */
 135         writel(val | 0x80, rcba_base + 0x3404);
 136
 137         val = readl(rcba_base + 0x3404);
 138         if (!(val & 0x80)) {
 139                 err = 1;
 140         } else {
 141                 val = val & 0x3;
 142                 force_hpet_address = 0xFED00000 | (val << 12);
 143         }
 144
 145         if (err) {
 146                 force_hpet_address = 0;
 147                 iounmap(rcba_base);
 148                 dev_printk(KERN_DEBUG, &dev->dev,
 149                         "Failed to force enable HPET\n");
 150         } else {
 151                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 152                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 153                         "0x%lx\n", force_hpet_address);
 154         }
 155 }
 156
 157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 158                          ich_force_enable_hpet);
 159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
 160                          ich_force_enable_hpet);
 161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 162                          ich_force_enable_hpet);
 163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 164                          ich_force_enable_hpet);
 165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 166                          ich_force_enable_hpet);
 167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 168                          ich_force_enable_hpet);
 169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 170                          ich_force_enable_hpet);
 171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
 172                          ich_force_enable_hpet);
 173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
 174                          ich_force_enable_hpet);
 175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16,   /* ICH10 */
 176                          ich_force_enable_hpet);
 177
 178 static struct pci_dev *cached_dev;
 179
 180 static void hpet_print_force_info(void)
 181 {
 182         printk(KERN_INFO "HPET not enabled in BIOS. "
 183                "You might try hpet=force boot option\n");
 184 }
 185
 186 static void old_ich_force_hpet_resume(void)
 187 {
 188         u32 val;
 189         u32 uninitialized_var(gen_cntl);
 190
 191         if (!force_hpet_address || !cached_dev)
 192                 return;
 193
 194         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 195         gen_cntl &= (~(0x7 << 15));
 196         gen_cntl |= (0x4 << 15);
 197
 198         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 199         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 200         val = gen_cntl >> 15;
 201         val &= 0x7;
 202         if (val == 0x4)
 203                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 204         else
 205                 BUG();
 206 }
 207
 208 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 209 {
 210         u32 val;
 211         u32 uninitialized_var(gen_cntl);
 212
 213         if (hpet_address || force_hpet_address)
 214                 return;
 215
 216         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 217         /*
 218          * Bit 17 is HPET enable bit.
 219          * Bit 16:15 control the HPET base address.
 220          */
 221         val = gen_cntl >> 15;
 222         val &= 0x7;
 223         if (val & 0x4) {
 224                 val &= 0x3;
 225                 force_hpet_address = 0xFED00000 | (val << 12);
 226                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 227                         force_hpet_address);
 228                 return;
 229         }
 230
 231         /*
 232          * HPET is disabled. Trying enabling at FED00000 and check
 233          * whether it sticks
 234          */
 235         gen_cntl &= (~(0x7 << 15));
 236         gen_cntl |= (0x4 << 15);
 237         pci_write_config_dword(dev, 0xD0, gen_cntl);
 238
 239         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 240
 241         val = gen_cntl >> 15;
 242         val &= 0x7;
 243         if (val & 0x4) {
 244                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 245                 val &= 0x3;
 246                 force_hpet_address = 0xFED00000 | (val << 12);
 247                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 248                         "0x%lx\n", force_hpet_address);
 249                 cached_dev = dev;
 250                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 251                 return;
 252         }
 253
 254         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 255 }
 256
 257 /*
 258  * Undocumented chipset features. Make sure that the user enforced
 259  * this.
 260  */
 261 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 262 {
 263         if (hpet_force_user)
 264                 old_ich_force_enable_hpet(dev);
 265         else
 266                 hpet_print_force_info();
 267 }
 268
 269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
 270                          old_ich_force_enable_hpet_user);
 271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 272                          old_ich_force_enable_hpet_user);
 273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
 274                          old_ich_force_enable_hpet_user);
 275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 276                          old_ich_force_enable_hpet_user);
 277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
 278                          old_ich_force_enable_hpet_user);
 279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 280                          old_ich_force_enable_hpet);
 281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 282                          old_ich_force_enable_hpet);
 283
 284
 285 static void vt8237_force_hpet_resume(void)
 286 {
 287         u32 val;
 288
 289         if (!force_hpet_address || !cached_dev)
 290                 return;
 291
 292         val = 0xfed00000 | 0x80;
 293         pci_write_config_dword(cached_dev, 0x68, val);
 294
 295         pci_read_config_dword(cached_dev, 0x68, &val);
 296         if (val & 0x80)
 297                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 298         else
 299                 BUG();
 300 }
 301
 302 static void vt8237_force_enable_hpet(struct pci_dev *dev)
 303 {
 304         u32 uninitialized_var(val);
 305
 306         if (hpet_address || force_hpet_address)
 307                 return;
 308
 309         if (!hpet_force_user) {
 310                 hpet_print_force_info();
 311                 return;
 312         }
 313
 314         pci_read_config_dword(dev, 0x68, &val);
 315         /*
 316          * Bit 7 is HPET enable bit.
 317          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
 318          */
 319         if (val & 0x80) {
 320                 force_hpet_address = (val & ~0x3ff);
 321                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 322                         force_hpet_address);
 323                 return;
 324         }
 325
 326         /*
 327          * HPET is disabled. Trying enabling at FED00000 and check
 328          * whether it sticks
 329          */
 330         val = 0xfed00000 | 0x80;
 331         pci_write_config_dword(dev, 0x68, val);
 332
 333         pci_read_config_dword(dev, 0x68, &val);
 334         if (val & 0x80) {
 335                 force_hpet_address = (val & ~0x3ff);
 336                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 337                         "0x%lx\n", force_hpet_address);
 338                 cached_dev = dev;
 339                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
 340                 return;
 341         }
 342
 343         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 344 }
 345
 346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 347                          vt8237_force_enable_hpet);
 348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
 349                          vt8237_force_enable_hpet);
 350
 351 static void ati_force_hpet_resume(void)
 352 {
 353         pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
 354         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 355 }
 356
 357 static u32 ati_ixp4x0_rev(struct pci_dev *dev)
 358 {
 359         u32 d;
 360         u8  b;
 361
 362         pci_read_config_byte(dev, 0xac, &b);
 363         b &= ~(1<<5);
 364         pci_write_config_byte(dev, 0xac, b);
 365         pci_read_config_dword(dev, 0x70, &d);
 366         d |= 1<<8;
 367         pci_write_config_dword(dev, 0x70, d);
 368         pci_read_config_dword(dev, 0x8, &d);
 369         d &= 0xff;
 370         dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
 371         return d;
 372 }
 373
 374 static void ati_force_enable_hpet(struct pci_dev *dev)
 375 {
 376         u32 d, val;
 377         u8  b;
 378
 379         if (hpet_address || force_hpet_address)
 380                 return;
 381
 382         if (!hpet_force_user) {
 383                 hpet_print_force_info();
 384                 return;
 385         }
 386
 387         d = ati_ixp4x0_rev(dev);
 388         if (d  < 0x82)
 389                 return;
 390
 391         /* base address */
 392         pci_write_config_dword(dev, 0x14, 0xfed00000);
 393         pci_read_config_dword(dev, 0x14, &val);
 394
 395         /* enable interrupt */
 396         outb(0x72, 0xcd6); b = inb(0xcd7);
 397         b |= 0x1;
 398         outb(0x72, 0xcd6); outb(b, 0xcd7);
 399         outb(0x72, 0xcd6); b = inb(0xcd7);
 400         if (!(b & 0x1))
 401                 return;
 402         pci_read_config_dword(dev, 0x64, &d);
 403         d |= (1<<10);
 404         pci_write_config_dword(dev, 0x64, d);
 405         pci_read_config_dword(dev, 0x64, &d);
 406         if (!(d & (1<<10)))
 407                 return;
 408
 409         force_hpet_address = val;
 410         force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
 411         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 412                    force_hpet_address);
 413         cached_dev = dev;
 414 }
 415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
 416                          ati_force_enable_hpet);
 417
 418 /*
 419  * Undocumented chipset feature taken from LinuxBIOS.
 420  */
 421 static void nvidia_force_hpet_resume(void)
 422 {
 423         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
 424         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 425 }
 426
 427 static void nvidia_force_enable_hpet(struct pci_dev *dev)
 428 {
 429         u32 uninitialized_var(val);
 430
 431         if (hpet_address || force_hpet_address)
 432                 return;
 433
 434         if (!hpet_force_user) {
 435                 hpet_print_force_info();
 436                 return;
 437         }
 438
 439         pci_write_config_dword(dev, 0x44, 0xfed00001);
 440         pci_read_config_dword(dev, 0x44, &val);
 441         force_hpet_address = val & 0xfffffffe;
 442         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
 443         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 444                 force_hpet_address);
 445         cached_dev = dev;
 446         return;
 447 }
 448
 449 /* ISA Bridges */
 450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
 451                         nvidia_force_enable_hpet);
 452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
 453                         nvidia_force_enable_hpet);
 454
 455 /* LPC bridges */
 456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
 457                         nvidia_force_enable_hpet);
 458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
 459                         nvidia_force_enable_hpet);
 460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
 461                         nvidia_force_enable_hpet);
 462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
 463                         nvidia_force_enable_hpet);
 464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
 465                         nvidia_force_enable_hpet);
 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
 467                         nvidia_force_enable_hpet);
 468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
 469                         nvidia_force_enable_hpet);
 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
 471                         nvidia_force_enable_hpet);
 472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
 473                         nvidia_force_enable_hpet);
 474
 475 void force_hpet_resume(void)
 476 {
 477         switch (force_hpet_resume_type) {
 478         case ICH_FORCE_HPET_RESUME:
 479                 ich_force_hpet_resume();
 480                 return;
 481         case OLD_ICH_FORCE_HPET_RESUME:
 482                 old_ich_force_hpet_resume();
 483                 return;
 484         case VT8237_FORCE_HPET_RESUME:
 485                 vt8237_force_hpet_resume();
 486                 return;
 487         case NVIDIA_FORCE_HPET_RESUME:
 488                 nvidia_force_hpet_resume();
 489                 return;
 490         case ATI_FORCE_HPET_RESUME:
 491                 ati_force_hpet_resume();
 492                 return;
 493         default:
 494                 break;
 495         }
 496 }
 497
 498 #endif