2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
32 static u64 perf_event_mask __read_mostly;
34 /* The maximal number of PEBS events: */
35 #define MAX_PEBS_EVENTS 4
37 /* The size of a BTS record in bytes: */
38 #define BTS_RECORD_SIZE 24
40 /* The size of a per-cpu BTS buffer in bytes: */
41 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
43 /* The BTS overflow threshold in bytes from the end of the buffer: */
44 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
48 * Bits in the debugctlmsr controlling branch tracing.
50 #define X86_DEBUGCTL_TR (1 << 6)
51 #define X86_DEBUGCTL_BTS (1 << 7)
52 #define X86_DEBUGCTL_BTINT (1 << 8)
53 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
54 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
57 * A debug store configuration.
59 * We only support architectures that use 64bit fields.
64 u64 bts_absolute_maximum;
65 u64 bts_interrupt_threshold;
68 u64 pebs_absolute_maximum;
69 u64 pebs_interrupt_threshold;
70 u64 pebs_event_reset[MAX_PEBS_EVENTS];
73 struct event_constraint {
75 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
84 int nb_id; /* NorthBridge id */
85 int refcnt; /* reference count */
86 struct perf_event *owners[X86_PMC_IDX_MAX];
87 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
90 struct cpu_hw_events {
91 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
92 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
93 unsigned long interrupts;
95 struct debug_store *ds;
99 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
100 u64 tags[X86_PMC_IDX_MAX];
101 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
102 struct amd_nb *amd_nb;
105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
106 { .idxmsk64 = (n) }, \
112 #define EVENT_CONSTRAINT(c, n, m) \
113 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
115 #define INTEL_EVENT_CONSTRAINT(c, n) \
116 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
118 #define FIXED_EVENT_CONSTRAINT(c, n) \
119 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
121 #define EVENT_CONSTRAINT_END \
122 EVENT_CONSTRAINT(0, 0, 0)
124 #define for_each_event_constraint(e, c) \
125 for ((e) = (c); (e)->cmask; (e)++)
128 * struct x86_pmu - generic x86 pmu
133 int (*handle_irq)(struct pt_regs *);
134 void (*disable_all)(void);
135 void (*enable_all)(void);
136 void (*enable)(struct hw_perf_event *, int);
137 void (*disable)(struct hw_perf_event *, int);
140 u64 (*event_map)(int);
141 u64 (*raw_event)(u64);
144 int num_events_fixed;
150 void (*enable_bts)(u64 config);
151 void (*disable_bts)(void);
153 struct event_constraint *
154 (*get_event_constraints)(struct cpu_hw_events *cpuc,
155 struct perf_event *event);
157 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
158 struct perf_event *event);
159 struct event_constraint *event_constraints;
161 void (*cpu_prepare)(int cpu);
162 void (*cpu_starting)(int cpu);
163 void (*cpu_dying)(int cpu);
164 void (*cpu_dead)(int cpu);
167 static struct x86_pmu x86_pmu __read_mostly;
169 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
173 static int x86_perf_event_set_period(struct perf_event *event);
176 * Generalized hw caching related hw_event table, filled
177 * in on a per model basis. A value of 0 means
178 * 'not supported', -1 means 'hw_event makes no sense on
179 * this CPU', any other value means the raw hw_event
183 #define C(x) PERF_COUNT_HW_CACHE_##x
185 static u64 __read_mostly hw_cache_event_ids
186 [PERF_COUNT_HW_CACHE_MAX]
187 [PERF_COUNT_HW_CACHE_OP_MAX]
188 [PERF_COUNT_HW_CACHE_RESULT_MAX];
191 * Propagate event elapsed time into the generic event.
192 * Can only be executed on the CPU where the event is active.
193 * Returns the delta events processed.
196 x86_perf_event_update(struct perf_event *event,
197 struct hw_perf_event *hwc, int idx)
199 int shift = 64 - x86_pmu.event_bits;
200 u64 prev_raw_count, new_raw_count;
203 if (idx == X86_PMC_IDX_FIXED_BTS)
207 * Careful: an NMI might modify the previous event value.
209 * Our tactic to handle this is to first atomically read and
210 * exchange a new raw count - then add that new-prev delta
211 * count to the generic event atomically:
214 prev_raw_count = atomic64_read(&hwc->prev_count);
215 rdmsrl(hwc->event_base + idx, new_raw_count);
217 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
218 new_raw_count) != prev_raw_count)
222 * Now we have the new raw value and have updated the prev
223 * timestamp already. We can now calculate the elapsed delta
224 * (event-)time and add that to the generic event.
226 * Careful, not all hw sign-extends above the physical width
229 delta = (new_raw_count << shift) - (prev_raw_count << shift);
232 atomic64_add(delta, &event->count);
233 atomic64_sub(delta, &hwc->period_left);
235 return new_raw_count;
238 static atomic_t active_events;
239 static DEFINE_MUTEX(pmc_reserve_mutex);
241 static bool reserve_pmc_hardware(void)
243 #ifdef CONFIG_X86_LOCAL_APIC
246 if (nmi_watchdog == NMI_LOCAL_APIC)
247 disable_lapic_nmi_watchdog();
249 for (i = 0; i < x86_pmu.num_events; i++) {
250 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
254 for (i = 0; i < x86_pmu.num_events; i++) {
255 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
262 #ifdef CONFIG_X86_LOCAL_APIC
264 for (i--; i >= 0; i--)
265 release_evntsel_nmi(x86_pmu.eventsel + i);
267 i = x86_pmu.num_events;
270 for (i--; i >= 0; i--)
271 release_perfctr_nmi(x86_pmu.perfctr + i);
273 if (nmi_watchdog == NMI_LOCAL_APIC)
274 enable_lapic_nmi_watchdog();
280 static void release_pmc_hardware(void)
282 #ifdef CONFIG_X86_LOCAL_APIC
285 for (i = 0; i < x86_pmu.num_events; i++) {
286 release_perfctr_nmi(x86_pmu.perfctr + i);
287 release_evntsel_nmi(x86_pmu.eventsel + i);
290 if (nmi_watchdog == NMI_LOCAL_APIC)
291 enable_lapic_nmi_watchdog();
295 static inline bool bts_available(void)
297 return x86_pmu.enable_bts != NULL;
300 static void init_debug_store_on_cpu(int cpu)
302 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
307 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
308 (u32)((u64)(unsigned long)ds),
309 (u32)((u64)(unsigned long)ds >> 32));
312 static void fini_debug_store_on_cpu(int cpu)
314 if (!per_cpu(cpu_hw_events, cpu).ds)
317 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
320 static void release_bts_hardware(void)
324 if (!bts_available())
329 for_each_online_cpu(cpu)
330 fini_debug_store_on_cpu(cpu);
332 for_each_possible_cpu(cpu) {
333 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
338 per_cpu(cpu_hw_events, cpu).ds = NULL;
340 kfree((void *)(unsigned long)ds->bts_buffer_base);
347 static int reserve_bts_hardware(void)
351 if (!bts_available())
356 for_each_possible_cpu(cpu) {
357 struct debug_store *ds;
361 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
362 if (unlikely(!buffer))
365 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
371 ds->bts_buffer_base = (u64)(unsigned long)buffer;
372 ds->bts_index = ds->bts_buffer_base;
373 ds->bts_absolute_maximum =
374 ds->bts_buffer_base + BTS_BUFFER_SIZE;
375 ds->bts_interrupt_threshold =
376 ds->bts_absolute_maximum - BTS_OVFL_TH;
378 per_cpu(cpu_hw_events, cpu).ds = ds;
383 release_bts_hardware();
385 for_each_online_cpu(cpu)
386 init_debug_store_on_cpu(cpu);
394 static void hw_perf_event_destroy(struct perf_event *event)
396 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
397 release_pmc_hardware();
398 release_bts_hardware();
399 mutex_unlock(&pmc_reserve_mutex);
403 static inline int x86_pmu_initialized(void)
405 return x86_pmu.handle_irq != NULL;
409 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
411 unsigned int cache_type, cache_op, cache_result;
414 config = attr->config;
416 cache_type = (config >> 0) & 0xff;
417 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
420 cache_op = (config >> 8) & 0xff;
421 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
424 cache_result = (config >> 16) & 0xff;
425 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
428 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
442 * Setup the hardware configuration for a given attr_type
444 static int __hw_perf_event_init(struct perf_event *event)
446 struct perf_event_attr *attr = &event->attr;
447 struct hw_perf_event *hwc = &event->hw;
451 if (!x86_pmu_initialized())
455 if (!atomic_inc_not_zero(&active_events)) {
456 mutex_lock(&pmc_reserve_mutex);
457 if (atomic_read(&active_events) == 0) {
458 if (!reserve_pmc_hardware())
461 err = reserve_bts_hardware();
464 atomic_inc(&active_events);
465 mutex_unlock(&pmc_reserve_mutex);
470 event->destroy = hw_perf_event_destroy;
474 * (keep 'enabled' bit clear for now)
476 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
480 hwc->last_tag = ~0ULL;
483 * Count user and OS events unless requested not to.
485 if (!attr->exclude_user)
486 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
487 if (!attr->exclude_kernel)
488 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
490 if (!hwc->sample_period) {
491 hwc->sample_period = x86_pmu.max_period;
492 hwc->last_period = hwc->sample_period;
493 atomic64_set(&hwc->period_left, hwc->sample_period);
496 * If we have a PMU initialized but no APIC
497 * interrupts, we cannot sample hardware
498 * events (user-space has to fall back and
499 * sample via a hrtimer based software event):
506 * Raw hw_event type provide the config in the hw_event structure
508 if (attr->type == PERF_TYPE_RAW) {
509 hwc->config |= x86_pmu.raw_event(attr->config);
510 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
511 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
516 if (attr->type == PERF_TYPE_HW_CACHE)
517 return set_ext_hw_attr(hwc, attr);
519 if (attr->config >= x86_pmu.max_events)
525 config = x86_pmu.event_map(attr->config);
536 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
537 (hwc->sample_period == 1)) {
538 /* BTS is not supported by this architecture. */
539 if (!bts_available())
542 /* BTS is currently only allowed for user-mode. */
543 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
547 hwc->config |= config;
552 static void x86_pmu_disable_all(void)
554 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
557 for (idx = 0; idx < x86_pmu.num_events; idx++) {
560 if (!test_bit(idx, cpuc->active_mask))
562 rdmsrl(x86_pmu.eventsel + idx, val);
563 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
565 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
566 wrmsrl(x86_pmu.eventsel + idx, val);
570 void hw_perf_disable(void)
572 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
574 if (!x86_pmu_initialized())
584 x86_pmu.disable_all();
587 static void x86_pmu_enable_all(void)
589 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
592 for (idx = 0; idx < x86_pmu.num_events; idx++) {
593 struct perf_event *event = cpuc->events[idx];
596 if (!test_bit(idx, cpuc->active_mask))
599 val = event->hw.config;
600 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
601 wrmsrl(x86_pmu.eventsel + idx, val);
605 static const struct pmu pmu;
607 static inline int is_x86_event(struct perf_event *event)
609 return event->pmu == &pmu;
612 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
614 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
615 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
616 int i, j, w, wmax, num = 0;
617 struct hw_perf_event *hwc;
619 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
621 for (i = 0; i < n; i++) {
622 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
627 * fastpath, try to reuse previous register
629 for (i = 0; i < n; i++) {
630 hwc = &cpuc->event_list[i]->hw;
637 /* constraint still honored */
638 if (!test_bit(hwc->idx, c->idxmsk))
641 /* not already used */
642 if (test_bit(hwc->idx, used_mask))
645 set_bit(hwc->idx, used_mask);
647 assign[i] = hwc->idx;
656 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
659 * weight = number of possible counters
661 * 1 = most constrained, only works on one counter
662 * wmax = least constrained, works on any counter
664 * assign events to counters starting with most
665 * constrained events.
667 wmax = x86_pmu.num_events;
670 * when fixed event counters are present,
671 * wmax is incremented by 1 to account
672 * for one more choice
674 if (x86_pmu.num_events_fixed)
677 for (w = 1, num = n; num && w <= wmax; w++) {
679 for (i = 0; num && i < n; i++) {
681 hwc = &cpuc->event_list[i]->hw;
686 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
687 if (!test_bit(j, used_mask))
691 if (j == X86_PMC_IDX_MAX)
694 set_bit(j, used_mask);
703 * scheduling failed or is just a simulation,
704 * free resources if necessary
706 if (!assign || num) {
707 for (i = 0; i < n; i++) {
708 if (x86_pmu.put_event_constraints)
709 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
712 return num ? -ENOSPC : 0;
716 * dogrp: true if must collect siblings events (group)
717 * returns total number of events and error code
719 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
721 struct perf_event *event;
724 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
726 /* current number of events already accepted */
729 if (is_x86_event(leader)) {
732 cpuc->event_list[n] = leader;
738 list_for_each_entry(event, &leader->sibling_list, group_entry) {
739 if (!is_x86_event(event) ||
740 event->state <= PERF_EVENT_STATE_OFF)
746 cpuc->event_list[n] = event;
752 static inline void x86_assign_hw_event(struct perf_event *event,
753 struct cpu_hw_events *cpuc, int i)
755 struct hw_perf_event *hwc = &event->hw;
757 hwc->idx = cpuc->assign[i];
758 hwc->last_cpu = smp_processor_id();
759 hwc->last_tag = ++cpuc->tags[i];
761 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
762 hwc->config_base = 0;
764 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
765 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
767 * We set it so that event_base + idx in wrmsr/rdmsr maps to
768 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
771 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
773 hwc->config_base = x86_pmu.eventsel;
774 hwc->event_base = x86_pmu.perfctr;
778 static inline int match_prev_assignment(struct hw_perf_event *hwc,
779 struct cpu_hw_events *cpuc,
782 return hwc->idx == cpuc->assign[i] &&
783 hwc->last_cpu == smp_processor_id() &&
784 hwc->last_tag == cpuc->tags[i];
787 static void x86_pmu_stop(struct perf_event *event);
789 void hw_perf_enable(void)
791 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
792 struct perf_event *event;
793 struct hw_perf_event *hwc;
796 if (!x86_pmu_initialized())
804 * apply assignment obtained either from
805 * hw_perf_group_sched_in() or x86_pmu_enable()
807 * step1: save events moving to new counters
808 * step2: reprogram moved events into new counters
810 for (i = 0; i < cpuc->n_events; i++) {
812 event = cpuc->event_list[i];
816 * we can avoid reprogramming counter if:
817 * - assigned same counter as last time
818 * - running on same CPU as last time
819 * - no other event has used the counter since
821 if (hwc->idx == -1 ||
822 match_prev_assignment(hwc, cpuc, i))
830 for (i = 0; i < cpuc->n_events; i++) {
832 event = cpuc->event_list[i];
835 if (hwc->idx == -1) {
836 x86_assign_hw_event(event, cpuc, i);
837 x86_perf_event_set_period(event);
840 * need to mark as active because x86_pmu_disable()
841 * clear active_mask and events[] yet it preserves
844 set_bit(hwc->idx, cpuc->active_mask);
845 cpuc->events[hwc->idx] = event;
847 x86_pmu.enable(hwc, hwc->idx);
848 perf_event_update_userpage(event);
851 perf_events_lapic_init();
857 x86_pmu.enable_all();
860 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
862 (void)checking_wrmsrl(hwc->config_base + idx,
863 hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
866 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
868 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
871 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
874 * Set the next IRQ period, based on the hwc->period_left value.
875 * To be called with the event disabled in hw:
878 x86_perf_event_set_period(struct perf_event *event)
880 struct hw_perf_event *hwc = &event->hw;
881 s64 left = atomic64_read(&hwc->period_left);
882 s64 period = hwc->sample_period;
883 int err, ret = 0, idx = hwc->idx;
885 if (idx == X86_PMC_IDX_FIXED_BTS)
889 * If we are way outside a reasonable range then just skip forward:
891 if (unlikely(left <= -period)) {
893 atomic64_set(&hwc->period_left, left);
894 hwc->last_period = period;
898 if (unlikely(left <= 0)) {
900 atomic64_set(&hwc->period_left, left);
901 hwc->last_period = period;
905 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
907 if (unlikely(left < 2))
910 if (left > x86_pmu.max_period)
911 left = x86_pmu.max_period;
913 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
916 * The hw event starts counting from this event offset,
917 * mark it to be able to extra future deltas:
919 atomic64_set(&hwc->prev_count, (u64)-left);
921 err = checking_wrmsrl(hwc->event_base + idx,
922 (u64)(-left) & x86_pmu.event_mask);
924 perf_event_update_userpage(event);
929 static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
931 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
933 __x86_pmu_enable_event(hwc, idx);
937 * activate a single event
939 * The event is added to the group of enabled events
940 * but only if it can be scehduled with existing events.
942 * Called with PMU disabled. If successful and return value 1,
943 * then guaranteed to call perf_enable() and hw_perf_enable()
945 static int x86_pmu_enable(struct perf_event *event)
947 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
948 struct hw_perf_event *hwc;
949 int assign[X86_PMC_IDX_MAX];
955 n = collect_events(cpuc, event, false);
959 ret = x86_schedule_events(cpuc, n, assign);
963 * copy new assignment, now we know it is possible
964 * will be used by hw_perf_enable()
966 memcpy(cpuc->assign, assign, n*sizeof(int));
969 cpuc->n_added = n - n0;
974 static int x86_pmu_start(struct perf_event *event)
976 struct hw_perf_event *hwc = &event->hw;
981 x86_perf_event_set_period(event);
982 x86_pmu.enable(hwc, hwc->idx);
987 static void x86_pmu_unthrottle(struct perf_event *event)
989 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
990 struct hw_perf_event *hwc = &event->hw;
992 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
993 cpuc->events[hwc->idx] != event))
996 x86_pmu.enable(hwc, hwc->idx);
999 void perf_event_print_debug(void)
1001 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1002 struct cpu_hw_events *cpuc;
1003 unsigned long flags;
1006 if (!x86_pmu.num_events)
1009 local_irq_save(flags);
1011 cpu = smp_processor_id();
1012 cpuc = &per_cpu(cpu_hw_events, cpu);
1014 if (x86_pmu.version >= 2) {
1015 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1016 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1017 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1018 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1021 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1022 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1023 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1024 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1026 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1028 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1029 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1030 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1032 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1034 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1035 cpu, idx, pmc_ctrl);
1036 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1037 cpu, idx, pmc_count);
1038 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1039 cpu, idx, prev_left);
1041 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1042 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1044 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1045 cpu, idx, pmc_count);
1047 local_irq_restore(flags);
1050 static void x86_pmu_stop(struct perf_event *event)
1052 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1053 struct hw_perf_event *hwc = &event->hw;
1057 * Must be done before we disable, otherwise the nmi handler
1058 * could reenable again:
1060 clear_bit(idx, cpuc->active_mask);
1061 x86_pmu.disable(hwc, idx);
1064 * Drain the remaining delta count out of a event
1065 * that we are disabling:
1067 x86_perf_event_update(event, hwc, idx);
1069 cpuc->events[idx] = NULL;
1072 static void x86_pmu_disable(struct perf_event *event)
1074 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1077 x86_pmu_stop(event);
1079 for (i = 0; i < cpuc->n_events; i++) {
1080 if (event == cpuc->event_list[i]) {
1082 if (x86_pmu.put_event_constraints)
1083 x86_pmu.put_event_constraints(cpuc, event);
1085 while (++i < cpuc->n_events)
1086 cpuc->event_list[i-1] = cpuc->event_list[i];
1092 perf_event_update_userpage(event);
1095 static int x86_pmu_handle_irq(struct pt_regs *regs)
1097 struct perf_sample_data data;
1098 struct cpu_hw_events *cpuc;
1099 struct perf_event *event;
1100 struct hw_perf_event *hwc;
1101 int idx, handled = 0;
1104 perf_sample_data_init(&data, 0);
1106 cpuc = &__get_cpu_var(cpu_hw_events);
1108 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1109 if (!test_bit(idx, cpuc->active_mask))
1112 event = cpuc->events[idx];
1115 val = x86_perf_event_update(event, hwc, idx);
1116 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1123 data.period = event->hw.last_period;
1125 if (!x86_perf_event_set_period(event))
1128 if (perf_event_overflow(event, 1, &data, regs))
1129 x86_pmu.disable(hwc, idx);
1133 inc_irq_stat(apic_perf_irqs);
1138 void smp_perf_pending_interrupt(struct pt_regs *regs)
1142 inc_irq_stat(apic_pending_irqs);
1143 perf_event_do_pending();
1147 void set_perf_event_pending(void)
1149 #ifdef CONFIG_X86_LOCAL_APIC
1150 if (!x86_pmu.apic || !x86_pmu_initialized())
1153 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1157 void perf_events_lapic_init(void)
1159 #ifdef CONFIG_X86_LOCAL_APIC
1160 if (!x86_pmu.apic || !x86_pmu_initialized())
1164 * Always use NMI for PMU
1166 apic_write(APIC_LVTPC, APIC_DM_NMI);
1170 static int __kprobes
1171 perf_event_nmi_handler(struct notifier_block *self,
1172 unsigned long cmd, void *__args)
1174 struct die_args *args = __args;
1175 struct pt_regs *regs;
1177 if (!atomic_read(&active_events))
1191 #ifdef CONFIG_X86_LOCAL_APIC
1192 apic_write(APIC_LVTPC, APIC_DM_NMI);
1195 * Can't rely on the handled return value to say it was our NMI, two
1196 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1198 * If the first NMI handles both, the latter will be empty and daze
1201 x86_pmu.handle_irq(regs);
1206 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1207 .notifier_call = perf_event_nmi_handler,
1212 static struct event_constraint unconstrained;
1213 static struct event_constraint emptyconstraint;
1215 static struct event_constraint *
1216 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1218 struct event_constraint *c;
1220 if (x86_pmu.event_constraints) {
1221 for_each_event_constraint(c, x86_pmu.event_constraints) {
1222 if ((event->hw.config & c->cmask) == c->code)
1227 return &unconstrained;
1230 static int x86_event_sched_in(struct perf_event *event,
1231 struct perf_cpu_context *cpuctx)
1235 event->state = PERF_EVENT_STATE_ACTIVE;
1236 event->oncpu = smp_processor_id();
1237 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1239 if (!is_x86_event(event))
1240 ret = event->pmu->enable(event);
1242 if (!ret && !is_software_event(event))
1243 cpuctx->active_oncpu++;
1245 if (!ret && event->attr.exclusive)
1246 cpuctx->exclusive = 1;
1251 static void x86_event_sched_out(struct perf_event *event,
1252 struct perf_cpu_context *cpuctx)
1254 event->state = PERF_EVENT_STATE_INACTIVE;
1257 if (!is_x86_event(event))
1258 event->pmu->disable(event);
1260 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1262 if (!is_software_event(event))
1263 cpuctx->active_oncpu--;
1265 if (event->attr.exclusive || !cpuctx->active_oncpu)
1266 cpuctx->exclusive = 0;
1270 * Called to enable a whole group of events.
1271 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1272 * Assumes the caller has disabled interrupts and has
1273 * frozen the PMU with hw_perf_save_disable.
1275 * called with PMU disabled. If successful and return value 1,
1276 * then guaranteed to call perf_enable() and hw_perf_enable()
1278 int hw_perf_group_sched_in(struct perf_event *leader,
1279 struct perf_cpu_context *cpuctx,
1280 struct perf_event_context *ctx)
1282 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1283 struct perf_event *sub;
1284 int assign[X86_PMC_IDX_MAX];
1287 /* n0 = total number of events */
1288 n0 = collect_events(cpuc, leader, true);
1292 ret = x86_schedule_events(cpuc, n0, assign);
1296 ret = x86_event_sched_in(leader, cpuctx);
1301 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1302 if (sub->state > PERF_EVENT_STATE_OFF) {
1303 ret = x86_event_sched_in(sub, cpuctx);
1310 * copy new assignment, now we know it is possible
1311 * will be used by hw_perf_enable()
1313 memcpy(cpuc->assign, assign, n0*sizeof(int));
1315 cpuc->n_events = n0;
1317 ctx->nr_active += n1;
1320 * 1 means successful and events are active
1321 * This is not quite true because we defer
1322 * actual activation until hw_perf_enable() but
1323 * this way we* ensure caller won't try to enable
1328 x86_event_sched_out(leader, cpuctx);
1330 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1331 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1332 x86_event_sched_out(sub, cpuctx);
1340 #include "perf_event_amd.c"
1341 #include "perf_event_p6.c"
1342 #include "perf_event_intel.c"
1344 static int __cpuinit
1345 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1347 unsigned int cpu = (long)hcpu;
1349 switch (action & ~CPU_TASKS_FROZEN) {
1350 case CPU_UP_PREPARE:
1351 if (x86_pmu.cpu_prepare)
1352 x86_pmu.cpu_prepare(cpu);
1356 if (x86_pmu.cpu_starting)
1357 x86_pmu.cpu_starting(cpu);
1361 if (x86_pmu.cpu_dying)
1362 x86_pmu.cpu_dying(cpu);
1366 if (x86_pmu.cpu_dead)
1367 x86_pmu.cpu_dead(cpu);
1377 static void __init pmu_check_apic(void)
1383 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1384 pr_info("no hardware sampling interrupt available.\n");
1387 void __init init_hw_perf_events(void)
1389 struct event_constraint *c;
1392 pr_info("Performance Events: ");
1394 switch (boot_cpu_data.x86_vendor) {
1395 case X86_VENDOR_INTEL:
1396 err = intel_pmu_init();
1398 case X86_VENDOR_AMD:
1399 err = amd_pmu_init();
1405 pr_cont("no PMU driver, software events only.\n");
1411 pr_cont("%s PMU driver.\n", x86_pmu.name);
1413 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1414 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1415 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1416 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1418 perf_event_mask = (1 << x86_pmu.num_events) - 1;
1419 perf_max_events = x86_pmu.num_events;
1421 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1422 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1423 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1424 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1428 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1429 x86_pmu.intel_ctrl = perf_event_mask;
1431 perf_events_lapic_init();
1432 register_die_notifier(&perf_event_nmi_notifier);
1434 unconstrained = (struct event_constraint)
1435 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1436 0, x86_pmu.num_events);
1438 if (x86_pmu.event_constraints) {
1439 for_each_event_constraint(c, x86_pmu.event_constraints) {
1440 if (c->cmask != INTEL_ARCH_FIXED_MASK)
1443 c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1444 c->weight += x86_pmu.num_events;
1448 pr_info("... version: %d\n", x86_pmu.version);
1449 pr_info("... bit width: %d\n", x86_pmu.event_bits);
1450 pr_info("... generic registers: %d\n", x86_pmu.num_events);
1451 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
1452 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1453 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
1454 pr_info("... event mask: %016Lx\n", perf_event_mask);
1456 perf_cpu_notifier(x86_pmu_notifier);
1459 static inline void x86_pmu_read(struct perf_event *event)
1461 x86_perf_event_update(event, &event->hw, event->hw.idx);
1464 static const struct pmu pmu = {
1465 .enable = x86_pmu_enable,
1466 .disable = x86_pmu_disable,
1467 .start = x86_pmu_start,
1468 .stop = x86_pmu_stop,
1469 .read = x86_pmu_read,
1470 .unthrottle = x86_pmu_unthrottle,
1474 * validate a single event group
1476 * validation include:
1477 * - check events are compatible which each other
1478 * - events do not compete for the same counter
1479 * - number of events <= number of counters
1481 * validation ensures the group can be loaded onto the
1482 * PMU if it was the only group available.
1484 static int validate_group(struct perf_event *event)
1486 struct perf_event *leader = event->group_leader;
1487 struct cpu_hw_events *fake_cpuc;
1491 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1496 * the event is not yet connected with its
1497 * siblings therefore we must first collect
1498 * existing siblings, then add the new event
1499 * before we can simulate the scheduling
1502 n = collect_events(fake_cpuc, leader, true);
1506 fake_cpuc->n_events = n;
1507 n = collect_events(fake_cpuc, event, false);
1511 fake_cpuc->n_events = n;
1513 ret = x86_schedule_events(fake_cpuc, n, NULL);
1521 const struct pmu *hw_perf_event_init(struct perf_event *event)
1523 const struct pmu *tmp;
1526 err = __hw_perf_event_init(event);
1529 * we temporarily connect event to its pmu
1530 * such that validate_group() can classify
1531 * it as an x86 event using is_x86_event()
1536 if (event->group_leader != event)
1537 err = validate_group(event);
1543 event->destroy(event);
1544 return ERR_PTR(err);
1555 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1557 if (entry->nr < PERF_MAX_STACK_DEPTH)
1558 entry->ip[entry->nr++] = ip;
1561 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1562 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1566 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1568 /* Ignore warnings */
1571 static void backtrace_warning(void *data, char *msg)
1573 /* Ignore warnings */
1576 static int backtrace_stack(void *data, char *name)
1581 static void backtrace_address(void *data, unsigned long addr, int reliable)
1583 struct perf_callchain_entry *entry = data;
1586 callchain_store(entry, addr);
1589 static const struct stacktrace_ops backtrace_ops = {
1590 .warning = backtrace_warning,
1591 .warning_symbol = backtrace_warning_symbol,
1592 .stack = backtrace_stack,
1593 .address = backtrace_address,
1594 .walk_stack = print_context_stack_bp,
1597 #include "../dumpstack.h"
1600 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1602 callchain_store(entry, PERF_CONTEXT_KERNEL);
1603 callchain_store(entry, regs->ip);
1605 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1609 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1611 static unsigned long
1612 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1614 unsigned long offset, addr = (unsigned long)from;
1615 int type = in_nmi() ? KM_NMI : KM_IRQ0;
1616 unsigned long size, len = 0;
1622 ret = __get_user_pages_fast(addr, 1, 0, &page);
1626 offset = addr & (PAGE_SIZE - 1);
1627 size = min(PAGE_SIZE - offset, n - len);
1629 map = kmap_atomic(page, type);
1630 memcpy(to, map+offset, size);
1631 kunmap_atomic(map, type);
1643 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1645 unsigned long bytes;
1647 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1649 return bytes == sizeof(*frame);
1653 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1655 struct stack_frame frame;
1656 const void __user *fp;
1658 if (!user_mode(regs))
1659 regs = task_pt_regs(current);
1661 fp = (void __user *)regs->bp;
1663 callchain_store(entry, PERF_CONTEXT_USER);
1664 callchain_store(entry, regs->ip);
1666 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1667 frame.next_frame = NULL;
1668 frame.return_address = 0;
1670 if (!copy_stack_frame(fp, &frame))
1673 if ((unsigned long)fp < regs->sp)
1676 callchain_store(entry, frame.return_address);
1677 fp = frame.next_frame;
1682 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1689 is_user = user_mode(regs);
1691 if (is_user && current->state != TASK_RUNNING)
1695 perf_callchain_kernel(regs, entry);
1698 perf_callchain_user(regs, entry);
1701 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1703 struct perf_callchain_entry *entry;
1706 entry = &__get_cpu_var(pmc_nmi_entry);
1708 entry = &__get_cpu_var(pmc_irq_entry);
1712 perf_do_callchain(regs, entry);