2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug = -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock);
78 static DEFINE_RAW_SPINLOCK(vector_lock);
81 * # of IRQ routing registers
83 int nr_ioapic_registers[MAX_IO_APICS];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type[MAX_MP_BUSSES];
108 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
110 int skip_ioapic_setup;
112 void arch_disable_smp_support(void)
116 noioapicreroute = -1;
118 skip_ioapic_setup = 1;
121 static int __init parse_noapic(char *str)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic);
129 struct irq_pin_list {
131 struct irq_pin_list *next;
134 static struct irq_pin_list *alloc_irq_pin_list(int node)
136 return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
143 static struct irq_cfg irq_cfgx[NR_IRQS];
146 int __init arch_early_irq_init(void)
151 if (!legacy_pic->nr_legacy_irqs) {
157 count = ARRAY_SIZE(irq_cfgx);
158 node = cpu_to_node(0);
160 for (i = 0; i < count; i++) {
161 set_irq_chip_data(i, &cfg[i]);
162 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
163 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
165 * For legacy IRQ's, start with assigning irq0 to irq15 to
166 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
168 if (i < legacy_pic->nr_legacy_irqs) {
169 cfg[i].vector = IRQ0_VECTOR + i;
170 cpumask_set_cpu(0, cfg[i].domain);
177 #ifdef CONFIG_SPARSE_IRQ
178 struct irq_cfg *irq_cfg(unsigned int irq)
180 return get_irq_chip_data(irq);
183 static struct irq_cfg *get_one_free_irq_cfg(int node)
187 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
189 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
192 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
194 free_cpumask_var(cfg->domain);
203 int arch_init_chip_data(struct irq_desc *desc, int node)
207 cfg = get_irq_desc_chip_data(desc);
209 cfg = get_one_free_irq_cfg(node);
210 desc->chip_data = cfg;
212 printk(KERN_ERR "can not alloc irq_cfg\n");
220 /* for move_irq_desc */
222 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
224 struct irq_pin_list *old_entry, *head, *tail, *entry;
226 cfg->irq_2_pin = NULL;
227 old_entry = old_cfg->irq_2_pin;
231 entry = alloc_irq_pin_list(node);
235 entry->apic = old_entry->apic;
236 entry->pin = old_entry->pin;
239 old_entry = old_entry->next;
241 entry = alloc_irq_pin_list(node);
249 /* still use the old one */
252 entry->apic = old_entry->apic;
253 entry->pin = old_entry->pin;
256 old_entry = old_entry->next;
260 cfg->irq_2_pin = head;
263 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
265 struct irq_pin_list *entry, *next;
267 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
270 entry = old_cfg->irq_2_pin;
277 old_cfg->irq_2_pin = NULL;
280 void arch_init_copy_chip_data(struct irq_desc *old_desc,
281 struct irq_desc *desc, int node)
284 struct irq_cfg *old_cfg;
286 cfg = get_one_free_irq_cfg(node);
291 desc->chip_data = cfg;
293 old_cfg = old_desc->chip_data;
295 cfg->vector = old_cfg->vector;
296 cfg->move_in_progress = old_cfg->move_in_progress;
297 cpumask_copy(cfg->domain, old_cfg->domain);
298 cpumask_copy(cfg->old_domain, old_cfg->old_domain);
300 init_copy_irq_2_pin(old_cfg, cfg, node);
303 static void free_irq_cfg(struct irq_cfg *cfg)
305 free_cpumask_var(cfg->domain);
306 free_cpumask_var(cfg->old_domain);
310 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
312 struct irq_cfg *old_cfg, *cfg;
314 old_cfg = get_irq_desc_chip_data(old_desc);
315 cfg = get_irq_desc_chip_data(desc);
321 free_irq_2_pin(old_cfg, cfg);
322 free_irq_cfg(old_cfg);
323 old_desc->chip_data = NULL;
326 /* end for move_irq_desc */
329 struct irq_cfg *irq_cfg(unsigned int irq)
331 return irq < nr_irqs ? irq_cfgx + irq : NULL;
338 unsigned int unused[3];
340 unsigned int unused2[11];
344 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
346 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
347 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
350 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
352 struct io_apic __iomem *io_apic = io_apic_base(apic);
353 writel(vector, &io_apic->eoi);
356 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
359 writel(reg, &io_apic->index);
360 return readl(&io_apic->data);
363 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
365 struct io_apic __iomem *io_apic = io_apic_base(apic);
366 writel(reg, &io_apic->index);
367 writel(value, &io_apic->data);
371 * Re-write a value: to be used for read-modify-write
372 * cycles where the read already set up the index register.
374 * Older SiS APIC requires we rewrite the index register
376 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
381 writel(reg, &io_apic->index);
382 writel(value, &io_apic->data);
385 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
387 struct irq_pin_list *entry;
390 raw_spin_lock_irqsave(&ioapic_lock, flags);
391 for_each_irq_pin(entry, cfg->irq_2_pin) {
396 reg = io_apic_read(entry->apic, 0x10 + pin*2);
397 /* Is the remote IRR bit set? */
398 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
399 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
403 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
409 struct { u32 w1, w2; };
410 struct IO_APIC_route_entry entry;
413 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
415 union entry_union eu;
417 raw_spin_lock_irqsave(&ioapic_lock, flags);
418 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
419 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
420 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
425 * When we write a new IO APIC routing entry, we need to write the high
426 * word first! If the mask bit in the low word is clear, we will enable
427 * the interrupt, and we need to make sure the entry is fully populated
428 * before that happens.
431 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
433 union entry_union eu = {{0, 0}};
436 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
437 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
440 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
443 raw_spin_lock_irqsave(&ioapic_lock, flags);
444 __ioapic_write_entry(apic, pin, e);
445 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
449 * When we mask an IO APIC routing entry, we need to write the low
450 * word first, in order to set the mask bit before we change the
453 static void ioapic_mask_entry(int apic, int pin)
456 union entry_union eu = { .entry.mask = 1 };
458 raw_spin_lock_irqsave(&ioapic_lock, flags);
459 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
460 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
461 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
465 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
466 * shared ISA-space IRQs, so we have to support them. We are super
467 * fast in the common case, and fast for shared ISA-space IRQs.
470 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
472 struct irq_pin_list **last, *entry;
474 /* don't allow duplicates */
475 last = &cfg->irq_2_pin;
476 for_each_irq_pin(entry, cfg->irq_2_pin) {
477 if (entry->apic == apic && entry->pin == pin)
482 entry = alloc_irq_pin_list(node);
484 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
495 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
497 if (__add_pin_to_irq_node(cfg, node, apic, pin))
498 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
502 * Reroute an IRQ to a different pin.
504 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
505 int oldapic, int oldpin,
506 int newapic, int newpin)
508 struct irq_pin_list *entry;
510 for_each_irq_pin(entry, cfg->irq_2_pin) {
511 if (entry->apic == oldapic && entry->pin == oldpin) {
512 entry->apic = newapic;
514 /* every one is different, right? */
519 /* old apic/pin didn't exist, so just add new ones */
520 add_pin_to_irq_node(cfg, node, newapic, newpin);
523 static void __io_apic_modify_irq(struct irq_pin_list *entry,
524 int mask_and, int mask_or,
525 void (*final)(struct irq_pin_list *entry))
527 unsigned int reg, pin;
530 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
533 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
538 static void io_apic_modify_irq(struct irq_cfg *cfg,
539 int mask_and, int mask_or,
540 void (*final)(struct irq_pin_list *entry))
542 struct irq_pin_list *entry;
544 for_each_irq_pin(entry, cfg->irq_2_pin)
545 __io_apic_modify_irq(entry, mask_and, mask_or, final);
548 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
550 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
551 IO_APIC_REDIR_MASKED, NULL);
554 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
556 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
557 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
560 static void io_apic_sync(struct irq_pin_list *entry)
563 * Synchronize the IO-APIC and the CPU by doing
564 * a dummy read from the IO-APIC
566 struct io_apic __iomem *io_apic;
567 io_apic = io_apic_base(entry->apic);
568 readl(&io_apic->data);
571 static void mask_ioapic(struct irq_cfg *cfg)
575 raw_spin_lock_irqsave(&ioapic_lock, flags);
576 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
577 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
580 static void mask_ioapic_irq(struct irq_data *data)
582 mask_ioapic(data->chip_data);
585 static void __unmask_ioapic(struct irq_cfg *cfg)
587 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
590 static void unmask_ioapic(struct irq_cfg *cfg)
594 raw_spin_lock_irqsave(&ioapic_lock, flags);
595 __unmask_ioapic(cfg);
596 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
599 static void unmask_ioapic_irq(struct irq_data *data)
601 unmask_ioapic(data->chip_data);
604 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
606 struct IO_APIC_route_entry entry;
608 /* Check delivery_mode to be sure we're not clearing an SMI pin */
609 entry = ioapic_read_entry(apic, pin);
610 if (entry.delivery_mode == dest_SMI)
613 * Disable it in the IO-APIC irq-routing table:
615 ioapic_mask_entry(apic, pin);
618 static void clear_IO_APIC (void)
622 for (apic = 0; apic < nr_ioapics; apic++)
623 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
624 clear_IO_APIC_pin(apic, pin);
629 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
630 * specific CPU-side IRQs.
634 static int pirq_entries[MAX_PIRQS] = {
635 [0 ... MAX_PIRQS - 1] = -1
638 static int __init ioapic_pirq_setup(char *str)
641 int ints[MAX_PIRQS+1];
643 get_options(str, ARRAY_SIZE(ints), ints);
645 apic_printk(APIC_VERBOSE, KERN_INFO
646 "PIRQ redirection, working around broken MP-BIOS.\n");
648 if (ints[0] < MAX_PIRQS)
651 for (i = 0; i < max; i++) {
652 apic_printk(APIC_VERBOSE, KERN_DEBUG
653 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
655 * PIRQs are mapped upside down, usually.
657 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
662 __setup("pirq=", ioapic_pirq_setup);
663 #endif /* CONFIG_X86_32 */
665 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
668 struct IO_APIC_route_entry **ioapic_entries;
670 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
675 for (apic = 0; apic < nr_ioapics; apic++) {
676 ioapic_entries[apic] =
677 kzalloc(sizeof(struct IO_APIC_route_entry) *
678 nr_ioapic_registers[apic], GFP_ATOMIC);
679 if (!ioapic_entries[apic])
683 return ioapic_entries;
687 kfree(ioapic_entries[apic]);
688 kfree(ioapic_entries);
694 * Saves all the IO-APIC RTE's
696 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
703 for (apic = 0; apic < nr_ioapics; apic++) {
704 if (!ioapic_entries[apic])
707 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
708 ioapic_entries[apic][pin] =
709 ioapic_read_entry(apic, pin);
716 * Mask all IO APIC entries.
718 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
725 for (apic = 0; apic < nr_ioapics; apic++) {
726 if (!ioapic_entries[apic])
729 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
730 struct IO_APIC_route_entry entry;
732 entry = ioapic_entries[apic][pin];
735 ioapic_write_entry(apic, pin, entry);
742 * Restore IO APIC entries which was saved in ioapic_entries.
744 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
751 for (apic = 0; apic < nr_ioapics; apic++) {
752 if (!ioapic_entries[apic])
755 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
756 ioapic_write_entry(apic, pin,
757 ioapic_entries[apic][pin]);
762 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
766 for (apic = 0; apic < nr_ioapics; apic++)
767 kfree(ioapic_entries[apic]);
769 kfree(ioapic_entries);
773 * Find the IRQ entry number of a certain pin.
775 static int find_irq_entry(int apic, int pin, int type)
779 for (i = 0; i < mp_irq_entries; i++)
780 if (mp_irqs[i].irqtype == type &&
781 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
782 mp_irqs[i].dstapic == MP_APIC_ALL) &&
783 mp_irqs[i].dstirq == pin)
790 * Find the pin to which IRQ[irq] (ISA) is connected
792 static int __init find_isa_irq_pin(int irq, int type)
796 for (i = 0; i < mp_irq_entries; i++) {
797 int lbus = mp_irqs[i].srcbus;
799 if (test_bit(lbus, mp_bus_not_pci) &&
800 (mp_irqs[i].irqtype == type) &&
801 (mp_irqs[i].srcbusirq == irq))
803 return mp_irqs[i].dstirq;
808 static int __init find_isa_irq_apic(int irq, int type)
812 for (i = 0; i < mp_irq_entries; i++) {
813 int lbus = mp_irqs[i].srcbus;
815 if (test_bit(lbus, mp_bus_not_pci) &&
816 (mp_irqs[i].irqtype == type) &&
817 (mp_irqs[i].srcbusirq == irq))
820 if (i < mp_irq_entries) {
822 for(apic = 0; apic < nr_ioapics; apic++) {
823 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
831 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
833 * EISA Edge/Level control register, ELCR
835 static int EISA_ELCR(unsigned int irq)
837 if (irq < legacy_pic->nr_legacy_irqs) {
838 unsigned int port = 0x4d0 + (irq >> 3);
839 return (inb(port) >> (irq & 7)) & 1;
841 apic_printk(APIC_VERBOSE, KERN_INFO
842 "Broken MPtable reports ISA irq %d\n", irq);
848 /* ISA interrupts are always polarity zero edge triggered,
849 * when listed as conforming in the MP table. */
851 #define default_ISA_trigger(idx) (0)
852 #define default_ISA_polarity(idx) (0)
854 /* EISA interrupts are always polarity zero and can be edge or level
855 * trigger depending on the ELCR value. If an interrupt is listed as
856 * EISA conforming in the MP table, that means its trigger type must
857 * be read in from the ELCR */
859 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
860 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
862 /* PCI interrupts are always polarity one level triggered,
863 * when listed as conforming in the MP table. */
865 #define default_PCI_trigger(idx) (1)
866 #define default_PCI_polarity(idx) (1)
868 /* MCA interrupts are always polarity zero level triggered,
869 * when listed as conforming in the MP table. */
871 #define default_MCA_trigger(idx) (1)
872 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
874 static int MPBIOS_polarity(int idx)
876 int bus = mp_irqs[idx].srcbus;
880 * Determine IRQ line polarity (high active or low active):
882 switch (mp_irqs[idx].irqflag & 3)
884 case 0: /* conforms, ie. bus-type dependent polarity */
885 if (test_bit(bus, mp_bus_not_pci))
886 polarity = default_ISA_polarity(idx);
888 polarity = default_PCI_polarity(idx);
890 case 1: /* high active */
895 case 2: /* reserved */
897 printk(KERN_WARNING "broken BIOS!!\n");
901 case 3: /* low active */
906 default: /* invalid */
908 printk(KERN_WARNING "broken BIOS!!\n");
916 static int MPBIOS_trigger(int idx)
918 int bus = mp_irqs[idx].srcbus;
922 * Determine IRQ trigger mode (edge or level sensitive):
924 switch ((mp_irqs[idx].irqflag>>2) & 3)
926 case 0: /* conforms, ie. bus-type dependent */
927 if (test_bit(bus, mp_bus_not_pci))
928 trigger = default_ISA_trigger(idx);
930 trigger = default_PCI_trigger(idx);
931 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
932 switch (mp_bus_id_to_type[bus]) {
933 case MP_BUS_ISA: /* ISA pin */
935 /* set before the switch */
938 case MP_BUS_EISA: /* EISA pin */
940 trigger = default_EISA_trigger(idx);
943 case MP_BUS_PCI: /* PCI pin */
945 /* set before the switch */
948 case MP_BUS_MCA: /* MCA pin */
950 trigger = default_MCA_trigger(idx);
955 printk(KERN_WARNING "broken BIOS!!\n");
967 case 2: /* reserved */
969 printk(KERN_WARNING "broken BIOS!!\n");
978 default: /* invalid */
980 printk(KERN_WARNING "broken BIOS!!\n");
988 static inline int irq_polarity(int idx)
990 return MPBIOS_polarity(idx);
993 static inline int irq_trigger(int idx)
995 return MPBIOS_trigger(idx);
998 static int pin_2_irq(int idx, int apic, int pin)
1001 int bus = mp_irqs[idx].srcbus;
1004 * Debugging check, we are in big trouble if this message pops up!
1006 if (mp_irqs[idx].dstirq != pin)
1007 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1009 if (test_bit(bus, mp_bus_not_pci)) {
1010 irq = mp_irqs[idx].srcbusirq;
1012 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
1014 if (gsi >= NR_IRQS_LEGACY)
1017 irq = gsi_top + gsi;
1020 #ifdef CONFIG_X86_32
1022 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1024 if ((pin >= 16) && (pin <= 23)) {
1025 if (pirq_entries[pin-16] != -1) {
1026 if (!pirq_entries[pin-16]) {
1027 apic_printk(APIC_VERBOSE, KERN_DEBUG
1028 "disabling PIRQ%d\n", pin-16);
1030 irq = pirq_entries[pin-16];
1031 apic_printk(APIC_VERBOSE, KERN_DEBUG
1032 "using PIRQ%d -> IRQ %d\n",
1043 * Find a specific PCI IRQ entry.
1044 * Not an __init, possibly needed by modules
1046 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1047 struct io_apic_irq_attr *irq_attr)
1049 int apic, i, best_guess = -1;
1051 apic_printk(APIC_DEBUG,
1052 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1054 if (test_bit(bus, mp_bus_not_pci)) {
1055 apic_printk(APIC_VERBOSE,
1056 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1059 for (i = 0; i < mp_irq_entries; i++) {
1060 int lbus = mp_irqs[i].srcbus;
1062 for (apic = 0; apic < nr_ioapics; apic++)
1063 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1064 mp_irqs[i].dstapic == MP_APIC_ALL)
1067 if (!test_bit(lbus, mp_bus_not_pci) &&
1068 !mp_irqs[i].irqtype &&
1070 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1071 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1073 if (!(apic || IO_APIC_IRQ(irq)))
1076 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1077 set_io_apic_irq_attr(irq_attr, apic,
1084 * Use the first all-but-pin matching entry as a
1085 * best-guess fuzzy result for broken mptables.
1087 if (best_guess < 0) {
1088 set_io_apic_irq_attr(irq_attr, apic,
1098 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1100 void lock_vector_lock(void)
1102 /* Used to the online set of cpus does not change
1103 * during assign_irq_vector.
1105 raw_spin_lock(&vector_lock);
1108 void unlock_vector_lock(void)
1110 raw_spin_unlock(&vector_lock);
1114 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1117 * NOTE! The local APIC isn't very good at handling
1118 * multiple interrupts at the same interrupt level.
1119 * As the interrupt level is determined by taking the
1120 * vector number and shifting that right by 4, we
1121 * want to spread these out a bit so that they don't
1122 * all fall in the same interrupt level.
1124 * Also, we've got to be careful not to trash gate
1125 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1127 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1128 static int current_offset = VECTOR_OFFSET_START % 8;
1129 unsigned int old_vector;
1131 cpumask_var_t tmp_mask;
1133 if (cfg->move_in_progress)
1136 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1139 old_vector = cfg->vector;
1141 cpumask_and(tmp_mask, mask, cpu_online_mask);
1142 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1143 if (!cpumask_empty(tmp_mask)) {
1144 free_cpumask_var(tmp_mask);
1149 /* Only try and allocate irqs on cpus that are present */
1151 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1155 apic->vector_allocation_domain(cpu, tmp_mask);
1157 vector = current_vector;
1158 offset = current_offset;
1161 if (vector >= first_system_vector) {
1162 /* If out of vectors on large boxen, must share them. */
1163 offset = (offset + 1) % 8;
1164 vector = FIRST_EXTERNAL_VECTOR + offset;
1166 if (unlikely(current_vector == vector))
1169 if (test_bit(vector, used_vectors))
1172 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1173 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1176 current_vector = vector;
1177 current_offset = offset;
1179 cfg->move_in_progress = 1;
1180 cpumask_copy(cfg->old_domain, cfg->domain);
1182 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1183 per_cpu(vector_irq, new_cpu)[vector] = irq;
1184 cfg->vector = vector;
1185 cpumask_copy(cfg->domain, tmp_mask);
1189 free_cpumask_var(tmp_mask);
1193 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1196 unsigned long flags;
1198 raw_spin_lock_irqsave(&vector_lock, flags);
1199 err = __assign_irq_vector(irq, cfg, mask);
1200 raw_spin_unlock_irqrestore(&vector_lock, flags);
1204 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1208 BUG_ON(!cfg->vector);
1210 vector = cfg->vector;
1211 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1212 per_cpu(vector_irq, cpu)[vector] = -1;
1215 cpumask_clear(cfg->domain);
1217 if (likely(!cfg->move_in_progress))
1219 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1220 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1222 if (per_cpu(vector_irq, cpu)[vector] != irq)
1224 per_cpu(vector_irq, cpu)[vector] = -1;
1228 cfg->move_in_progress = 0;
1231 void __setup_vector_irq(int cpu)
1233 /* Initialize vector_irq on a new cpu */
1235 struct irq_cfg *cfg;
1236 struct irq_desc *desc;
1239 * vector_lock will make sure that we don't run into irq vector
1240 * assignments that might be happening on another cpu in parallel,
1241 * while we setup our initial vector to irq mappings.
1243 raw_spin_lock(&vector_lock);
1244 /* Mark the inuse vectors */
1245 for_each_irq_desc(irq, desc) {
1246 cfg = get_irq_desc_chip_data(desc);
1249 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1250 * will be part of the irq_cfg's domain.
1252 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1253 cpumask_set_cpu(cpu, cfg->domain);
1255 if (!cpumask_test_cpu(cpu, cfg->domain))
1257 vector = cfg->vector;
1258 per_cpu(vector_irq, cpu)[vector] = irq;
1260 /* Mark the free vectors */
1261 for (vector = 0; vector < NR_VECTORS; ++vector) {
1262 irq = per_cpu(vector_irq, cpu)[vector];
1267 if (!cpumask_test_cpu(cpu, cfg->domain))
1268 per_cpu(vector_irq, cpu)[vector] = -1;
1270 raw_spin_unlock(&vector_lock);
1273 static struct irq_chip ioapic_chip;
1274 static struct irq_chip ir_ioapic_chip;
1276 #define IOAPIC_AUTO -1
1277 #define IOAPIC_EDGE 0
1278 #define IOAPIC_LEVEL 1
1280 #ifdef CONFIG_X86_32
1281 static inline int IO_APIC_irq_trigger(int irq)
1285 for (apic = 0; apic < nr_ioapics; apic++) {
1286 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1287 idx = find_irq_entry(apic, pin, mp_INT);
1288 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1289 return irq_trigger(idx);
1293 * nonexistent IRQs are edge default
1298 static inline int IO_APIC_irq_trigger(int irq)
1304 static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1307 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1308 trigger == IOAPIC_LEVEL)
1309 irq_set_status_flags(irq, IRQ_LEVEL);
1311 irq_clear_status_flags(irq, IRQ_LEVEL);
1313 if (irq_remapped(irq)) {
1314 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1316 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1320 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1321 handle_edge_irq, "edge");
1325 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1326 trigger == IOAPIC_LEVEL)
1327 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1331 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1332 handle_edge_irq, "edge");
1335 int setup_ioapic_entry(int apic_id, int irq,
1336 struct IO_APIC_route_entry *entry,
1337 unsigned int destination, int trigger,
1338 int polarity, int vector, int pin)
1341 * add it to the IO-APIC irq-routing table:
1343 memset(entry,0,sizeof(*entry));
1345 if (intr_remapping_enabled) {
1346 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1348 struct IR_IO_APIC_route_entry *ir_entry =
1349 (struct IR_IO_APIC_route_entry *) entry;
1353 panic("No mapping iommu for ioapic %d\n", apic_id);
1355 index = alloc_irte(iommu, irq, 1);
1357 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1359 prepare_irte(&irte, vector, destination);
1361 /* Set source-id of interrupt request */
1362 set_ioapic_sid(&irte, apic_id);
1364 modify_irte(irq, &irte);
1366 ir_entry->index2 = (index >> 15) & 0x1;
1368 ir_entry->format = 1;
1369 ir_entry->index = (index & 0x7fff);
1371 * IO-APIC RTE will be configured with virtual vector.
1372 * irq handler will do the explicit EOI to the io-apic.
1374 ir_entry->vector = pin;
1376 entry->delivery_mode = apic->irq_delivery_mode;
1377 entry->dest_mode = apic->irq_dest_mode;
1378 entry->dest = destination;
1379 entry->vector = vector;
1382 entry->mask = 0; /* enable IRQ */
1383 entry->trigger = trigger;
1384 entry->polarity = polarity;
1386 /* Mask level triggered irqs.
1387 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1394 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1395 struct irq_cfg *cfg, int trigger, int polarity)
1397 struct IO_APIC_route_entry entry;
1400 if (!IO_APIC_IRQ(irq))
1403 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1404 * controllers like 8259. Now that IO-APIC can handle this irq, update
1407 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1408 apic->vector_allocation_domain(0, cfg->domain);
1410 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1413 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1415 apic_printk(APIC_VERBOSE,KERN_DEBUG
1416 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1417 "IRQ %d Mode:%i Active:%i)\n",
1418 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1419 irq, trigger, polarity);
1422 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1423 dest, trigger, polarity, cfg->vector, pin)) {
1424 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1425 mp_ioapics[apic_id].apicid, pin);
1426 __clear_irq_vector(irq, cfg);
1430 ioapic_register_intr(irq, trigger);
1431 if (irq < legacy_pic->nr_legacy_irqs)
1432 legacy_pic->mask(irq);
1434 ioapic_write_entry(apic_id, pin, entry);
1438 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1439 } mp_ioapic_routing[MAX_IO_APICS];
1441 static void __init setup_IO_APIC_irqs(void)
1443 int apic_id, pin, idx, irq;
1445 struct irq_desc *desc;
1446 struct irq_cfg *cfg;
1447 int node = cpu_to_node(0);
1449 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1451 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1452 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1453 idx = find_irq_entry(apic_id, pin, mp_INT);
1457 apic_printk(APIC_VERBOSE,
1458 KERN_DEBUG " %d-%d",
1459 mp_ioapics[apic_id].apicid, pin);
1461 apic_printk(APIC_VERBOSE, " %d-%d",
1462 mp_ioapics[apic_id].apicid, pin);
1466 apic_printk(APIC_VERBOSE,
1467 " (apicid-pin) not connected\n");
1471 irq = pin_2_irq(idx, apic_id, pin);
1473 if ((apic_id > 0) && (irq > 16))
1477 * Skip the timer IRQ if there's a quirk handler
1478 * installed and if it returns 1:
1480 if (apic->multi_timer_check &&
1481 apic->multi_timer_check(apic_id, irq))
1484 desc = irq_to_desc_alloc_node(irq, node);
1486 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1489 cfg = get_irq_desc_chip_data(desc);
1490 add_pin_to_irq_node(cfg, node, apic_id, pin);
1492 * don't mark it in pin_programmed, so later acpi could
1493 * set it correctly when irq < 16
1495 setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
1500 apic_printk(APIC_VERBOSE,
1501 " (apicid-pin) not connected\n");
1505 * for the gsit that is not in first ioapic
1506 * but could not use acpi_register_gsi()
1507 * like some special sci in IBM x3330
1509 void setup_IO_APIC_irq_extra(u32 gsi)
1511 int apic_id = 0, pin, idx, irq;
1512 int node = cpu_to_node(0);
1513 struct irq_desc *desc;
1514 struct irq_cfg *cfg;
1517 * Convert 'gsi' to 'ioapic.pin'.
1519 apic_id = mp_find_ioapic(gsi);
1523 pin = mp_find_ioapic_pin(apic_id, gsi);
1524 idx = find_irq_entry(apic_id, pin, mp_INT);
1528 irq = pin_2_irq(idx, apic_id, pin);
1529 #ifdef CONFIG_SPARSE_IRQ
1530 desc = irq_to_desc(irq);
1534 desc = irq_to_desc_alloc_node(irq, node);
1536 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1540 cfg = get_irq_desc_chip_data(desc);
1541 add_pin_to_irq_node(cfg, node, apic_id, pin);
1543 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1544 pr_debug("Pin %d-%d already programmed\n",
1545 mp_ioapics[apic_id].apicid, pin);
1548 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1550 setup_ioapic_irq(apic_id, pin, irq, cfg,
1551 irq_trigger(idx), irq_polarity(idx));
1555 * Set up the timer pin, possibly with the 8259A-master behind.
1557 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1560 struct IO_APIC_route_entry entry;
1562 if (intr_remapping_enabled)
1565 memset(&entry, 0, sizeof(entry));
1568 * We use logical delivery to get the timer IRQ
1571 entry.dest_mode = apic->irq_dest_mode;
1572 entry.mask = 0; /* don't mask IRQ for edge */
1573 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1574 entry.delivery_mode = apic->irq_delivery_mode;
1577 entry.vector = vector;
1580 * The timer IRQ doesn't have to know that behind the
1581 * scene we may have a 8259A-master in AEOI mode ...
1583 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1586 * Add it to the IO-APIC irq-routing table:
1588 ioapic_write_entry(apic_id, pin, entry);
1592 __apicdebuginit(void) print_IO_APIC(void)
1595 union IO_APIC_reg_00 reg_00;
1596 union IO_APIC_reg_01 reg_01;
1597 union IO_APIC_reg_02 reg_02;
1598 union IO_APIC_reg_03 reg_03;
1599 unsigned long flags;
1600 struct irq_cfg *cfg;
1601 struct irq_desc *desc;
1604 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1605 for (i = 0; i < nr_ioapics; i++)
1606 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1607 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1610 * We are a bit conservative about what we expect. We have to
1611 * know about every hardware change ASAP.
1613 printk(KERN_INFO "testing the IO APIC.......................\n");
1615 for (apic = 0; apic < nr_ioapics; apic++) {
1617 raw_spin_lock_irqsave(&ioapic_lock, flags);
1618 reg_00.raw = io_apic_read(apic, 0);
1619 reg_01.raw = io_apic_read(apic, 1);
1620 if (reg_01.bits.version >= 0x10)
1621 reg_02.raw = io_apic_read(apic, 2);
1622 if (reg_01.bits.version >= 0x20)
1623 reg_03.raw = io_apic_read(apic, 3);
1624 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1627 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1628 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1629 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1630 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1631 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1633 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1634 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1636 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1637 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1640 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1641 * but the value of reg_02 is read as the previous read register
1642 * value, so ignore it if reg_02 == reg_01.
1644 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1645 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1646 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1650 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1651 * or reg_03, but the value of reg_0[23] is read as the previous read
1652 * register value, so ignore it if reg_03 == reg_0[12].
1654 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1655 reg_03.raw != reg_01.raw) {
1656 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1657 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1660 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1662 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1663 " Stat Dmod Deli Vect:\n");
1665 for (i = 0; i <= reg_01.bits.entries; i++) {
1666 struct IO_APIC_route_entry entry;
1668 entry = ioapic_read_entry(apic, i);
1670 printk(KERN_DEBUG " %02x %03X ",
1675 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1680 entry.delivery_status,
1682 entry.delivery_mode,
1687 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1688 for_each_irq_desc(irq, desc) {
1689 struct irq_pin_list *entry;
1691 cfg = get_irq_desc_chip_data(desc);
1694 entry = cfg->irq_2_pin;
1697 printk(KERN_DEBUG "IRQ%d ", irq);
1698 for_each_irq_pin(entry, cfg->irq_2_pin)
1699 printk("-> %d:%d", entry->apic, entry->pin);
1703 printk(KERN_INFO ".................................... done.\n");
1708 __apicdebuginit(void) print_APIC_field(int base)
1714 for (i = 0; i < 8; i++)
1715 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1717 printk(KERN_CONT "\n");
1720 __apicdebuginit(void) print_local_APIC(void *dummy)
1722 unsigned int i, v, ver, maxlvt;
1725 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1726 smp_processor_id(), hard_smp_processor_id());
1727 v = apic_read(APIC_ID);
1728 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1729 v = apic_read(APIC_LVR);
1730 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1731 ver = GET_APIC_VERSION(v);
1732 maxlvt = lapic_get_maxlvt();
1734 v = apic_read(APIC_TASKPRI);
1735 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1737 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1738 if (!APIC_XAPIC(ver)) {
1739 v = apic_read(APIC_ARBPRI);
1740 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1741 v & APIC_ARBPRI_MASK);
1743 v = apic_read(APIC_PROCPRI);
1744 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1748 * Remote read supported only in the 82489DX and local APIC for
1749 * Pentium processors.
1751 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1752 v = apic_read(APIC_RRR);
1753 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1756 v = apic_read(APIC_LDR);
1757 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1758 if (!x2apic_enabled()) {
1759 v = apic_read(APIC_DFR);
1760 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1762 v = apic_read(APIC_SPIV);
1763 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1765 printk(KERN_DEBUG "... APIC ISR field:\n");
1766 print_APIC_field(APIC_ISR);
1767 printk(KERN_DEBUG "... APIC TMR field:\n");
1768 print_APIC_field(APIC_TMR);
1769 printk(KERN_DEBUG "... APIC IRR field:\n");
1770 print_APIC_field(APIC_IRR);
1772 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1773 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1774 apic_write(APIC_ESR, 0);
1776 v = apic_read(APIC_ESR);
1777 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1780 icr = apic_icr_read();
1781 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1782 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1784 v = apic_read(APIC_LVTT);
1785 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1787 if (maxlvt > 3) { /* PC is LVT#4. */
1788 v = apic_read(APIC_LVTPC);
1789 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1791 v = apic_read(APIC_LVT0);
1792 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1793 v = apic_read(APIC_LVT1);
1794 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1796 if (maxlvt > 2) { /* ERR is LVT#3. */
1797 v = apic_read(APIC_LVTERR);
1798 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1801 v = apic_read(APIC_TMICT);
1802 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1803 v = apic_read(APIC_TMCCT);
1804 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1805 v = apic_read(APIC_TDCR);
1806 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1808 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1809 v = apic_read(APIC_EFEAT);
1810 maxlvt = (v >> 16) & 0xff;
1811 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1812 v = apic_read(APIC_ECTRL);
1813 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1814 for (i = 0; i < maxlvt; i++) {
1815 v = apic_read(APIC_EILVTn(i));
1816 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1822 __apicdebuginit(void) print_local_APICs(int maxcpu)
1830 for_each_online_cpu(cpu) {
1833 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1838 __apicdebuginit(void) print_PIC(void)
1841 unsigned long flags;
1843 if (!legacy_pic->nr_legacy_irqs)
1846 printk(KERN_DEBUG "\nprinting PIC contents\n");
1848 raw_spin_lock_irqsave(&i8259A_lock, flags);
1850 v = inb(0xa1) << 8 | inb(0x21);
1851 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1853 v = inb(0xa0) << 8 | inb(0x20);
1854 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1858 v = inb(0xa0) << 8 | inb(0x20);
1862 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1864 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1866 v = inb(0x4d1) << 8 | inb(0x4d0);
1867 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1870 static int __initdata show_lapic = 1;
1871 static __init int setup_show_lapic(char *arg)
1875 if (strcmp(arg, "all") == 0) {
1876 show_lapic = CONFIG_NR_CPUS;
1878 get_option(&arg, &num);
1885 __setup("show_lapic=", setup_show_lapic);
1887 __apicdebuginit(int) print_ICs(void)
1889 if (apic_verbosity == APIC_QUIET)
1894 /* don't print out if apic is not there */
1895 if (!cpu_has_apic && !apic_from_smp_config())
1898 print_local_APICs(show_lapic);
1904 fs_initcall(print_ICs);
1907 /* Where if anywhere is the i8259 connect in external int mode */
1908 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1910 void __init enable_IO_APIC(void)
1912 int i8259_apic, i8259_pin;
1915 if (!legacy_pic->nr_legacy_irqs)
1918 for(apic = 0; apic < nr_ioapics; apic++) {
1920 /* See if any of the pins is in ExtINT mode */
1921 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1922 struct IO_APIC_route_entry entry;
1923 entry = ioapic_read_entry(apic, pin);
1925 /* If the interrupt line is enabled and in ExtInt mode
1926 * I have found the pin where the i8259 is connected.
1928 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1929 ioapic_i8259.apic = apic;
1930 ioapic_i8259.pin = pin;
1936 /* Look to see what if the MP table has reported the ExtINT */
1937 /* If we could not find the appropriate pin by looking at the ioapic
1938 * the i8259 probably is not connected the ioapic but give the
1939 * mptable a chance anyway.
1941 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1942 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1943 /* Trust the MP table if nothing is setup in the hardware */
1944 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1945 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1946 ioapic_i8259.pin = i8259_pin;
1947 ioapic_i8259.apic = i8259_apic;
1949 /* Complain if the MP table and the hardware disagree */
1950 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1951 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1953 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1957 * Do not trust the IO-APIC being empty at bootup
1963 * Not an __init, needed by the reboot code
1965 void disable_IO_APIC(void)
1968 * Clear the IO-APIC before rebooting:
1972 if (!legacy_pic->nr_legacy_irqs)
1976 * If the i8259 is routed through an IOAPIC
1977 * Put that IOAPIC in virtual wire mode
1978 * so legacy interrupts can be delivered.
1980 * With interrupt-remapping, for now we will use virtual wire A mode,
1981 * as virtual wire B is little complex (need to configure both
1982 * IOAPIC RTE aswell as interrupt-remapping table entry).
1983 * As this gets called during crash dump, keep this simple for now.
1985 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1986 struct IO_APIC_route_entry entry;
1988 memset(&entry, 0, sizeof(entry));
1989 entry.mask = 0; /* Enabled */
1990 entry.trigger = 0; /* Edge */
1992 entry.polarity = 0; /* High */
1993 entry.delivery_status = 0;
1994 entry.dest_mode = 0; /* Physical */
1995 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1997 entry.dest = read_apic_id();
2000 * Add it to the IO-APIC irq-routing table:
2002 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2006 * Use virtual wire A mode when interrupt remapping is enabled.
2008 if (cpu_has_apic || apic_from_smp_config())
2009 disconnect_bsp_APIC(!intr_remapping_enabled &&
2010 ioapic_i8259.pin != -1);
2013 #ifdef CONFIG_X86_32
2015 * function to set the IO-APIC physical IDs based on the
2016 * values stored in the MPC table.
2018 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2021 void __init setup_ioapic_ids_from_mpc(void)
2023 union IO_APIC_reg_00 reg_00;
2024 physid_mask_t phys_id_present_map;
2027 unsigned char old_id;
2028 unsigned long flags;
2033 * Don't check I/O APIC IDs for xAPIC systems. They have
2034 * no meaning without the serial APIC bus.
2036 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2037 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2040 * This is broken; anything with a real cpu count has to
2041 * circumvent this idiocy regardless.
2043 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2046 * Set the IOAPIC ID to the value stored in the MPC table.
2048 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2050 /* Read the register 0 value */
2051 raw_spin_lock_irqsave(&ioapic_lock, flags);
2052 reg_00.raw = io_apic_read(apic_id, 0);
2053 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2055 old_id = mp_ioapics[apic_id].apicid;
2057 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2058 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2059 apic_id, mp_ioapics[apic_id].apicid);
2060 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2062 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2066 * Sanity check, is the ID really free? Every APIC in a
2067 * system must have a unique ID or we get lots of nice
2068 * 'stuck on smp_invalidate_needed IPI wait' messages.
2070 if (apic->check_apicid_used(&phys_id_present_map,
2071 mp_ioapics[apic_id].apicid)) {
2072 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2073 apic_id, mp_ioapics[apic_id].apicid);
2074 for (i = 0; i < get_physical_broadcast(); i++)
2075 if (!physid_isset(i, phys_id_present_map))
2077 if (i >= get_physical_broadcast())
2078 panic("Max APIC ID exceeded!\n");
2079 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2081 physid_set(i, phys_id_present_map);
2082 mp_ioapics[apic_id].apicid = i;
2085 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2086 apic_printk(APIC_VERBOSE, "Setting %d in the "
2087 "phys_id_present_map\n",
2088 mp_ioapics[apic_id].apicid);
2089 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2094 * We need to adjust the IRQ routing table
2095 * if the ID changed.
2097 if (old_id != mp_ioapics[apic_id].apicid)
2098 for (i = 0; i < mp_irq_entries; i++)
2099 if (mp_irqs[i].dstapic == old_id)
2101 = mp_ioapics[apic_id].apicid;
2104 * Read the right value from the MPC table and
2105 * write it into the ID register.
2107 apic_printk(APIC_VERBOSE, KERN_INFO
2108 "...changing IO-APIC physical APIC ID to %d ...",
2109 mp_ioapics[apic_id].apicid);
2111 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2112 raw_spin_lock_irqsave(&ioapic_lock, flags);
2113 io_apic_write(apic_id, 0, reg_00.raw);
2114 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2119 raw_spin_lock_irqsave(&ioapic_lock, flags);
2120 reg_00.raw = io_apic_read(apic_id, 0);
2121 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2122 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2123 printk("could not set ID!\n");
2125 apic_printk(APIC_VERBOSE, " ok.\n");
2130 int no_timer_check __initdata;
2132 static int __init notimercheck(char *s)
2137 __setup("no_timer_check", notimercheck);
2140 * There is a nasty bug in some older SMP boards, their mptable lies
2141 * about the timer IRQ. We do the following to work around the situation:
2143 * - timer IRQ defaults to IO-APIC IRQ
2144 * - if this function detects that timer IRQs are defunct, then we fall
2145 * back to ISA timer IRQs
2147 static int __init timer_irq_works(void)
2149 unsigned long t1 = jiffies;
2150 unsigned long flags;
2155 local_save_flags(flags);
2157 /* Let ten ticks pass... */
2158 mdelay((10 * 1000) / HZ);
2159 local_irq_restore(flags);
2162 * Expect a few ticks at least, to be sure some possible
2163 * glue logic does not lock up after one or two first
2164 * ticks in a non-ExtINT mode. Also the local APIC
2165 * might have cached one ExtINT interrupt. Finally, at
2166 * least one tick may be lost due to delays.
2170 if (time_after(jiffies, t1 + 4))
2176 * In the SMP+IOAPIC case it might happen that there are an unspecified
2177 * number of pending IRQ events unhandled. These cases are very rare,
2178 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2179 * better to do it this way as thus we do not have to be aware of
2180 * 'pending' interrupts in the IRQ path, except at this point.
2183 * Edge triggered needs to resend any interrupt
2184 * that was delayed but this is now handled in the device
2189 * Starting up a edge-triggered IO-APIC interrupt is
2190 * nasty - we need to make sure that we get the edge.
2191 * If it is already asserted for some reason, we need
2192 * return 1 to indicate that is was pending.
2194 * This is not complete - we should be able to fake
2195 * an edge even if it isn't on the 8259A...
2198 static unsigned int startup_ioapic_irq(struct irq_data *data)
2200 int was_pending = 0, irq = data->irq;
2201 unsigned long flags;
2203 raw_spin_lock_irqsave(&ioapic_lock, flags);
2204 if (irq < legacy_pic->nr_legacy_irqs) {
2205 legacy_pic->mask(irq);
2206 if (legacy_pic->irq_pending(irq))
2209 __unmask_ioapic(data->chip_data);
2210 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2215 static int ioapic_retrigger_irq(struct irq_data *data)
2217 struct irq_cfg *cfg = data->chip_data;
2218 unsigned long flags;
2220 raw_spin_lock_irqsave(&vector_lock, flags);
2221 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2222 raw_spin_unlock_irqrestore(&vector_lock, flags);
2228 * Level and edge triggered IO-APIC interrupts need different handling,
2229 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2230 * handled with the level-triggered descriptor, but that one has slightly
2231 * more overhead. Level-triggered interrupts cannot be handled with the
2232 * edge-triggered handler, without risking IRQ storms and other ugly
2237 void send_cleanup_vector(struct irq_cfg *cfg)
2239 cpumask_var_t cleanup_mask;
2241 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2243 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2244 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2246 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2247 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2248 free_cpumask_var(cleanup_mask);
2250 cfg->move_in_progress = 0;
2253 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2256 struct irq_pin_list *entry;
2257 u8 vector = cfg->vector;
2259 for_each_irq_pin(entry, cfg->irq_2_pin) {
2265 * With interrupt-remapping, destination information comes
2266 * from interrupt-remapping table entry.
2268 if (!irq_remapped(irq))
2269 io_apic_write(apic, 0x11 + pin*2, dest);
2270 reg = io_apic_read(apic, 0x10 + pin*2);
2271 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2273 io_apic_modify(apic, 0x10 + pin*2, reg);
2278 * Either sets data->affinity to a valid value, and returns
2279 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2280 * leaves data->affinity untouched.
2282 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2283 unsigned int *dest_id)
2285 struct irq_cfg *cfg = data->chip_data;
2287 if (!cpumask_intersects(mask, cpu_online_mask))
2290 if (assign_irq_vector(data->irq, data->chip_data, mask))
2293 cpumask_copy(data->affinity, mask);
2295 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2300 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2303 unsigned int dest, irq = data->irq;
2304 unsigned long flags;
2307 raw_spin_lock_irqsave(&ioapic_lock, flags);
2308 ret = __ioapic_set_affinity(data, mask, &dest);
2310 /* Only the high 8 bits are valid. */
2311 dest = SET_APIC_LOGICAL_ID(dest);
2312 __target_IO_APIC_irq(irq, dest, data->chip_data);
2314 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2318 #ifdef CONFIG_INTR_REMAP
2321 * Migrate the IO-APIC irq in the presence of intr-remapping.
2323 * For both level and edge triggered, irq migration is a simple atomic
2324 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2326 * For level triggered, we eliminate the io-apic RTE modification (with the
2327 * updated vector information), by using a virtual vector (io-apic pin number).
2328 * Real vector that is used for interrupting cpu will be coming from
2329 * the interrupt-remapping table entry.
2332 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2335 struct irq_cfg *cfg = data->chip_data;
2336 unsigned int dest, irq = data->irq;
2339 if (!cpumask_intersects(mask, cpu_online_mask))
2342 if (get_irte(irq, &irte))
2345 if (assign_irq_vector(irq, cfg, mask))
2348 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2350 irte.vector = cfg->vector;
2351 irte.dest_id = IRTE_DEST(dest);
2354 * Modified the IRTE and flushes the Interrupt entry cache.
2356 modify_irte(irq, &irte);
2358 if (cfg->move_in_progress)
2359 send_cleanup_vector(cfg);
2361 cpumask_copy(data->affinity, mask);
2367 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2374 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2376 unsigned vector, me;
2382 me = smp_processor_id();
2383 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2386 struct irq_desc *desc;
2387 struct irq_cfg *cfg;
2388 irq = __get_cpu_var(vector_irq)[vector];
2393 desc = irq_to_desc(irq);
2398 raw_spin_lock(&desc->lock);
2401 * Check if the irq migration is in progress. If so, we
2402 * haven't received the cleanup request yet for this irq.
2404 if (cfg->move_in_progress)
2407 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2410 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2412 * Check if the vector that needs to be cleanedup is
2413 * registered at the cpu's IRR. If so, then this is not
2414 * the best time to clean it up. Lets clean it up in the
2415 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2418 if (irr & (1 << (vector % 32))) {
2419 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2422 __get_cpu_var(vector_irq)[vector] = -1;
2424 raw_spin_unlock(&desc->lock);
2430 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2434 if (likely(!cfg->move_in_progress))
2437 me = smp_processor_id();
2439 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2440 send_cleanup_vector(cfg);
2443 static void irq_complete_move(struct irq_cfg *cfg)
2445 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2448 void irq_force_complete_move(int irq)
2450 struct irq_cfg *cfg = get_irq_chip_data(irq);
2455 __irq_complete_move(cfg, cfg->vector);
2458 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2461 static void ack_apic_edge(struct irq_data *data)
2463 irq_complete_move(data->chip_data);
2464 move_native_irq(data->irq);
2468 atomic_t irq_mis_count;
2471 * IO-APIC versions below 0x20 don't support EOI register.
2472 * For the record, here is the information about various versions:
2474 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2475 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2478 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2479 * version as 0x2. This is an error with documentation and these ICH chips
2480 * use io-apic's of version 0x20.
2482 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2483 * Otherwise, we simulate the EOI message manually by changing the trigger
2484 * mode to edge and then back to level, with RTE being masked during this.
2486 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2488 struct irq_pin_list *entry;
2489 unsigned long flags;
2491 raw_spin_lock_irqsave(&ioapic_lock, flags);
2492 for_each_irq_pin(entry, cfg->irq_2_pin) {
2493 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2495 * Intr-remapping uses pin number as the virtual vector
2496 * in the RTE. Actual vector is programmed in
2497 * intr-remapping table entry. Hence for the io-apic
2498 * EOI we use the pin number.
2500 if (irq_remapped(irq))
2501 io_apic_eoi(entry->apic, entry->pin);
2503 io_apic_eoi(entry->apic, cfg->vector);
2505 __mask_and_edge_IO_APIC_irq(entry);
2506 __unmask_and_level_IO_APIC_irq(entry);
2509 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2512 static void ack_apic_level(struct irq_data *data)
2514 struct irq_cfg *cfg = data->chip_data;
2515 int i, do_unmask_irq = 0, irq = data->irq;
2516 struct irq_desc *desc = irq_to_desc(irq);
2519 irq_complete_move(cfg);
2520 #ifdef CONFIG_GENERIC_PENDING_IRQ
2521 /* If we are moving the irq we need to mask it */
2522 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2529 * It appears there is an erratum which affects at least version 0x11
2530 * of I/O APIC (that's the 82093AA and cores integrated into various
2531 * chipsets). Under certain conditions a level-triggered interrupt is
2532 * erroneously delivered as edge-triggered one but the respective IRR
2533 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2534 * message but it will never arrive and further interrupts are blocked
2535 * from the source. The exact reason is so far unknown, but the
2536 * phenomenon was observed when two consecutive interrupt requests
2537 * from a given source get delivered to the same CPU and the source is
2538 * temporarily disabled in between.
2540 * A workaround is to simulate an EOI message manually. We achieve it
2541 * by setting the trigger mode to edge and then to level when the edge
2542 * trigger mode gets detected in the TMR of a local APIC for a
2543 * level-triggered interrupt. We mask the source for the time of the
2544 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2545 * The idea is from Manfred Spraul. --macro
2547 * Also in the case when cpu goes offline, fixup_irqs() will forward
2548 * any unhandled interrupt on the offlined cpu to the new cpu
2549 * destination that is handling the corresponding interrupt. This
2550 * interrupt forwarding is done via IPI's. Hence, in this case also
2551 * level-triggered io-apic interrupt will be seen as an edge
2552 * interrupt in the IRR. And we can't rely on the cpu's EOI
2553 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2554 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2555 * supporting EOI register, we do an explicit EOI to clear the
2556 * remote IRR and on IO-APIC's which don't have an EOI register,
2557 * we use the above logic (mask+edge followed by unmask+level) from
2558 * Manfred Spraul to clear the remote IRR.
2561 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2564 * We must acknowledge the irq before we move it or the acknowledge will
2565 * not propagate properly.
2570 * Tail end of clearing remote IRR bit (either by delivering the EOI
2571 * message via io-apic EOI register write or simulating it using
2572 * mask+edge followed by unnask+level logic) manually when the
2573 * level triggered interrupt is seen as the edge triggered interrupt
2576 if (!(v & (1 << (i & 0x1f)))) {
2577 atomic_inc(&irq_mis_count);
2579 eoi_ioapic_irq(irq, cfg);
2582 /* Now we can move and renable the irq */
2583 if (unlikely(do_unmask_irq)) {
2584 /* Only migrate the irq if the ack has been received.
2586 * On rare occasions the broadcast level triggered ack gets
2587 * delayed going to ioapics, and if we reprogram the
2588 * vector while Remote IRR is still set the irq will never
2591 * To prevent this scenario we read the Remote IRR bit
2592 * of the ioapic. This has two effects.
2593 * - On any sane system the read of the ioapic will
2594 * flush writes (and acks) going to the ioapic from
2596 * - We get to see if the ACK has actually been delivered.
2598 * Based on failed experiments of reprogramming the
2599 * ioapic entry from outside of irq context starting
2600 * with masking the ioapic entry and then polling until
2601 * Remote IRR was clear before reprogramming the
2602 * ioapic I don't trust the Remote IRR bit to be
2603 * completey accurate.
2605 * However there appears to be no other way to plug
2606 * this race, so if the Remote IRR bit is not
2607 * accurate and is causing problems then it is a hardware bug
2608 * and you can go talk to the chipset vendor about it.
2610 if (!io_apic_level_ack_pending(cfg))
2611 move_masked_irq(irq);
2616 #ifdef CONFIG_INTR_REMAP
2617 static void ir_ack_apic_edge(struct irq_data *data)
2622 static void ir_ack_apic_level(struct irq_data *data)
2625 eoi_ioapic_irq(data->irq, data->chip_data);
2627 #endif /* CONFIG_INTR_REMAP */
2629 static struct irq_chip ioapic_chip __read_mostly = {
2631 .irq_startup = startup_ioapic_irq,
2632 .irq_mask = mask_ioapic_irq,
2633 .irq_unmask = unmask_ioapic_irq,
2634 .irq_ack = ack_apic_edge,
2635 .irq_eoi = ack_apic_level,
2637 .irq_set_affinity = ioapic_set_affinity,
2639 .irq_retrigger = ioapic_retrigger_irq,
2642 static struct irq_chip ir_ioapic_chip __read_mostly = {
2643 .name = "IR-IO-APIC",
2644 .irq_startup = startup_ioapic_irq,
2645 .irq_mask = mask_ioapic_irq,
2646 .irq_unmask = unmask_ioapic_irq,
2647 #ifdef CONFIG_INTR_REMAP
2648 .irq_ack = ir_ack_apic_edge,
2649 .irq_eoi = ir_ack_apic_level,
2651 .irq_set_affinity = ir_ioapic_set_affinity,
2654 .irq_retrigger = ioapic_retrigger_irq,
2657 static inline void init_IO_APIC_traps(void)
2660 struct irq_desc *desc;
2661 struct irq_cfg *cfg;
2664 * NOTE! The local APIC isn't very good at handling
2665 * multiple interrupts at the same interrupt level.
2666 * As the interrupt level is determined by taking the
2667 * vector number and shifting that right by 4, we
2668 * want to spread these out a bit so that they don't
2669 * all fall in the same interrupt level.
2671 * Also, we've got to be careful not to trash gate
2672 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2674 for_each_irq_desc(irq, desc) {
2675 cfg = get_irq_desc_chip_data(desc);
2676 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2678 * Hmm.. We don't have an entry for this,
2679 * so default to an old-fashioned 8259
2680 * interrupt if we can..
2682 if (irq < legacy_pic->nr_legacy_irqs)
2683 legacy_pic->make_irq(irq);
2685 /* Strange. Oh, well.. */
2686 desc->chip = &no_irq_chip;
2692 * The local APIC irq-chip implementation:
2695 static void mask_lapic_irq(struct irq_data *data)
2699 v = apic_read(APIC_LVT0);
2700 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2703 static void unmask_lapic_irq(struct irq_data *data)
2707 v = apic_read(APIC_LVT0);
2708 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2711 static void ack_lapic_irq(struct irq_data *data)
2716 static struct irq_chip lapic_chip __read_mostly = {
2717 .name = "local-APIC",
2718 .irq_mask = mask_lapic_irq,
2719 .irq_unmask = unmask_lapic_irq,
2720 .irq_ack = ack_lapic_irq,
2723 static void lapic_register_intr(int irq)
2725 irq_clear_status_flags(irq, IRQ_LEVEL);
2726 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2730 static void __init setup_nmi(void)
2733 * Dirty trick to enable the NMI watchdog ...
2734 * We put the 8259A master into AEOI mode and
2735 * unmask on all local APICs LVT0 as NMI.
2737 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2738 * is from Maciej W. Rozycki - so we do not have to EOI from
2739 * the NMI handler or the timer interrupt.
2741 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2743 enable_NMI_through_LVT0();
2745 apic_printk(APIC_VERBOSE, " done.\n");
2749 * This looks a bit hackish but it's about the only one way of sending
2750 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2751 * not support the ExtINT mode, unfortunately. We need to send these
2752 * cycles as some i82489DX-based boards have glue logic that keeps the
2753 * 8259A interrupt line asserted until INTA. --macro
2755 static inline void __init unlock_ExtINT_logic(void)
2758 struct IO_APIC_route_entry entry0, entry1;
2759 unsigned char save_control, save_freq_select;
2761 pin = find_isa_irq_pin(8, mp_INT);
2766 apic = find_isa_irq_apic(8, mp_INT);
2772 entry0 = ioapic_read_entry(apic, pin);
2773 clear_IO_APIC_pin(apic, pin);
2775 memset(&entry1, 0, sizeof(entry1));
2777 entry1.dest_mode = 0; /* physical delivery */
2778 entry1.mask = 0; /* unmask IRQ now */
2779 entry1.dest = hard_smp_processor_id();
2780 entry1.delivery_mode = dest_ExtINT;
2781 entry1.polarity = entry0.polarity;
2785 ioapic_write_entry(apic, pin, entry1);
2787 save_control = CMOS_READ(RTC_CONTROL);
2788 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2789 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2791 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2796 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2800 CMOS_WRITE(save_control, RTC_CONTROL);
2801 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2802 clear_IO_APIC_pin(apic, pin);
2804 ioapic_write_entry(apic, pin, entry0);
2807 static int disable_timer_pin_1 __initdata;
2808 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2809 static int __init disable_timer_pin_setup(char *arg)
2811 disable_timer_pin_1 = 1;
2814 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2816 int timer_through_8259 __initdata;
2819 * This code may look a bit paranoid, but it's supposed to cooperate with
2820 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2821 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2822 * fanatically on his truly buggy board.
2824 * FIXME: really need to revamp this for all platforms.
2826 static inline void __init check_timer(void)
2828 struct irq_cfg *cfg = get_irq_chip_data(0);
2829 int node = cpu_to_node(0);
2830 int apic1, pin1, apic2, pin2;
2831 unsigned long flags;
2834 local_irq_save(flags);
2837 * get/set the timer IRQ vector:
2839 legacy_pic->mask(0);
2840 assign_irq_vector(0, cfg, apic->target_cpus());
2843 * As IRQ0 is to be enabled in the 8259A, the virtual
2844 * wire has to be disabled in the local APIC. Also
2845 * timer interrupts need to be acknowledged manually in
2846 * the 8259A for the i82489DX when using the NMI
2847 * watchdog as that APIC treats NMIs as level-triggered.
2848 * The AEOI mode will finish them in the 8259A
2851 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2852 legacy_pic->init(1);
2853 #ifdef CONFIG_X86_32
2857 ver = apic_read(APIC_LVR);
2858 ver = GET_APIC_VERSION(ver);
2859 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2863 pin1 = find_isa_irq_pin(0, mp_INT);
2864 apic1 = find_isa_irq_apic(0, mp_INT);
2865 pin2 = ioapic_i8259.pin;
2866 apic2 = ioapic_i8259.apic;
2868 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2869 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2870 cfg->vector, apic1, pin1, apic2, pin2);
2873 * Some BIOS writers are clueless and report the ExtINTA
2874 * I/O APIC input from the cascaded 8259A as the timer
2875 * interrupt input. So just in case, if only one pin
2876 * was found above, try it both directly and through the
2880 if (intr_remapping_enabled)
2881 panic("BIOS bug: timer not connected to IO-APIC");
2885 } else if (pin2 == -1) {
2892 * Ok, does IRQ0 through the IOAPIC work?
2895 add_pin_to_irq_node(cfg, node, apic1, pin1);
2896 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2898 /* for edge trigger, setup_ioapic_irq already
2899 * leave it unmasked.
2900 * so only need to unmask if it is level-trigger
2901 * do we really have level trigger timer?
2904 idx = find_irq_entry(apic1, pin1, mp_INT);
2905 if (idx != -1 && irq_trigger(idx))
2908 if (timer_irq_works()) {
2909 if (nmi_watchdog == NMI_IO_APIC) {
2911 legacy_pic->unmask(0);
2913 if (disable_timer_pin_1 > 0)
2914 clear_IO_APIC_pin(0, pin1);
2917 if (intr_remapping_enabled)
2918 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2919 local_irq_disable();
2920 clear_IO_APIC_pin(apic1, pin1);
2922 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2923 "8254 timer not connected to IO-APIC\n");
2925 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2926 "(IRQ0) through the 8259A ...\n");
2927 apic_printk(APIC_QUIET, KERN_INFO
2928 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2930 * legacy devices should be connected to IO APIC #0
2932 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2933 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2934 legacy_pic->unmask(0);
2935 if (timer_irq_works()) {
2936 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2937 timer_through_8259 = 1;
2938 if (nmi_watchdog == NMI_IO_APIC) {
2939 legacy_pic->mask(0);
2941 legacy_pic->unmask(0);
2946 * Cleanup, just in case ...
2948 local_irq_disable();
2949 legacy_pic->mask(0);
2950 clear_IO_APIC_pin(apic2, pin2);
2951 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2954 if (nmi_watchdog == NMI_IO_APIC) {
2955 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2956 "through the IO-APIC - disabling NMI Watchdog!\n");
2957 nmi_watchdog = NMI_NONE;
2959 #ifdef CONFIG_X86_32
2963 apic_printk(APIC_QUIET, KERN_INFO
2964 "...trying to set up timer as Virtual Wire IRQ...\n");
2966 lapic_register_intr(0);
2967 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2968 legacy_pic->unmask(0);
2970 if (timer_irq_works()) {
2971 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2974 local_irq_disable();
2975 legacy_pic->mask(0);
2976 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2977 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2979 apic_printk(APIC_QUIET, KERN_INFO
2980 "...trying to set up timer as ExtINT IRQ...\n");
2982 legacy_pic->init(0);
2983 legacy_pic->make_irq(0);
2984 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2986 unlock_ExtINT_logic();
2988 if (timer_irq_works()) {
2989 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2992 local_irq_disable();
2993 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2994 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2995 "report. Then try booting with the 'noapic' option.\n");
2997 local_irq_restore(flags);
3001 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3002 * to devices. However there may be an I/O APIC pin available for
3003 * this interrupt regardless. The pin may be left unconnected, but
3004 * typically it will be reused as an ExtINT cascade interrupt for
3005 * the master 8259A. In the MPS case such a pin will normally be
3006 * reported as an ExtINT interrupt in the MP table. With ACPI
3007 * there is no provision for ExtINT interrupts, and in the absence
3008 * of an override it would be treated as an ordinary ISA I/O APIC
3009 * interrupt, that is edge-triggered and unmasked by default. We
3010 * used to do this, but it caused problems on some systems because
3011 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3012 * the same ExtINT cascade interrupt to drive the local APIC of the
3013 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3014 * the I/O APIC in all cases now. No actual device should request
3015 * it anyway. --macro
3017 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3019 void __init setup_IO_APIC(void)
3023 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3025 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3027 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3029 * Set up IO-APIC IRQ routing.
3031 x86_init.mpparse.setup_ioapic_ids();
3034 setup_IO_APIC_irqs();
3035 init_IO_APIC_traps();
3036 if (legacy_pic->nr_legacy_irqs)
3041 * Called after all the initialization is done. If we didnt find any
3042 * APIC bugs then we can allow the modify fast path
3045 static int __init io_apic_bug_finalize(void)
3047 if (sis_apic_bug == -1)
3052 late_initcall(io_apic_bug_finalize);
3054 struct sysfs_ioapic_data {
3055 struct sys_device dev;
3056 struct IO_APIC_route_entry entry[0];
3058 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3060 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3062 struct IO_APIC_route_entry *entry;
3063 struct sysfs_ioapic_data *data;
3066 data = container_of(dev, struct sysfs_ioapic_data, dev);
3067 entry = data->entry;
3068 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3069 *entry = ioapic_read_entry(dev->id, i);
3074 static int ioapic_resume(struct sys_device *dev)
3076 struct IO_APIC_route_entry *entry;
3077 struct sysfs_ioapic_data *data;
3078 unsigned long flags;
3079 union IO_APIC_reg_00 reg_00;
3082 data = container_of(dev, struct sysfs_ioapic_data, dev);
3083 entry = data->entry;
3085 raw_spin_lock_irqsave(&ioapic_lock, flags);
3086 reg_00.raw = io_apic_read(dev->id, 0);
3087 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3088 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3089 io_apic_write(dev->id, 0, reg_00.raw);
3091 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3092 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3093 ioapic_write_entry(dev->id, i, entry[i]);
3098 static struct sysdev_class ioapic_sysdev_class = {
3100 .suspend = ioapic_suspend,
3101 .resume = ioapic_resume,
3104 static int __init ioapic_init_sysfs(void)
3106 struct sys_device * dev;
3109 error = sysdev_class_register(&ioapic_sysdev_class);
3113 for (i = 0; i < nr_ioapics; i++ ) {
3114 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3115 * sizeof(struct IO_APIC_route_entry);
3116 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3117 if (!mp_ioapic_data[i]) {
3118 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3121 dev = &mp_ioapic_data[i]->dev;
3123 dev->cls = &ioapic_sysdev_class;
3124 error = sysdev_register(dev);
3126 kfree(mp_ioapic_data[i]);
3127 mp_ioapic_data[i] = NULL;
3128 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3136 device_initcall(ioapic_init_sysfs);
3139 * Dynamic irq allocate and deallocation
3141 unsigned int create_irq_nr(unsigned int irq_want, int node)
3143 /* Allocate an unused irq */
3146 unsigned long flags;
3147 struct irq_cfg *cfg_new = NULL;
3148 struct irq_desc *desc_new = NULL;
3151 if (irq_want < nr_irqs_gsi)
3152 irq_want = nr_irqs_gsi;
3154 raw_spin_lock_irqsave(&vector_lock, flags);
3155 for (new = irq_want; new < nr_irqs; new++) {
3156 desc_new = irq_to_desc_alloc_node(new, node);
3158 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3161 cfg_new = get_irq_desc_chip_data(desc_new);
3163 if (cfg_new->vector != 0)
3166 desc_new = move_irq_desc(desc_new, node);
3167 cfg_new = get_irq_desc_chip_data(desc_new);
3169 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3173 raw_spin_unlock_irqrestore(&vector_lock, flags);
3176 dynamic_irq_init_keep_chip_data(irq);
3181 int create_irq(void)
3183 int node = cpu_to_node(0);
3184 unsigned int irq_want;
3187 irq_want = nr_irqs_gsi;
3188 irq = create_irq_nr(irq_want, node);
3196 void destroy_irq(unsigned int irq)
3198 unsigned long flags;
3200 dynamic_irq_cleanup_keep_chip_data(irq);
3203 raw_spin_lock_irqsave(&vector_lock, flags);
3204 __clear_irq_vector(irq, get_irq_chip_data(irq));
3205 raw_spin_unlock_irqrestore(&vector_lock, flags);
3209 * MSI message composition
3211 #ifdef CONFIG_PCI_MSI
3212 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3213 struct msi_msg *msg, u8 hpet_id)
3215 struct irq_cfg *cfg;
3223 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3227 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3229 if (irq_remapped(irq)) {
3234 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3235 BUG_ON(ir_index == -1);
3237 prepare_irte(&irte, cfg->vector, dest);
3239 /* Set source-id of interrupt request */
3241 set_msi_sid(&irte, pdev);
3243 set_hpet_sid(&irte, hpet_id);
3245 modify_irte(irq, &irte);
3247 msg->address_hi = MSI_ADDR_BASE_HI;
3248 msg->data = sub_handle;
3249 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3251 MSI_ADDR_IR_INDEX1(ir_index) |
3252 MSI_ADDR_IR_INDEX2(ir_index);
3254 if (x2apic_enabled())
3255 msg->address_hi = MSI_ADDR_BASE_HI |
3256 MSI_ADDR_EXT_DEST_ID(dest);
3258 msg->address_hi = MSI_ADDR_BASE_HI;
3262 ((apic->irq_dest_mode == 0) ?
3263 MSI_ADDR_DEST_MODE_PHYSICAL:
3264 MSI_ADDR_DEST_MODE_LOGICAL) |
3265 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3266 MSI_ADDR_REDIRECTION_CPU:
3267 MSI_ADDR_REDIRECTION_LOWPRI) |
3268 MSI_ADDR_DEST_ID(dest);
3271 MSI_DATA_TRIGGER_EDGE |
3272 MSI_DATA_LEVEL_ASSERT |
3273 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3274 MSI_DATA_DELIVERY_FIXED:
3275 MSI_DATA_DELIVERY_LOWPRI) |
3276 MSI_DATA_VECTOR(cfg->vector);
3283 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3285 struct irq_cfg *cfg = data->chip_data;
3289 if (__ioapic_set_affinity(data, mask, &dest))
3292 __get_cached_msi_msg(data->msi_desc, &msg);
3294 msg.data &= ~MSI_DATA_VECTOR_MASK;
3295 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3296 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3297 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3299 __write_msi_msg(data->msi_desc, &msg);
3303 #ifdef CONFIG_INTR_REMAP
3305 * Migrate the MSI irq to another cpumask. This migration is
3306 * done in the process context using interrupt-remapping hardware.
3309 ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3312 struct irq_cfg *cfg = data->chip_data;
3313 unsigned int dest, irq = data->irq;
3316 if (get_irte(irq, &irte))
3319 if (__ioapic_set_affinity(data, mask, &dest))
3322 irte.vector = cfg->vector;
3323 irte.dest_id = IRTE_DEST(dest);
3326 * atomically update the IRTE with the new destination and vector.
3328 modify_irte(irq, &irte);
3331 * After this point, all the interrupts will start arriving
3332 * at the new destination. So, time to cleanup the previous
3333 * vector allocation.
3335 if (cfg->move_in_progress)
3336 send_cleanup_vector(cfg);
3342 #endif /* CONFIG_SMP */
3345 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3346 * which implement the MSI or MSI-X Capability Structure.
3348 static struct irq_chip msi_chip = {
3350 .irq_unmask = unmask_msi_irq,
3351 .irq_mask = mask_msi_irq,
3352 .irq_ack = ack_apic_edge,
3354 .irq_set_affinity = msi_set_affinity,
3356 .irq_retrigger = ioapic_retrigger_irq,
3359 static struct irq_chip msi_ir_chip = {
3360 .name = "IR-PCI-MSI",
3361 .irq_unmask = unmask_msi_irq,
3362 .irq_mask = mask_msi_irq,
3363 #ifdef CONFIG_INTR_REMAP
3364 .irq_ack = ir_ack_apic_edge,
3366 .irq_set_affinity = ir_msi_set_affinity,
3369 .irq_retrigger = ioapic_retrigger_irq,
3373 * Map the PCI dev to the corresponding remapping hardware unit
3374 * and allocate 'nvec' consecutive interrupt-remapping table entries
3377 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3379 struct intel_iommu *iommu;
3382 iommu = map_dev_to_ir(dev);
3385 "Unable to map PCI %s to iommu\n", pci_name(dev));
3389 index = alloc_irte(iommu, irq, nvec);
3392 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3399 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3404 ret = msi_compose_msg(dev, irq, &msg, -1);
3408 set_irq_msi(irq, msidesc);
3409 write_msi_msg(irq, &msg);
3411 if (irq_remapped(irq)) {
3412 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3413 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3415 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3417 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3422 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3424 int node, ret, sub_handle, index = 0;
3425 unsigned int irq, irq_want;
3426 struct msi_desc *msidesc;
3427 struct intel_iommu *iommu = NULL;
3429 /* x86 doesn't support multiple MSI yet */
3430 if (type == PCI_CAP_ID_MSI && nvec > 1)
3433 node = dev_to_node(&dev->dev);
3434 irq_want = nr_irqs_gsi;
3436 list_for_each_entry(msidesc, &dev->msi_list, list) {
3437 irq = create_irq_nr(irq_want, node);
3441 if (!intr_remapping_enabled)
3446 * allocate the consecutive block of IRTE's
3449 index = msi_alloc_irte(dev, irq, nvec);
3455 iommu = map_dev_to_ir(dev);
3461 * setup the mapping between the irq and the IRTE
3462 * base index, the sub_handle pointing to the
3463 * appropriate interrupt remap table entry.
3465 set_irte_irq(irq, iommu, index, sub_handle);
3468 ret = setup_msi_irq(dev, msidesc, irq);
3480 void arch_teardown_msi_irq(unsigned int irq)
3485 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3488 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3491 struct irq_cfg *cfg = data->chip_data;
3492 unsigned int dest, irq = data->irq;
3495 if (__ioapic_set_affinity(data, mask, &dest))
3498 dmar_msi_read(irq, &msg);
3500 msg.data &= ~MSI_DATA_VECTOR_MASK;
3501 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3502 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3503 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3505 dmar_msi_write(irq, &msg);
3510 #endif /* CONFIG_SMP */
3512 static struct irq_chip dmar_msi_type = {
3514 .irq_unmask = dmar_msi_unmask,
3515 .irq_mask = dmar_msi_mask,
3516 .irq_ack = ack_apic_edge,
3518 .irq_set_affinity = dmar_msi_set_affinity,
3520 .irq_retrigger = ioapic_retrigger_irq,
3523 int arch_setup_dmar_msi(unsigned int irq)
3528 ret = msi_compose_msg(NULL, irq, &msg, -1);
3531 dmar_msi_write(irq, &msg);
3532 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3538 #ifdef CONFIG_HPET_TIMER
3541 static int hpet_msi_set_affinity(struct irq_data *data,
3542 const struct cpumask *mask, bool force)
3544 struct irq_cfg *cfg = data->chip_data;
3548 if (__ioapic_set_affinity(data, mask, &dest))
3551 hpet_msi_read(data->handler_data, &msg);
3553 msg.data &= ~MSI_DATA_VECTOR_MASK;
3554 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3555 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3556 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3558 hpet_msi_write(data->handler_data, &msg);
3563 #endif /* CONFIG_SMP */
3565 static struct irq_chip ir_hpet_msi_type = {
3566 .name = "IR-HPET_MSI",
3567 .irq_unmask = hpet_msi_unmask,
3568 .irq_mask = hpet_msi_mask,
3569 #ifdef CONFIG_INTR_REMAP
3570 .irq_ack = ir_ack_apic_edge,
3572 .irq_set_affinity = ir_msi_set_affinity,
3575 .irq_retrigger = ioapic_retrigger_irq,
3578 static struct irq_chip hpet_msi_type = {
3580 .irq_unmask = hpet_msi_unmask,
3581 .irq_mask = hpet_msi_mask,
3582 .irq_ack = ack_apic_edge,
3584 .irq_set_affinity = hpet_msi_set_affinity,
3586 .irq_retrigger = ioapic_retrigger_irq,
3589 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3594 if (intr_remapping_enabled) {
3595 struct intel_iommu *iommu = map_hpet_to_ir(id);
3601 index = alloc_irte(iommu, irq, 1);
3606 ret = msi_compose_msg(NULL, irq, &msg, id);
3610 hpet_msi_write(get_irq_data(irq), &msg);
3611 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3612 if (irq_remapped(irq))
3613 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3614 handle_edge_irq, "edge");
3616 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3617 handle_edge_irq, "edge");
3623 #endif /* CONFIG_PCI_MSI */
3625 * Hypertransport interrupt support
3627 #ifdef CONFIG_HT_IRQ
3631 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3633 struct ht_irq_msg msg;
3634 fetch_ht_irq_msg(irq, &msg);
3636 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3637 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3639 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3640 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3642 write_ht_irq_msg(irq, &msg);
3646 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3648 struct irq_cfg *cfg = data->chip_data;
3651 if (__ioapic_set_affinity(data, mask, &dest))
3654 target_ht_irq(data->irq, dest, cfg->vector);
3660 static struct irq_chip ht_irq_chip = {
3662 .irq_mask = mask_ht_irq,
3663 .irq_unmask = unmask_ht_irq,
3664 .irq_ack = ack_apic_edge,
3666 .irq_set_affinity = ht_set_affinity,
3668 .irq_retrigger = ioapic_retrigger_irq,
3671 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3673 struct irq_cfg *cfg;
3680 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3682 struct ht_irq_msg msg;
3685 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3686 apic->target_cpus());
3688 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3692 HT_IRQ_LOW_DEST_ID(dest) |
3693 HT_IRQ_LOW_VECTOR(cfg->vector) |
3694 ((apic->irq_dest_mode == 0) ?
3695 HT_IRQ_LOW_DM_PHYSICAL :
3696 HT_IRQ_LOW_DM_LOGICAL) |
3697 HT_IRQ_LOW_RQEOI_EDGE |
3698 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3699 HT_IRQ_LOW_MT_FIXED :
3700 HT_IRQ_LOW_MT_ARBITRATED) |
3701 HT_IRQ_LOW_IRQ_MASKED;
3703 write_ht_irq_msg(irq, &msg);
3705 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3706 handle_edge_irq, "edge");
3708 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3712 #endif /* CONFIG_HT_IRQ */
3714 int __init io_apic_get_redir_entries (int ioapic)
3716 union IO_APIC_reg_01 reg_01;
3717 unsigned long flags;
3719 raw_spin_lock_irqsave(&ioapic_lock, flags);
3720 reg_01.raw = io_apic_read(ioapic, 1);
3721 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3723 /* The register returns the maximum index redir index
3724 * supported, which is one less than the total number of redir
3727 return reg_01.bits.entries + 1;
3730 void __init probe_nr_irqs_gsi(void)
3734 nr = gsi_top + NR_IRQS_LEGACY;
3735 if (nr > nr_irqs_gsi)
3738 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3741 #ifdef CONFIG_SPARSE_IRQ
3742 int __init arch_probe_nr_irqs(void)
3746 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3747 nr_irqs = NR_VECTORS * nr_cpu_ids;
3749 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3750 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3752 * for MSI and HT dyn irq
3754 nr += nr_irqs_gsi * 16;
3759 return NR_IRQS_LEGACY;
3763 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3764 struct io_apic_irq_attr *irq_attr)
3766 struct irq_desc *desc;
3767 struct irq_cfg *cfg;
3770 int trigger, polarity;
3772 ioapic = irq_attr->ioapic;
3773 if (!IO_APIC_IRQ(irq)) {
3774 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3780 node = dev_to_node(dev);
3782 node = cpu_to_node(0);
3784 desc = irq_to_desc_alloc_node(irq, node);
3786 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3790 pin = irq_attr->ioapic_pin;
3791 trigger = irq_attr->trigger;
3792 polarity = irq_attr->polarity;
3794 cfg = get_irq_desc_chip_data(desc);
3797 * IRQs < 16 are already in the irq_2_pin[] map
3799 if (irq >= legacy_pic->nr_legacy_irqs) {
3800 if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) {
3801 printk(KERN_INFO "can not add pin %d for irq %d\n",
3807 setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
3812 int io_apic_set_pci_routing(struct device *dev, int irq,
3813 struct io_apic_irq_attr *irq_attr)
3817 * Avoid pin reprogramming. PRTs typically include entries
3818 * with redundant pin->gsi mappings (but unique PCI devices);
3819 * we only program the IOAPIC on the first.
3821 ioapic = irq_attr->ioapic;
3822 pin = irq_attr->ioapic_pin;
3823 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3824 pr_debug("Pin %d-%d already programmed\n",
3825 mp_ioapics[ioapic].apicid, pin);
3828 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3830 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3833 u8 __init io_apic_unique_id(u8 id)
3835 #ifdef CONFIG_X86_32
3836 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3837 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3838 return io_apic_get_unique_id(nr_ioapics, id);
3843 DECLARE_BITMAP(used, 256);
3845 bitmap_zero(used, 256);
3846 for (i = 0; i < nr_ioapics; i++) {
3847 struct mpc_ioapic *ia = &mp_ioapics[i];
3848 __set_bit(ia->apicid, used);
3850 if (!test_bit(id, used))
3852 return find_first_zero_bit(used, 256);
3856 #ifdef CONFIG_X86_32
3857 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3859 union IO_APIC_reg_00 reg_00;
3860 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3862 unsigned long flags;
3866 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3867 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3868 * supports up to 16 on one shared APIC bus.
3870 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3871 * advantage of new APIC bus architecture.
3874 if (physids_empty(apic_id_map))
3875 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3877 raw_spin_lock_irqsave(&ioapic_lock, flags);
3878 reg_00.raw = io_apic_read(ioapic, 0);
3879 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3881 if (apic_id >= get_physical_broadcast()) {
3882 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3883 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3884 apic_id = reg_00.bits.ID;
3888 * Every APIC in a system must have a unique ID or we get lots of nice
3889 * 'stuck on smp_invalidate_needed IPI wait' messages.
3891 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3893 for (i = 0; i < get_physical_broadcast(); i++) {
3894 if (!apic->check_apicid_used(&apic_id_map, i))
3898 if (i == get_physical_broadcast())
3899 panic("Max apic_id exceeded!\n");
3901 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3902 "trying %d\n", ioapic, apic_id, i);
3907 apic->apicid_to_cpu_present(apic_id, &tmp);
3908 physids_or(apic_id_map, apic_id_map, tmp);
3910 if (reg_00.bits.ID != apic_id) {
3911 reg_00.bits.ID = apic_id;
3913 raw_spin_lock_irqsave(&ioapic_lock, flags);
3914 io_apic_write(ioapic, 0, reg_00.raw);
3915 reg_00.raw = io_apic_read(ioapic, 0);
3916 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3919 if (reg_00.bits.ID != apic_id) {
3920 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3925 apic_printk(APIC_VERBOSE, KERN_INFO
3926 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3932 int __init io_apic_get_version(int ioapic)
3934 union IO_APIC_reg_01 reg_01;
3935 unsigned long flags;
3937 raw_spin_lock_irqsave(&ioapic_lock, flags);
3938 reg_01.raw = io_apic_read(ioapic, 1);
3939 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3941 return reg_01.bits.version;
3944 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3946 int ioapic, pin, idx;
3948 if (skip_ioapic_setup)
3951 ioapic = mp_find_ioapic(gsi);
3955 pin = mp_find_ioapic_pin(ioapic, gsi);
3959 idx = find_irq_entry(ioapic, pin, mp_INT);
3963 *trigger = irq_trigger(idx);
3964 *polarity = irq_polarity(idx);
3969 * This function currently is only a helper for the i386 smp boot process where
3970 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3971 * so mask in all cases should simply be apic->target_cpus()
3974 void __init setup_ioapic_dest(void)
3976 int pin, ioapic, irq, irq_entry;
3977 struct irq_desc *desc;
3978 const struct cpumask *mask;
3980 if (skip_ioapic_setup == 1)
3983 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3984 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3985 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3986 if (irq_entry == -1)
3988 irq = pin_2_irq(irq_entry, ioapic, pin);
3990 if ((ioapic > 0) && (irq > 16))
3993 desc = irq_to_desc(irq);
3996 * Honour affinities which have been set in early boot
3999 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4000 mask = desc->irq_data.affinity;
4002 mask = apic->target_cpus();
4004 if (intr_remapping_enabled)
4005 ir_ioapic_set_affinity(&desc->irq_data, mask, false);
4007 ioapic_set_affinity(&desc->irq_data, mask, false);
4013 #define IOAPIC_RESOURCE_NAME_SIZE 11
4015 static struct resource *ioapic_resources;
4017 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4020 struct resource *res;
4024 if (nr_ioapics <= 0)
4027 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4030 mem = alloc_bootmem(n);
4033 mem += sizeof(struct resource) * nr_ioapics;
4035 for (i = 0; i < nr_ioapics; i++) {
4037 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4038 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4039 mem += IOAPIC_RESOURCE_NAME_SIZE;
4042 ioapic_resources = res;
4047 void __init ioapic_init_mappings(void)
4049 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4050 struct resource *ioapic_res;
4053 ioapic_res = ioapic_setup_resources(nr_ioapics);
4054 for (i = 0; i < nr_ioapics; i++) {
4055 if (smp_found_config) {
4056 ioapic_phys = mp_ioapics[i].apicaddr;
4057 #ifdef CONFIG_X86_32
4060 "WARNING: bogus zero IO-APIC "
4061 "address found in MPTABLE, "
4062 "disabling IO/APIC support!\n");
4063 smp_found_config = 0;
4064 skip_ioapic_setup = 1;
4065 goto fake_ioapic_page;
4069 #ifdef CONFIG_X86_32
4072 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4073 ioapic_phys = __pa(ioapic_phys);
4075 set_fixmap_nocache(idx, ioapic_phys);
4076 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4077 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4081 ioapic_res->start = ioapic_phys;
4082 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4087 void __init ioapic_insert_resources(void)
4090 struct resource *r = ioapic_resources;
4095 "IO APIC resources couldn't be allocated.\n");
4099 for (i = 0; i < nr_ioapics; i++) {
4100 insert_resource(&iomem_resource, r);
4105 int mp_find_ioapic(u32 gsi)
4109 /* Find the IOAPIC that manages this GSI. */
4110 for (i = 0; i < nr_ioapics; i++) {
4111 if ((gsi >= mp_gsi_routing[i].gsi_base)
4112 && (gsi <= mp_gsi_routing[i].gsi_end))
4116 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4120 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4122 if (WARN_ON(ioapic == -1))
4124 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4127 return gsi - mp_gsi_routing[ioapic].gsi_base;
4130 static int bad_ioapic(unsigned long address)
4132 if (nr_ioapics >= MAX_IO_APICS) {
4133 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4134 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4138 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4139 " found in table, skipping!\n");
4145 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4150 if (bad_ioapic(address))
4155 mp_ioapics[idx].type = MP_IOAPIC;
4156 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4157 mp_ioapics[idx].apicaddr = address;
4159 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4160 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4161 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4164 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4165 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4167 entries = io_apic_get_redir_entries(idx);
4168 mp_gsi_routing[idx].gsi_base = gsi_base;
4169 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4172 * The number of IO-APIC IRQ registers (== #pins):
4174 nr_ioapic_registers[idx] = entries;
4176 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4177 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4179 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4180 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4181 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4182 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4187 /* Enable IOAPIC early just for system timer */
4188 void __init pre_init_apic_IRQ0(void)
4190 struct irq_cfg *cfg;
4192 printk(KERN_INFO "Early APIC setup for system timer0\n");
4194 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4196 irq_to_desc_alloc_node(0, 0);
4201 add_pin_to_irq_node(cfg, 0, 0, 0);
4202 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4204 setup_ioapic_irq(0, 0, 0, cfg, 0, 0);