2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
21 #include <asm/cpufeature.h>
22 #include <asm/processor.h>
23 #include <asm/sigcontext.h>
25 #include <asm/uaccess.h>
26 #include <asm/xsave.h>
28 extern unsigned int sig_xstate_size;
29 extern void fpu_init(void);
30 extern void mxcsr_feature_mask_init(void);
31 extern int init_fpu(struct task_struct *child);
32 extern asmlinkage void math_state_restore(void);
33 extern void __math_state_restore(void);
34 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
36 extern user_regset_active_fn fpregs_active, xfpregs_active;
37 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
39 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
43 * xstateregs_active == fpregs_active. Please refer to the comment
44 * at the definition of fpregs_active.
46 #define xstateregs_active fpregs_active
48 extern struct _fpx_sw_bytes fx_sw_reserved;
49 #ifdef CONFIG_IA32_EMULATION
50 extern unsigned int sig_xstate_ia32_size;
51 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
54 extern int save_i387_xstate_ia32(void __user *buf);
55 extern int restore_i387_xstate_ia32(void __user *buf);
58 #define X87_FSW_ES (1 << 7) /* Exception Summary */
60 static __always_inline __pure bool use_xsaveopt(void)
62 return static_cpu_has(X86_FEATURE_XSAVEOPT);
65 static __always_inline __pure bool use_xsave(void)
67 return static_cpu_has(X86_FEATURE_XSAVE);
70 extern void __sanitize_i387_state(struct task_struct *);
72 static inline void sanitize_i387_state(struct task_struct *tsk)
76 __sanitize_i387_state(tsk);
81 /* Ignore delayed exceptions from user space */
82 static inline void tolerant_fwait(void)
84 asm volatile("1: fwait\n"
86 _ASM_EXTABLE(1b, 2b));
89 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
93 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
95 ".section .fixup,\"ax\"\n"
96 "3: movl $-1,%[err]\n"
101 #if 0 /* See comment in fxsave() below. */
102 : [fx] "r" (fx), "m" (*fx), "0" (0));
104 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
109 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
110 is pending. Clear the x87 state here by setting it to fixed
111 values. The kernel data segment can be sometimes 0 and sometimes
112 new user value. Both should be ok.
113 Use the PDA as safe address because it should be already in L1. */
114 static inline void fpu_clear(struct fpu *fpu)
116 struct xsave_struct *xstate = &fpu->state->xsave;
117 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
120 * xsave header may indicate the init state of the FP.
123 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
126 if (unlikely(fx->swd & X87_FSW_ES))
127 asm volatile("fnclex");
128 alternative_input(ASM_NOP8 ASM_NOP2,
129 " emms\n" /* clear stack tags */
130 " fildl %%gs:0", /* load to clear state */
131 X86_FEATURE_FXSAVE_LEAK);
134 static inline void clear_fpu_state(struct task_struct *tsk)
136 fpu_clear(&tsk->thread.fpu);
139 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
143 asm volatile("1: rex64/fxsave (%[fx])\n\t"
145 ".section .fixup,\"ax\"\n"
146 "3: movl $-1,%[err]\n"
150 : [err] "=r" (err), "=m" (*fx)
151 #if 0 /* See comment in fxsave() below. */
152 : [fx] "r" (fx), "0" (0));
154 : [fx] "cdaSDb" (fx), "0" (0));
157 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
159 /* No need to clear here because the caller clears USED_MATH */
163 static inline void fpu_fxsave(struct fpu *fpu)
165 /* Using "rex64; fxsave %0" is broken because, if the memory operand
166 uses any extended registers for addressing, a second REX prefix
167 will be generated (to the assembler, rex64 followed by semicolon
168 is a separate instruction), and hence the 64-bitness is lost. */
170 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
171 starting with gas 2.16. */
172 __asm__ __volatile__("fxsaveq %0"
173 : "=m" (fpu->state->fxsave));
175 /* Using, as a workaround, the properly prefixed form below isn't
176 accepted by any binutils version so far released, complaining that
177 the same type of prefix is used twice if an extended register is
178 needed for addressing (fix submitted to mainline 2005-11-21). */
179 __asm__ __volatile__("rex64/fxsave %0"
180 : "=m" (fpu->state->fxsave));
182 /* This, however, we can work around by forcing the compiler to select
183 an addressing mode that doesn't require extended registers. */
184 __asm__ __volatile__("rex64/fxsave (%1)"
185 : "=m" (fpu->state->fxsave)
186 : "cdaSDb" (&fpu->state->fxsave));
190 static inline void fpu_save_init(struct fpu *fpu)
200 static inline void __save_init_fpu(struct task_struct *tsk)
202 fpu_save_init(&tsk->thread.fpu);
203 task_thread_info(tsk)->status &= ~TS_USEDFPU;
206 #else /* CONFIG_X86_32 */
208 #ifdef CONFIG_MATH_EMULATION
209 extern void finit_soft_fpu(struct i387_soft_struct *soft);
211 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
214 static inline void tolerant_fwait(void)
216 asm volatile("fnclex ; fwait");
219 /* perform fxrstor iff the processor has extended states, otherwise frstor */
220 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
223 * The "nop" is needed to make the instructions the same
235 /* We need a safe address that is cheap to find and that is already
236 in L1 during context switch. The best choices are unfortunately
237 different for UP and SMP */
239 #define safe_address (__per_cpu_offset[0])
241 #define safe_address (kstat_cpu(0).cpustat.user)
245 * These must be called with preempt disabled
247 static inline void fpu_save_init(struct fpu *fpu)
250 struct xsave_struct *xstate = &fpu->state->xsave;
251 struct i387_fxsave_struct *fx = &fpu->state->fxsave;
256 * xsave header may indicate the init state of the FP.
258 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
261 if (unlikely(fx->swd & X87_FSW_ES))
262 asm volatile("fnclex");
265 * we can do a simple return here or be paranoid :)
270 /* Use more nops than strictly needed in case the compiler
273 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
275 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
277 [fx] "m" (fpu->state->fxsave),
278 [fsw] "m" (fpu->state->fxsave.swd) : "memory");
280 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
281 is pending. Clear the x87 state here by setting it to fixed
282 values. safe_address is a random variable that should be in L1 */
284 GENERIC_NOP8 GENERIC_NOP2,
285 "emms\n\t" /* clear stack tags */
286 "fildl %[addr]", /* set F?P to defined value */
287 X86_FEATURE_FXSAVE_LEAK,
288 [addr] "m" (safe_address));
293 static inline void __save_init_fpu(struct task_struct *tsk)
295 fpu_save_init(&tsk->thread.fpu);
296 task_thread_info(tsk)->status &= ~TS_USEDFPU;
300 #endif /* CONFIG_X86_64 */
302 static inline int fpu_fxrstor_checking(struct fpu *fpu)
304 return fxrstor_checking(&fpu->state->fxsave);
307 static inline int fpu_restore_checking(struct fpu *fpu)
310 return fpu_xrstor_checking(fpu);
312 return fpu_fxrstor_checking(fpu);
315 static inline int restore_fpu_checking(struct task_struct *tsk)
317 return fpu_restore_checking(&tsk->thread.fpu);
321 * Signal frame handlers...
323 extern int save_i387_xstate(void __user *buf);
324 extern int restore_i387_xstate(void __user *buf);
326 static inline void __unlazy_fpu(struct task_struct *tsk)
328 if (task_thread_info(tsk)->status & TS_USEDFPU) {
329 __save_init_fpu(tsk);
332 tsk->fpu_counter = 0;
335 static inline void __clear_fpu(struct task_struct *tsk)
337 if (task_thread_info(tsk)->status & TS_USEDFPU) {
339 task_thread_info(tsk)->status &= ~TS_USEDFPU;
344 static inline void kernel_fpu_begin(void)
346 struct thread_info *me = current_thread_info();
348 if (me->status & TS_USEDFPU)
349 __save_init_fpu(me->task);
354 static inline void kernel_fpu_end(void)
360 static inline bool irq_fpu_usable(void)
362 struct pt_regs *regs;
364 return !in_interrupt() || !(regs = get_irq_regs()) || \
365 user_mode(regs) || (read_cr0() & X86_CR0_TS);
369 * Some instructions like VIA's padlock instructions generate a spurious
370 * DNA fault but don't modify SSE registers. And these instructions
371 * get used from interrupt context as well. To prevent these kernel instructions
372 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
373 * should use them only in the context of irq_ts_save/restore()
375 static inline int irq_ts_save(void)
378 * If in process context and not atomic, we can take a spurious DNA fault.
379 * Otherwise, doing clts() in process context requires disabling preemption
380 * or some heavy lifting like kernel_fpu_begin()
385 if (read_cr0() & X86_CR0_TS) {
393 static inline void irq_ts_restore(int TS_state)
401 static inline void save_init_fpu(struct task_struct *tsk)
403 __save_init_fpu(tsk);
407 #define unlazy_fpu __unlazy_fpu
408 #define clear_fpu __clear_fpu
410 #else /* CONFIG_X86_32 */
413 * These disable preemption on their own and are safe
415 static inline void save_init_fpu(struct task_struct *tsk)
418 __save_init_fpu(tsk);
423 static inline void unlazy_fpu(struct task_struct *tsk)
430 static inline void clear_fpu(struct task_struct *tsk)
437 #endif /* CONFIG_X86_64 */
440 * i387 state interaction
442 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
445 return tsk->thread.fpu.state->fxsave.cwd;
447 return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
451 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
454 return tsk->thread.fpu.state->fxsave.swd;
456 return (unsigned short)tsk->thread.fpu.state->fsave.swd;
460 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
463 return tsk->thread.fpu.state->fxsave.mxcsr;
465 return MXCSR_DEFAULT;
469 static bool fpu_allocated(struct fpu *fpu)
471 return fpu->state != NULL;
474 static inline int fpu_alloc(struct fpu *fpu)
476 if (fpu_allocated(fpu))
478 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
481 WARN_ON((unsigned long)fpu->state & 15);
485 static inline void fpu_free(struct fpu *fpu)
488 kmem_cache_free(task_xstate_cachep, fpu->state);
493 static inline void fpu_copy(struct fpu *dst, struct fpu *src)
495 memcpy(dst->state, src->state, xstate_size);
498 #endif /* __ASSEMBLY__ */
500 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
501 #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
503 #endif /* _ASM_X86_I387_H */