2 * Low-level SPU handling
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/poll.h>
29 #include <linux/ptrace.h>
30 #include <linux/slab.h>
31 #include <linux/wait.h>
35 #include <asm/semaphore.h>
37 #include <asm/mmu_context.h>
39 #include "interrupt.h"
41 static int __spu_trap_invalid_dma(struct spu *spu)
43 pr_debug("%s\n", __FUNCTION__);
44 force_sig(SIGBUS, /* info, */ current);
48 static int __spu_trap_dma_align(struct spu *spu)
50 pr_debug("%s\n", __FUNCTION__);
51 force_sig(SIGBUS, /* info, */ current);
55 static int __spu_trap_error(struct spu *spu)
57 pr_debug("%s\n", __FUNCTION__);
58 force_sig(SIGILL, /* info, */ current);
62 static void spu_restart_dma(struct spu *spu)
64 struct spu_priv2 __iomem *priv2 = spu->priv2;
65 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
68 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
70 struct spu_priv2 __iomem *priv2;
73 pr_debug("%s\n", __FUNCTION__);
75 if (REGION_ID(ea) != USER_REGION_ID) {
76 pr_debug("invalid region access at %016lx\n", ea);
83 if (spu->slb_replace >= 8)
86 out_be64(&priv2->slb_index_W, spu->slb_replace);
87 out_be64(&priv2->slb_vsid_RW,
88 (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT)
90 out_be64(&priv2->slb_esid_RW, (ea & ESID_MASK) | SLB_ESID_V);
94 pr_debug("set slb %d context %lx, ea %016lx, vsid %016lx, esid %016lx\n",
95 spu->slb_replace, mm->context.id, ea,
96 (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT)| SLB_VSID_USER,
97 (ea & ESID_MASK) | SLB_ESID_V);
101 static int __spu_trap_data_map(struct spu *spu, unsigned long ea)
104 struct spu_priv1 __iomem *priv1;
106 pr_debug("%s\n", __FUNCTION__);
108 dsisr = in_be64(&priv1->mfc_dsisr_RW);
110 wake_up(&spu->stop_wq);
115 static int __spu_trap_mailbox(struct spu *spu)
117 wake_up_all(&spu->ibox_wq);
118 kill_fasync(&spu->ibox_fasync, SIGIO, POLLIN);
120 /* atomically disable SPU mailbox interrupts */
121 spin_lock(&spu->register_lock);
122 out_be64(&spu->priv1->int_mask_class2_RW,
123 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x1);
124 spin_unlock(&spu->register_lock);
128 static int __spu_trap_stop(struct spu *spu)
130 pr_debug("%s\n", __FUNCTION__);
131 spu->stop_code = in_be32(&spu->problem->spu_status_R);
132 wake_up(&spu->stop_wq);
136 static int __spu_trap_halt(struct spu *spu)
138 pr_debug("%s\n", __FUNCTION__);
139 spu->stop_code = in_be32(&spu->problem->spu_status_R);
140 wake_up(&spu->stop_wq);
144 static int __spu_trap_tag_group(struct spu *spu)
146 pr_debug("%s\n", __FUNCTION__);
147 /* wake_up(&spu->dma_wq); */
151 static int __spu_trap_spubox(struct spu *spu)
153 wake_up_all(&spu->wbox_wq);
154 kill_fasync(&spu->wbox_fasync, SIGIO, POLLOUT);
156 /* atomically disable SPU mailbox interrupts */
157 spin_lock(&spu->register_lock);
158 out_be64(&spu->priv1->int_mask_class2_RW,
159 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x10);
160 spin_unlock(&spu->register_lock);
165 spu_irq_class_0(int irq, void *data, struct pt_regs *regs)
170 spu->class_0_pending = 1;
171 wake_up(&spu->stop_wq);
177 spu_irq_class_0_bottom(struct spu *spu)
181 spu->class_0_pending = 0;
183 stat = in_be64(&spu->priv1->int_stat_class0_RW);
185 if (stat & 1) /* invalid MFC DMA */
186 __spu_trap_invalid_dma(spu);
188 if (stat & 2) /* invalid DMA alignment */
189 __spu_trap_dma_align(spu);
191 if (stat & 4) /* error on SPU */
192 __spu_trap_error(spu);
194 out_be64(&spu->priv1->int_stat_class0_RW, stat);
199 spu_irq_class_1(int irq, void *data, struct pt_regs *regs)
202 unsigned long stat, dar;
205 stat = in_be64(&spu->priv1->int_stat_class1_RW);
206 dar = in_be64(&spu->priv1->mfc_dar_RW);
208 if (stat & 1) /* segment fault */
209 __spu_trap_data_seg(spu, dar);
211 if (stat & 2) { /* mapping fault */
212 __spu_trap_data_map(spu, dar);
215 if (stat & 4) /* ls compare & suspend on get */
218 if (stat & 8) /* ls compare & suspend on put */
221 out_be64(&spu->priv1->int_stat_class1_RW, stat);
222 return stat ? IRQ_HANDLED : IRQ_NONE;
226 spu_irq_class_2(int irq, void *data, struct pt_regs *regs)
232 stat = in_be64(&spu->priv1->int_stat_class2_RW);
234 pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat,
235 in_be64(&spu->priv1->int_mask_class2_RW));
238 if (stat & 1) /* PPC core mailbox */
239 __spu_trap_mailbox(spu);
241 if (stat & 2) /* SPU stop-and-signal */
242 __spu_trap_stop(spu);
244 if (stat & 4) /* SPU halted */
245 __spu_trap_halt(spu);
247 if (stat & 8) /* DMA tag group complete */
248 __spu_trap_tag_group(spu);
250 if (stat & 0x10) /* SPU mailbox threshold */
251 __spu_trap_spubox(spu);
253 out_be64(&spu->priv1->int_stat_class2_RW, stat);
254 return stat ? IRQ_HANDLED : IRQ_NONE;
258 spu_request_irqs(struct spu *spu)
263 irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
265 snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", spu->number);
266 ret = request_irq(irq_base + spu->isrc,
267 spu_irq_class_0, 0, spu->irq_c0, spu);
270 out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
272 snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", spu->number);
273 ret = request_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc,
274 spu_irq_class_1, 0, spu->irq_c1, spu);
277 out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
279 snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", spu->number);
280 ret = request_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc,
281 spu_irq_class_2, 0, spu->irq_c2, spu);
284 out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
288 free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
290 free_irq(irq_base + spu->isrc, spu);
296 spu_free_irqs(struct spu *spu)
300 irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
302 free_irq(irq_base + spu->isrc, spu);
303 free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
304 free_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc, spu);
307 static LIST_HEAD(spu_list);
308 static DECLARE_MUTEX(spu_mutex);
310 static void spu_init_channels(struct spu *spu)
312 static const struct {
316 { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
317 { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
319 { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
320 { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
321 { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
323 struct spu_priv2 *priv2;
328 /* initialize all channel data to zero */
329 for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
332 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
333 for (count = 0; count < zero_list[i].count; count++)
334 out_be64(&priv2->spu_chnldata_RW, 0);
337 /* initialize channel counts to meaningful values */
338 for (i = 0; i < ARRAY_SIZE(count_list); i++) {
339 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
340 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
344 static void spu_init_regs(struct spu *spu)
346 out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
347 out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
348 out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
351 struct spu *spu_alloc(void)
356 if (!list_empty(&spu_list)) {
357 spu = list_entry(spu_list.next, struct spu, list);
358 list_del_init(&spu->list);
359 pr_debug("Got SPU %x %d\n", spu->isrc, spu->number);
361 pr_debug("No SPU left\n");
367 spu_init_channels(spu);
373 EXPORT_SYMBOL(spu_alloc);
375 void spu_free(struct spu *spu)
378 spu->ibox_fasync = NULL;
379 spu->wbox_fasync = NULL;
380 list_add_tail(&spu->list, &spu_list);
383 EXPORT_SYMBOL(spu_free);
385 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
386 static int spu_handle_mm_fault(struct spu *spu)
388 struct spu_priv1 __iomem *priv1;
389 struct mm_struct *mm = spu->mm;
390 struct vm_area_struct *vma;
391 u64 ea, dsisr, is_write;
395 ea = in_be64(&priv1->mfc_dar_RW);
396 dsisr = in_be64(&priv1->mfc_dsisr_RW);
398 if (!IS_VALID_EA(ea)) {
405 if (mm->pgd == NULL) {
409 down_read(&mm->mmap_sem);
410 vma = find_vma(mm, ea);
413 if (vma->vm_start <= ea)
415 if (!(vma->vm_flags & VM_GROWSDOWN))
418 if (expand_stack(vma, ea))
422 is_write = dsisr & MFC_DSISR_ACCESS_PUT;
424 if (!(vma->vm_flags & VM_WRITE))
427 if (dsisr & MFC_DSISR_ACCESS_DENIED)
429 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
433 switch (handle_mm_fault(mm, vma, ea, is_write)) {
440 case VM_FAULT_SIGBUS:
449 up_read(&mm->mmap_sem);
453 up_read(&mm->mmap_sem);
457 static int spu_handle_pte_fault(struct spu *spu)
459 struct spu_priv1 __iomem *priv1;
460 u64 ea, dsisr, access, error = 0UL;
464 ea = in_be64(&priv1->mfc_dar_RW);
465 dsisr = in_be64(&priv1->mfc_dsisr_RW);
466 access = (_PAGE_PRESENT | _PAGE_USER);
467 if (dsisr & MFC_DSISR_PTE_NOT_FOUND) {
468 if (hash_page(ea, access, 0x300) != 0)
469 error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
471 if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) ||
472 (dsisr & MFC_DSISR_ACCESS_DENIED)) {
473 if ((ret = spu_handle_mm_fault(spu)) != 0)
474 error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
476 error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
479 spu_restart_dma(spu);
484 int spu_run(struct spu *spu)
486 struct spu_problem __iomem *prob;
487 struct spu_priv1 __iomem *priv1;
488 struct spu_priv2 __iomem *priv2;
489 unsigned long status;
497 spu->mm = current->mm;
499 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
502 ret = wait_event_interruptible(spu->stop_wq,
503 (!((status = in_be32(&prob->spu_status_R)) & 0x1))
504 || (in_be64(&priv1->mfc_dsisr_RW) & MFC_DSISR_PTE_NOT_FOUND)
505 || spu->class_0_pending);
507 if (status & SPU_STATUS_STOPPED_BY_STOP)
509 else if (status & SPU_STATUS_STOPPED_BY_HALT)
511 else if (in_be64(&priv1->mfc_dsisr_RW) & MFC_DSISR_PTE_NOT_FOUND)
512 ret = spu_handle_pte_fault(spu);
514 if (spu->class_0_pending)
515 spu_irq_class_0_bottom(spu);
517 if (!ret && signal_pending(current))
522 /* Ensure SPU is stopped. */
523 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
525 while (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)
528 out_be64(&priv2->slb_invalidate_all_W, 0);
529 out_be64(&priv1->tlb_invalidate_entry_W, 0UL);
534 /* Check for SPU breakpoint. */
535 if (unlikely(current->ptrace & PT_PTRACED)) {
536 status = in_be32(&prob->spu_status_R);
538 if ((status & SPU_STATUS_STOPPED_BY_STOP)
539 && status >> SPU_STOP_STATUS_SHIFT == 0x3fff) {
540 force_sig(SIGTRAP, current);
547 EXPORT_SYMBOL(spu_run);
549 static void __iomem * __init map_spe_prop(struct device_node *n,
552 struct address_prop {
553 unsigned long address;
555 } __attribute__((packed)) *prop;
560 p = get_property(n, name, &proplen);
561 if (proplen != sizeof (struct address_prop))
566 return ioremap(prop->address, prop->len);
569 static void spu_unmap(struct spu *spu)
573 iounmap(spu->problem);
574 iounmap((u8 __iomem *)spu->local_store);
577 static int __init spu_map_device(struct spu *spu, struct device_node *spe)
583 prop = get_property(spe, "isrc", NULL);
586 spu->isrc = *(unsigned int *)prop;
588 spu->name = get_property(spe, "name", NULL);
592 prop = get_property(spe, "local-store", NULL);
595 spu->local_store_phys = *(unsigned long *)prop;
597 /* we use local store as ram, not io memory */
598 spu->local_store = (void __force *)map_spe_prop(spe, "local-store");
599 if (!spu->local_store)
602 spu->problem= map_spe_prop(spe, "problem");
606 spu->priv1= map_spe_prop(spe, "priv1");
610 spu->priv2= map_spe_prop(spe, "priv2");
622 static int __init find_spu_node_id(struct device_node *spe)
625 struct device_node *cpu;
627 cpu = spe->parent->parent;
628 id = (unsigned int *)get_property(cpu, "node-id", NULL);
633 static int __init create_spu(struct device_node *spe)
640 spu = kmalloc(sizeof (*spu), GFP_KERNEL);
644 ret = spu_map_device(spu, spe);
648 spu->node = find_spu_node_id(spe);
650 spu->slb_replace = 0;
652 spu->class_0_pending = 0;
653 spin_lock_init(&spu->register_lock);
655 out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
656 out_be64(&spu->priv1->mfc_sr1_RW, 0x33);
658 init_waitqueue_head(&spu->stop_wq);
659 init_waitqueue_head(&spu->wbox_wq);
660 init_waitqueue_head(&spu->ibox_wq);
662 spu->ibox_fasync = NULL;
663 spu->wbox_fasync = NULL;
666 spu->number = number++;
667 ret = spu_request_irqs(spu);
671 list_add(&spu->list, &spu_list);
674 pr_debug(KERN_DEBUG "Using SPE %s %02x %p %p %p %p %d\n",
675 spu->name, spu->isrc, spu->local_store,
676 spu->problem, spu->priv1, spu->priv2, spu->number);
688 static void destroy_spu(struct spu *spu)
690 list_del_init(&spu->list);
697 static void cleanup_spu_base(void)
699 struct spu *spu, *tmp;
701 list_for_each_entry_safe(spu, tmp, &spu_list, list)
705 module_exit(cleanup_spu_base);
707 static int __init init_spu_base(void)
709 struct device_node *node;
713 for (node = of_find_node_by_type(NULL, "spe");
714 node; node = of_find_node_by_type(node, "spe")) {
715 ret = create_spu(node);
717 printk(KERN_WARNING "%s: Error initializing %s\n",
718 __FUNCTION__, node->name);
723 /* in some old firmware versions, the spe is called 'spc', so we
724 look for that as well */
725 for (node = of_find_node_by_type(NULL, "spc");
726 node; node = of_find_node_by_type(node, "spc")) {
727 ret = create_spu(node);
729 printk(KERN_WARNING "%s: Error initializing %s\n",
730 __FUNCTION__, node->name);
737 module_init(init_spu_base);
739 MODULE_LICENSE("GPL");
740 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");