arch/mn10300/include/asm/system.h

   1 /* MN10300 System definitions
   2  *
   3  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public Licence
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the Licence, or (at your option) any later version.
  10  */
  11 #ifndef _ASM_SYSTEM_H
  12 #define _ASM_SYSTEM_H
  13
  14 #include <asm/cpu-regs.h>
  15
  16 #ifdef __KERNEL__
  17 #ifndef __ASSEMBLY__
  18
  19 #include <linux/kernel.h>
  20 #include <linux/irqflags.h>
  21
  22 #if !defined(CONFIG_LAZY_SAVE_FPU)
  23 struct fpu_state_struct;
  24 extern asmlinkage void fpu_save(struct fpu_state_struct *);
  25 #define switch_fpu(prev, next)                                          \
  26         do {                                                            \
  27                 if ((prev)->thread.fpu_flags & THREAD_HAS_FPU) {        \
  28                         (prev)->thread.fpu_flags &= ~THREAD_HAS_FPU;    \
  29                         (prev)->thread.uregs->epsw &= ~EPSW_FE;         \
  30                         fpu_save(&(prev)->thread.fpu_state);            \
  31                 }                                                       \
  32         } while (0)
  33 #else
  34 #define switch_fpu(prev, next) do {} while (0)
  35 #endif
  36
  37 struct task_struct;
  38 struct thread_struct;
  39
  40 extern asmlinkage
  41 struct task_struct *__switch_to(struct thread_struct *prev,
  42                                 struct thread_struct *next,
  43                                 struct task_struct *prev_task);
  44
  45 /* context switching is now performed out-of-line in switch_to.S */
  46 #define switch_to(prev, next, last)                                     \
  47 do {                                                                    \
  48         switch_fpu(prev, next);                                         \
  49         current->thread.wchan = (u_long) __builtin_return_address(0);   \
  50         (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
  51         mb();                                                           \
  52         current->thread.wchan = 0;                                      \
  53 } while (0)
  54
  55 #define arch_align_stack(x) (x)
  56
  57 #define nop() asm volatile ("nop")
  58
  59 #endif /* !__ASSEMBLY__ */
  60
  61 /*
  62  * Force strict CPU ordering.
  63  * And yes, this is required on UP too when we're talking
  64  * to devices.
  65  *
  66  * For now, "wmb()" doesn't actually do anything, as all
  67  * Intel CPU's follow what Intel calls a *Processor Order*,
  68  * in which all writes are seen in the program order even
  69  * outside the CPU.
  70  *
  71  * I expect future Intel CPU's to have a weaker ordering,
  72  * but I'd also expect them to finally get their act together
  73  * and add some real memory barriers if so.
  74  *
  75  * Some non intel clones support out of order store. wmb() ceases to be a
  76  * nop for these.
  77  */
  78
  79 #define mb()    asm volatile ("": : :"memory")
  80 #define rmb()   mb()
  81 #define wmb()   asm volatile ("": : :"memory")
  82
  83 #ifdef CONFIG_SMP
  84 #define smp_mb()        mb()
  85 #define smp_rmb()       rmb()
  86 #define smp_wmb()       wmb()
  87 #else
  88 #define smp_mb()        barrier()
  89 #define smp_rmb()       barrier()
  90 #define smp_wmb()       barrier()
  91 #endif
  92
  93 #define set_mb(var, value)  do { var = value;  mb(); } while (0)
  94 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
  95
  96 #define read_barrier_depends()          do {} while (0)
  97 #define smp_read_barrier_depends()      do {} while (0)
  98
  99 /*****************************************************************************/
 100 /*
 101  * MN10300 doesn't actually have an exchange instruction
 102  */
 103 #ifndef __ASSEMBLY__
 104
 105 struct __xchg_dummy { unsigned long a[100]; };
 106 #define __xg(x) ((struct __xchg_dummy *)(x))
 107
 108 static inline
 109 unsigned long __xchg(volatile unsigned long *m, unsigned long val)
 110 {
 111         unsigned long retval;
 112         unsigned long flags;
 113
 114         local_irq_save(flags);
 115         retval = *m;
 116         *m = val;
 117         local_irq_restore(flags);
 118         return retval;
 119 }
 120
 121 #define xchg(ptr, v)                                            \
 122         ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr),    \
 123                                      (unsigned long)(v)))
 124
 125 static inline unsigned long __cmpxchg(volatile unsigned long *m,
 126                                       unsigned long old, unsigned long new)
 127 {
 128         unsigned long retval;
 129         unsigned long flags;
 130
 131         local_irq_save(flags);
 132         retval = *m;
 133         if (retval == old)
 134                 *m = new;
 135         local_irq_restore(flags);
 136         return retval;
 137 }
 138
 139 #define cmpxchg(ptr, o, n)                                      \
 140         ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
 141                                         (unsigned long)(o),     \
 142                                         (unsigned long)(n)))
 143
 144 #endif /* !__ASSEMBLY__ */
 145
 146 #endif /* __KERNEL__ */
 147 #endif /* _ASM_SYSTEM_H */