arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/module.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/system.h>
  26 #include <asm/watch.h>
  27 #include <asm/spram.h>
  28 /*
  29  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  30  * the implementation of the "wait" feature differs between CPU families. This
  31  * points to the function that implements CPU specific wait.
  32  * The wait instruction stops the pipeline and reduces the power consumption of
  33  * the CPU very much.
  34  */
  35 void (*cpu_wait)(void);
  36 EXPORT_SYMBOL(cpu_wait);
  37
  38 static void r3081_wait(void)
  39 {
  40         unsigned long cfg = read_c0_conf();
  41         write_c0_conf(cfg | R30XX_CONF_HALT);
  42 }
  43
  44 static void r39xx_wait(void)
  45 {
  46         local_irq_disable();
  47         if (!need_resched())
  48                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  49         local_irq_enable();
  50 }
  51
  52 extern void r4k_wait(void);
  53
  54 /*
  55  * This variant is preferable as it allows testing need_resched and going to
  56  * sleep depending on the outcome atomically.  Unfortunately the "It is
  57  * implementation-dependent whether the pipeline restarts when a non-enabled
  58  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  59  * using this version a gamble.
  60  */
  61 void r4k_wait_irqoff(void)
  62 {
  63         local_irq_disable();
  64         if (!need_resched())
  65                 __asm__("       .set    push            \n"
  66                         "       .set    mips3           \n"
  67                         "       wait                    \n"
  68                         "       .set    pop             \n");
  69         local_irq_enable();
  70         __asm__("       .globl __pastwait       \n"
  71                 "__pastwait:                    \n");
  72         return;
  73 }
  74
  75 /*
  76  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  77  * have any pending stores when the WAIT instruction is executed.
  78  */
  79 static void rm7k_wait_irqoff(void)
  80 {
  81         local_irq_disable();
  82         if (!need_resched())
  83                 __asm__(
  84                 "       .set    push                                    \n"
  85                 "       .set    mips3                                   \n"
  86                 "       .set    noat                                    \n"
  87                 "       mfc0    $1, $12                                 \n"
  88                 "       sync                                            \n"
  89                 "       mtc0    $1, $12         # stalls until W stage  \n"
  90                 "       wait                                            \n"
  91                 "       mtc0    $1, $12         # stalls until W stage  \n"
  92                 "       .set    pop                                     \n");
  93         local_irq_enable();
  94 }
  95
  96 /*
  97  * The Au1xxx wait is available only if using 32khz counter or
  98  * external timer source, but specifically not CP0 Counter.
  99  * alchemy/common/time.c may override cpu_wait!
 100  */
 101 static void au1k_wait(void)
 102 {
 103         __asm__("       .set    mips3                   \n"
 104                 "       cache   0x14, 0(%0)             \n"
 105                 "       cache   0x14, 32(%0)            \n"
 106                 "       sync                            \n"
 107                 "       nop                             \n"
 108                 "       wait                            \n"
 109                 "       nop                             \n"
 110                 "       nop                             \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       .set    mips0                   \n"
 114                 : : "r" (au1k_wait));
 115 }
 116
 117 static int __initdata nowait;
 118
 119 static int __init wait_disable(char *s)
 120 {
 121         nowait = 1;
 122
 123         return 1;
 124 }
 125
 126 __setup("nowait", wait_disable);
 127
 128 static int __cpuinitdata mips_fpu_disabled;
 129
 130 static int __init fpu_disable(char *s)
 131 {
 132         cpu_data[0].options &= ~MIPS_CPU_FPU;
 133         mips_fpu_disabled = 1;
 134
 135         return 1;
 136 }
 137
 138 __setup("nofpu", fpu_disable);
 139
 140 int __cpuinitdata mips_dsp_disabled;
 141
 142 static int __init dsp_disable(char *s)
 143 {
 144         cpu_data[0].ases &= ~MIPS_ASE_DSP;
 145         mips_dsp_disabled = 1;
 146
 147         return 1;
 148 }
 149
 150 __setup("nodsp", dsp_disable);
 151
 152 void __init check_wait(void)
 153 {
 154         struct cpuinfo_mips *c = &current_cpu_data;
 155
 156         if (nowait) {
 157                 printk("Wait instruction disabled.\n");
 158                 return;
 159         }
 160
 161         switch (c->cputype) {
 162         case CPU_R3081:
 163         case CPU_R3081E:
 164                 cpu_wait = r3081_wait;
 165                 break;
 166         case CPU_TX3927:
 167                 cpu_wait = r39xx_wait;
 168                 break;
 169         case CPU_R4200:
 170 /*      case CPU_R4300: */
 171         case CPU_R4600:
 172         case CPU_R4640:
 173         case CPU_R4650:
 174         case CPU_R4700:
 175         case CPU_R5000:
 176         case CPU_R5500:
 177         case CPU_NEVADA:
 178         case CPU_4KC:
 179         case CPU_4KEC:
 180         case CPU_4KSC:
 181         case CPU_5KC:
 182         case CPU_25KF:
 183         case CPU_PR4450:
 184         case CPU_BMIPS3300:
 185         case CPU_BMIPS4350:
 186         case CPU_BMIPS4380:
 187         case CPU_BMIPS5000:
 188         case CPU_CAVIUM_OCTEON:
 189         case CPU_CAVIUM_OCTEON_PLUS:
 190         case CPU_CAVIUM_OCTEON2:
 191         case CPU_JZRISC:
 192                 cpu_wait = r4k_wait;
 193                 break;
 194
 195         case CPU_RM7000:
 196                 cpu_wait = rm7k_wait_irqoff;
 197                 break;
 198
 199         case CPU_24K:
 200         case CPU_34K:
 201         case CPU_1004K:
 202                 cpu_wait = r4k_wait;
 203                 if (read_c0_config7() & MIPS_CONF7_WII)
 204                         cpu_wait = r4k_wait_irqoff;
 205                 break;
 206
 207         case CPU_74K:
 208                 cpu_wait = r4k_wait;
 209                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 210                         cpu_wait = r4k_wait_irqoff;
 211                 break;
 212
 213         case CPU_TX49XX:
 214                 cpu_wait = r4k_wait_irqoff;
 215                 break;
 216         case CPU_ALCHEMY:
 217                 cpu_wait = au1k_wait;
 218                 break;
 219         case CPU_20KC:
 220                 /*
 221                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 222                  * WAIT on Rev2.0 and Rev3.0 has E16.
 223                  * Rev3.1 WAIT is nop, why bother
 224                  */
 225                 if ((c->processor_id & 0xff) <= 0x64)
 226                         break;
 227
 228                 /*
 229                  * Another rev is incremeting c0_count at a reduced clock
 230                  * rate while in WAIT mode.  So we basically have the choice
 231                  * between using the cp0 timer as clocksource or avoiding
 232                  * the WAIT instruction.  Until more details are known,
 233                  * disable the use of WAIT for 20Kc entirely.
 234                    cpu_wait = r4k_wait;
 235                  */
 236                 break;
 237         case CPU_RM9000:
 238                 if ((c->processor_id & 0x00ff) >= 0x40)
 239                         cpu_wait = r4k_wait;
 240                 break;
 241         default:
 242                 break;
 243         }
 244 }
 245
 246 static inline void check_errata(void)
 247 {
 248         struct cpuinfo_mips *c = &current_cpu_data;
 249
 250         switch (c->cputype) {
 251         case CPU_34K:
 252                 /*
 253                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 254                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 255                  * making use of VPE1 will be responsable for that VPE.
 256                  */
 257                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 258                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 259                 break;
 260         default:
 261                 break;
 262         }
 263 }
 264
 265 void __init check_bugs32(void)
 266 {
 267         check_errata();
 268 }
 269
 270 /*
 271  * Probe whether cpu has config register by trying to play with
 272  * alternate cache bit and see whether it matters.
 273  * It's used by cpu_probe to distinguish between R3000A and R3081.
 274  */
 275 static inline int cpu_has_confreg(void)
 276 {
 277 #ifdef CONFIG_CPU_R3000
 278         extern unsigned long r3k_cache_size(unsigned long);
 279         unsigned long size1, size2;
 280         unsigned long cfg = read_c0_conf();
 281
 282         size1 = r3k_cache_size(ST0_ISC);
 283         write_c0_conf(cfg ^ R30XX_CONF_AC);
 284         size2 = r3k_cache_size(ST0_ISC);
 285         write_c0_conf(cfg);
 286         return size1 != size2;
 287 #else
 288         return 0;
 289 #endif
 290 }
 291
 292 /*
 293  * Get the FPU Implementation/Revision.
 294  */
 295 static inline unsigned long cpu_get_fpu_id(void)
 296 {
 297         unsigned long tmp, fpu_id;
 298
 299         tmp = read_c0_status();
 300         __enable_fpu();
 301         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 302         write_c0_status(tmp);
 303         return fpu_id;
 304 }
 305
 306 /*
 307  * Check the CPU has an FPU the official way.
 308  */
 309 static inline int __cpu_has_fpu(void)
 310 {
 311         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 312 }
 313
 314 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 315 {
 316 #ifdef __NEED_VMBITS_PROBE
 317         write_c0_entryhi(0x3fffffffffffe000ULL);
 318         back_to_back_c0_hazard();
 319         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 320 #endif
 321 }
 322
 323 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 324                 | MIPS_CPU_COUNTER)
 325
 326 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 327 {
 328         switch (c->processor_id & 0xff00) {
 329         case PRID_IMP_R2000:
 330                 c->cputype = CPU_R2000;
 331                 __cpu_name[cpu] = "R2000";
 332                 c->isa_level = MIPS_CPU_ISA_I;
 333                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 334                              MIPS_CPU_NOFPUEX;
 335                 if (__cpu_has_fpu())
 336                         c->options |= MIPS_CPU_FPU;
 337                 c->tlbsize = 64;
 338                 break;
 339         case PRID_IMP_R3000:
 340                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 341                         if (cpu_has_confreg()) {
 342                                 c->cputype = CPU_R3081E;
 343                                 __cpu_name[cpu] = "R3081";
 344                         } else {
 345                                 c->cputype = CPU_R3000A;
 346                                 __cpu_name[cpu] = "R3000A";
 347                         }
 348                         break;
 349                 } else {
 350                         c->cputype = CPU_R3000;
 351                         __cpu_name[cpu] = "R3000";
 352                 }
 353                 c->isa_level = MIPS_CPU_ISA_I;
 354                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 355                              MIPS_CPU_NOFPUEX;
 356                 if (__cpu_has_fpu())
 357                         c->options |= MIPS_CPU_FPU;
 358                 c->tlbsize = 64;
 359                 break;
 360         case PRID_IMP_R4000:
 361                 if (read_c0_config() & CONF_SC) {
 362                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 363                                 c->cputype = CPU_R4400PC;
 364                                 __cpu_name[cpu] = "R4400PC";
 365                         } else {
 366                                 c->cputype = CPU_R4000PC;
 367                                 __cpu_name[cpu] = "R4000PC";
 368                         }
 369                 } else {
 370                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 371                                 c->cputype = CPU_R4400SC;
 372                                 __cpu_name[cpu] = "R4400SC";
 373                         } else {
 374                                 c->cputype = CPU_R4000SC;
 375                                 __cpu_name[cpu] = "R4000SC";
 376                         }
 377                 }
 378
 379                 c->isa_level = MIPS_CPU_ISA_III;
 380                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 381                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 382                              MIPS_CPU_LLSC;
 383                 c->tlbsize = 48;
 384                 break;
 385         case PRID_IMP_VR41XX:
 386                 switch (c->processor_id & 0xf0) {
 387                 case PRID_REV_VR4111:
 388                         c->cputype = CPU_VR4111;
 389                         __cpu_name[cpu] = "NEC VR4111";
 390                         break;
 391                 case PRID_REV_VR4121:
 392                         c->cputype = CPU_VR4121;
 393                         __cpu_name[cpu] = "NEC VR4121";
 394                         break;
 395                 case PRID_REV_VR4122:
 396                         if ((c->processor_id & 0xf) < 0x3) {
 397                                 c->cputype = CPU_VR4122;
 398                                 __cpu_name[cpu] = "NEC VR4122";
 399                         } else {
 400                                 c->cputype = CPU_VR4181A;
 401                                 __cpu_name[cpu] = "NEC VR4181A";
 402                         }
 403                         break;
 404                 case PRID_REV_VR4130:
 405                         if ((c->processor_id & 0xf) < 0x4) {
 406                                 c->cputype = CPU_VR4131;
 407                                 __cpu_name[cpu] = "NEC VR4131";
 408                         } else {
 409                                 c->cputype = CPU_VR4133;
 410                                 __cpu_name[cpu] = "NEC VR4133";
 411                         }
 412                         break;
 413                 default:
 414                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 415                         c->cputype = CPU_VR41XX;
 416                         __cpu_name[cpu] = "NEC Vr41xx";
 417                         break;
 418                 }
 419                 c->isa_level = MIPS_CPU_ISA_III;
 420                 c->options = R4K_OPTS;
 421                 c->tlbsize = 32;
 422                 break;
 423         case PRID_IMP_R4300:
 424                 c->cputype = CPU_R4300;
 425                 __cpu_name[cpu] = "R4300";
 426                 c->isa_level = MIPS_CPU_ISA_III;
 427                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 428                              MIPS_CPU_LLSC;
 429                 c->tlbsize = 32;
 430                 break;
 431         case PRID_IMP_R4600:
 432                 c->cputype = CPU_R4600;
 433                 __cpu_name[cpu] = "R4600";
 434                 c->isa_level = MIPS_CPU_ISA_III;
 435                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 436                              MIPS_CPU_LLSC;
 437                 c->tlbsize = 48;
 438                 break;
 439         #if 0
 440         case PRID_IMP_R4650:
 441                 /*
 442                  * This processor doesn't have an MMU, so it's not
 443                  * "real easy" to run Linux on it. It is left purely
 444                  * for documentation.  Commented out because it shares
 445                  * it's c0_prid id number with the TX3900.
 446                  */
 447                 c->cputype = CPU_R4650;
 448                 __cpu_name[cpu] = "R4650";
 449                 c->isa_level = MIPS_CPU_ISA_III;
 450                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 451                 c->tlbsize = 48;
 452                 break;
 453         #endif
 454         case PRID_IMP_TX39:
 455                 c->isa_level = MIPS_CPU_ISA_I;
 456                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 457
 458                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 459                         c->cputype = CPU_TX3927;
 460                         __cpu_name[cpu] = "TX3927";
 461                         c->tlbsize = 64;
 462                 } else {
 463                         switch (c->processor_id & 0xff) {
 464                         case PRID_REV_TX3912:
 465                                 c->cputype = CPU_TX3912;
 466                                 __cpu_name[cpu] = "TX3912";
 467                                 c->tlbsize = 32;
 468                                 break;
 469                         case PRID_REV_TX3922:
 470                                 c->cputype = CPU_TX3922;
 471                                 __cpu_name[cpu] = "TX3922";
 472                                 c->tlbsize = 64;
 473                                 break;
 474                         }
 475                 }
 476                 break;
 477         case PRID_IMP_R4700:
 478                 c->cputype = CPU_R4700;
 479                 __cpu_name[cpu] = "R4700";
 480                 c->isa_level = MIPS_CPU_ISA_III;
 481                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 482                              MIPS_CPU_LLSC;
 483                 c->tlbsize = 48;
 484                 break;
 485         case PRID_IMP_TX49:
 486                 c->cputype = CPU_TX49XX;
 487                 __cpu_name[cpu] = "R49XX";
 488                 c->isa_level = MIPS_CPU_ISA_III;
 489                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 490                 if (!(c->processor_id & 0x08))
 491                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 492                 c->tlbsize = 48;
 493                 break;
 494         case PRID_IMP_R5000:
 495                 c->cputype = CPU_R5000;
 496                 __cpu_name[cpu] = "R5000";
 497                 c->isa_level = MIPS_CPU_ISA_IV;
 498                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 499                              MIPS_CPU_LLSC;
 500                 c->tlbsize = 48;
 501                 break;
 502         case PRID_IMP_R5432:
 503                 c->cputype = CPU_R5432;
 504                 __cpu_name[cpu] = "R5432";
 505                 c->isa_level = MIPS_CPU_ISA_IV;
 506                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 507                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 508                 c->tlbsize = 48;
 509                 break;
 510         case PRID_IMP_R5500:
 511                 c->cputype = CPU_R5500;
 512                 __cpu_name[cpu] = "R5500";
 513                 c->isa_level = MIPS_CPU_ISA_IV;
 514                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 515                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 516                 c->tlbsize = 48;
 517                 break;
 518         case PRID_IMP_NEVADA:
 519                 c->cputype = CPU_NEVADA;
 520                 __cpu_name[cpu] = "Nevada";
 521                 c->isa_level = MIPS_CPU_ISA_IV;
 522                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 523                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 524                 c->tlbsize = 48;
 525                 break;
 526         case PRID_IMP_R6000:
 527                 c->cputype = CPU_R6000;
 528                 __cpu_name[cpu] = "R6000";
 529                 c->isa_level = MIPS_CPU_ISA_II;
 530                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 531                              MIPS_CPU_LLSC;
 532                 c->tlbsize = 32;
 533                 break;
 534         case PRID_IMP_R6000A:
 535                 c->cputype = CPU_R6000A;
 536                 __cpu_name[cpu] = "R6000A";
 537                 c->isa_level = MIPS_CPU_ISA_II;
 538                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 539                              MIPS_CPU_LLSC;
 540                 c->tlbsize = 32;
 541                 break;
 542         case PRID_IMP_RM7000:
 543                 c->cputype = CPU_RM7000;
 544                 __cpu_name[cpu] = "RM7000";
 545                 c->isa_level = MIPS_CPU_ISA_IV;
 546                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 547                              MIPS_CPU_LLSC;
 548                 /*
 549                  * Undocumented RM7000:  Bit 29 in the info register of
 550                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 551                  * entries.
 552                  *
 553                  * 29      1 =>    64 entry JTLB
 554                  *         0 =>    48 entry JTLB
 555                  */
 556                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 557                 break;
 558         case PRID_IMP_RM9000:
 559                 c->cputype = CPU_RM9000;
 560                 __cpu_name[cpu] = "RM9000";
 561                 c->isa_level = MIPS_CPU_ISA_IV;
 562                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 563                              MIPS_CPU_LLSC;
 564                 /*
 565                  * Bit 29 in the info register of the RM9000
 566                  * indicates if the TLB has 48 or 64 entries.
 567                  *
 568                  * 29      1 =>    64 entry JTLB
 569                  *         0 =>    48 entry JTLB
 570                  */
 571                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 572                 break;
 573         case PRID_IMP_R8000:
 574                 c->cputype = CPU_R8000;
 575                 __cpu_name[cpu] = "RM8000";
 576                 c->isa_level = MIPS_CPU_ISA_IV;
 577                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 578                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 579                              MIPS_CPU_LLSC;
 580                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 581                 break;
 582         case PRID_IMP_R10000:
 583                 c->cputype = CPU_R10000;
 584                 __cpu_name[cpu] = "R10000";
 585                 c->isa_level = MIPS_CPU_ISA_IV;
 586                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 587                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 588                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 589                              MIPS_CPU_LLSC;
 590                 c->tlbsize = 64;
 591                 break;
 592         case PRID_IMP_R12000:
 593                 c->cputype = CPU_R12000;
 594                 __cpu_name[cpu] = "R12000";
 595                 c->isa_level = MIPS_CPU_ISA_IV;
 596                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 597                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 598                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 599                              MIPS_CPU_LLSC;
 600                 c->tlbsize = 64;
 601                 break;
 602         case PRID_IMP_R14000:
 603                 c->cputype = CPU_R14000;
 604                 __cpu_name[cpu] = "R14000";
 605                 c->isa_level = MIPS_CPU_ISA_IV;
 606                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 607                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 608                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 609                              MIPS_CPU_LLSC;
 610                 c->tlbsize = 64;
 611                 break;
 612         case PRID_IMP_LOONGSON2:
 613                 c->cputype = CPU_LOONGSON2;
 614                 __cpu_name[cpu] = "ICT Loongson-2";
 615                 c->isa_level = MIPS_CPU_ISA_III;
 616                 c->options = R4K_OPTS |
 617                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 618                              MIPS_CPU_32FPR;
 619                 c->tlbsize = 64;
 620                 break;
 621         }
 622 }
 623
 624 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 625         "Unsupported ISA type, c0.config0: %d.";
 626
 627 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 628 {
 629         unsigned int config0;
 630         int isa;
 631
 632         config0 = read_c0_config();
 633
 634         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 635                 c->options |= MIPS_CPU_TLB;
 636         isa = (config0 & MIPS_CONF_AT) >> 13;
 637         switch (isa) {
 638         case 0:
 639                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 640                 case 0:
 641                         c->isa_level = MIPS_CPU_ISA_M32R1;
 642                         break;
 643                 case 1:
 644                         c->isa_level = MIPS_CPU_ISA_M32R2;
 645                         break;
 646                 default:
 647                         goto unknown;
 648                 }
 649                 break;
 650         case 2:
 651                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 652                 case 0:
 653                         c->isa_level = MIPS_CPU_ISA_M64R1;
 654                         break;
 655                 case 1:
 656                         c->isa_level = MIPS_CPU_ISA_M64R2;
 657                         break;
 658                 default:
 659                         goto unknown;
 660                 }
 661                 break;
 662         default:
 663                 goto unknown;
 664         }
 665
 666         return config0 & MIPS_CONF_M;
 667
 668 unknown:
 669         panic(unknown_isa, config0);
 670 }
 671
 672 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 673 {
 674         unsigned int config1;
 675
 676         config1 = read_c0_config1();
 677
 678         if (config1 & MIPS_CONF1_MD)
 679                 c->ases |= MIPS_ASE_MDMX;
 680         if (config1 & MIPS_CONF1_WR)
 681                 c->options |= MIPS_CPU_WATCH;
 682         if (config1 & MIPS_CONF1_CA)
 683                 c->ases |= MIPS_ASE_MIPS16;
 684         if (config1 & MIPS_CONF1_EP)
 685                 c->options |= MIPS_CPU_EJTAG;
 686         if (config1 & MIPS_CONF1_FP) {
 687                 c->options |= MIPS_CPU_FPU;
 688                 c->options |= MIPS_CPU_32FPR;
 689         }
 690         if (cpu_has_tlb)
 691                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 692
 693         return config1 & MIPS_CONF_M;
 694 }
 695
 696 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 697 {
 698         unsigned int config2;
 699
 700         config2 = read_c0_config2();
 701
 702         if (config2 & MIPS_CONF2_SL)
 703                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 704
 705         return config2 & MIPS_CONF_M;
 706 }
 707
 708 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 709 {
 710         unsigned int config3;
 711
 712         config3 = read_c0_config3();
 713
 714         if (config3 & MIPS_CONF3_SM)
 715                 c->ases |= MIPS_ASE_SMARTMIPS;
 716         if (config3 & MIPS_CONF3_DSP)
 717                 c->ases |= MIPS_ASE_DSP;
 718         if (config3 & MIPS_CONF3_VINT)
 719                 c->options |= MIPS_CPU_VINT;
 720         if (config3 & MIPS_CONF3_VEIC)
 721                 c->options |= MIPS_CPU_VEIC;
 722         if (config3 & MIPS_CONF3_MT)
 723                 c->ases |= MIPS_ASE_MIPSMT;
 724         if (config3 & MIPS_CONF3_ULRI)
 725                 c->options |= MIPS_CPU_ULRI;
 726
 727         return config3 & MIPS_CONF_M;
 728 }
 729
 730 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 731 {
 732         unsigned int config4;
 733
 734         config4 = read_c0_config4();
 735
 736         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 737             && cpu_has_tlb)
 738                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 739
 740         return config4 & MIPS_CONF_M;
 741 }
 742
 743 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 744 {
 745         int ok;
 746
 747         /* MIPS32 or MIPS64 compliant CPU.  */
 748         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 749                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 750
 751         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 752
 753         ok = decode_config0(c);                 /* Read Config registers.  */
 754         BUG_ON(!ok);                            /* Arch spec violation!  */
 755         if (ok)
 756                 ok = decode_config1(c);
 757         if (ok)
 758                 ok = decode_config2(c);
 759         if (ok)
 760                 ok = decode_config3(c);
 761         if (ok)
 762                 ok = decode_config4(c);
 763
 764         mips_probe_watch_registers(c);
 765
 766         if (cpu_has_mips_r2)
 767                 c->core = read_c0_ebase() & 0x3ff;
 768 }
 769
 770 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 771 {
 772         decode_configs(c);
 773         switch (c->processor_id & 0xff00) {
 774         case PRID_IMP_4KC:
 775                 c->cputype = CPU_4KC;
 776                 __cpu_name[cpu] = "MIPS 4Kc";
 777                 break;
 778         case PRID_IMP_4KEC:
 779         case PRID_IMP_4KECR2:
 780                 c->cputype = CPU_4KEC;
 781                 __cpu_name[cpu] = "MIPS 4KEc";
 782                 break;
 783         case PRID_IMP_4KSC:
 784         case PRID_IMP_4KSD:
 785                 c->cputype = CPU_4KSC;
 786                 __cpu_name[cpu] = "MIPS 4KSc";
 787                 break;
 788         case PRID_IMP_5KC:
 789                 c->cputype = CPU_5KC;
 790                 __cpu_name[cpu] = "MIPS 5Kc";
 791                 break;
 792         case PRID_IMP_20KC:
 793                 c->cputype = CPU_20KC;
 794                 __cpu_name[cpu] = "MIPS 20Kc";
 795                 break;
 796         case PRID_IMP_24K:
 797         case PRID_IMP_24KE:
 798                 c->cputype = CPU_24K;
 799                 __cpu_name[cpu] = "MIPS 24Kc";
 800                 break;
 801         case PRID_IMP_25KF:
 802                 c->cputype = CPU_25KF;
 803                 __cpu_name[cpu] = "MIPS 25Kc";
 804                 break;
 805         case PRID_IMP_34K:
 806                 c->cputype = CPU_34K;
 807                 __cpu_name[cpu] = "MIPS 34Kc";
 808                 break;
 809         case PRID_IMP_74K:
 810                 c->cputype = CPU_74K;
 811                 __cpu_name[cpu] = "MIPS 74Kc";
 812                 break;
 813         case PRID_IMP_1004K:
 814                 c->cputype = CPU_1004K;
 815                 __cpu_name[cpu] = "MIPS 1004Kc";
 816                 break;
 817         }
 818
 819         spram_config();
 820 }
 821
 822 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 823 {
 824         decode_configs(c);
 825         switch (c->processor_id & 0xff00) {
 826         case PRID_IMP_AU1_REV1:
 827         case PRID_IMP_AU1_REV2:
 828                 c->cputype = CPU_ALCHEMY;
 829                 switch ((c->processor_id >> 24) & 0xff) {
 830                 case 0:
 831                         __cpu_name[cpu] = "Au1000";
 832                         break;
 833                 case 1:
 834                         __cpu_name[cpu] = "Au1500";
 835                         break;
 836                 case 2:
 837                         __cpu_name[cpu] = "Au1100";
 838                         break;
 839                 case 3:
 840                         __cpu_name[cpu] = "Au1550";
 841                         break;
 842                 case 4:
 843                         __cpu_name[cpu] = "Au1200";
 844                         if ((c->processor_id & 0xff) == 2)
 845                                 __cpu_name[cpu] = "Au1250";
 846                         break;
 847                 case 5:
 848                         __cpu_name[cpu] = "Au1210";
 849                         break;
 850                 default:
 851                         __cpu_name[cpu] = "Au1xxx";
 852                         break;
 853                 }
 854                 break;
 855         }
 856 }
 857
 858 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 859 {
 860         decode_configs(c);
 861
 862         switch (c->processor_id & 0xff00) {
 863         case PRID_IMP_SB1:
 864                 c->cputype = CPU_SB1;
 865                 __cpu_name[cpu] = "SiByte SB1";
 866                 /* FPU in pass1 is known to have issues. */
 867                 if ((c->processor_id & 0xff) < 0x02)
 868                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 869                 break;
 870         case PRID_IMP_SB1A:
 871                 c->cputype = CPU_SB1A;
 872                 __cpu_name[cpu] = "SiByte SB1A";
 873                 break;
 874         }
 875 }
 876
 877 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 878 {
 879         decode_configs(c);
 880         switch (c->processor_id & 0xff00) {
 881         case PRID_IMP_SR71000:
 882                 c->cputype = CPU_SR71000;
 883                 __cpu_name[cpu] = "Sandcraft SR71000";
 884                 c->scache.ways = 8;
 885                 c->tlbsize = 64;
 886                 break;
 887         }
 888 }
 889
 890 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 891 {
 892         decode_configs(c);
 893         switch (c->processor_id & 0xff00) {
 894         case PRID_IMP_PR4450:
 895                 c->cputype = CPU_PR4450;
 896                 __cpu_name[cpu] = "Philips PR4450";
 897                 c->isa_level = MIPS_CPU_ISA_M32R1;
 898                 break;
 899         }
 900 }
 901
 902 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 903 {
 904         decode_configs(c);
 905         switch (c->processor_id & 0xff00) {
 906         case PRID_IMP_BMIPS32:
 907                 c->cputype = CPU_BMIPS32;
 908                 __cpu_name[cpu] = "Broadcom BMIPS32";
 909                 break;
 910         case PRID_IMP_BMIPS3300:
 911         case PRID_IMP_BMIPS3300_ALT:
 912         case PRID_IMP_BMIPS3300_BUG:
 913                 c->cputype = CPU_BMIPS3300;
 914                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 915                 break;
 916         case PRID_IMP_BMIPS43XX: {
 917                 int rev = c->processor_id & 0xff;
 918
 919                 if (rev >= PRID_REV_BMIPS4380_LO &&
 920                                 rev <= PRID_REV_BMIPS4380_HI) {
 921                         c->cputype = CPU_BMIPS4380;
 922                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 923                 } else {
 924                         c->cputype = CPU_BMIPS4350;
 925                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 926                 }
 927                 break;
 928         }
 929         case PRID_IMP_BMIPS5000:
 930                 c->cputype = CPU_BMIPS5000;
 931                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 932                 c->options |= MIPS_CPU_ULRI;
 933                 break;
 934         case PRID_IMP_BMIPS4KC:
 935                 c->cputype = CPU_4KC;
 936                 __cpu_name[cpu] = "MIPS 4Kc";
 937                 break;
 938         }
 939 }
 940
 941 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 942 {
 943         decode_configs(c);
 944         switch (c->processor_id & 0xff00) {
 945         case PRID_IMP_CAVIUM_CN38XX:
 946         case PRID_IMP_CAVIUM_CN31XX:
 947         case PRID_IMP_CAVIUM_CN30XX:
 948                 c->cputype = CPU_CAVIUM_OCTEON;
 949                 __cpu_name[cpu] = "Cavium Octeon";
 950                 goto platform;
 951         case PRID_IMP_CAVIUM_CN58XX:
 952         case PRID_IMP_CAVIUM_CN56XX:
 953         case PRID_IMP_CAVIUM_CN50XX:
 954         case PRID_IMP_CAVIUM_CN52XX:
 955                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 956                 __cpu_name[cpu] = "Cavium Octeon+";
 957 platform:
 958                 if (cpu == 0)
 959                         __elf_platform = "octeon";
 960                 break;
 961         case PRID_IMP_CAVIUM_CN63XX:
 962                 c->cputype = CPU_CAVIUM_OCTEON2;
 963                 __cpu_name[cpu] = "Cavium Octeon II";
 964                 if (cpu == 0)
 965                         __elf_platform = "octeon2";
 966                 break;
 967         default:
 968                 printk(KERN_INFO "Unknown Octeon chip!\n");
 969                 c->cputype = CPU_UNKNOWN;
 970                 break;
 971         }
 972 }
 973
 974 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 975 {
 976         decode_configs(c);
 977         /* JZRISC does not implement the CP0 counter. */
 978         c->options &= ~MIPS_CPU_COUNTER;
 979         switch (c->processor_id & 0xff00) {
 980         case PRID_IMP_JZRISC:
 981                 c->cputype = CPU_JZRISC;
 982                 __cpu_name[cpu] = "Ingenic JZRISC";
 983                 break;
 984         default:
 985                 panic("Unknown Ingenic Processor ID!");
 986                 break;
 987         }
 988 }
 989
 990 const char *__cpu_name[NR_CPUS];
 991 const char *__elf_platform;
 992
 993 __cpuinit void cpu_probe(void)
 994 {
 995         struct cpuinfo_mips *c = &current_cpu_data;
 996         unsigned int cpu = smp_processor_id();
 997
 998         c->processor_id = PRID_IMP_UNKNOWN;
 999         c->fpu_id       = FPIR_IMP_NONE;
1000         c->cputype      = CPU_UNKNOWN;
1001
1002         c->processor_id = read_c0_prid();
1003         switch (c->processor_id & 0xff0000) {
1004         case PRID_COMP_LEGACY:
1005                 cpu_probe_legacy(c, cpu);
1006                 break;
1007         case PRID_COMP_MIPS:
1008                 cpu_probe_mips(c, cpu);
1009                 break;
1010         case PRID_COMP_ALCHEMY:
1011                 cpu_probe_alchemy(c, cpu);
1012                 break;
1013         case PRID_COMP_SIBYTE:
1014                 cpu_probe_sibyte(c, cpu);
1015                 break;
1016         case PRID_COMP_BROADCOM:
1017                 cpu_probe_broadcom(c, cpu);
1018                 break;
1019         case PRID_COMP_SANDCRAFT:
1020                 cpu_probe_sandcraft(c, cpu);
1021                 break;
1022         case PRID_COMP_NXP:
1023                 cpu_probe_nxp(c, cpu);
1024                 break;
1025         case PRID_COMP_CAVIUM:
1026                 cpu_probe_cavium(c, cpu);
1027                 break;
1028         case PRID_COMP_INGENIC:
1029                 cpu_probe_ingenic(c, cpu);
1030                 break;
1031         }
1032
1033         BUG_ON(!__cpu_name[cpu]);
1034         BUG_ON(c->cputype == CPU_UNKNOWN);
1035
1036         /*
1037          * Platform code can force the cpu type to optimize code
1038          * generation. In that case be sure the cpu type is correctly
1039          * manually setup otherwise it could trigger some nasty bugs.
1040          */
1041         BUG_ON(current_cpu_type() != c->cputype);
1042
1043         if (mips_fpu_disabled)
1044                 c->options &= ~MIPS_CPU_FPU;
1045
1046         if (mips_dsp_disabled)
1047                 c->ases &= ~MIPS_ASE_DSP;
1048
1049         if (c->options & MIPS_CPU_FPU) {
1050                 c->fpu_id = cpu_get_fpu_id();
1051
1052                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1053                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1054                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1055                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1056                         if (c->fpu_id & MIPS_FPIR_3D)
1057                                 c->ases |= MIPS_ASE_MIPS3D;
1058                 }
1059         }
1060
1061         if (cpu_has_mips_r2)
1062                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1063         else
1064                 c->srsets = 1;
1065
1066         cpu_probe_vmbits(c);
1067 }
1068
1069 __cpuinit void cpu_report(void)
1070 {
1071         struct cpuinfo_mips *c = &current_cpu_data;
1072
1073         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1074                c->processor_id, cpu_name_string());
1075         if (c->options & MIPS_CPU_FPU)
1076                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1077 }