arch/mips/cavium-octeon/smp.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
   7  */
   8 #include <linux/cpu.h>
   9 #include <linux/init.h>
  10 #include <linux/delay.h>
  11 #include <linux/smp.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/sched.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mmu_context.h>
  18 #include <asm/system.h>
  19 #include <asm/time.h>
  20
  21 #include <asm/octeon/octeon.h>
  22
  23 #include "octeon_boot.h"
  24
  25 volatile unsigned long octeon_processor_boot = 0xff;
  26 volatile unsigned long octeon_processor_sp;
  27 volatile unsigned long octeon_processor_gp;
  28
  29 #ifdef CONFIG_HOTPLUG_CPU
  30 static unsigned int InitTLBStart_addr;
  31 #endif
  32
  33 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
  34 {
  35         const int coreid = cvmx_get_core_num();
  36         uint64_t action;
  37
  38         /* Load the mailbox register to figure out what we're supposed to do */
  39         action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));
  40
  41         /* Clear the mailbox to clear the interrupt */
  42         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
  43
  44         if (action & SMP_CALL_FUNCTION)
  45                 smp_call_function_interrupt();
  46
  47         /* Check if we've been told to flush the icache */
  48         if (action & SMP_ICACHE_FLUSH)
  49                 asm volatile ("synci 0($0)\n");
  50         return IRQ_HANDLED;
  51 }
  52
  53 /**
  54  * Cause the function described by call_data to be executed on the passed
  55  * cpu.  When the function has finished, increment the finished field of
  56  * call_data.
  57  */
  58 void octeon_send_ipi_single(int cpu, unsigned int action)
  59 {
  60         int coreid = cpu_logical_map(cpu);
  61         /*
  62         pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
  63                coreid, action);
  64         */
  65         cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
  66 }
  67
  68 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
  69                                         unsigned int action)
  70 {
  71         unsigned int i;
  72
  73         for_each_cpu_mask(i, *mask)
  74                 octeon_send_ipi_single(i, action);
  75 }
  76
  77 /**
  78  * Detect available CPUs, populate cpu_possible_map
  79  */
  80 static void octeon_smp_hotplug_setup(void)
  81 {
  82 #ifdef CONFIG_HOTPLUG_CPU
  83         uint32_t labi_signature;
  84
  85         labi_signature =
  86                 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
  87                                         LABI_ADDR_IN_BOOTLOADER +
  88                                         offsetof(struct linux_app_boot_info,
  89                                                     labi_signature)));
  90         if (labi_signature != LABI_SIGNATURE)
  91                 pr_err("The bootloader version on this board is incorrect\n");
  92         InitTLBStart_addr =
  93                 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
  94                                    LABI_ADDR_IN_BOOTLOADER +
  95                                            offsetof(struct linux_app_boot_info,
  96                                                     InitTLBStart_addr)));
  97 #endif
  98 }
  99
 100 static void octeon_smp_setup(void)
 101 {
 102         const int coreid = cvmx_get_core_num();
 103         int cpus;
 104         int id;
 105         int core_mask = octeon_get_boot_coremask();
 106 #ifdef CONFIG_HOTPLUG_CPU
 107         unsigned int num_cores = cvmx_octeon_num_cores();
 108 #endif
 109
 110         /* The present CPUs are initially just the boot cpu (CPU 0). */
 111         for (id = 0; id < NR_CPUS; id++) {
 112                 set_cpu_possible(id, id == 0);
 113                 set_cpu_present(id, id == 0);
 114         }
 115
 116         __cpu_number_map[coreid] = 0;
 117         __cpu_logical_map[0] = coreid;
 118
 119         /* The present CPUs get the lowest CPU numbers. */
 120         cpus = 1;
 121         for (id = 0; id < NR_CPUS; id++) {
 122                 if ((id != coreid) && (core_mask & (1 << id))) {
 123                         set_cpu_possible(cpus, true);
 124                         set_cpu_present(cpus, true);
 125                         __cpu_number_map[id] = cpus;
 126                         __cpu_logical_map[cpus] = id;
 127                         cpus++;
 128                 }
 129         }
 130
 131 #ifdef CONFIG_HOTPLUG_CPU
 132         /*
 133          * The possible CPUs are all those present on the chip.  We
 134          * will assign CPU numbers for possible cores as well.  Cores
 135          * are always consecutively numberd from 0.
 136          */
 137         for (id = 0; id < num_cores && id < NR_CPUS; id++) {
 138                 if (!(core_mask & (1 << id))) {
 139                         set_cpu_possible(cpus, true);
 140                         __cpu_number_map[id] = cpus;
 141                         __cpu_logical_map[cpus] = id;
 142                         cpus++;
 143                 }
 144         }
 145 #endif
 146
 147         octeon_smp_hotplug_setup();
 148 }
 149
 150 /**
 151  * Firmware CPU startup hook
 152  *
 153  */
 154 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
 155 {
 156         int count;
 157
 158         pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
 159                 cpu_logical_map(cpu));
 160
 161         octeon_processor_sp = __KSTK_TOS(idle);
 162         octeon_processor_gp = (unsigned long)(task_thread_info(idle));
 163         octeon_processor_boot = cpu_logical_map(cpu);
 164         mb();
 165
 166         count = 10000;
 167         while (octeon_processor_sp && count) {
 168                 /* Waiting for processor to get the SP and GP */
 169                 udelay(1);
 170                 count--;
 171         }
 172         if (count == 0)
 173                 pr_err("Secondary boot timeout\n");
 174 }
 175
 176 /**
 177  * After we've done initial boot, this function is called to allow the
 178  * board code to clean up state, if needed
 179  */
 180 static void octeon_init_secondary(void)
 181 {
 182         const int coreid = cvmx_get_core_num();
 183         union cvmx_ciu_intx_sum0 interrupt_enable;
 184
 185 #ifdef CONFIG_HOTPLUG_CPU
 186         unsigned int cur_exception_base;
 187
 188         cur_exception_base = cvmx_read64_uint32(
 189                 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 190                              LABI_ADDR_IN_BOOTLOADER +
 191                              offsetof(struct linux_app_boot_info,
 192                                       cur_exception_base)));
 193         /* cur_exception_base is incremented in bootloader after setting */
 194         write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
 195 #endif
 196         octeon_check_cpu_bist();
 197         octeon_init_cvmcount();
 198         /*
 199         pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
 200         */
 201         /* Enable Mailbox interrupts to this core. These are the only
 202            interrupts allowed on line 3 */
 203         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
 204         interrupt_enable.u64 = 0;
 205         interrupt_enable.s.mbox = 0x3;
 206         cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
 207         cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
 208         cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
 209         cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
 210         /* Enable core interrupt processing for 2,3 and 7 */
 211         set_c0_status(0x8c01);
 212 }
 213
 214 /**
 215  * Callout to firmware before smp_init
 216  *
 217  */
 218 void octeon_prepare_cpus(unsigned int max_cpus)
 219 {
 220         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
 221         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
 222                         "mailbox0", mailbox_interrupt)) {
 223                 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
 224         }
 225         if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
 226                         "mailbox1", mailbox_interrupt)) {
 227                 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
 228         }
 229 }
 230
 231 /**
 232  * Last chance for the board code to finish SMP initialization before
 233  * the CPU is "online".
 234  */
 235 static void octeon_smp_finish(void)
 236 {
 237 #ifdef CONFIG_CAVIUM_GDB
 238         unsigned long tmp;
 239         /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
 240            to be not masked by this core so we know the signal is received by
 241            someone */
 242         asm volatile ("dmfc0 %0, $22\n"
 243                       "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
 244 #endif
 245
 246         octeon_user_io_init();
 247
 248         /* to generate the first CPU timer interrupt */
 249         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 250 }
 251
 252 /**
 253  * Hook for after all CPUs are online
 254  */
 255 static void octeon_cpus_done(void)
 256 {
 257 #ifdef CONFIG_CAVIUM_GDB
 258         unsigned long tmp;
 259         /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
 260            to be not masked by this core so we know the signal is received by
 261            someone */
 262         asm volatile ("dmfc0 %0, $22\n"
 263                       "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
 264 #endif
 265 }
 266
 267 #ifdef CONFIG_HOTPLUG_CPU
 268
 269 /* State of each CPU. */
 270 DEFINE_PER_CPU(int, cpu_state);
 271
 272 extern void fixup_irqs(void);
 273
 274 static DEFINE_SPINLOCK(smp_reserve_lock);
 275
 276 static int octeon_cpu_disable(void)
 277 {
 278         unsigned int cpu = smp_processor_id();
 279
 280         if (cpu == 0)
 281                 return -EBUSY;
 282
 283         spin_lock(&smp_reserve_lock);
 284
 285         cpu_clear(cpu, cpu_online_map);
 286         cpu_clear(cpu, cpu_callin_map);
 287         local_irq_disable();
 288         fixup_irqs();
 289         local_irq_enable();
 290
 291         flush_cache_all();
 292         local_flush_tlb_all();
 293
 294         spin_unlock(&smp_reserve_lock);
 295
 296         return 0;
 297 }
 298
 299 static void octeon_cpu_die(unsigned int cpu)
 300 {
 301         int coreid = cpu_logical_map(cpu);
 302         uint32_t avail_coremask;
 303         struct cvmx_bootmem_named_block_desc *block_desc;
 304
 305         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
 306                 cpu_relax();
 307
 308         /*
 309          * This is a bit complicated strategics of getting/settig available
 310          * cores mask, copied from bootloader
 311          */
 312         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
 313         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 314
 315         if (!block_desc) {
 316                 avail_coremask =
 317                         cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 318                                                    LABI_ADDR_IN_BOOTLOADER +
 319                                                    offsetof
 320                                                    (struct linux_app_boot_info,
 321                                                     avail_coremask)));
 322         } else {                       /* alternative, already initialized */
 323                avail_coremask =
 324                    cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 325                                                    block_desc->base_addr +
 326                                                   AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
 327         }
 328
 329         avail_coremask |= 1 << coreid;
 330
 331         /* Setting avail_coremask for bootoct binary */
 332         if (!block_desc) {
 333                 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 334                                                 LABI_ADDR_IN_BOOTLOADER +
 335                                                 offsetof(struct linux_app_boot_info,
 336                                                          avail_coremask)),
 337                                    avail_coremask);
 338         } else {
 339                 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 340                                                 block_desc->base_addr +
 341                                                 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
 342                                    avail_coremask);
 343         }
 344
 345         pr_info("Reset core %d. Available Coremask = %x\n", coreid,
 346                 avail_coremask);
 347         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
 348         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 349 }
 350
 351 void play_dead(void)
 352 {
 353         int coreid = cvmx_get_core_num();
 354
 355         idle_task_exit();
 356         octeon_processor_boot = 0xff;
 357         per_cpu(cpu_state, coreid) = CPU_DEAD;
 358
 359         while (1)       /* core will be reset here */
 360                 ;
 361 }
 362
 363 extern void kernel_entry(unsigned long arg1, ...);
 364
 365 static void start_after_reset(void)
 366 {
 367         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
 368 }
 369
 370 int octeon_update_boot_vector(unsigned int cpu)
 371 {
 372
 373         int coreid = cpu_logical_map(cpu);
 374         unsigned int avail_coremask;
 375         struct cvmx_bootmem_named_block_desc *block_desc;
 376         struct boot_init_vector *boot_vect =
 377                 (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
 378                                                   BOOTLOADER_BOOT_VECTOR);
 379
 380         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 381
 382         if (!block_desc) {
 383                 avail_coremask =
 384                         cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 385                                            LABI_ADDR_IN_BOOTLOADER +
 386                                                 offsetof(struct linux_app_boot_info,
 387                                                 avail_coremask)));
 388         } else {                       /* alternative, already initialized */
 389                avail_coremask =
 390                    cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
 391                                                    block_desc->base_addr +
 392                                                    AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
 393         }
 394
 395         if (!(avail_coremask & (1 << coreid))) {
 396                 /* core not available, assume, that catched by simple-executive */
 397                 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
 398                 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 399         }
 400
 401         boot_vect[coreid].app_start_func_addr =
 402                 (uint32_t) (unsigned long) start_after_reset;
 403         boot_vect[coreid].code_addr = InitTLBStart_addr;
 404
 405         CVMX_SYNC;
 406
 407         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
 408
 409         return 0;
 410 }
 411
 412 static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
 413         unsigned long action, void *hcpu)
 414 {
 415         unsigned int cpu = (unsigned long)hcpu;
 416
 417         switch (action) {
 418         case CPU_UP_PREPARE:
 419                 octeon_update_boot_vector(cpu);
 420                 break;
 421         case CPU_ONLINE:
 422                 pr_info("Cpu %d online\n", cpu);
 423                 break;
 424         case CPU_DEAD:
 425                 break;
 426         }
 427
 428         return NOTIFY_OK;
 429 }
 430
 431 static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
 432         .notifier_call = octeon_cpu_callback,
 433 };
 434
 435 static int __cpuinit register_cavium_notifier(void)
 436 {
 437         register_hotcpu_notifier(&octeon_cpu_notifier);
 438
 439         return 0;
 440 }
 441
 442 late_initcall(register_cavium_notifier);
 443
 444 #endif  /* CONFIG_HOTPLUG_CPU */
 445
 446 struct plat_smp_ops octeon_smp_ops = {
 447         .send_ipi_single        = octeon_send_ipi_single,
 448         .send_ipi_mask          = octeon_send_ipi_mask,
 449         .init_secondary         = octeon_init_secondary,
 450         .smp_finish             = octeon_smp_finish,
 451         .cpus_done              = octeon_cpus_done,
 452         .boot_secondary         = octeon_boot_secondary,
 453         .smp_setup              = octeon_smp_setup,
 454         .prepare_cpus           = octeon_prepare_cpus,
 455 #ifdef CONFIG_HOTPLUG_CPU
 456         .cpu_disable            = octeon_cpu_disable,
 457         .cpu_die                = octeon_cpu_die,
 458 #endif
 459 };