arch/blackfin/mach-bf561/include/mach/mem_map.h

   1 /*
   2  * Memory MAP
   3  * Common header file for blackfin BF561 of processors.
   4  */
   5
   6 #ifndef _MEM_MAP_561_H_
   7 #define _MEM_MAP_561_H_
   8
   9 #define COREMMR_BASE           0xFFE00000        /* Core MMRs */
  10 #define SYSMMR_BASE            0xFFC00000        /* System MMRs */
  11
  12 /* Async Memory Banks */
  13 #define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
  14 #define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
  15 #define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
  16 #define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
  17 #define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
  18 #define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
  19 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
  20 #define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
  21
  22 /* Boot ROM Memory */
  23
  24 #define BOOT_ROM_START          0xEF000000
  25 #define BOOT_ROM_LENGTH         0x800
  26
  27 /* Level 1 Memory */
  28
  29 #ifdef CONFIG_BFIN_ICACHE
  30 #define BFIN_ICACHESIZE (16*1024)
  31 #else
  32 #define BFIN_ICACHESIZE (0*1024)
  33 #endif
  34
  35 /* Memory Map for ADSP-BF561 processors */
  36
  37 #ifdef CONFIG_BF561
  38 #define COREA_L1_CODE_START       0xFFA00000
  39 #define COREA_L1_DATA_A_START     0xFF800000
  40 #define COREA_L1_DATA_B_START     0xFF900000
  41 #define COREB_L1_CODE_START       0xFF600000
  42 #define COREB_L1_DATA_A_START     0xFF400000
  43 #define COREB_L1_DATA_B_START     0xFF500000
  44
  45 #define L1_CODE_START       COREA_L1_CODE_START
  46 #define L1_DATA_A_START     COREA_L1_DATA_A_START
  47 #define L1_DATA_B_START     COREA_L1_DATA_B_START
  48
  49 #define L1_CODE_LENGTH      0x4000
  50
  51 #ifdef CONFIG_BFIN_DCACHE
  52
  53 #ifdef CONFIG_BFIN_DCACHE_BANKA
  54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  55 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  56 #define L1_DATA_B_LENGTH      0x8000
  57 #define BFIN_DCACHESIZE (16*1024)
  58 #define BFIN_DSUPBANKS  1
  59 #else
  60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  61 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  62 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
  63 #define BFIN_DCACHESIZE (32*1024)
  64 #define BFIN_DSUPBANKS  2
  65 #endif
  66
  67 #else
  68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
  69 #define L1_DATA_A_LENGTH      0x8000
  70 #define L1_DATA_B_LENGTH      0x8000
  71 #define BFIN_DCACHESIZE (0*1024)
  72 #define BFIN_DSUPBANKS  0
  73 #endif /*CONFIG_BFIN_DCACHE*/
  74 #endif
  75
  76 /* Level 2 Memory */
  77 #define L2_START                0xFEB00000
  78 #define L2_LENGTH               0x20000
  79
  80 /* Scratch Pad Memory */
  81
  82 #define COREA_L1_SCRATCH_START  0xFFB00000
  83 #define COREB_L1_SCRATCH_START  0xFF700000
  84
  85 #define L1_SCRATCH_START        COREA_L1_SCRATCH_START
  86 #define L1_SCRATCH_LENGTH       0x1000
  87
  88 #ifndef __ASSEMBLY__
  89
  90 #ifdef CONFIG_SMP
  91
  92 #define get_l1_scratch_start_cpu(cpu)                           \
  93         ({ unsigned long __addr;                                \
  94            __addr = (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;\
  95            __addr; })
  96
  97 #define get_l1_code_start_cpu(cpu)                              \
  98         ({ unsigned long __addr;                                \
  99            __addr = (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START;  \
 100            __addr; })
 101
 102 #define get_l1_data_a_start_cpu(cpu)                            \
 103         ({ unsigned long __addr;                                \
 104            __addr = (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;\
 105            __addr; })
 106
 107 #define get_l1_data_b_start_cpu(cpu)                            \
 108         ({ unsigned long __addr;                                \
 109            __addr = (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;\
 110            __addr; })
 111
 112 #define get_l1_scratch_start()  get_l1_scratch_start_cpu(blackfin_core_id())
 113 #define get_l1_code_start()     get_l1_code_start_cpu(blackfin_core_id())
 114 #define get_l1_data_a_start()   get_l1_data_a_start_cpu(blackfin_core_id())
 115 #define get_l1_data_b_start()   get_l1_data_b_start_cpu(blackfin_core_id())
 116
 117 #else /* !CONFIG_SMP */
 118 #define get_l1_scratch_start_cpu(cpu)   L1_SCRATCH_START
 119 #define get_l1_code_start_cpu(cpu)      L1_CODE_START
 120 #define get_l1_data_a_start_cpu(cpu)    L1_DATA_A_START
 121 #define get_l1_data_b_start_cpu(cpu)    L1_DATA_B_START
 122 #define get_l1_scratch_start()          L1_SCRATCH_START
 123 #define get_l1_code_start()             L1_CODE_START
 124 #define get_l1_data_a_start()           L1_DATA_A_START
 125 #define get_l1_data_b_start()           L1_DATA_B_START
 126 #endif /* !CONFIG_SMP */
 127
 128 #else /* __ASSEMBLY__ */
 129
 130 /*
 131  * The following macros both return the address of the PDA for the
 132  * current core.
 133  *
 134  * In its first safe (and hairy) form, the macro neither clobbers any
 135  * register aside of the output Preg, nor uses the stack, since it
 136  * could be called with an invalid stack pointer, or the current stack
 137  * space being uncovered by any CPLB (e.g. early exception handling).
 138  *
 139  * The constraints on the second form are a bit relaxed, and the code
 140  * is allowed to use the specified Dreg for determining the PDA
 141  * address to be returned into Preg.
 142  */
 143 #ifdef CONFIG_SMP
 144 #define GET_PDA_SAFE(preg)              \
 145         preg.l = lo(DSPID);             \
 146         preg.h = hi(DSPID);             \
 147         preg = [preg];                  \
 148         preg = preg << 2;               \
 149         preg = preg << 2;               \
 150         preg = preg << 2;               \
 151         preg = preg << 2;               \
 152         preg = preg << 2;               \
 153         preg = preg << 2;               \
 154         preg = preg << 2;               \
 155         preg = preg << 2;               \
 156         preg = preg << 2;               \
 157         preg = preg << 2;               \
 158         preg = preg << 2;               \
 159         preg = preg << 2;               \
 160         if cc jump 2f;                  \
 161         cc = preg == 0x0;               \
 162         preg.l = _cpu_pda;              \
 163         preg.h = _cpu_pda;              \
 164         if !cc jump 3f;                 \
 165 1:                                      \
 166         /* preg = 0x0; */               \
 167         cc = !cc; /* restore cc to 0 */ \
 168         jump 4f;                        \
 169 2:                                      \
 170         cc = preg == 0x0;               \
 171         preg.l = _cpu_pda;              \
 172         preg.h = _cpu_pda;              \
 173         if cc jump 4f;                  \
 174         /* preg = 0x1000000; */         \
 175         cc = !cc; /* restore cc to 1 */ \
 176 3:                                      \
 177         preg = [preg];                  \
 178 4:
 179
 180 #define GET_PDA(preg, dreg)             \
 181         preg.l = lo(DSPID);             \
 182         preg.h = hi(DSPID);             \
 183         dreg = [preg];                  \
 184         preg.l = _cpu_pda;              \
 185         preg.h = _cpu_pda;              \
 186         cc = bittst(dreg, 0);           \
 187         if !cc jump 1f;                 \
 188         preg = [preg];                  \
 189 1:                                      \
 190
 191 #define GET_CPUID(preg, dreg)           \
 192         preg.l = lo(DSPID);             \
 193         preg.h = hi(DSPID);             \
 194         dreg = [preg];                  \
 195         dreg = ROT dreg BY -1;          \
 196         dreg = CC;
 197
 198 #else
 199 #define GET_PDA_SAFE(preg)              \
 200         preg.l = _cpu_pda;              \
 201         preg.h = _cpu_pda;
 202
 203 #define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
 204 #endif /* CONFIG_SMP */
 205
 206 #endif /* __ASSEMBLY__ */
 207
 208 #endif                          /* _MEM_MAP_533_H_ */