2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
26 select HAVE_FUNCTION_GRAPH_TRACER
27 select HAVE_FUNCTION_TRACER
29 select HAVE_KERNEL_GZIP
30 select HAVE_KERNEL_BZIP2
31 select HAVE_KERNEL_LZMA
33 select ARCH_WANT_OPTIONAL_GPIOLIB
42 config GENERIC_FIND_NEXT_BIT
45 config GENERIC_HWEIGHT
48 config GENERIC_HARDIRQS
51 config GENERIC_IRQ_PROBE
54 config GENERIC_HARDIRQS_NO__DO_IRQ
60 config FORCE_MAX_ZONEORDER
64 config GENERIC_CALIBRATE_DELAY
67 config LOCKDEP_SUPPORT
70 config STACKTRACE_SUPPORT
73 config TRACE_IRQFLAGS_SUPPORT
78 source "kernel/Kconfig.preempt"
80 source "kernel/Kconfig.freezer"
82 menu "Blackfin Processor Options"
84 comment "Processor and Board Settings"
93 BF512 Processor Support.
98 BF514 Processor Support.
103 BF516 Processor Support.
108 BF518 Processor Support.
113 BF522 Processor Support.
118 BF523 Processor Support.
123 BF524 Processor Support.
128 BF525 Processor Support.
133 BF526 Processor Support.
138 BF527 Processor Support.
143 BF531 Processor Support.
148 BF532 Processor Support.
153 BF533 Processor Support.
158 BF534 Processor Support.
163 BF536 Processor Support.
168 BF537 Processor Support.
173 BF538 Processor Support.
178 BF539 Processor Support.
183 BF542 Processor Support.
188 BF542 Processor Support.
193 BF544 Processor Support.
198 BF544 Processor Support.
203 BF547 Processor Support.
208 BF547 Processor Support.
213 BF548 Processor Support.
218 BF548 Processor Support.
223 BF549 Processor Support.
228 BF549 Processor Support.
233 BF561 Processor Support.
239 select GENERIC_CLOCKEVENTS
240 bool "Symmetric multi-processing support"
242 This enables support for systems with more than one CPU,
243 like the dual core BF561. If you have a system with only one
244 CPU, say N. If you have a system with more than one CPU, say Y.
246 If you don't know what to do here, say N.
260 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
261 default 2 if (BF537 || BF536 || BF534)
262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
263 default 4 if (BF538 || BF539)
267 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
268 default 3 if (BF537 || BF536 || BF534 || BF54xM)
269 default 5 if (BF561 || BF538 || BF539)
270 default 6 if (BF533 || BF532 || BF531)
274 default BF_REV_0_0 if (BF51x || BF52x)
275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
280 depends on (BF51x || BF52x || (BF54x && !BF54xM))
284 depends on (BF51x || BF52x || (BF54x && !BF54xM))
288 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
292 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
300 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
304 depends on (BF533 || BF532 || BF531)
316 depends on (BF512 || BF514 || BF516 || BF518)
321 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
326 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
331 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
336 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
339 config MEM_GENERIC_BOARD
341 depends on GENERIC_BOARD
344 config MEM_MT48LC64M4A2FB_7E
346 depends on (BFIN533_STAMP)
349 config MEM_MT48LC16M16A2TG_75
351 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
352 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
353 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
354 || BFIN527_BLUETECHNIX_CM)
357 config MEM_MT48LC32M8A2_75
359 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
362 config MEM_MT48LC8M32B2B5_7
364 depends on (BFIN561_BLUETECHNIX_CM)
367 config MEM_MT48LC32M16A2TG_75
369 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
372 config MEM_MT48LC32M8A2_75
374 depends on (BFIN518F_EZBRD)
377 config MEM_MT48H32M16LFCJ_75
379 depends on (BFIN526_EZBRD)
382 source "arch/blackfin/mach-bf518/Kconfig"
383 source "arch/blackfin/mach-bf527/Kconfig"
384 source "arch/blackfin/mach-bf533/Kconfig"
385 source "arch/blackfin/mach-bf561/Kconfig"
386 source "arch/blackfin/mach-bf537/Kconfig"
387 source "arch/blackfin/mach-bf538/Kconfig"
388 source "arch/blackfin/mach-bf548/Kconfig"
390 menu "Board customizations"
393 bool "Default bootloader kernel arguments"
396 string "Initial kernel command string"
397 depends on CMDLINE_BOOL
398 default "console=ttyBF0,57600"
400 If you don't have a boot loader capable of passing a command line string
401 to the kernel, you may specify one here. As a minimum, you should specify
402 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
405 hex "Kernel load address for booting"
407 range 0x1000 0x20000000
409 This option allows you to set the load address of the kernel.
410 This can be useful if you are on a board which has a small amount
411 of memory or you wish to reserve some memory at the beginning of
414 Note that you need to keep this value above 4k (0x1000) as this
415 memory region is used to capture NULL pointer references as well
416 as some core kernel functions.
419 hex "Kernel ROM Base"
422 range 0x20000000 0x20400000 if !(BF54x || BF561)
423 range 0x20000000 0x30000000 if (BF54x || BF561)
426 comment "Clock/PLL Setup"
429 int "Frequency of the crystal on the board in Hz"
430 default "10000000" if BFIN532_IP0X
431 default "11059200" if BFIN533_STAMP
432 default "24576000" if PNAV10
433 default "25000000" # most people use this
434 default "27000000" if BFIN533_EZKIT
435 default "30000000" if BFIN561_EZKIT
437 The frequency of CLKIN crystal oscillator on the board in Hz.
438 Warning: This value should match the crystal on the board. Otherwise,
439 peripherals won't work properly.
441 config BFIN_KERNEL_CLOCK
442 bool "Re-program Clocks while Kernel boots?"
445 This option decides if kernel clocks are re-programed from the
446 bootloader settings. If the clocks are not set, the SDRAM settings
447 are also not changed, and the Bootloader does 100% of the hardware
452 depends on BFIN_KERNEL_CLOCK
457 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
460 If this is set the clock will be divided by 2, before it goes to the PLL.
464 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
466 default "22" if BFIN533_EZKIT
467 default "45" if BFIN533_STAMP
468 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
469 default "22" if BFIN533_BLUETECHNIX_CM
470 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
471 default "20" if BFIN561_EZKIT
472 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
474 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
475 PLL Frequency = (Crystal Frequency) * (this setting)
478 prompt "Core Clock Divider"
479 depends on BFIN_KERNEL_CLOCK
482 This sets the frequency of the core. It can be 1, 2, 4 or 8
483 Core Frequency = (PLL frequency) / (this setting)
499 int "System Clock Divider"
500 depends on BFIN_KERNEL_CLOCK
504 This sets the frequency of the system clock (including SDRAM or DDR).
505 This can be between 1 and 15
506 System Clock = (PLL frequency) / (this setting)
509 prompt "DDR SDRAM Chip Type"
510 depends on BFIN_KERNEL_CLOCK
512 default MEM_MT46V32M16_5B
514 config MEM_MT46V32M16_6T
517 config MEM_MT46V32M16_5B
522 prompt "DDR/SDRAM Timing"
523 depends on BFIN_KERNEL_CLOCK
524 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
526 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
527 The calculated SDRAM timing parameters may not be 100%
528 accurate - This option is therefore marked experimental.
530 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
531 bool "Calculate Timings (EXPERIMENTAL)"
532 depends on EXPERIMENTAL
534 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
535 bool "Provide accurate Timings based on target SCLK"
537 Please consult the Blackfin Hardware Reference Manuals as well
538 as the memory device datasheet.
539 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
542 menu "Memory Init Control"
543 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
560 config MEM_EBIU_DDRQUE
577 # Max & Min Speeds for various Chips
581 default 400000000 if BF512
582 default 400000000 if BF514
583 default 400000000 if BF516
584 default 400000000 if BF518
585 default 400000000 if BF522
586 default 600000000 if BF523
587 default 400000000 if BF524
588 default 600000000 if BF525
589 default 400000000 if BF526
590 default 600000000 if BF527
591 default 400000000 if BF531
592 default 400000000 if BF532
593 default 750000000 if BF533
594 default 500000000 if BF534
595 default 400000000 if BF536
596 default 600000000 if BF537
597 default 533333333 if BF538
598 default 533333333 if BF539
599 default 600000000 if BF542
600 default 533333333 if BF544
601 default 600000000 if BF547
602 default 600000000 if BF548
603 default 533333333 if BF549
604 default 600000000 if BF561
618 comment "Kernel Timer/Scheduler"
620 source kernel/Kconfig.hz
625 config GENERIC_CLOCKEVENTS
626 bool "Generic clock events"
630 prompt "Kernel Tick Source"
631 depends on GENERIC_CLOCKEVENTS
632 default TICKSOURCE_CORETMR
634 config TICKSOURCE_GPTMR0
635 bool "Gptimer0 (SCLK domain)"
638 config TICKSOURCE_CORETMR
639 bool "Core timer (CCLK domain)"
643 config CYCLES_CLOCKSOURCE
644 bool "Use 'CYCLES' as a clocksource"
645 depends on GENERIC_CLOCKEVENTS
646 depends on !BFIN_SCRATCH_REG_CYCLES
649 If you say Y here, you will enable support for using the 'cycles'
650 registers as a clock source. Doing so means you will be unable to
651 safely write to the 'cycles' register during runtime. You will
652 still be able to read it (such as for performance monitoring), but
653 writing the registers will most likely crash the kernel.
655 config GPTMR0_CLOCKSOURCE
656 bool "Use GPTimer0 as a clocksource"
658 depends on GENERIC_CLOCKEVENTS
659 depends on !TICKSOURCE_GPTMR0
661 config ARCH_USES_GETTIMEOFFSET
662 depends on !GENERIC_CLOCKEVENTS
665 source kernel/time/Kconfig
670 prompt "Blackfin Exception Scratch Register"
671 default BFIN_SCRATCH_REG_RETN
673 Select the resource to reserve for the Exception handler:
674 - RETN: Non-Maskable Interrupt (NMI)
675 - RETE: Exception Return (JTAG/ICE)
676 - CYCLES: Performance counter
678 If you are unsure, please select "RETN".
680 config BFIN_SCRATCH_REG_RETN
683 Use the RETN register in the Blackfin exception handler
684 as a stack scratch register. This means you cannot
685 safely use NMI on the Blackfin while running Linux, but
686 you can debug the system with a JTAG ICE and use the
687 CYCLES performance registers.
689 If you are unsure, please select "RETN".
691 config BFIN_SCRATCH_REG_RETE
694 Use the RETE register in the Blackfin exception handler
695 as a stack scratch register. This means you cannot
696 safely use a JTAG ICE while debugging a Blackfin board,
697 but you can safely use the CYCLES performance registers
700 If you are unsure, please select "RETN".
702 config BFIN_SCRATCH_REG_CYCLES
705 Use the CYCLES register in the Blackfin exception handler
706 as a stack scratch register. This means you cannot
707 safely use the CYCLES performance registers on a Blackfin
708 board at anytime, but you can debug the system with a JTAG
711 If you are unsure, please select "RETN".
718 menu "Blackfin Kernel Optimizations"
721 comment "Memory Optimizations"
724 bool "Locate interrupt entry code in L1 Memory"
727 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
728 into L1 instruction memory. (less latency)
730 config EXCPT_IRQ_SYSC_L1
731 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
734 If enabled, the entire ASM lowlevel exception and interrupt entry code
735 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
739 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
742 If enabled, the frequently called do_irq dispatcher function is linked
743 into L1 instruction memory. (less latency)
745 config CORE_TIMER_IRQ_L1
746 bool "Locate frequently called timer_interrupt() function in L1 Memory"
749 If enabled, the frequently called timer_interrupt() function is linked
750 into L1 instruction memory. (less latency)
753 bool "Locate frequently idle function in L1 Memory"
756 If enabled, the frequently called idle function is linked
757 into L1 instruction memory. (less latency)
760 bool "Locate kernel schedule function in L1 Memory"
763 If enabled, the frequently called kernel schedule is linked
764 into L1 instruction memory. (less latency)
766 config ARITHMETIC_OPS_L1
767 bool "Locate kernel owned arithmetic functions in L1 Memory"
770 If enabled, arithmetic functions are linked
771 into L1 instruction memory. (less latency)
774 bool "Locate access_ok function in L1 Memory"
777 If enabled, the access_ok function is linked
778 into L1 instruction memory. (less latency)
781 bool "Locate memset function in L1 Memory"
784 If enabled, the memset function is linked
785 into L1 instruction memory. (less latency)
788 bool "Locate memcpy function in L1 Memory"
791 If enabled, the memcpy function is linked
792 into L1 instruction memory. (less latency)
794 config SYS_BFIN_SPINLOCK_L1
795 bool "Locate sys_bfin_spinlock function in L1 Memory"
798 If enabled, sys_bfin_spinlock function is linked
799 into L1 instruction memory. (less latency)
801 config IP_CHECKSUM_L1
802 bool "Locate IP Checksum function in L1 Memory"
805 If enabled, the IP Checksum function is linked
806 into L1 instruction memory. (less latency)
808 config CACHELINE_ALIGNED_L1
809 bool "Locate cacheline_aligned data to L1 Data Memory"
814 If enabled, cacheline_aligned data is linked
815 into L1 data memory. (less latency)
817 config SYSCALL_TAB_L1
818 bool "Locate Syscall Table L1 Data Memory"
822 If enabled, the Syscall LUT is linked
823 into L1 data memory. (less latency)
825 config CPLB_SWITCH_TAB_L1
826 bool "Locate CPLB Switch Tables L1 Data Memory"
830 If enabled, the CPLB Switch Tables are linked
831 into L1 data memory. (less latency)
834 bool "Support locating application stack in L1 Scratch Memory"
837 If enabled the application stack can be located in L1
838 scratch memory (less latency).
840 Currently only works with FLAT binaries.
842 config EXCEPTION_L1_SCRATCH
843 bool "Locate exception stack in L1 Scratch Memory"
845 depends on !APP_STACK_L1
847 Whenever an exception occurs, use the L1 Scratch memory for
848 stack storage. You cannot place the stacks of FLAT binaries
849 in L1 when using this option.
851 If you don't use L1 Scratch, then you should say Y here.
853 comment "Speed Optimizations"
854 config BFIN_INS_LOWOVERHEAD
855 bool "ins[bwl] low overhead, higher interrupt latency"
858 Reads on the Blackfin are speculative. In Blackfin terms, this means
859 they can be interrupted at any time (even after they have been issued
860 on to the external bus), and re-issued after the interrupt occurs.
861 For memory - this is not a big deal, since memory does not change if
864 If a FIFO is sitting on the end of the read, it will see two reads,
865 when the core only sees one since the FIFO receives both the read
866 which is cancelled (and not delivered to the core) and the one which
867 is re-issued (which is delivered to the core).
869 To solve this, interrupts are turned off before reads occur to
870 I/O space. This option controls which the overhead/latency of
871 controlling interrupts during this time
872 "n" turns interrupts off every read
873 (higher overhead, but lower interrupt latency)
874 "y" turns interrupts off every loop
875 (low overhead, but longer interrupt latency)
877 default behavior is to leave this set to on (type "Y"). If you are experiencing
878 interrupt latency issues, it is safe and OK to turn this off.
883 prompt "Kernel executes from"
885 Choose the memory type that the kernel will be running in.
890 The kernel will be resident in RAM when running.
895 The kernel will be resident in FLASH/ROM when running.
902 tristate "Enable Blackfin General Purpose Timers API"
905 Enable support for the General Purpose Timers API. If you
908 To compile this driver as a module, choose M here: the module
909 will be called gptimers.
912 prompt "Uncached DMA region"
913 default DMA_UNCACHED_1M
914 config DMA_UNCACHED_4M
915 bool "Enable 4M DMA region"
916 config DMA_UNCACHED_2M
917 bool "Enable 2M DMA region"
918 config DMA_UNCACHED_1M
919 bool "Enable 1M DMA region"
920 config DMA_UNCACHED_NONE
921 bool "Disable DMA region"
925 comment "Cache Support"
930 config BFIN_EXTMEM_ICACHEABLE
931 bool "Enable ICACHE for external memory"
932 depends on BFIN_ICACHE
934 config BFIN_L2_ICACHEABLE
935 bool "Enable ICACHE for L2 SRAM"
936 depends on BFIN_ICACHE
937 depends on BF54x || BF561
943 config BFIN_DCACHE_BANKA
944 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
945 depends on BFIN_DCACHE && !BF531
947 config BFIN_EXTMEM_DCACHEABLE
948 bool "Enable DCACHE for external memory"
949 depends on BFIN_DCACHE
952 prompt "External memory DCACHE policy"
953 depends on BFIN_EXTMEM_DCACHEABLE
954 default BFIN_EXTMEM_WRITEBACK if !SMP
955 default BFIN_EXTMEM_WRITETHROUGH if SMP
956 config BFIN_EXTMEM_WRITEBACK
961 Cached data will be written back to SDRAM only when needed.
962 This can give a nice increase in performance, but beware of
963 broken drivers that do not properly invalidate/flush their
966 Write Through Policy:
967 Cached data will always be written back to SDRAM when the
968 cache is updated. This is a completely safe setting, but
969 performance is worse than Write Back.
971 If you are unsure of the options and you want to be safe,
972 then go with Write Through.
974 config BFIN_EXTMEM_WRITETHROUGH
978 Cached data will be written back to SDRAM only when needed.
979 This can give a nice increase in performance, but beware of
980 broken drivers that do not properly invalidate/flush their
983 Write Through Policy:
984 Cached data will always be written back to SDRAM when the
985 cache is updated. This is a completely safe setting, but
986 performance is worse than Write Back.
988 If you are unsure of the options and you want to be safe,
989 then go with Write Through.
993 config BFIN_L2_DCACHEABLE
994 bool "Enable DCACHE for L2 SRAM"
995 depends on BFIN_DCACHE
996 depends on (BF54x || BF561) && !SMP
999 prompt "L2 SRAM DCACHE policy"
1000 depends on BFIN_L2_DCACHEABLE
1001 default BFIN_L2_WRITEBACK
1002 config BFIN_L2_WRITEBACK
1005 config BFIN_L2_WRITETHROUGH
1006 bool "Write through"
1010 comment "Memory Protection Unit"
1012 bool "Enable the memory protection unit (EXPERIMENTAL)"
1015 Use the processor's MPU to protect applications from accessing
1016 memory they do not own. This comes at a performance penalty
1017 and is recommended only for debugging.
1019 comment "Asynchronous Memory Configuration"
1021 menu "EBIU_AMGCTL Global Control"
1023 bool "Enable CLKOUT"
1027 bool "DMA has priority over core for ext. accesses"
1032 bool "Bank 0 16 bit packing enable"
1037 bool "Bank 1 16 bit packing enable"
1042 bool "Bank 2 16 bit packing enable"
1047 bool "Bank 3 16 bit packing enable"
1051 prompt "Enable Asynchronous Memory Banks"
1055 bool "Disable All Banks"
1058 bool "Enable Bank 0"
1060 config C_AMBEN_B0_B1
1061 bool "Enable Bank 0 & 1"
1063 config C_AMBEN_B0_B1_B2
1064 bool "Enable Bank 0 & 1 & 2"
1067 bool "Enable All Banks"
1071 menu "EBIU_AMBCTL Control"
1073 hex "Bank 0 (AMBCTL0.L)"
1076 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1077 used to control the Asynchronous Memory Bank 0 settings.
1080 hex "Bank 1 (AMBCTL0.H)"
1082 default 0x5558 if BF54x
1084 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1085 used to control the Asynchronous Memory Bank 1 settings.
1088 hex "Bank 2 (AMBCTL1.L)"
1091 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1092 used to control the Asynchronous Memory Bank 2 settings.
1095 hex "Bank 3 (AMBCTL1.H)"
1098 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1099 used to control the Asynchronous Memory Bank 3 settings.
1103 config EBIU_MBSCTLVAL
1104 hex "EBIU Bank Select Control Register"
1109 hex "Flash Memory Mode Control Register"
1114 hex "Flash Memory Bank Control Register"
1119 #############################################################################
1120 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1126 Support for PCI bus.
1128 source "drivers/pci/Kconfig"
1131 bool "Support for hot-pluggable device"
1133 Say Y here if you want to plug devices into your computer while
1134 the system is running, and be able to use them quickly. In many
1135 cases, the devices can likewise be unplugged at any time too.
1137 One well known example of this is PCMCIA- or PC-cards, credit-card
1138 size devices such as network cards, modems or hard drives which are
1139 plugged into slots found on all modern laptop computers. Another
1140 example, used on modern desktops as well as laptops, is USB.
1142 Enable HOTPLUG and build a modular kernel. Get agent software
1143 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1144 Then your kernel will automatically call out to a user mode "policy
1145 agent" (/sbin/hotplug) to load modules and set up software needed
1146 to use devices as you hotplug them.
1148 source "drivers/pcmcia/Kconfig"
1150 source "drivers/pci/hotplug/Kconfig"
1154 menu "Executable file formats"
1156 source "fs/Kconfig.binfmt"
1160 menu "Power management options"
1163 source "kernel/power/Kconfig"
1165 config ARCH_SUSPEND_POSSIBLE
1169 prompt "Standby Power Saving Mode"
1171 default PM_BFIN_SLEEP_DEEPER
1172 config PM_BFIN_SLEEP_DEEPER
1175 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1176 power dissipation by disabling the clock to the processor core (CCLK).
1177 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1178 to 0.85 V to provide the greatest power savings, while preserving the
1180 The PLL and system clock (SCLK) continue to operate at a very low
1181 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1182 the SDRAM is put into Self Refresh Mode. Typically an external event
1183 such as GPIO interrupt or RTC activity wakes up the processor.
1184 Various Peripherals such as UART, SPORT, PPI may not function as
1185 normal during Sleep Deeper, due to the reduced SCLK frequency.
1186 When in the sleep mode, system DMA access to L1 memory is not supported.
1188 If unsure, select "Sleep Deeper".
1190 config PM_BFIN_SLEEP
1193 Sleep Mode (High Power Savings) - The sleep mode reduces power
1194 dissipation by disabling the clock to the processor core (CCLK).
1195 The PLL and system clock (SCLK), however, continue to operate in
1196 this mode. Typically an external event or RTC activity will wake
1197 up the processor. When in the sleep mode, system DMA access to L1
1198 memory is not supported.
1200 If unsure, select "Sleep Deeper".
1203 config PM_WAKEUP_BY_GPIO
1204 bool "Allow Wakeup from Standby by GPIO"
1205 depends on PM && !BF54x
1207 config PM_WAKEUP_GPIO_NUMBER
1210 depends on PM_WAKEUP_BY_GPIO
1214 prompt "GPIO Polarity"
1215 depends on PM_WAKEUP_BY_GPIO
1216 default PM_WAKEUP_GPIO_POLAR_H
1217 config PM_WAKEUP_GPIO_POLAR_H
1219 config PM_WAKEUP_GPIO_POLAR_L
1221 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1223 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1225 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1229 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1232 config PM_BFIN_WAKE_PH6
1233 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1234 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1237 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1239 config PM_BFIN_WAKE_GP
1240 bool "Allow Wake-Up from GPIOs"
1241 depends on PM && BF54x
1244 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1245 (all processors, except ADSP-BF549). This option sets
1246 the general-purpose wake-up enable (GPWE) control bit to enable
1247 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1248 On ADSP-BF549 this option enables the the same functionality on the
1249 /MRXON pin also PH7.
1253 menu "CPU Frequency scaling"
1256 source "drivers/cpufreq/Kconfig"
1258 config BFIN_CPU_FREQ
1261 select CPU_FREQ_TABLE
1265 bool "CPU Voltage scaling"
1266 depends on EXPERIMENTAL
1270 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1271 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1272 manuals. There is a theoretical risk that during VDDINT transitions
1277 source "net/Kconfig"
1279 source "drivers/Kconfig"
1283 source "arch/blackfin/Kconfig.debug"
1285 source "security/Kconfig"
1287 source "crypto/Kconfig"
1289 source "lib/Kconfig"