arch/arm/plat-versatile/timer-sp.c

   1 /*
   2  *  linux/arch/arm/plat-versatile/timer-sp.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/clocksource.h>
  22 #include <linux/clockchips.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26
  27 #include <asm/hardware/arm_timer.h>
  28
  29 #include <mach/platform.h>
  30
  31 #include <plat/timer-sp.h>
  32
  33 /*
  34  * How long is the timer interval?
  35  */
  36 #define TIMER_RELOAD    (TICKS_PER_uSEC * mSEC_10)
  37
  38
  39 static void __iomem *clksrc_base;
  40
  41 static cycle_t sp804_read(struct clocksource *cs)
  42 {
  43         return ~readl(clksrc_base + TIMER_VALUE);
  44 }
  45
  46 static struct clocksource clocksource_sp804 = {
  47         .name           = "timer3",
  48         .rating         = 200,
  49         .read           = sp804_read,
  50         .mask           = CLOCKSOURCE_MASK(32),
  51         .shift          = 20,
  52         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  53 };
  54
  55 void __init sp804_clocksource_init(void __iomem *base)
  56 {
  57         struct clocksource *cs = &clocksource_sp804;
  58
  59         clksrc_base = base;
  60
  61         /* setup timer 0 as free-running clocksource */
  62         writel(0, clksrc_base + TIMER_CTRL);
  63         writel(0xffffffff, clksrc_base + TIMER_LOAD);
  64         writel(0xffffffff, clksrc_base + TIMER_VALUE);
  65         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
  66                 clksrc_base + TIMER_CTRL);
  67
  68         cs->mult = clocksource_khz2mult(1000, cs->shift);
  69         clocksource_register(cs);
  70 }
  71
  72
  73 static void __iomem *clkevt_base;
  74
  75 /*
  76  * IRQ handler for the timer
  77  */
  78 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
  79 {
  80         struct clock_event_device *evt = dev_id;
  81
  82         /* clear the interrupt */
  83         writel(1, clkevt_base + TIMER_INTCLR);
  84
  85         evt->event_handler(evt);
  86
  87         return IRQ_HANDLED;
  88 }
  89
  90 static void sp804_set_mode(enum clock_event_mode mode,
  91         struct clock_event_device *evt)
  92 {
  93         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
  94
  95         writel(ctrl, clkevt_base + TIMER_CTRL);
  96
  97         switch (mode) {
  98         case CLOCK_EVT_MODE_PERIODIC:
  99                 writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
 100                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 101                 break;
 102
 103         case CLOCK_EVT_MODE_ONESHOT:
 104                 /* period set, and timer enabled in 'next_event' hook */
 105                 ctrl |= TIMER_CTRL_ONESHOT;
 106                 break;
 107
 108         case CLOCK_EVT_MODE_UNUSED:
 109         case CLOCK_EVT_MODE_SHUTDOWN:
 110         default:
 111                 break;
 112         }
 113
 114         writel(ctrl, clkevt_base + TIMER_CTRL);
 115 }
 116
 117 static int sp804_set_next_event(unsigned long next,
 118         struct clock_event_device *evt)
 119 {
 120         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 121
 122         writel(next, clkevt_base + TIMER_LOAD);
 123         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 124
 125         return 0;
 126 }
 127
 128 static struct clock_event_device sp804_clockevent = {
 129         .name           = "timer0",
 130         .shift          = 32,
 131         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 132         .set_mode       = sp804_set_mode,
 133         .set_next_event = sp804_set_next_event,
 134         .rating         = 300,
 135         .cpumask        = cpu_all_mask,
 136 };
 137
 138 static struct irqaction sp804_timer_irq = {
 139         .name           = "timer",
 140         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 141         .handler        = sp804_timer_interrupt,
 142         .dev_id         = &sp804_clockevent,
 143 };
 144
 145 void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
 146 {
 147         struct clock_event_device *evt = &sp804_clockevent;
 148
 149         clkevt_base = base;
 150
 151         evt->irq = timer_irq;
 152         evt->mult = div_sc(1000000, NSEC_PER_SEC, evt->shift);
 153         evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
 154         evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 155
 156         setup_irq(timer_irq, &sp804_timer_irq);
 157         clockevents_register_device(evt);
 158 }