2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
12 #include <linux/dmaengine.h>
13 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
15 #include <linux/dmaengine.h>
17 /* dev types for memcpy */
18 #define STEDMA40_DEV_DST_MEMORY (-1)
19 #define STEDMA40_DEV_SRC_MEMORY (-1)
22 * Description of bitfields of channel_type variable is available in
27 STEDMA40_MODE_LOGICAL = 0,
28 STEDMA40_MODE_PHYSICAL,
29 STEDMA40_MODE_OPERATION,
32 enum stedma40_mode_opt {
33 STEDMA40_PCHAN_BASIC_MODE = 0,
34 STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
35 STEDMA40_PCHAN_MODULO_MODE,
36 STEDMA40_PCHAN_DOUBLE_DST_MODE,
37 STEDMA40_LCHAN_SRC_PHY_DST_LOG,
38 STEDMA40_LCHAN_SRC_LOG_DST_PHY,
41 /* End of channel_type configuration */
43 #define STEDMA40_ESIZE_8_BIT 0x0
44 #define STEDMA40_ESIZE_16_BIT 0x1
45 #define STEDMA40_ESIZE_32_BIT 0x2
46 #define STEDMA40_ESIZE_64_BIT 0x3
48 /* The value 4 indicates that PEN-reg shall be set to 0 */
49 #define STEDMA40_PSIZE_PHY_1 0x4
50 #define STEDMA40_PSIZE_PHY_2 0x0
51 #define STEDMA40_PSIZE_PHY_4 0x1
52 #define STEDMA40_PSIZE_PHY_8 0x2
53 #define STEDMA40_PSIZE_PHY_16 0x3
56 * The number of elements differ in logical and
59 #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
60 #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
61 #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
62 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
64 /* Maximum number of possible physical channels */
65 #define STEDMA40_MAX_PHYS 32
67 enum stedma40_flow_ctrl {
68 STEDMA40_NO_FLOW_CTRL,
72 enum stedma40_periph_data_width {
73 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
74 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
75 STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
76 STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
79 enum stedma40_xfer_dir {
80 STEDMA40_MEM_TO_MEM = 1,
81 STEDMA40_MEM_TO_PERIPH,
82 STEDMA40_PERIPH_TO_MEM,
83 STEDMA40_PERIPH_TO_PERIPH
88 * struct stedma40_chan_cfg - dst/src channel configuration
90 * @big_endian: true if the src/dst should be read as big endian
91 * @data_width: Data width of the src/dst hardware
93 * @flow_ctrl: Flow control on/off.
95 struct stedma40_half_channel_info {
97 enum stedma40_periph_data_width data_width;
99 enum stedma40_flow_ctrl flow_ctrl;
103 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
105 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
106 * @channel_type: priority, mode, mode options and interrupt configuration.
107 * @high_priority: true if high-priority
108 * @mode: channel mode: physical, logical, or operation
109 * @mode_opt: options for the chosen channel mode
110 * @src_dev_type: Src device type
111 * @dst_dev_type: Dst device type
112 * @src_info: Parameters for dst half channel
113 * @dst_info: Parameters for dst half channel
116 * This structure has to be filled by the client drivers.
117 * It is recommended to do all dma configurations for clients in the machine.
120 struct stedma40_chan_cfg {
121 enum stedma40_xfer_dir dir;
122 unsigned int channel_type;
124 enum stedma40_mode mode;
125 enum stedma40_mode_opt mode_opt;
128 struct stedma40_half_channel_info src_info;
129 struct stedma40_half_channel_info dst_info;
133 * struct stedma40_platform_data - Configuration struct for the dma device.
135 * @dev_len: length of dev_tx and dev_rx
136 * @dev_tx: mapping between destination event line and io address
137 * @dev_rx: mapping between source event line and io address
138 * @memcpy: list of memcpy event lines
139 * @memcpy_len: length of memcpy
140 * @memcpy_conf_phy: default configuration of physical channel memcpy
141 * @memcpy_conf_log: default configuration of logical channel memcpy
142 * @disabled_channels: A vector, ending with -1, that marks physical channels
143 * that are for different reasons not available for the driver.
145 struct stedma40_platform_data {
147 const dma_addr_t *dev_tx;
148 const dma_addr_t *dev_rx;
151 struct stedma40_chan_cfg *memcpy_conf_phy;
152 struct stedma40_chan_cfg *memcpy_conf_log;
153 int disabled_channels[STEDMA40_MAX_PHYS];
156 #ifdef CONFIG_STE_DMA40
159 * stedma40_filter() - Provides stedma40_chan_cfg to the
160 * ste_dma40 dma driver via the dmaengine framework.
161 * does some checking of what's provided.
163 * Never directly called by client. It used by dmaengine.
164 * @chan: dmaengine handle.
165 * @data: Must be of type: struct stedma40_chan_cfg and is
166 * the configuration of the framework.
171 bool stedma40_filter(struct dma_chan *chan, void *data);
174 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
175 * scattergatter lists.
177 * @chan: dmaengine handle
178 * @sgl_dst: Destination scatter list
179 * @sgl_src: Source scatter list
180 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
181 * and each element must match the corresponding element in the other scatter
183 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
186 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
187 struct scatterlist *sgl_dst,
188 struct scatterlist *sgl_src,
189 unsigned int sgl_len,
190 unsigned long flags);
193 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
196 * @chan: dmaengine handle
197 * @addr: source or destination physicall address.
198 * @size: bytes to transfer
199 * @direction: direction of transfer
200 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
204 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
207 enum dma_data_direction direction,
210 struct scatterlist sg;
211 sg_init_table(&sg, 1);
212 sg.dma_address = addr;
215 return chan->device->device_prep_slave_sg(chan, &sg, 1,
220 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
226 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
229 enum dma_data_direction direction,