2 * arch/arm/plat-iop/time.c
4 * Timer code for IOP32x and IOP33x based systems
6 * Author: Deepak Saxena <dsaxena@mvista.com>
8 * Copyright 2002-2003 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/time.h>
19 #include <linux/init.h>
20 #include <linux/timex.h>
22 #include <linux/clocksource.h>
23 #include <linux/clockchips.h>
24 #include <mach/hardware.h>
26 #include <asm/uaccess.h>
27 #include <asm/mach/irq.h>
28 #include <asm/mach/time.h>
29 #include <mach/time.h>
32 * IOP clocksource (free-running timer 1).
34 static cycle_t iop_clocksource_read(struct clocksource *unused)
36 return 0xffffffffu - read_tcr1();
39 static struct clocksource iop_clocksource = {
42 .read = iop_clocksource_read,
43 .mask = CLOCKSOURCE_MASK(32),
44 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
47 static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
52 /* Find shift and mult values for hz. */
55 temp = (u64) NSEC_PER_SEC << shift;
57 if ((temp >> 32) == 0)
59 } while (--shift != 0);
62 cs->mult = (u32) temp;
64 printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
65 cs->name, cs->shift, cs->mult);
69 * IOP clockevents (interrupting timer 0).
71 static int iop_set_next_event(unsigned long delta,
72 struct clock_event_device *unused)
74 u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
77 write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
79 write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
84 static unsigned long ticks_per_jiffy;
86 static void iop_set_mode(enum clock_event_mode mode,
87 struct clock_event_device *unused)
89 u32 tmr = read_tmr0();
92 case CLOCK_EVT_MODE_PERIODIC:
93 write_tmr0(tmr & ~IOP_TMR_EN);
94 write_tcr0(ticks_per_jiffy - 1);
95 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
97 case CLOCK_EVT_MODE_ONESHOT:
98 /* ->set_next_event sets period and enables timer */
99 tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
101 case CLOCK_EVT_MODE_RESUME:
104 case CLOCK_EVT_MODE_SHUTDOWN:
105 case CLOCK_EVT_MODE_UNUSED:
114 static struct clock_event_device iop_clockevent = {
115 .name = "iop_timer0",
116 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
118 .set_next_event = iop_set_next_event,
119 .set_mode = iop_set_mode,
122 static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
127 /* Find shift and mult values for hz. */
130 temp = (u64) hz << shift;
131 do_div(temp, NSEC_PER_SEC);
132 if ((temp >> 32) == 0)
134 } while (--shift != 0);
137 ce->mult = (u32) temp;
139 printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
140 ce->name, ce->shift, ce->mult);
143 static unsigned long ticks_per_usec;
144 static unsigned long next_jiffy_time;
146 unsigned long iop_gettimeoffset(void)
148 unsigned long offset, temp;
150 /* enable cp6, if necessary, to avoid taking the overhead of an
151 * undefined instruction trap
154 "mrc p15, 0, %0, c15, c1, 0\n\t"
155 "tst %0, #(1 << 6)\n\t"
156 "orreq %0, %0, #(1 << 6)\n\t"
157 "mcreq p15, 0, %0, c15, c1, 0\n\t"
158 #ifdef CONFIG_CPU_XSCALE
159 "mrceq p15, 0, %0, c15, c1, 0\n\t"
161 "subeq pc, pc, #4\n\t"
163 : "=r"(temp) : : "cc");
165 offset = next_jiffy_time - read_tcr1();
167 return offset / ticks_per_usec;
171 iop_timer_interrupt(int irq, void *dev_id)
173 struct clock_event_device *evt = dev_id;
176 evt->event_handler(evt);
180 static struct irqaction iop_timer_irq = {
181 .name = "IOP Timer Tick",
182 .handler = iop_timer_interrupt,
183 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
184 .dev_id = &iop_clockevent,
187 static unsigned long iop_tick_rate;
188 unsigned long get_iop_tick_rate(void)
190 return iop_tick_rate;
192 EXPORT_SYMBOL(get_iop_tick_rate);
194 void __init iop_init_time(unsigned long tick_rate)
198 ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
199 ticks_per_usec = tick_rate / 1000000;
200 next_jiffy_time = 0xffffffff;
201 iop_tick_rate = tick_rate;
203 timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
204 IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
207 * Set up interrupting clockevent timer 0.
209 write_tmr0(timer_ctl & ~IOP_TMR_EN);
210 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
211 iop_clockevent_set_hz(&iop_clockevent, tick_rate);
212 iop_clockevent.max_delta_ns =
213 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
214 iop_clockevent.min_delta_ns =
215 clockevent_delta2ns(0xf, &iop_clockevent);
216 iop_clockevent.cpumask = cpumask_of(0);
217 clockevents_register_device(&iop_clockevent);
218 write_trr0(ticks_per_jiffy - 1);
219 write_tcr0(ticks_per_jiffy - 1);
220 write_tmr0(timer_ctl);
223 * Set up free-running clocksource timer 1.
225 write_trr1(0xffffffff);
226 write_tcr1(0xffffffff);
227 write_tmr1(timer_ctl);
228 iop_clocksource_set_hz(&iop_clocksource, tick_rate);
229 clocksource_register(&iop_clocksource);