2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/gpio.h>
17 #include <linux/delay.h>
19 #include <linux/fsl_devices.h>
20 #include <linux/fec.h>
22 #include <mach/common.h>
23 #include <mach/hardware.h>
24 #include <mach/imx-uart.h>
25 #include <mach/iomux-mx51.h>
27 #include <mach/mxc_ehci.h>
30 #include <asm/setup.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/time.h>
37 #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
38 #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
39 #define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
40 #define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
43 #define MX51_USB_CTRL_1_OFFSET 0x10
44 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
46 #define MX51_USB_PLLDIV_12_MHZ 0x00
47 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
48 #define MX51_USB_PLL_DIV_24_MHZ 0x02
50 static struct platform_device *devices[] __initdata = {
54 static struct pad_desc mx51babbage_pads[] = {
56 MX51_PAD_UART1_RXD__UART1_RXD,
57 MX51_PAD_UART1_TXD__UART1_TXD,
58 MX51_PAD_UART1_RTS__UART1_RTS,
59 MX51_PAD_UART1_CTS__UART1_CTS,
62 MX51_PAD_UART2_RXD__UART2_RXD,
63 MX51_PAD_UART2_TXD__UART2_TXD,
66 MX51_PAD_EIM_D25__UART3_RXD,
67 MX51_PAD_EIM_D26__UART3_TXD,
68 MX51_PAD_EIM_D27__UART3_RTS,
69 MX51_PAD_EIM_D24__UART3_CTS,
72 MX51_PAD_EIM_D16__I2C1_SDA,
73 MX51_PAD_EIM_D19__I2C1_SCL,
76 MX51_PAD_KEY_COL4__I2C2_SCL,
77 MX51_PAD_KEY_COL5__I2C2_SDA,
80 MX51_PAD_I2C1_CLK__HSI2C_CLK,
81 MX51_PAD_I2C1_DAT__HSI2C_DAT,
84 MX51_PAD_USBH1_CLK__USBH1_CLK,
85 MX51_PAD_USBH1_DIR__USBH1_DIR,
86 MX51_PAD_USBH1_NXT__USBH1_NXT,
87 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
88 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
89 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
90 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
91 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
92 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
93 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
94 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
96 /* USB HUB reset line*/
97 MX51_PAD_GPIO_1_7__GPIO_1_7,
100 MX51_PAD_EIM_EB2__FEC_MDIO,
101 MX51_PAD_EIM_EB3__FEC_RDAT1,
102 MX51_PAD_EIM_CS2__FEC_RDAT2,
103 MX51_PAD_EIM_CS3__FEC_RDAT3,
104 MX51_PAD_EIM_CS4__FEC_RX_ER,
105 MX51_PAD_EIM_CS5__FEC_CRS,
106 MX51_PAD_NANDF_RB2__FEC_COL,
107 MX51_PAD_NANDF_RB3__FEC_RXCLK,
108 MX51_PAD_NANDF_RB6__FEC_RDAT0,
109 MX51_PAD_NANDF_RB7__FEC_TDAT0,
110 MX51_PAD_NANDF_CS2__FEC_TX_ER,
111 MX51_PAD_NANDF_CS3__FEC_MDC,
112 MX51_PAD_NANDF_CS4__FEC_TDAT1,
113 MX51_PAD_NANDF_CS5__FEC_TDAT2,
114 MX51_PAD_NANDF_CS6__FEC_TDAT3,
115 MX51_PAD_NANDF_CS7__FEC_TX_EN,
116 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
118 /* FEC PHY reset line */
119 MX51_PAD_EIM_A20__GPIO_2_14,
123 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
124 static struct imxuart_platform_data uart_pdata = {
125 .flags = IMXUART_HAVE_RTSCTS,
128 static inline void mxc_init_imx_uart(void)
130 mxc_register_device(&mxc_uart_device0, &uart_pdata);
131 mxc_register_device(&mxc_uart_device1, &uart_pdata);
132 mxc_register_device(&mxc_uart_device2, &uart_pdata);
134 #else /* !SERIAL_IMX */
135 static inline void mxc_init_imx_uart(void)
138 #endif /* SERIAL_IMX */
140 static struct imxi2c_platform_data babbage_i2c_data = {
144 static struct imxi2c_platform_data babbage_hsi2c_data = {
148 static int gpio_usbh1_active(void)
150 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
151 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
154 /* Set USBH1_STP to GPIO and toggle it */
155 mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
156 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
159 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
162 gpio_direction_output(BABBAGE_USBH1_STP, 0);
163 gpio_set_value(BABBAGE_USBH1_STP, 1);
165 gpio_free(BABBAGE_USBH1_STP);
167 /* De-assert USB PHY RESETB */
168 mxc_iomux_v3_setup_pad(&phyreset_gpio);
169 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
172 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
175 gpio_direction_output(BABBAGE_PHY_RESET, 1);
179 static inline void babbage_usbhub_reset(void)
183 /* Bring USB hub out of reset */
184 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
186 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
189 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
191 /* USB HUB RESET - De-assert USB HUB RESET_N */
193 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
195 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
198 static inline void babbage_fec_reset(void)
203 ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
205 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
208 gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
209 gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
211 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
214 /* This function is board specific as the bit mask for the plldiv will also
215 be different for other Freescale SoCs, thus a common bitmask is not
216 possible and cannot get place in /plat-mxc/ehci.c.*/
217 static int initialize_otg_port(struct platform_device *pdev)
220 void __iomem *usb_base;
221 void __iomem *usbother_base;
223 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
224 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
226 /* Set the PHY clock to 19.2MHz */
227 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
228 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
229 v |= MX51_USB_PLL_DIV_19_2_MHZ;
230 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
235 static int initialize_usbh1_port(struct platform_device *pdev)
238 void __iomem *usb_base;
239 void __iomem *usbother_base;
241 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
242 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
244 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
245 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
246 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
251 static struct mxc_usbh_platform_data dr_utmi_config = {
252 .init = initialize_otg_port,
253 .portsc = MXC_EHCI_UTMI_16BIT,
254 .flags = MXC_EHCI_INTERNAL_PHY,
257 static struct fsl_usb2_platform_data usb_pdata = {
258 .operating_mode = FSL_USB2_DR_DEVICE,
259 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
262 static struct mxc_usbh_platform_data usbh1_config = {
263 .init = initialize_usbh1_port,
264 .portsc = MXC_EHCI_MODE_ULPI,
265 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
268 static int otg_mode_host;
270 static int __init babbage_otg_mode(char *options)
272 if (!strcmp(options, "host"))
274 else if (!strcmp(options, "device"))
277 pr_info("otg_mode neither \"host\" nor \"device\". "
278 "Defaulting to device\n");
281 __setup("otg_mode=", babbage_otg_mode);
284 * Board specific initialization.
286 static void __init mxc_board_init(void)
288 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
290 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
291 ARRAY_SIZE(mx51babbage_pads));
294 platform_add_devices(devices, ARRAY_SIZE(devices));
296 mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
297 mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
298 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
301 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
303 initialize_otg_port(NULL);
304 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
308 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
309 /* setback USBH1_STP to be function */
310 mxc_iomux_v3_setup_pad(&usbh1stp);
311 babbage_usbhub_reset();
314 static void __init mx51_babbage_timer_init(void)
316 mx51_clocks_init(32768, 24000000, 22579200, 0);
319 static struct sys_timer mxc_timer = {
320 .init = mx51_babbage_timer_init,
323 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
324 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
325 .phys_io = MX51_AIPS1_BASE_ADDR,
326 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
327 .boot_params = PHYS_OFFSET + 0x100,
328 .map_io = mx51_map_io,
329 .init_irq = mx51_init_irq,
330 .init_machine = mxc_board_init,