2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/gpio.h>
17 #include <linux/delay.h>
19 #include <linux/fsl_devices.h>
20 #include <linux/fec.h>
22 #include <mach/common.h>
23 #include <mach/hardware.h>
24 #include <mach/iomux-mx51.h>
25 #include <mach/mxc_ehci.h>
28 #include <asm/setup.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/time.h>
33 #include "devices-imx51.h"
36 #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
37 #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
38 #define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
39 #define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
42 #define MX51_USB_CTRL_1_OFFSET 0x10
43 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
45 #define MX51_USB_PLLDIV_12_MHZ 0x00
46 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
47 #define MX51_USB_PLL_DIV_24_MHZ 0x02
49 static struct platform_device *devices[] __initdata = {
53 static struct pad_desc mx51babbage_pads[] = {
55 MX51_PAD_UART1_RXD__UART1_RXD,
56 MX51_PAD_UART1_TXD__UART1_TXD,
57 MX51_PAD_UART1_RTS__UART1_RTS,
58 MX51_PAD_UART1_CTS__UART1_CTS,
61 MX51_PAD_UART2_RXD__UART2_RXD,
62 MX51_PAD_UART2_TXD__UART2_TXD,
65 MX51_PAD_EIM_D25__UART3_RXD,
66 MX51_PAD_EIM_D26__UART3_TXD,
67 MX51_PAD_EIM_D27__UART3_RTS,
68 MX51_PAD_EIM_D24__UART3_CTS,
71 MX51_PAD_EIM_D16__I2C1_SDA,
72 MX51_PAD_EIM_D19__I2C1_SCL,
75 MX51_PAD_KEY_COL4__I2C2_SCL,
76 MX51_PAD_KEY_COL5__I2C2_SDA,
79 MX51_PAD_I2C1_CLK__HSI2C_CLK,
80 MX51_PAD_I2C1_DAT__HSI2C_DAT,
83 MX51_PAD_USBH1_CLK__USBH1_CLK,
84 MX51_PAD_USBH1_DIR__USBH1_DIR,
85 MX51_PAD_USBH1_NXT__USBH1_NXT,
86 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
87 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
88 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
89 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
90 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
91 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
92 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
93 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
95 /* USB HUB reset line*/
96 MX51_PAD_GPIO_1_7__GPIO_1_7,
99 MX51_PAD_EIM_EB2__FEC_MDIO,
100 MX51_PAD_EIM_EB3__FEC_RDAT1,
101 MX51_PAD_EIM_CS2__FEC_RDAT2,
102 MX51_PAD_EIM_CS3__FEC_RDAT3,
103 MX51_PAD_EIM_CS4__FEC_RX_ER,
104 MX51_PAD_EIM_CS5__FEC_CRS,
105 MX51_PAD_NANDF_RB2__FEC_COL,
106 MX51_PAD_NANDF_RB3__FEC_RXCLK,
107 MX51_PAD_NANDF_RB6__FEC_RDAT0,
108 MX51_PAD_NANDF_RB7__FEC_TDAT0,
109 MX51_PAD_NANDF_CS2__FEC_TX_ER,
110 MX51_PAD_NANDF_CS3__FEC_MDC,
111 MX51_PAD_NANDF_CS4__FEC_TDAT1,
112 MX51_PAD_NANDF_CS5__FEC_TDAT2,
113 MX51_PAD_NANDF_CS6__FEC_TDAT3,
114 MX51_PAD_NANDF_CS7__FEC_TX_EN,
115 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
117 /* FEC PHY reset line */
118 MX51_PAD_EIM_A20__GPIO_2_14,
122 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
123 static const struct imxuart_platform_data uart_pdata __initconst = {
124 .flags = IMXUART_HAVE_RTSCTS,
127 static inline void mxc_init_imx_uart(void)
129 imx51_add_imx_uart(0, &uart_pdata);
130 imx51_add_imx_uart(1, &uart_pdata);
131 imx51_add_imx_uart(2, &uart_pdata);
133 #else /* !SERIAL_IMX */
134 static inline void mxc_init_imx_uart(void)
137 #endif /* SERIAL_IMX */
139 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
143 static struct imxi2c_platform_data babbage_hsi2c_data = {
147 static int gpio_usbh1_active(void)
149 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
150 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
153 /* Set USBH1_STP to GPIO and toggle it */
154 mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
155 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
158 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
161 gpio_direction_output(BABBAGE_USBH1_STP, 0);
162 gpio_set_value(BABBAGE_USBH1_STP, 1);
164 gpio_free(BABBAGE_USBH1_STP);
166 /* De-assert USB PHY RESETB */
167 mxc_iomux_v3_setup_pad(&phyreset_gpio);
168 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
171 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
174 gpio_direction_output(BABBAGE_PHY_RESET, 1);
178 static inline void babbage_usbhub_reset(void)
182 /* Bring USB hub out of reset */
183 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
185 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
188 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
190 /* USB HUB RESET - De-assert USB HUB RESET_N */
192 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
194 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
197 static inline void babbage_fec_reset(void)
202 ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
204 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
207 gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
208 gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
210 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
213 /* This function is board specific as the bit mask for the plldiv will also
214 be different for other Freescale SoCs, thus a common bitmask is not
215 possible and cannot get place in /plat-mxc/ehci.c.*/
216 static int initialize_otg_port(struct platform_device *pdev)
219 void __iomem *usb_base;
220 void __iomem *usbother_base;
222 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
223 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
225 /* Set the PHY clock to 19.2MHz */
226 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
227 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
228 v |= MX51_USB_PLL_DIV_19_2_MHZ;
229 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
234 static int initialize_usbh1_port(struct platform_device *pdev)
237 void __iomem *usb_base;
238 void __iomem *usbother_base;
240 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
241 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
243 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
244 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
245 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
250 static struct mxc_usbh_platform_data dr_utmi_config = {
251 .init = initialize_otg_port,
252 .portsc = MXC_EHCI_UTMI_16BIT,
253 .flags = MXC_EHCI_INTERNAL_PHY,
256 static struct fsl_usb2_platform_data usb_pdata = {
257 .operating_mode = FSL_USB2_DR_DEVICE,
258 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
261 static struct mxc_usbh_platform_data usbh1_config = {
262 .init = initialize_usbh1_port,
263 .portsc = MXC_EHCI_MODE_ULPI,
264 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
267 static int otg_mode_host;
269 static int __init babbage_otg_mode(char *options)
271 if (!strcmp(options, "host"))
273 else if (!strcmp(options, "device"))
276 pr_info("otg_mode neither \"host\" nor \"device\". "
277 "Defaulting to device\n");
280 __setup("otg_mode=", babbage_otg_mode);
283 * Board specific initialization.
285 static void __init mxc_board_init(void)
287 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
289 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
290 ARRAY_SIZE(mx51babbage_pads));
293 platform_add_devices(devices, ARRAY_SIZE(devices));
295 imx51_add_imx_i2c(0, &babbage_i2c_data);
296 imx51_add_imx_i2c(1, &babbage_i2c_data);
297 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
300 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
302 initialize_otg_port(NULL);
303 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
307 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
308 /* setback USBH1_STP to be function */
309 mxc_iomux_v3_setup_pad(&usbh1stp);
310 babbage_usbhub_reset();
313 static void __init mx51_babbage_timer_init(void)
315 mx51_clocks_init(32768, 24000000, 22579200, 0);
318 static struct sys_timer mxc_timer = {
319 .init = mx51_babbage_timer_init,
322 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
323 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
324 .phys_io = MX51_AIPS1_BASE_ADDR,
325 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
326 .boot_params = MX51_PHYS_OFFSET + 0x100,
327 .map_io = mx51_map_io,
328 .init_irq = mx51_init_irq,
329 .init_machine = mxc_board_init,