2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/sysdev.h>
19 #include <linux/amba/bus.h>
20 #include <linux/amba/kmi.h>
21 #include <linux/amba/clcd.h>
22 #include <linux/amba/mmci.h>
25 #include <asm/clkdev.h>
26 #include <mach/clkdev.h>
27 #include <mach/hardware.h>
28 #include <mach/platform.h>
30 #include <asm/setup.h>
31 #include <asm/mach-types.h>
32 #include <asm/hardware/icst525.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/flash.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/time.h>
45 #define INTCP_PA_MMC_BASE 0x1c000000
46 #define INTCP_PA_AACI_BASE 0x1d000000
48 #define INTCP_PA_FLASH_BASE 0x24000000
49 #define INTCP_FLASH_SIZE SZ_32M
51 #define INTCP_PA_CLCD_BASE 0xc0000000
53 #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40
54 #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
55 #define INTCP_VA_SIC_BASE IO_ADDRESS(0xca000000)
57 #define INTCP_PA_ETH_BASE 0xc8000000
58 #define INTCP_ETH_SIZE 0x10
60 #define INTCP_VA_CTRL_BASE IO_ADDRESS(0xcb000000)
61 #define INTCP_FLASHPROG 0x04
62 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
63 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
67 * f1000000 10000000 Core module registers
68 * f1100000 11000000 System controller registers
69 * f1200000 12000000 EBI registers
70 * f1300000 13000000 Counter/Timer
71 * f1400000 14000000 Interrupt controller
72 * f1600000 16000000 UART 0
73 * f1700000 17000000 UART 1
74 * f1a00000 1a000000 Debug LEDs
75 * f1b00000 1b000000 GPIO
78 static struct map_desc intcp_io_desc[] __initdata = {
80 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
81 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
85 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
86 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
90 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
91 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
95 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
96 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
100 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
101 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
105 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
106 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
110 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
111 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
115 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
116 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
120 .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
121 .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
125 .virtual = IO_ADDRESS(0xca000000),
126 .pfn = __phys_to_pfn(0xca000000),
130 .virtual = IO_ADDRESS(0xcb000000),
131 .pfn = __phys_to_pfn(0xcb000000),
137 static void __init intcp_map_io(void)
139 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
142 #define cic_writel __raw_writel
143 #define cic_readl __raw_readl
144 #define pic_writel __raw_writel
145 #define pic_readl __raw_readl
146 #define sic_writel __raw_writel
147 #define sic_readl __raw_readl
149 static void cic_mask_irq(unsigned int irq)
151 irq -= IRQ_CIC_START;
152 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
155 static void cic_unmask_irq(unsigned int irq)
157 irq -= IRQ_CIC_START;
158 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
161 static struct irq_chip cic_chip = {
164 .mask = cic_mask_irq,
165 .unmask = cic_unmask_irq,
168 static void pic_mask_irq(unsigned int irq)
170 irq -= IRQ_PIC_START;
171 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
174 static void pic_unmask_irq(unsigned int irq)
176 irq -= IRQ_PIC_START;
177 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
180 static struct irq_chip pic_chip = {
183 .mask = pic_mask_irq,
184 .unmask = pic_unmask_irq,
187 static void sic_mask_irq(unsigned int irq)
189 irq -= IRQ_SIC_START;
190 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
193 static void sic_unmask_irq(unsigned int irq)
195 irq -= IRQ_SIC_START;
196 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
199 static struct irq_chip sic_chip = {
202 .mask = sic_mask_irq,
203 .unmask = sic_unmask_irq,
207 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
209 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
212 do_bad_IRQ(irq, desc);
217 irq = ffs(status) - 1;
218 status &= ~(1 << irq);
220 irq += IRQ_SIC_START;
222 generic_handle_irq(irq);
226 static void __init intcp_init_irq(void)
231 * Disable all interrupt sources
233 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
234 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
236 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
241 set_irq_chip(i, &pic_chip);
242 set_irq_handler(i, handle_level_irq);
243 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
246 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
247 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
249 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
250 set_irq_chip(i, &cic_chip);
251 set_irq_handler(i, handle_level_irq);
252 set_irq_flags(i, IRQF_VALID);
255 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
256 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
258 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
259 set_irq_chip(i, &sic_chip);
260 set_irq_handler(i, handle_level_irq);
261 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
264 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
270 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
271 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
273 static const struct icst525_params cp_auxvco_params = {
282 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
286 val = readl(CM_AUXOSC) & ~0x7ffff;
287 val |= vco.v | (vco.r << 9) | (vco.s << 16);
289 writel(0xa05f, CM_LOCK);
290 writel(val, CM_AUXOSC);
294 static struct clk cp_auxclk = {
295 .params = &cp_auxvco_params,
296 .setvco = cp_auxvco_set,
299 static struct clk_lookup cp_lookups[] = {
309 static int intcp_flash_init(void)
313 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
314 val |= CINTEGRATOR_FLASHPROG_FLWREN;
315 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
320 static void intcp_flash_exit(void)
324 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
325 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
326 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
329 static void intcp_flash_set_vpp(int on)
333 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
335 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
337 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
338 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
341 static struct flash_platform_data intcp_flash_data = {
342 .map_name = "cfi_probe",
344 .init = intcp_flash_init,
345 .exit = intcp_flash_exit,
346 .set_vpp = intcp_flash_set_vpp,
349 static struct resource intcp_flash_resource = {
350 .start = INTCP_PA_FLASH_BASE,
351 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
352 .flags = IORESOURCE_MEM,
355 static struct platform_device intcp_flash_device = {
359 .platform_data = &intcp_flash_data,
362 .resource = &intcp_flash_resource,
365 static struct resource smc91x_resources[] = {
367 .start = INTCP_PA_ETH_BASE,
368 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
369 .flags = IORESOURCE_MEM,
372 .start = IRQ_CP_ETHINT,
373 .end = IRQ_CP_ETHINT,
374 .flags = IORESOURCE_IRQ,
378 static struct platform_device smc91x_device = {
381 .num_resources = ARRAY_SIZE(smc91x_resources),
382 .resource = smc91x_resources,
385 static struct platform_device *intcp_devs[] __initdata = {
391 * It seems that the card insertion interrupt remains active after
392 * we've acknowledged it. We therefore ignore the interrupt, and
393 * rely on reading it from the SIC. This also means that we must
394 * clear the latched interrupt.
396 static unsigned int mmc_status(struct device *dev)
398 unsigned int status = readl(IO_ADDRESS(0xca000000) + 4);
399 writel(8, IO_ADDRESS(0xcb000000) + 8);
404 static struct mmci_platform_data mmc_data = {
405 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
406 .status = mmc_status,
411 static struct amba_device mmc_device = {
413 .init_name = "mb:1c",
414 .platform_data = &mmc_data,
417 .start = INTCP_PA_MMC_BASE,
418 .end = INTCP_PA_MMC_BASE + SZ_4K - 1,
419 .flags = IORESOURCE_MEM,
421 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
425 static struct amba_device aaci_device = {
427 .init_name = "mb:1d",
430 .start = INTCP_PA_AACI_BASE,
431 .end = INTCP_PA_AACI_BASE + SZ_4K - 1,
432 .flags = IORESOURCE_MEM,
434 .irq = { IRQ_CP_AACIINT, NO_IRQ },
442 static struct clcd_panel vga = {
456 .vmode = FB_VMODE_NONINTERLACED,
460 .tim2 = TIM2_BCD | TIM2_IPC,
461 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
467 * Ensure VGA is selected.
469 static void cp_clcd_enable(struct clcd_fb *fb)
473 if (fb->fb.var.bits_per_pixel <= 8)
474 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
475 else if (fb->fb.var.bits_per_pixel <= 16)
476 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
477 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
478 | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
480 val = 0; /* no idea for this, don't trust the docs */
482 cm_control(CM_CTRL_LCDMUXSEL_MASK|
488 CM_CTRL_n24BITEN, val);
491 static unsigned long framesize = SZ_1M;
493 static int cp_clcd_setup(struct clcd_fb *fb)
499 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
501 if (!fb->fb.screen_base) {
502 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
506 fb->fb.fix.smem_start = dma;
507 fb->fb.fix.smem_len = framesize;
512 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
514 return dma_mmap_writecombine(&fb->dev->dev, vma,
516 fb->fb.fix.smem_start,
517 fb->fb.fix.smem_len);
520 static void cp_clcd_remove(struct clcd_fb *fb)
522 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
523 fb->fb.screen_base, fb->fb.fix.smem_start);
526 static struct clcd_board clcd_data = {
527 .name = "Integrator/CP",
528 .check = clcdfb_check,
529 .decode = clcdfb_decode,
530 .enable = cp_clcd_enable,
531 .setup = cp_clcd_setup,
532 .mmap = cp_clcd_mmap,
533 .remove = cp_clcd_remove,
536 static struct amba_device clcd_device = {
538 .init_name = "mb:c0",
539 .coherent_dma_mask = ~0,
540 .platform_data = &clcd_data,
543 .start = INTCP_PA_CLCD_BASE,
544 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
545 .flags = IORESOURCE_MEM,
548 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
552 static struct amba_device *amba_devs[] __initdata = {
558 static void __init intcp_init(void)
562 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
563 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
565 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
566 struct amba_device *d = amba_devs[i];
567 amba_device_register(d, &iomem_resource);
571 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
573 static void __init intcp_timer_init(void)
575 integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
578 static struct sys_timer cp_timer = {
579 .init = intcp_timer_init,
582 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
583 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
584 .phys_io = 0x16000000,
585 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
586 .boot_params = 0x00000100,
587 .map_io = intcp_map_io,
588 .init_irq = intcp_init_irq,
590 .init_machine = intcp_init,