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tg3: Fix firmware event timeouts
[net-next-2.6.git] / drivers / net / tg3.c
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1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
26#include <linux/in.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36#include <linux/brcmphy.h>
37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
41#include <linux/prefetch.h>
42#include <linux/dma-mapping.h>
43
44#include <net/checksum.h>
45#include <net/ip.h>
46
47#include <asm/system.h>
48#include <asm/io.h>
49#include <asm/byteorder.h>
50#include <asm/uaccess.h>
51
52#ifdef CONFIG_SPARC
53#include <asm/idprom.h>
54#include <asm/prom.h>
55#endif
56
57#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
58#define TG3_VLAN_TAG_USED 1
59#else
60#define TG3_VLAN_TAG_USED 0
61#endif
62
63#define TG3_TSO_SUPPORT 1
64
65#include "tg3.h"
66
67#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": "
69#define DRV_MODULE_VERSION "3.93"
70#define DRV_MODULE_RELDATE "May 22, 2008"
71
72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0
74#define TG3_DEF_TX_MODE 0
75#define TG3_DEF_MSG_ENABLE \
76 (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR)
84
85/* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
87 */
88#define TG3_TX_TIMEOUT (5 * HZ)
89
90/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
94
95/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
98 */
99#define TG3_RX_RING_SIZE 512
100#define TG3_DEF_RX_RING_PENDING 200
101#define TG3_RX_JUMBO_RING_SIZE 256
102#define TG3_DEF_RX_JUMBO_RING_PENDING 100
103
104/* Do not place this n-ring entries value into the tp struct itself,
105 * we really want to expose these constants to GCC so that modulo et
106 * al. operations are done with shifts and masks instead of with
107 * hw multiply/modulo instructions. Another solution would be to
108 * replace things like '% foo' with '& (foo - 1)'.
109 */
110#define TG3_RX_RCB_RING_SIZE(tp) \
111 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
112
113#define TG3_TX_RING_SIZE 512
114#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
115
116#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_RING_SIZE)
118#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_JUMBO_RING_SIZE)
120#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RCB_RING_SIZE(tp))
122#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
123 TG3_TX_RING_SIZE)
124#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
125
126#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
127#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
128
129/* minimum number of free TX descriptors required to wake up TX process */
130#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
131
132/* number of ETHTOOL_GSTATS u64's */
133#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
134
135#define TG3_NUM_TEST 6
136
137static char version[] __devinitdata =
138 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
139
140MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
141MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
142MODULE_LICENSE("GPL");
143MODULE_VERSION(DRV_MODULE_VERSION);
144
145static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
146module_param(tg3_debug, int, 0);
147MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
148
149static struct pci_device_id tg3_pci_tbl[] = {
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
209 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
210 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
212 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
213 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
214 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
215 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
216 {}
217};
218
219MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
220
221static const struct {
222 const char string[ETH_GSTRING_LEN];
223} ethtool_stats_keys[TG3_NUM_STATS] = {
224 { "rx_octets" },
225 { "rx_fragments" },
226 { "rx_ucast_packets" },
227 { "rx_mcast_packets" },
228 { "rx_bcast_packets" },
229 { "rx_fcs_errors" },
230 { "rx_align_errors" },
231 { "rx_xon_pause_rcvd" },
232 { "rx_xoff_pause_rcvd" },
233 { "rx_mac_ctrl_rcvd" },
234 { "rx_xoff_entered" },
235 { "rx_frame_too_long_errors" },
236 { "rx_jabbers" },
237 { "rx_undersize_packets" },
238 { "rx_in_length_errors" },
239 { "rx_out_length_errors" },
240 { "rx_64_or_less_octet_packets" },
241 { "rx_65_to_127_octet_packets" },
242 { "rx_128_to_255_octet_packets" },
243 { "rx_256_to_511_octet_packets" },
244 { "rx_512_to_1023_octet_packets" },
245 { "rx_1024_to_1522_octet_packets" },
246 { "rx_1523_to_2047_octet_packets" },
247 { "rx_2048_to_4095_octet_packets" },
248 { "rx_4096_to_8191_octet_packets" },
249 { "rx_8192_to_9022_octet_packets" },
250
251 { "tx_octets" },
252 { "tx_collisions" },
253
254 { "tx_xon_sent" },
255 { "tx_xoff_sent" },
256 { "tx_flow_control" },
257 { "tx_mac_errors" },
258 { "tx_single_collisions" },
259 { "tx_mult_collisions" },
260 { "tx_deferred" },
261 { "tx_excessive_collisions" },
262 { "tx_late_collisions" },
263 { "tx_collide_2times" },
264 { "tx_collide_3times" },
265 { "tx_collide_4times" },
266 { "tx_collide_5times" },
267 { "tx_collide_6times" },
268 { "tx_collide_7times" },
269 { "tx_collide_8times" },
270 { "tx_collide_9times" },
271 { "tx_collide_10times" },
272 { "tx_collide_11times" },
273 { "tx_collide_12times" },
274 { "tx_collide_13times" },
275 { "tx_collide_14times" },
276 { "tx_collide_15times" },
277 { "tx_ucast_packets" },
278 { "tx_mcast_packets" },
279 { "tx_bcast_packets" },
280 { "tx_carrier_sense_errors" },
281 { "tx_discards" },
282 { "tx_errors" },
283
284 { "dma_writeq_full" },
285 { "dma_write_prioq_full" },
286 { "rxbds_empty" },
287 { "rx_discards" },
288 { "rx_errors" },
289 { "rx_threshold_hit" },
290
291 { "dma_readq_full" },
292 { "dma_read_prioq_full" },
293 { "tx_comp_queue_full" },
294
295 { "ring_set_send_prod_index" },
296 { "ring_status_update" },
297 { "nic_irqs" },
298 { "nic_avoided_irqs" },
299 { "nic_tx_threshold_hit" }
300};
301
302static const struct {
303 const char string[ETH_GSTRING_LEN];
304} ethtool_test_keys[TG3_NUM_TEST] = {
305 { "nvram test (online) " },
306 { "link test (online) " },
307 { "register test (offline)" },
308 { "memory test (offline)" },
309 { "loopback test (offline)" },
310 { "interrupt test (offline)" },
311};
312
313static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
314{
315 writel(val, tp->regs + off);
316}
317
318static u32 tg3_read32(struct tg3 *tp, u32 off)
319{
320 return (readl(tp->regs + off));
321}
322
323static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
324{
325 writel(val, tp->aperegs + off);
326}
327
328static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
329{
330 return (readl(tp->aperegs + off));
331}
332
333static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
334{
335 unsigned long flags;
336
337 spin_lock_irqsave(&tp->indirect_lock, flags);
338 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
340 spin_unlock_irqrestore(&tp->indirect_lock, flags);
341}
342
343static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
344{
345 writel(val, tp->regs + off);
346 readl(tp->regs + off);
347}
348
349static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
350{
351 unsigned long flags;
352 u32 val;
353
354 spin_lock_irqsave(&tp->indirect_lock, flags);
355 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
356 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
357 spin_unlock_irqrestore(&tp->indirect_lock, flags);
358 return val;
359}
360
361static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
362{
363 unsigned long flags;
364
365 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
366 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
367 TG3_64BIT_REG_LOW, val);
368 return;
369 }
370 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
371 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
372 TG3_64BIT_REG_LOW, val);
373 return;
374 }
375
376 spin_lock_irqsave(&tp->indirect_lock, flags);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
378 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
379 spin_unlock_irqrestore(&tp->indirect_lock, flags);
380
381 /* In indirect mode when disabling interrupts, we also need
382 * to clear the interrupt bit in the GRC local ctrl register.
383 */
384 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
385 (val == 0x1)) {
386 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
387 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
388 }
389}
390
391static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
392{
393 unsigned long flags;
394 u32 val;
395
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
398 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
399 spin_unlock_irqrestore(&tp->indirect_lock, flags);
400 return val;
401}
402
403/* usec_wait specifies the wait time in usec when writing to certain registers
404 * where it is unsafe to read back the register without some delay.
405 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
406 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
407 */
408static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
409{
410 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
411 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
412 /* Non-posted methods */
413 tp->write32(tp, off, val);
414 else {
415 /* Posted method */
416 tg3_write32(tp, off, val);
417 if (usec_wait)
418 udelay(usec_wait);
419 tp->read32(tp, off);
420 }
421 /* Wait again after the read for the posted method to guarantee that
422 * the wait time is met.
423 */
424 if (usec_wait)
425 udelay(usec_wait);
426}
427
428static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
429{
430 tp->write32_mbox(tp, off, val);
431 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
432 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
433 tp->read32_mbox(tp, off);
434}
435
436static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
437{
438 void __iomem *mbox = tp->regs + off;
439 writel(val, mbox);
440 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
441 writel(val, mbox);
442 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
443 readl(mbox);
444}
445
446static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
447{
448 return (readl(tp->regs + off + GRCMBOX_BASE));
449}
450
451static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
452{
453 writel(val, tp->regs + off + GRCMBOX_BASE);
454}
455
456#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
457#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
458#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
459#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
460#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
461
462#define tw32(reg,val) tp->write32(tp, reg, val)
463#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
464#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
465#define tr32(reg) tp->read32(tp, reg)
466
467static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
468{
469 unsigned long flags;
470
471 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
472 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
473 return;
474
475 spin_lock_irqsave(&tp->indirect_lock, flags);
476 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
477 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
479
480 /* Always leave this as zero. */
481 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
482 } else {
483 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
484 tw32_f(TG3PCI_MEM_WIN_DATA, val);
485
486 /* Always leave this as zero. */
487 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
488 }
489 spin_unlock_irqrestore(&tp->indirect_lock, flags);
490}
491
492static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
493{
494 unsigned long flags;
495
496 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
497 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
498 *val = 0;
499 return;
500 }
501
502 spin_lock_irqsave(&tp->indirect_lock, flags);
503 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
505 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
506
507 /* Always leave this as zero. */
508 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
509 } else {
510 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
511 *val = tr32(TG3PCI_MEM_WIN_DATA);
512
513 /* Always leave this as zero. */
514 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
515 }
516 spin_unlock_irqrestore(&tp->indirect_lock, flags);
517}
518
519static void tg3_ape_lock_init(struct tg3 *tp)
520{
521 int i;
522
523 /* Make sure the driver hasn't any stale locks. */
524 for (i = 0; i < 8; i++)
525 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
526 APE_LOCK_GRANT_DRIVER);
527}
528
529static int tg3_ape_lock(struct tg3 *tp, int locknum)
530{
531 int i, off;
532 int ret = 0;
533 u32 status;
534
535 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
536 return 0;
537
538 switch (locknum) {
539 case TG3_APE_LOCK_GRC:
540 case TG3_APE_LOCK_MEM:
541 break;
542 default:
543 return -EINVAL;
544 }
545
546 off = 4 * locknum;
547
548 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
549
550 /* Wait for up to 1 millisecond to acquire lock. */
551 for (i = 0; i < 100; i++) {
552 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
553 if (status == APE_LOCK_GRANT_DRIVER)
554 break;
555 udelay(10);
556 }
557
558 if (status != APE_LOCK_GRANT_DRIVER) {
559 /* Revoke the lock request. */
560 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
561 APE_LOCK_GRANT_DRIVER);
562
563 ret = -EBUSY;
564 }
565
566 return ret;
567}
568
569static void tg3_ape_unlock(struct tg3 *tp, int locknum)
570{
571 int off;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return;
575
576 switch (locknum) {
577 case TG3_APE_LOCK_GRC:
578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return;
582 }
583
584 off = 4 * locknum;
585 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
586}
587
588static void tg3_disable_ints(struct tg3 *tp)
589{
590 tw32(TG3PCI_MISC_HOST_CTRL,
591 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
592 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
593}
594
595static inline void tg3_cond_int(struct tg3 *tp)
596{
597 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
598 (tp->hw_status->status & SD_STATUS_UPDATED))
599 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
600 else
601 tw32(HOSTCC_MODE, tp->coalesce_mode |
602 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
603}
604
605static void tg3_enable_ints(struct tg3 *tp)
606{
607 tp->irq_sync = 0;
608 wmb();
609
610 tw32(TG3PCI_MISC_HOST_CTRL,
611 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
612 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
613 (tp->last_tag << 24));
614 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
615 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
616 (tp->last_tag << 24));
617 tg3_cond_int(tp);
618}
619
620static inline unsigned int tg3_has_work(struct tg3 *tp)
621{
622 struct tg3_hw_status *sblk = tp->hw_status;
623 unsigned int work_exists = 0;
624
625 /* check for phy events */
626 if (!(tp->tg3_flags &
627 (TG3_FLAG_USE_LINKCHG_REG |
628 TG3_FLAG_POLL_SERDES))) {
629 if (sblk->status & SD_STATUS_LINK_CHG)
630 work_exists = 1;
631 }
632 /* check for RX/TX work to do */
633 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
634 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
635 work_exists = 1;
636
637 return work_exists;
638}
639
640/* tg3_restart_ints
641 * similar to tg3_enable_ints, but it accurately determines whether there
642 * is new work pending and can return without flushing the PIO write
643 * which reenables interrupts
644 */
645static void tg3_restart_ints(struct tg3 *tp)
646{
647 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
648 tp->last_tag << 24);
649 mmiowb();
650
651 /* When doing tagged status, this work check is unnecessary.
652 * The last_tag we write above tells the chip which piece of
653 * work we've completed.
654 */
655 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
656 tg3_has_work(tp))
657 tw32(HOSTCC_MODE, tp->coalesce_mode |
658 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
659}
660
661static inline void tg3_netif_stop(struct tg3 *tp)
662{
663 tp->dev->trans_start = jiffies; /* prevent tx timeout */
664 napi_disable(&tp->napi);
665 netif_tx_disable(tp->dev);
666}
667
668static inline void tg3_netif_start(struct tg3 *tp)
669{
670 netif_wake_queue(tp->dev);
671 /* NOTE: unconditional netif_wake_queue is only appropriate
672 * so long as all callers are assured to have free tx slots
673 * (such as after tg3_init_hw)
674 */
675 napi_enable(&tp->napi);
676 tp->hw_status->status |= SD_STATUS_UPDATED;
677 tg3_enable_ints(tp);
678}
679
680static void tg3_switch_clocks(struct tg3 *tp)
681{
682 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
683 u32 orig_clock_ctrl;
684
685 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
686 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
687 return;
688
689 orig_clock_ctrl = clock_ctrl;
690 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
691 CLOCK_CTRL_CLKRUN_OENABLE |
692 0x1f);
693 tp->pci_clock_ctrl = clock_ctrl;
694
695 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
696 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
697 tw32_wait_f(TG3PCI_CLOCK_CTRL,
698 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
699 }
700 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
701 tw32_wait_f(TG3PCI_CLOCK_CTRL,
702 clock_ctrl |
703 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
704 40);
705 tw32_wait_f(TG3PCI_CLOCK_CTRL,
706 clock_ctrl | (CLOCK_CTRL_ALTCLK),
707 40);
708 }
709 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
710}
711
712#define PHY_BUSY_LOOPS 5000
713
714static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
715{
716 u32 frame_val;
717 unsigned int loops;
718 int ret;
719
720 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
721 tw32_f(MAC_MI_MODE,
722 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
723 udelay(80);
724 }
725
726 *val = 0x0;
727
728 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
729 MI_COM_PHY_ADDR_MASK);
730 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
731 MI_COM_REG_ADDR_MASK);
732 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
733
734 tw32_f(MAC_MI_COM, frame_val);
735
736 loops = PHY_BUSY_LOOPS;
737 while (loops != 0) {
738 udelay(10);
739 frame_val = tr32(MAC_MI_COM);
740
741 if ((frame_val & MI_COM_BUSY) == 0) {
742 udelay(5);
743 frame_val = tr32(MAC_MI_COM);
744 break;
745 }
746 loops -= 1;
747 }
748
749 ret = -EBUSY;
750 if (loops != 0) {
751 *val = frame_val & MI_COM_DATA_MASK;
752 ret = 0;
753 }
754
755 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
756 tw32_f(MAC_MI_MODE, tp->mi_mode);
757 udelay(80);
758 }
759
760 return ret;
761}
762
763static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
764{
765 u32 frame_val;
766 unsigned int loops;
767 int ret;
768
769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
770 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
771 return 0;
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE,
775 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
776 udelay(80);
777 }
778
779 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
780 MI_COM_PHY_ADDR_MASK);
781 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
782 MI_COM_REG_ADDR_MASK);
783 frame_val |= (val & MI_COM_DATA_MASK);
784 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
785
786 tw32_f(MAC_MI_COM, frame_val);
787
788 loops = PHY_BUSY_LOOPS;
789 while (loops != 0) {
790 udelay(10);
791 frame_val = tr32(MAC_MI_COM);
792 if ((frame_val & MI_COM_BUSY) == 0) {
793 udelay(5);
794 frame_val = tr32(MAC_MI_COM);
795 break;
796 }
797 loops -= 1;
798 }
799
800 ret = -EBUSY;
801 if (loops != 0)
802 ret = 0;
803
804 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
805 tw32_f(MAC_MI_MODE, tp->mi_mode);
806 udelay(80);
807 }
808
809 return ret;
810}
811
812static int tg3_bmcr_reset(struct tg3 *tp)
813{
814 u32 phy_control;
815 int limit, err;
816
817 /* OK, reset it, and poll the BMCR_RESET bit until it
818 * clears or we time out.
819 */
820 phy_control = BMCR_RESET;
821 err = tg3_writephy(tp, MII_BMCR, phy_control);
822 if (err != 0)
823 return -EBUSY;
824
825 limit = 5000;
826 while (limit--) {
827 err = tg3_readphy(tp, MII_BMCR, &phy_control);
828 if (err != 0)
829 return -EBUSY;
830
831 if ((phy_control & BMCR_RESET) == 0) {
832 udelay(40);
833 break;
834 }
835 udelay(10);
836 }
837 if (limit <= 0)
838 return -EBUSY;
839
840 return 0;
841}
842
843static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
844{
845 struct tg3 *tp = (struct tg3 *)bp->priv;
846 u32 val;
847
848 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
849 return -EAGAIN;
850
851 if (tg3_readphy(tp, reg, &val))
852 return -EIO;
853
854 return val;
855}
856
857static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
858{
859 struct tg3 *tp = (struct tg3 *)bp->priv;
860
861 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
862 return -EAGAIN;
863
864 if (tg3_writephy(tp, reg, val))
865 return -EIO;
866
867 return 0;
868}
869
870static int tg3_mdio_reset(struct mii_bus *bp)
871{
872 return 0;
873}
874
875static void tg3_mdio_config(struct tg3 *tp)
876{
877 u32 val;
878
879 if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
880 PHY_INTERFACE_MODE_RGMII)
881 return;
882
883 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
884 MAC_PHYCFG1_RGMII_SND_STAT_EN);
885 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
886 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
887 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
888 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
889 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
890 }
891 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
892
893 val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
894 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
895 val |= MAC_PHYCFG2_INBAND_ENABLE;
896 tw32(MAC_PHYCFG2, val);
897
898 val = tr32(MAC_EXT_RGMII_MODE);
899 val &= ~(MAC_RGMII_MODE_RX_INT_B |
900 MAC_RGMII_MODE_RX_QUALITY |
901 MAC_RGMII_MODE_RX_ACTIVITY |
902 MAC_RGMII_MODE_RX_ENG_DET |
903 MAC_RGMII_MODE_TX_ENABLE |
904 MAC_RGMII_MODE_TX_LOWPWR |
905 MAC_RGMII_MODE_TX_RESET);
906 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
907 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
908 val |= MAC_RGMII_MODE_RX_INT_B |
909 MAC_RGMII_MODE_RX_QUALITY |
910 MAC_RGMII_MODE_RX_ACTIVITY |
911 MAC_RGMII_MODE_RX_ENG_DET;
912 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
913 val |= MAC_RGMII_MODE_TX_ENABLE |
914 MAC_RGMII_MODE_TX_LOWPWR |
915 MAC_RGMII_MODE_TX_RESET;
916 }
917 tw32(MAC_EXT_RGMII_MODE, val);
918}
919
920static void tg3_mdio_start(struct tg3 *tp)
921{
922 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
923 mutex_lock(&tp->mdio_bus.mdio_lock);
924 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
925 mutex_unlock(&tp->mdio_bus.mdio_lock);
926 }
927
928 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
929 tw32_f(MAC_MI_MODE, tp->mi_mode);
930 udelay(80);
931
932 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
933 tg3_mdio_config(tp);
934}
935
936static void tg3_mdio_stop(struct tg3 *tp)
937{
938 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
939 mutex_lock(&tp->mdio_bus.mdio_lock);
940 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
941 mutex_unlock(&tp->mdio_bus.mdio_lock);
942 }
943}
944
945static int tg3_mdio_init(struct tg3 *tp)
946{
947 int i;
948 u32 reg;
949 struct phy_device *phydev;
950 struct mii_bus *mdio_bus = &tp->mdio_bus;
951
952 tg3_mdio_start(tp);
953
954 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
955 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
956 return 0;
957
958 memset(mdio_bus, 0, sizeof(*mdio_bus));
959
960 mdio_bus->name = "tg3 mdio bus";
961 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
962 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
963 mdio_bus->priv = tp;
964 mdio_bus->dev = &tp->pdev->dev;
965 mdio_bus->read = &tg3_mdio_read;
966 mdio_bus->write = &tg3_mdio_write;
967 mdio_bus->reset = &tg3_mdio_reset;
968 mdio_bus->phy_mask = ~(1 << PHY_ADDR);
969 mdio_bus->irq = &tp->mdio_irq[0];
970
971 for (i = 0; i < PHY_MAX_ADDR; i++)
972 mdio_bus->irq[i] = PHY_POLL;
973
974 /* The bus registration will look for all the PHYs on the mdio bus.
975 * Unfortunately, it does not ensure the PHY is powered up before
976 * accessing the PHY ID registers. A chip reset is the
977 * quickest way to bring the device back to an operational state..
978 */
979 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
980 tg3_bmcr_reset(tp);
981
982 i = mdiobus_register(mdio_bus);
983 if (i) {
984 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
985 tp->dev->name, i);
986 return i;
987 }
988
989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
990
991 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
992
993 switch (phydev->phy_id) {
994 case TG3_PHY_ID_BCM50610:
995 phydev->interface = PHY_INTERFACE_MODE_RGMII;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
997 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
998 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
999 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1000 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1001 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1002 break;
1003 case TG3_PHY_ID_BCMAC131:
1004 phydev->interface = PHY_INTERFACE_MODE_MII;
1005 break;
1006 }
1007
1008 tg3_mdio_config(tp);
1009
1010 return 0;
1011}
1012
1013static void tg3_mdio_fini(struct tg3 *tp)
1014{
1015 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1016 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1017 mdiobus_unregister(&tp->mdio_bus);
1018 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1019 }
1020}
1021
1022/* tp->lock is held. */
1023static inline void tg3_generate_fw_event(struct tg3 *tp)
1024{
1025 u32 val;
1026
1027 val = tr32(GRC_RX_CPU_EVENT);
1028 val |= GRC_RX_CPU_DRIVER_EVENT;
1029 tw32_f(GRC_RX_CPU_EVENT, val);
1030
1031 tp->last_event_jiffies = jiffies;
1032}
1033
1034#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1035
1036/* tp->lock is held. */
1037static void tg3_wait_for_event_ack(struct tg3 *tp)
1038{
1039 int i;
1040 unsigned int delay_cnt;
1041 long time_remain;
1042
1043 /* If enough time has passed, no wait is necessary. */
1044 time_remain = (long)(tp->last_event_jiffies + 1 +
1045 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1046 (long)jiffies;
1047 if (time_remain < 0)
1048 return;
1049
1050 /* Check if we can shorten the wait time. */
1051 delay_cnt = jiffies_to_usecs(time_remain);
1052 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1053 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1054 delay_cnt = (delay_cnt >> 3) + 1;
1055
1056 for (i = 0; i < delay_cnt; i++) {
1057 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1058 break;
1059 udelay(8);
1060 }
1061}
1062
1063/* tp->lock is held. */
1064static void tg3_ump_link_report(struct tg3 *tp)
1065{
1066 u32 reg;
1067 u32 val;
1068
1069 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1070 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1071 return;
1072
1073 tg3_wait_for_event_ack(tp);
1074
1075 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1076
1077 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1078
1079 val = 0;
1080 if (!tg3_readphy(tp, MII_BMCR, &reg))
1081 val = reg << 16;
1082 if (!tg3_readphy(tp, MII_BMSR, &reg))
1083 val |= (reg & 0xffff);
1084 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1085
1086 val = 0;
1087 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1088 val = reg << 16;
1089 if (!tg3_readphy(tp, MII_LPA, &reg))
1090 val |= (reg & 0xffff);
1091 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1092
1093 val = 0;
1094 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1095 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1096 val = reg << 16;
1097 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1098 val |= (reg & 0xffff);
1099 }
1100 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1101
1102 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1103 val = reg << 16;
1104 else
1105 val = 0;
1106 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1107
1108 tg3_generate_fw_event(tp);
1109}
1110
1111static void tg3_link_report(struct tg3 *tp)
1112{
1113 if (!netif_carrier_ok(tp->dev)) {
1114 if (netif_msg_link(tp))
1115 printk(KERN_INFO PFX "%s: Link is down.\n",
1116 tp->dev->name);
1117 tg3_ump_link_report(tp);
1118 } else if (netif_msg_link(tp)) {
1119 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1120 tp->dev->name,
1121 (tp->link_config.active_speed == SPEED_1000 ?
1122 1000 :
1123 (tp->link_config.active_speed == SPEED_100 ?
1124 100 : 10)),
1125 (tp->link_config.active_duplex == DUPLEX_FULL ?
1126 "full" : "half"));
1127
1128 printk(KERN_INFO PFX
1129 "%s: Flow control is %s for TX and %s for RX.\n",
1130 tp->dev->name,
1131 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1132 "on" : "off",
1133 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1134 "on" : "off");
1135 tg3_ump_link_report(tp);
1136 }
1137}
1138
1139static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1140{
1141 u16 miireg;
1142
1143 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1144 miireg = ADVERTISE_PAUSE_CAP;
1145 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1146 miireg = ADVERTISE_PAUSE_ASYM;
1147 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1148 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1149 else
1150 miireg = 0;
1151
1152 return miireg;
1153}
1154
1155static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1156{
1157 u16 miireg;
1158
1159 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1160 miireg = ADVERTISE_1000XPAUSE;
1161 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1162 miireg = ADVERTISE_1000XPSE_ASYM;
1163 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1164 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1165 else
1166 miireg = 0;
1167
1168 return miireg;
1169}
1170
1171static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1172{
1173 u8 cap = 0;
1174
1175 if (lcladv & ADVERTISE_PAUSE_CAP) {
1176 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1177 if (rmtadv & LPA_PAUSE_CAP)
1178 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1179 else if (rmtadv & LPA_PAUSE_ASYM)
1180 cap = TG3_FLOW_CTRL_RX;
1181 } else {
1182 if (rmtadv & LPA_PAUSE_CAP)
1183 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1184 }
1185 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1186 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1187 cap = TG3_FLOW_CTRL_TX;
1188 }
1189
1190 return cap;
1191}
1192
1193static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1194{
1195 u8 cap = 0;
1196
1197 if (lcladv & ADVERTISE_1000XPAUSE) {
1198 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1199 if (rmtadv & LPA_1000XPAUSE)
1200 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1201 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1202 cap = TG3_FLOW_CTRL_RX;
1203 } else {
1204 if (rmtadv & LPA_1000XPAUSE)
1205 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1206 }
1207 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1208 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1209 cap = TG3_FLOW_CTRL_TX;
1210 }
1211
1212 return cap;
1213}
1214
1215static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1216{
1217 u8 autoneg;
1218 u8 flowctrl = 0;
1219 u32 old_rx_mode = tp->rx_mode;
1220 u32 old_tx_mode = tp->tx_mode;
1221
1222 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1223 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1224 else
1225 autoneg = tp->link_config.autoneg;
1226
1227 if (autoneg == AUTONEG_ENABLE &&
1228 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1229 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1230 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1231 else
1232 flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1233 } else
1234 flowctrl = tp->link_config.flowctrl;
1235
1236 tp->link_config.active_flowctrl = flowctrl;
1237
1238 if (flowctrl & TG3_FLOW_CTRL_RX)
1239 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1240 else
1241 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1242
1243 if (old_rx_mode != tp->rx_mode)
1244 tw32_f(MAC_RX_MODE, tp->rx_mode);
1245
1246 if (flowctrl & TG3_FLOW_CTRL_TX)
1247 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1248 else
1249 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1250
1251 if (old_tx_mode != tp->tx_mode)
1252 tw32_f(MAC_TX_MODE, tp->tx_mode);
1253}
1254
1255static void tg3_adjust_link(struct net_device *dev)
1256{
1257 u8 oldflowctrl, linkmesg = 0;
1258 u32 mac_mode, lcl_adv, rmt_adv;
1259 struct tg3 *tp = netdev_priv(dev);
1260 struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1261
1262 spin_lock(&tp->lock);
1263
1264 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1265 MAC_MODE_HALF_DUPLEX);
1266
1267 oldflowctrl = tp->link_config.active_flowctrl;
1268
1269 if (phydev->link) {
1270 lcl_adv = 0;
1271 rmt_adv = 0;
1272
1273 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1274 mac_mode |= MAC_MODE_PORT_MODE_MII;
1275 else
1276 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1277
1278 if (phydev->duplex == DUPLEX_HALF)
1279 mac_mode |= MAC_MODE_HALF_DUPLEX;
1280 else {
1281 lcl_adv = tg3_advert_flowctrl_1000T(
1282 tp->link_config.flowctrl);
1283
1284 if (phydev->pause)
1285 rmt_adv = LPA_PAUSE_CAP;
1286 if (phydev->asym_pause)
1287 rmt_adv |= LPA_PAUSE_ASYM;
1288 }
1289
1290 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1291 } else
1292 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1293
1294 if (mac_mode != tp->mac_mode) {
1295 tp->mac_mode = mac_mode;
1296 tw32_f(MAC_MODE, tp->mac_mode);
1297 udelay(40);
1298 }
1299
1300 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1301 tw32(MAC_TX_LENGTHS,
1302 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1303 (6 << TX_LENGTHS_IPG_SHIFT) |
1304 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1305 else
1306 tw32(MAC_TX_LENGTHS,
1307 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1308 (6 << TX_LENGTHS_IPG_SHIFT) |
1309 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1310
1311 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1312 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1313 phydev->speed != tp->link_config.active_speed ||
1314 phydev->duplex != tp->link_config.active_duplex ||
1315 oldflowctrl != tp->link_config.active_flowctrl)
1316 linkmesg = 1;
1317
1318 tp->link_config.active_speed = phydev->speed;
1319 tp->link_config.active_duplex = phydev->duplex;
1320
1321 spin_unlock(&tp->lock);
1322
1323 if (linkmesg)
1324 tg3_link_report(tp);
1325}
1326
1327static int tg3_phy_init(struct tg3 *tp)
1328{
1329 struct phy_device *phydev;
1330
1331 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1332 return 0;
1333
1334 /* Bring the PHY back to a known state. */
1335 tg3_bmcr_reset(tp);
1336
1337 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1338
1339 /* Attach the MAC to the PHY. */
1340 phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1341 phydev->dev_flags, phydev->interface);
1342 if (IS_ERR(phydev)) {
1343 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1344 return PTR_ERR(phydev);
1345 }
1346
1347 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1348
1349 /* Mask with MAC supported features. */
1350 phydev->supported &= (PHY_GBIT_FEATURES |
1351 SUPPORTED_Pause |
1352 SUPPORTED_Asym_Pause);
1353
1354 phydev->advertising = phydev->supported;
1355
1356 printk(KERN_INFO
1357 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1358 tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1359
1360 return 0;
1361}
1362
1363static void tg3_phy_start(struct tg3 *tp)
1364{
1365 struct phy_device *phydev;
1366
1367 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1368 return;
1369
1370 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1371
1372 if (tp->link_config.phy_is_low_power) {
1373 tp->link_config.phy_is_low_power = 0;
1374 phydev->speed = tp->link_config.orig_speed;
1375 phydev->duplex = tp->link_config.orig_duplex;
1376 phydev->autoneg = tp->link_config.orig_autoneg;
1377 phydev->advertising = tp->link_config.orig_advertising;
1378 }
1379
1380 phy_start(phydev);
1381
1382 phy_start_aneg(phydev);
1383}
1384
1385static void tg3_phy_stop(struct tg3 *tp)
1386{
1387 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1388 return;
1389
1390 phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1391}
1392
1393static void tg3_phy_fini(struct tg3 *tp)
1394{
1395 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1396 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1397 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1398 }
1399}
1400
1401static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1402{
1403 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1404 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1405}
1406
1407static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1408{
1409 u32 phy;
1410
1411 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1412 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1413 return;
1414
1415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1416 u32 ephy;
1417
1418 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1419 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1420 ephy | MII_TG3_EPHY_SHADOW_EN);
1421 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1422 if (enable)
1423 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1424 else
1425 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1426 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1427 }
1428 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1429 }
1430 } else {
1431 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1432 MII_TG3_AUXCTL_SHDWSEL_MISC;
1433 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1434 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1435 if (enable)
1436 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1437 else
1438 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1439 phy |= MII_TG3_AUXCTL_MISC_WREN;
1440 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1441 }
1442 }
1443}
1444
1445static void tg3_phy_set_wirespeed(struct tg3 *tp)
1446{
1447 u32 val;
1448
1449 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1450 return;
1451
1452 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1453 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1454 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1455 (val | (1 << 15) | (1 << 4)));
1456}
1457
1458static void tg3_phy_apply_otp(struct tg3 *tp)
1459{
1460 u32 otp, phy;
1461
1462 if (!tp->phy_otp)
1463 return;
1464
1465 otp = tp->phy_otp;
1466
1467 /* Enable SM_DSP clock and tx 6dB coding. */
1468 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1469 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1470 MII_TG3_AUXCTL_ACTL_TX_6DB;
1471 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1472
1473 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1474 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1475 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1476
1477 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1478 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1479 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1480
1481 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1482 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1483 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1484
1485 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1486 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1487
1488 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1489 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1490
1491 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1492 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1493 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1494
1495 /* Turn off SM_DSP clock. */
1496 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1497 MII_TG3_AUXCTL_ACTL_TX_6DB;
1498 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1499}
1500
1501static int tg3_wait_macro_done(struct tg3 *tp)
1502{
1503 int limit = 100;
1504
1505 while (limit--) {
1506 u32 tmp32;
1507
1508 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1509 if ((tmp32 & 0x1000) == 0)
1510 break;
1511 }
1512 }
1513 if (limit <= 0)
1514 return -EBUSY;
1515
1516 return 0;
1517}
1518
1519static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1520{
1521 static const u32 test_pat[4][6] = {
1522 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1523 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1524 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1525 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1526 };
1527 int chan;
1528
1529 for (chan = 0; chan < 4; chan++) {
1530 int i;
1531
1532 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1533 (chan * 0x2000) | 0x0200);
1534 tg3_writephy(tp, 0x16, 0x0002);
1535
1536 for (i = 0; i < 6; i++)
1537 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1538 test_pat[chan][i]);
1539
1540 tg3_writephy(tp, 0x16, 0x0202);
1541 if (tg3_wait_macro_done(tp)) {
1542 *resetp = 1;
1543 return -EBUSY;
1544 }
1545
1546 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1547 (chan * 0x2000) | 0x0200);
1548 tg3_writephy(tp, 0x16, 0x0082);
1549 if (tg3_wait_macro_done(tp)) {
1550 *resetp = 1;
1551 return -EBUSY;
1552 }
1553
1554 tg3_writephy(tp, 0x16, 0x0802);
1555 if (tg3_wait_macro_done(tp)) {
1556 *resetp = 1;
1557 return -EBUSY;
1558 }
1559
1560 for (i = 0; i < 6; i += 2) {
1561 u32 low, high;
1562
1563 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1564 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1565 tg3_wait_macro_done(tp)) {
1566 *resetp = 1;
1567 return -EBUSY;
1568 }
1569 low &= 0x7fff;
1570 high &= 0x000f;
1571 if (low != test_pat[chan][i] ||
1572 high != test_pat[chan][i+1]) {
1573 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1574 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1575 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1576
1577 return -EBUSY;
1578 }
1579 }
1580 }
1581
1582 return 0;
1583}
1584
1585static int tg3_phy_reset_chanpat(struct tg3 *tp)
1586{
1587 int chan;
1588
1589 for (chan = 0; chan < 4; chan++) {
1590 int i;
1591
1592 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1593 (chan * 0x2000) | 0x0200);
1594 tg3_writephy(tp, 0x16, 0x0002);
1595 for (i = 0; i < 6; i++)
1596 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1597 tg3_writephy(tp, 0x16, 0x0202);
1598 if (tg3_wait_macro_done(tp))
1599 return -EBUSY;
1600 }
1601
1602 return 0;
1603}
1604
1605static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1606{
1607 u32 reg32, phy9_orig;
1608 int retries, do_phy_reset, err;
1609
1610 retries = 10;
1611 do_phy_reset = 1;
1612 do {
1613 if (do_phy_reset) {
1614 err = tg3_bmcr_reset(tp);
1615 if (err)
1616 return err;
1617 do_phy_reset = 0;
1618 }
1619
1620 /* Disable transmitter and interrupt. */
1621 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1622 continue;
1623
1624 reg32 |= 0x3000;
1625 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1626
1627 /* Set full-duplex, 1000 mbps. */
1628 tg3_writephy(tp, MII_BMCR,
1629 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1630
1631 /* Set to master mode. */
1632 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1633 continue;
1634
1635 tg3_writephy(tp, MII_TG3_CTRL,
1636 (MII_TG3_CTRL_AS_MASTER |
1637 MII_TG3_CTRL_ENABLE_AS_MASTER));
1638
1639 /* Enable SM_DSP_CLOCK and 6dB. */
1640 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1641
1642 /* Block the PHY control access. */
1643 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1644 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1645
1646 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1647 if (!err)
1648 break;
1649 } while (--retries);
1650
1651 err = tg3_phy_reset_chanpat(tp);
1652 if (err)
1653 return err;
1654
1655 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1656 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1657
1658 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1659 tg3_writephy(tp, 0x16, 0x0000);
1660
1661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1663 /* Set Extended packet length bit for jumbo frames */
1664 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1665 }
1666 else {
1667 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1668 }
1669
1670 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1671
1672 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1673 reg32 &= ~0x3000;
1674 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1675 } else if (!err)
1676 err = -EBUSY;
1677
1678 return err;
1679}
1680
1681/* This will reset the tigon3 PHY if there is no valid
1682 * link unless the FORCE argument is non-zero.
1683 */
1684static int tg3_phy_reset(struct tg3 *tp)
1685{
1686 u32 cpmuctrl;
1687 u32 phy_status;
1688 int err;
1689
1690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1691 u32 val;
1692
1693 val = tr32(GRC_MISC_CFG);
1694 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1695 udelay(40);
1696 }
1697 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1698 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1699 if (err != 0)
1700 return -EBUSY;
1701
1702 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1703 netif_carrier_off(tp->dev);
1704 tg3_link_report(tp);
1705 }
1706
1707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1710 err = tg3_phy_reset_5703_4_5(tp);
1711 if (err)
1712 return err;
1713 goto out;
1714 }
1715
1716 cpmuctrl = 0;
1717 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1718 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1719 cpmuctrl = tr32(TG3_CPMU_CTRL);
1720 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1721 tw32(TG3_CPMU_CTRL,
1722 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1723 }
1724
1725 err = tg3_bmcr_reset(tp);
1726 if (err)
1727 return err;
1728
1729 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1730 u32 phy;
1731
1732 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1733 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1734
1735 tw32(TG3_CPMU_CTRL, cpmuctrl);
1736 }
1737
1738 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1739 u32 val;
1740
1741 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1742 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1743 CPMU_LSPD_1000MB_MACCLK_12_5) {
1744 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1745 udelay(40);
1746 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1747 }
1748
1749 /* Disable GPHY autopowerdown. */
1750 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1751 MII_TG3_MISC_SHDW_WREN |
1752 MII_TG3_MISC_SHDW_APD_SEL |
1753 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1754 }
1755
1756 tg3_phy_apply_otp(tp);
1757
1758out:
1759 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1760 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1761 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1762 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1763 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1764 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1765 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1766 }
1767 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1768 tg3_writephy(tp, 0x1c, 0x8d68);
1769 tg3_writephy(tp, 0x1c, 0x8d68);
1770 }
1771 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1772 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1773 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1775 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1776 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1777 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1778 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1779 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1780 }
1781 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1782 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1783 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1784 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1786 tg3_writephy(tp, MII_TG3_TEST1,
1787 MII_TG3_TEST1_TRIM_EN | 0x4);
1788 } else
1789 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1790 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1791 }
1792 /* Set Extended packet length bit (bit 14) on all chips that */
1793 /* support jumbo frames */
1794 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1795 /* Cannot do read-modify-write on 5401 */
1796 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1797 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1798 u32 phy_reg;
1799
1800 /* Set bit 14 with read-modify-write to preserve other bits */
1801 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1802 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1803 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1804 }
1805
1806 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1807 * jumbo frames transmission.
1808 */
1809 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1810 u32 phy_reg;
1811
1812 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1813 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1814 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1815 }
1816
1817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1818 /* adjust output voltage */
1819 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1820 }
1821
1822 tg3_phy_toggle_automdix(tp, 1);
1823 tg3_phy_set_wirespeed(tp);
1824 return 0;
1825}
1826
1827static void tg3_frob_aux_power(struct tg3 *tp)
1828{
1829 struct tg3 *tp_peer = tp;
1830
1831 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1832 return;
1833
1834 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1835 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1836 struct net_device *dev_peer;
1837
1838 dev_peer = pci_get_drvdata(tp->pdev_peer);
1839 /* remove_one() may have been run on the peer. */
1840 if (!dev_peer)
1841 tp_peer = tp;
1842 else
1843 tp_peer = netdev_priv(dev_peer);
1844 }
1845
1846 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1847 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1848 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1849 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1852 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1853 (GRC_LCLCTRL_GPIO_OE0 |
1854 GRC_LCLCTRL_GPIO_OE1 |
1855 GRC_LCLCTRL_GPIO_OE2 |
1856 GRC_LCLCTRL_GPIO_OUTPUT0 |
1857 GRC_LCLCTRL_GPIO_OUTPUT1),
1858 100);
1859 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1860 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1861 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1862 GRC_LCLCTRL_GPIO_OE1 |
1863 GRC_LCLCTRL_GPIO_OE2 |
1864 GRC_LCLCTRL_GPIO_OUTPUT0 |
1865 GRC_LCLCTRL_GPIO_OUTPUT1 |
1866 tp->grc_local_ctrl;
1867 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1868
1869 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1870 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1871
1872 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1873 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1874 } else {
1875 u32 no_gpio2;
1876 u32 grc_local_ctrl = 0;
1877
1878 if (tp_peer != tp &&
1879 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1880 return;
1881
1882 /* Workaround to prevent overdrawing Amps. */
1883 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1884 ASIC_REV_5714) {
1885 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1886 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1887 grc_local_ctrl, 100);
1888 }
1889
1890 /* On 5753 and variants, GPIO2 cannot be used. */
1891 no_gpio2 = tp->nic_sram_data_cfg &
1892 NIC_SRAM_DATA_CFG_NO_GPIO2;
1893
1894 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1895 GRC_LCLCTRL_GPIO_OE1 |
1896 GRC_LCLCTRL_GPIO_OE2 |
1897 GRC_LCLCTRL_GPIO_OUTPUT1 |
1898 GRC_LCLCTRL_GPIO_OUTPUT2;
1899 if (no_gpio2) {
1900 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1901 GRC_LCLCTRL_GPIO_OUTPUT2);
1902 }
1903 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1904 grc_local_ctrl, 100);
1905
1906 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1907
1908 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1909 grc_local_ctrl, 100);
1910
1911 if (!no_gpio2) {
1912 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1913 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1914 grc_local_ctrl, 100);
1915 }
1916 }
1917 } else {
1918 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1919 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1920 if (tp_peer != tp &&
1921 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1922 return;
1923
1924 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1925 (GRC_LCLCTRL_GPIO_OE1 |
1926 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1927
1928 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1929 GRC_LCLCTRL_GPIO_OE1, 100);
1930
1931 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1932 (GRC_LCLCTRL_GPIO_OE1 |
1933 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1934 }
1935 }
1936}
1937
1938static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1939{
1940 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1941 return 1;
1942 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1943 if (speed != SPEED_10)
1944 return 1;
1945 } else if (speed == SPEED_10)
1946 return 1;
1947
1948 return 0;
1949}
1950
1951static int tg3_setup_phy(struct tg3 *, int);
1952
1953#define RESET_KIND_SHUTDOWN 0
1954#define RESET_KIND_INIT 1
1955#define RESET_KIND_SUSPEND 2
1956
1957static void tg3_write_sig_post_reset(struct tg3 *, int);
1958static int tg3_halt_cpu(struct tg3 *, u32);
1959static int tg3_nvram_lock(struct tg3 *);
1960static void tg3_nvram_unlock(struct tg3 *);
1961
1962static void tg3_power_down_phy(struct tg3 *tp)
1963{
1964 u32 val;
1965
1966 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1967 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1968 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1969 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1970
1971 sg_dig_ctrl |=
1972 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1973 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1974 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1975 }
1976 return;
1977 }
1978
1979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1980 tg3_bmcr_reset(tp);
1981 val = tr32(GRC_MISC_CFG);
1982 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1983 udelay(40);
1984 return;
1985 } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1986 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1987 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1988 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1989 }
1990
1991 /* The PHY should not be powered down on some chips because
1992 * of bugs.
1993 */
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1996 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1997 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1998 return;
1999
2000 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
2001 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2002 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2003 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2004 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2005 }
2006
2007 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2008}
2009
2010static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2011{
2012 u32 misc_host_ctrl;
2013
2014 /* Make sure register accesses (indirect or otherwise)
2015 * will function correctly.
2016 */
2017 pci_write_config_dword(tp->pdev,
2018 TG3PCI_MISC_HOST_CTRL,
2019 tp->misc_host_ctrl);
2020
2021 switch (state) {
2022 case PCI_D0:
2023 pci_enable_wake(tp->pdev, state, false);
2024 pci_set_power_state(tp->pdev, PCI_D0);
2025
2026 /* Switch out of Vaux if it is a NIC */
2027 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2028 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2029
2030 return 0;
2031
2032 case PCI_D1:
2033 case PCI_D2:
2034 case PCI_D3hot:
2035 break;
2036
2037 default:
2038 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2039 tp->dev->name, state);
2040 return -EINVAL;
2041 }
2042 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2043 tw32(TG3PCI_MISC_HOST_CTRL,
2044 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2045
2046 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2047 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2048 !tp->link_config.phy_is_low_power) {
2049 struct phy_device *phydev;
2050 u32 advertising;
2051
2052 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2053
2054 tp->link_config.phy_is_low_power = 1;
2055
2056 tp->link_config.orig_speed = phydev->speed;
2057 tp->link_config.orig_duplex = phydev->duplex;
2058 tp->link_config.orig_autoneg = phydev->autoneg;
2059 tp->link_config.orig_advertising = phydev->advertising;
2060
2061 advertising = ADVERTISED_TP |
2062 ADVERTISED_Pause |
2063 ADVERTISED_Autoneg |
2064 ADVERTISED_10baseT_Half;
2065
2066 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2067 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2068 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2069 advertising |=
2070 ADVERTISED_100baseT_Half |
2071 ADVERTISED_100baseT_Full |
2072 ADVERTISED_10baseT_Full;
2073 else
2074 advertising |= ADVERTISED_10baseT_Full;
2075 }
2076
2077 phydev->advertising = advertising;
2078
2079 phy_start_aneg(phydev);
2080 }
2081 } else {
2082 if (tp->link_config.phy_is_low_power == 0) {
2083 tp->link_config.phy_is_low_power = 1;
2084 tp->link_config.orig_speed = tp->link_config.speed;
2085 tp->link_config.orig_duplex = tp->link_config.duplex;
2086 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2087 }
2088
2089 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2090 tp->link_config.speed = SPEED_10;
2091 tp->link_config.duplex = DUPLEX_HALF;
2092 tp->link_config.autoneg = AUTONEG_ENABLE;
2093 tg3_setup_phy(tp, 0);
2094 }
2095 }
2096
2097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2098 u32 val;
2099
2100 val = tr32(GRC_VCPU_EXT_CTRL);
2101 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2102 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2103 int i;
2104 u32 val;
2105
2106 for (i = 0; i < 200; i++) {
2107 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2108 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2109 break;
2110 msleep(1);
2111 }
2112 }
2113 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2114 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2115 WOL_DRV_STATE_SHUTDOWN |
2116 WOL_DRV_WOL |
2117 WOL_SET_MAGIC_PKT);
2118
2119 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2120 u32 mac_mode;
2121
2122 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2123 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2124 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2125 udelay(40);
2126 }
2127
2128 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2129 mac_mode = MAC_MODE_PORT_MODE_GMII;
2130 else
2131 mac_mode = MAC_MODE_PORT_MODE_MII;
2132
2133 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2135 ASIC_REV_5700) {
2136 u32 speed = (tp->tg3_flags &
2137 TG3_FLAG_WOL_SPEED_100MB) ?
2138 SPEED_100 : SPEED_10;
2139 if (tg3_5700_link_polarity(tp, speed))
2140 mac_mode |= MAC_MODE_LINK_POLARITY;
2141 else
2142 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2143 }
2144 } else {
2145 mac_mode = MAC_MODE_PORT_MODE_TBI;
2146 }
2147
2148 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2149 tw32(MAC_LED_CTRL, tp->led_ctrl);
2150
2151 if (pci_pme_capable(tp->pdev, state) &&
2152 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2153 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2154
2155 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2156 mac_mode |= tp->mac_mode &
2157 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2158 if (mac_mode & MAC_MODE_APE_TX_EN)
2159 mac_mode |= MAC_MODE_TDE_ENABLE;
2160 }
2161
2162 tw32_f(MAC_MODE, mac_mode);
2163 udelay(100);
2164
2165 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2166 udelay(10);
2167 }
2168
2169 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2170 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2172 u32 base_val;
2173
2174 base_val = tp->pci_clock_ctrl;
2175 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2176 CLOCK_CTRL_TXCLK_DISABLE);
2177
2178 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2179 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2180 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2181 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2182 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2183 /* do nothing */
2184 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2185 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2186 u32 newbits1, newbits2;
2187
2188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2190 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2191 CLOCK_CTRL_TXCLK_DISABLE |
2192 CLOCK_CTRL_ALTCLK);
2193 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2194 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2195 newbits1 = CLOCK_CTRL_625_CORE;
2196 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2197 } else {
2198 newbits1 = CLOCK_CTRL_ALTCLK;
2199 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2200 }
2201
2202 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2203 40);
2204
2205 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2206 40);
2207
2208 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2209 u32 newbits3;
2210
2211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2213 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2214 CLOCK_CTRL_TXCLK_DISABLE |
2215 CLOCK_CTRL_44MHZ_CORE);
2216 } else {
2217 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2218 }
2219
2220 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2221 tp->pci_clock_ctrl | newbits3, 40);
2222 }
2223 }
2224
2225 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2226 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2227 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2228 tg3_power_down_phy(tp);
2229
2230 tg3_frob_aux_power(tp);
2231
2232 /* Workaround for unstable PLL clock */
2233 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2234 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2235 u32 val = tr32(0x7d00);
2236
2237 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2238 tw32(0x7d00, val);
2239 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2240 int err;
2241
2242 err = tg3_nvram_lock(tp);
2243 tg3_halt_cpu(tp, RX_CPU_BASE);
2244 if (!err)
2245 tg3_nvram_unlock(tp);
2246 }
2247 }
2248
2249 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2250
2251 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
2252 pci_enable_wake(tp->pdev, state, true);
2253
2254 /* Finally, set the new power state. */
2255 pci_set_power_state(tp->pdev, state);
2256
2257 return 0;
2258}
2259
2260static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2261{
2262 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2263 case MII_TG3_AUX_STAT_10HALF:
2264 *speed = SPEED_10;
2265 *duplex = DUPLEX_HALF;
2266 break;
2267
2268 case MII_TG3_AUX_STAT_10FULL:
2269 *speed = SPEED_10;
2270 *duplex = DUPLEX_FULL;
2271 break;
2272
2273 case MII_TG3_AUX_STAT_100HALF:
2274 *speed = SPEED_100;
2275 *duplex = DUPLEX_HALF;
2276 break;
2277
2278 case MII_TG3_AUX_STAT_100FULL:
2279 *speed = SPEED_100;
2280 *duplex = DUPLEX_FULL;
2281 break;
2282
2283 case MII_TG3_AUX_STAT_1000HALF:
2284 *speed = SPEED_1000;
2285 *duplex = DUPLEX_HALF;
2286 break;
2287
2288 case MII_TG3_AUX_STAT_1000FULL:
2289 *speed = SPEED_1000;
2290 *duplex = DUPLEX_FULL;
2291 break;
2292
2293 default:
2294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2295 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2296 SPEED_10;
2297 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2298 DUPLEX_HALF;
2299 break;
2300 }
2301 *speed = SPEED_INVALID;
2302 *duplex = DUPLEX_INVALID;
2303 break;
2304 }
2305}
2306
2307static void tg3_phy_copper_begin(struct tg3 *tp)
2308{
2309 u32 new_adv;
2310 int i;
2311
2312 if (tp->link_config.phy_is_low_power) {
2313 /* Entering low power mode. Disable gigabit and
2314 * 100baseT advertisements.
2315 */
2316 tg3_writephy(tp, MII_TG3_CTRL, 0);
2317
2318 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2319 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2320 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2321 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2322
2323 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2324 } else if (tp->link_config.speed == SPEED_INVALID) {
2325 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2326 tp->link_config.advertising &=
2327 ~(ADVERTISED_1000baseT_Half |
2328 ADVERTISED_1000baseT_Full);
2329
2330 new_adv = ADVERTISE_CSMA;
2331 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2332 new_adv |= ADVERTISE_10HALF;
2333 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2334 new_adv |= ADVERTISE_10FULL;
2335 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2336 new_adv |= ADVERTISE_100HALF;
2337 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2338 new_adv |= ADVERTISE_100FULL;
2339
2340 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2341
2342 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2343
2344 if (tp->link_config.advertising &
2345 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2346 new_adv = 0;
2347 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2348 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2349 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2350 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2351 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2352 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2353 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2354 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2355 MII_TG3_CTRL_ENABLE_AS_MASTER);
2356 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2357 } else {
2358 tg3_writephy(tp, MII_TG3_CTRL, 0);
2359 }
2360 } else {
2361 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2362 new_adv |= ADVERTISE_CSMA;
2363
2364 /* Asking for a specific link mode. */
2365 if (tp->link_config.speed == SPEED_1000) {
2366 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2367
2368 if (tp->link_config.duplex == DUPLEX_FULL)
2369 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2370 else
2371 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2372 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2373 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2374 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2375 MII_TG3_CTRL_ENABLE_AS_MASTER);
2376 } else {
2377 if (tp->link_config.speed == SPEED_100) {
2378 if (tp->link_config.duplex == DUPLEX_FULL)
2379 new_adv |= ADVERTISE_100FULL;
2380 else
2381 new_adv |= ADVERTISE_100HALF;
2382 } else {
2383 if (tp->link_config.duplex == DUPLEX_FULL)
2384 new_adv |= ADVERTISE_10FULL;
2385 else
2386 new_adv |= ADVERTISE_10HALF;
2387 }
2388 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2389
2390 new_adv = 0;
2391 }
2392
2393 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2394 }
2395
2396 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2397 tp->link_config.speed != SPEED_INVALID) {
2398 u32 bmcr, orig_bmcr;
2399
2400 tp->link_config.active_speed = tp->link_config.speed;
2401 tp->link_config.active_duplex = tp->link_config.duplex;
2402
2403 bmcr = 0;
2404 switch (tp->link_config.speed) {
2405 default:
2406 case SPEED_10:
2407 break;
2408
2409 case SPEED_100:
2410 bmcr |= BMCR_SPEED100;
2411 break;
2412
2413 case SPEED_1000:
2414 bmcr |= TG3_BMCR_SPEED1000;
2415 break;
2416 }
2417
2418 if (tp->link_config.duplex == DUPLEX_FULL)
2419 bmcr |= BMCR_FULLDPLX;
2420
2421 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2422 (bmcr != orig_bmcr)) {
2423 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2424 for (i = 0; i < 1500; i++) {
2425 u32 tmp;
2426
2427 udelay(10);
2428 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2429 tg3_readphy(tp, MII_BMSR, &tmp))
2430 continue;
2431 if (!(tmp & BMSR_LSTATUS)) {
2432 udelay(40);
2433 break;
2434 }
2435 }
2436 tg3_writephy(tp, MII_BMCR, bmcr);
2437 udelay(40);
2438 }
2439 } else {
2440 tg3_writephy(tp, MII_BMCR,
2441 BMCR_ANENABLE | BMCR_ANRESTART);
2442 }
2443}
2444
2445static int tg3_init_5401phy_dsp(struct tg3 *tp)
2446{
2447 int err;
2448
2449 /* Turn off tap power management. */
2450 /* Set Extended packet length bit */
2451 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2452
2453 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2454 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2455
2456 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2457 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2458
2459 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2460 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2461
2462 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2463 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2464
2465 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2466 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2467
2468 udelay(40);
2469
2470 return err;
2471}
2472
2473static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2474{
2475 u32 adv_reg, all_mask = 0;
2476
2477 if (mask & ADVERTISED_10baseT_Half)
2478 all_mask |= ADVERTISE_10HALF;
2479 if (mask & ADVERTISED_10baseT_Full)
2480 all_mask |= ADVERTISE_10FULL;
2481 if (mask & ADVERTISED_100baseT_Half)
2482 all_mask |= ADVERTISE_100HALF;
2483 if (mask & ADVERTISED_100baseT_Full)
2484 all_mask |= ADVERTISE_100FULL;
2485
2486 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2487 return 0;
2488
2489 if ((adv_reg & all_mask) != all_mask)
2490 return 0;
2491 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2492 u32 tg3_ctrl;
2493
2494 all_mask = 0;
2495 if (mask & ADVERTISED_1000baseT_Half)
2496 all_mask |= ADVERTISE_1000HALF;
2497 if (mask & ADVERTISED_1000baseT_Full)
2498 all_mask |= ADVERTISE_1000FULL;
2499
2500 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2501 return 0;
2502
2503 if ((tg3_ctrl & all_mask) != all_mask)
2504 return 0;
2505 }
2506 return 1;
2507}
2508
2509static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2510{
2511 u32 curadv, reqadv;
2512
2513 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2514 return 1;
2515
2516 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2517 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2518
2519 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2520 if (curadv != reqadv)
2521 return 0;
2522
2523 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2524 tg3_readphy(tp, MII_LPA, rmtadv);
2525 } else {
2526 /* Reprogram the advertisement register, even if it
2527 * does not affect the current link. If the link
2528 * gets renegotiated in the future, we can save an
2529 * additional renegotiation cycle by advertising
2530 * it correctly in the first place.
2531 */
2532 if (curadv != reqadv) {
2533 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2534 ADVERTISE_PAUSE_ASYM);
2535 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2536 }
2537 }
2538
2539 return 1;
2540}
2541
2542static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2543{
2544 int current_link_up;
2545 u32 bmsr, dummy;
2546 u32 lcl_adv, rmt_adv;
2547 u16 current_speed;
2548 u8 current_duplex;
2549 int i, err;
2550
2551 tw32(MAC_EVENT, 0);
2552
2553 tw32_f(MAC_STATUS,
2554 (MAC_STATUS_SYNC_CHANGED |
2555 MAC_STATUS_CFG_CHANGED |
2556 MAC_STATUS_MI_COMPLETION |
2557 MAC_STATUS_LNKSTATE_CHANGED));
2558 udelay(40);
2559
2560 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2561 tw32_f(MAC_MI_MODE,
2562 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2563 udelay(80);
2564 }
2565
2566 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2567
2568 /* Some third-party PHYs need to be reset on link going
2569 * down.
2570 */
2571 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2574 netif_carrier_ok(tp->dev)) {
2575 tg3_readphy(tp, MII_BMSR, &bmsr);
2576 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2577 !(bmsr & BMSR_LSTATUS))
2578 force_reset = 1;
2579 }
2580 if (force_reset)
2581 tg3_phy_reset(tp);
2582
2583 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2584 tg3_readphy(tp, MII_BMSR, &bmsr);
2585 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2586 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2587 bmsr = 0;
2588
2589 if (!(bmsr & BMSR_LSTATUS)) {
2590 err = tg3_init_5401phy_dsp(tp);
2591 if (err)
2592 return err;
2593
2594 tg3_readphy(tp, MII_BMSR, &bmsr);
2595 for (i = 0; i < 1000; i++) {
2596 udelay(10);
2597 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2598 (bmsr & BMSR_LSTATUS)) {
2599 udelay(40);
2600 break;
2601 }
2602 }
2603
2604 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2605 !(bmsr & BMSR_LSTATUS) &&
2606 tp->link_config.active_speed == SPEED_1000) {
2607 err = tg3_phy_reset(tp);
2608 if (!err)
2609 err = tg3_init_5401phy_dsp(tp);
2610 if (err)
2611 return err;
2612 }
2613 }
2614 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2615 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2616 /* 5701 {A0,B0} CRC bug workaround */
2617 tg3_writephy(tp, 0x15, 0x0a75);
2618 tg3_writephy(tp, 0x1c, 0x8c68);
2619 tg3_writephy(tp, 0x1c, 0x8d68);
2620 tg3_writephy(tp, 0x1c, 0x8c68);
2621 }
2622
2623 /* Clear pending interrupts... */
2624 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2625 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2626
2627 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2628 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2629 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2630 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2631
2632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2634 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2635 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2636 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2637 else
2638 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2639 }
2640
2641 current_link_up = 0;
2642 current_speed = SPEED_INVALID;
2643 current_duplex = DUPLEX_INVALID;
2644
2645 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2646 u32 val;
2647
2648 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2649 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2650 if (!(val & (1 << 10))) {
2651 val |= (1 << 10);
2652 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2653 goto relink;
2654 }
2655 }
2656
2657 bmsr = 0;
2658 for (i = 0; i < 100; i++) {
2659 tg3_readphy(tp, MII_BMSR, &bmsr);
2660 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2661 (bmsr & BMSR_LSTATUS))
2662 break;
2663 udelay(40);
2664 }
2665
2666 if (bmsr & BMSR_LSTATUS) {
2667 u32 aux_stat, bmcr;
2668
2669 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2670 for (i = 0; i < 2000; i++) {
2671 udelay(10);
2672 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2673 aux_stat)
2674 break;
2675 }
2676
2677 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2678 &current_speed,
2679 &current_duplex);
2680
2681 bmcr = 0;
2682 for (i = 0; i < 200; i++) {
2683 tg3_readphy(tp, MII_BMCR, &bmcr);
2684 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2685 continue;
2686 if (bmcr && bmcr != 0x7fff)
2687 break;
2688 udelay(10);
2689 }
2690
2691 lcl_adv = 0;
2692 rmt_adv = 0;
2693
2694 tp->link_config.active_speed = current_speed;
2695 tp->link_config.active_duplex = current_duplex;
2696
2697 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2698 if ((bmcr & BMCR_ANENABLE) &&
2699 tg3_copper_is_advertising_all(tp,
2700 tp->link_config.advertising)) {
2701 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2702 &rmt_adv))
2703 current_link_up = 1;
2704 }
2705 } else {
2706 if (!(bmcr & BMCR_ANENABLE) &&
2707 tp->link_config.speed == current_speed &&
2708 tp->link_config.duplex == current_duplex &&
2709 tp->link_config.flowctrl ==
2710 tp->link_config.active_flowctrl) {
2711 current_link_up = 1;
2712 }
2713 }
2714
2715 if (current_link_up == 1 &&
2716 tp->link_config.active_duplex == DUPLEX_FULL)
2717 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2718 }
2719
2720relink:
2721 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2722 u32 tmp;
2723
2724 tg3_phy_copper_begin(tp);
2725
2726 tg3_readphy(tp, MII_BMSR, &tmp);
2727 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2728 (tmp & BMSR_LSTATUS))
2729 current_link_up = 1;
2730 }
2731
2732 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2733 if (current_link_up == 1) {
2734 if (tp->link_config.active_speed == SPEED_100 ||
2735 tp->link_config.active_speed == SPEED_10)
2736 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2737 else
2738 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2739 } else
2740 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2741
2742 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2743 if (tp->link_config.active_duplex == DUPLEX_HALF)
2744 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2745
2746 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2747 if (current_link_up == 1 &&
2748 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2749 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2750 else
2751 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2752 }
2753
2754 /* ??? Without this setting Netgear GA302T PHY does not
2755 * ??? send/receive packets...
2756 */
2757 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2758 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2759 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2760 tw32_f(MAC_MI_MODE, tp->mi_mode);
2761 udelay(80);
2762 }
2763
2764 tw32_f(MAC_MODE, tp->mac_mode);
2765 udelay(40);
2766
2767 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2768 /* Polled via timer. */
2769 tw32_f(MAC_EVENT, 0);
2770 } else {
2771 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2772 }
2773 udelay(40);
2774
2775 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2776 current_link_up == 1 &&
2777 tp->link_config.active_speed == SPEED_1000 &&
2778 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2779 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2780 udelay(120);
2781 tw32_f(MAC_STATUS,
2782 (MAC_STATUS_SYNC_CHANGED |
2783 MAC_STATUS_CFG_CHANGED));
2784 udelay(40);
2785 tg3_write_mem(tp,
2786 NIC_SRAM_FIRMWARE_MBOX,
2787 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2788 }
2789
2790 if (current_link_up != netif_carrier_ok(tp->dev)) {
2791 if (current_link_up)
2792 netif_carrier_on(tp->dev);
2793 else
2794 netif_carrier_off(tp->dev);
2795 tg3_link_report(tp);
2796 }
2797
2798 return 0;
2799}
2800
2801struct tg3_fiber_aneginfo {
2802 int state;
2803#define ANEG_STATE_UNKNOWN 0
2804#define ANEG_STATE_AN_ENABLE 1
2805#define ANEG_STATE_RESTART_INIT 2
2806#define ANEG_STATE_RESTART 3
2807#define ANEG_STATE_DISABLE_LINK_OK 4
2808#define ANEG_STATE_ABILITY_DETECT_INIT 5
2809#define ANEG_STATE_ABILITY_DETECT 6
2810#define ANEG_STATE_ACK_DETECT_INIT 7
2811#define ANEG_STATE_ACK_DETECT 8
2812#define ANEG_STATE_COMPLETE_ACK_INIT 9
2813#define ANEG_STATE_COMPLETE_ACK 10
2814#define ANEG_STATE_IDLE_DETECT_INIT 11
2815#define ANEG_STATE_IDLE_DETECT 12
2816#define ANEG_STATE_LINK_OK 13
2817#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2818#define ANEG_STATE_NEXT_PAGE_WAIT 15
2819
2820 u32 flags;
2821#define MR_AN_ENABLE 0x00000001
2822#define MR_RESTART_AN 0x00000002
2823#define MR_AN_COMPLETE 0x00000004
2824#define MR_PAGE_RX 0x00000008
2825#define MR_NP_LOADED 0x00000010
2826#define MR_TOGGLE_TX 0x00000020
2827#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2828#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2829#define MR_LP_ADV_SYM_PAUSE 0x00000100
2830#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2831#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2832#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2833#define MR_LP_ADV_NEXT_PAGE 0x00001000
2834#define MR_TOGGLE_RX 0x00002000
2835#define MR_NP_RX 0x00004000
2836
2837#define MR_LINK_OK 0x80000000
2838
2839 unsigned long link_time, cur_time;
2840
2841 u32 ability_match_cfg;
2842 int ability_match_count;
2843
2844 char ability_match, idle_match, ack_match;
2845
2846 u32 txconfig, rxconfig;
2847#define ANEG_CFG_NP 0x00000080
2848#define ANEG_CFG_ACK 0x00000040
2849#define ANEG_CFG_RF2 0x00000020
2850#define ANEG_CFG_RF1 0x00000010
2851#define ANEG_CFG_PS2 0x00000001
2852#define ANEG_CFG_PS1 0x00008000
2853#define ANEG_CFG_HD 0x00004000
2854#define ANEG_CFG_FD 0x00002000
2855#define ANEG_CFG_INVAL 0x00001f06
2856
2857};
2858#define ANEG_OK 0
2859#define ANEG_DONE 1
2860#define ANEG_TIMER_ENAB 2
2861#define ANEG_FAILED -1
2862
2863#define ANEG_STATE_SETTLE_TIME 10000
2864
2865static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2866 struct tg3_fiber_aneginfo *ap)
2867{
2868 u16 flowctrl;
2869 unsigned long delta;
2870 u32 rx_cfg_reg;
2871 int ret;
2872
2873 if (ap->state == ANEG_STATE_UNKNOWN) {
2874 ap->rxconfig = 0;
2875 ap->link_time = 0;
2876 ap->cur_time = 0;
2877 ap->ability_match_cfg = 0;
2878 ap->ability_match_count = 0;
2879 ap->ability_match = 0;
2880 ap->idle_match = 0;
2881 ap->ack_match = 0;
2882 }
2883 ap->cur_time++;
2884
2885 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2886 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2887
2888 if (rx_cfg_reg != ap->ability_match_cfg) {
2889 ap->ability_match_cfg = rx_cfg_reg;
2890 ap->ability_match = 0;
2891 ap->ability_match_count = 0;
2892 } else {
2893 if (++ap->ability_match_count > 1) {
2894 ap->ability_match = 1;
2895 ap->ability_match_cfg = rx_cfg_reg;
2896 }
2897 }
2898 if (rx_cfg_reg & ANEG_CFG_ACK)
2899 ap->ack_match = 1;
2900 else
2901 ap->ack_match = 0;
2902
2903 ap->idle_match = 0;
2904 } else {
2905 ap->idle_match = 1;
2906 ap->ability_match_cfg = 0;
2907 ap->ability_match_count = 0;
2908 ap->ability_match = 0;
2909 ap->ack_match = 0;
2910
2911 rx_cfg_reg = 0;
2912 }
2913
2914 ap->rxconfig = rx_cfg_reg;
2915 ret = ANEG_OK;
2916
2917 switch(ap->state) {
2918 case ANEG_STATE_UNKNOWN:
2919 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2920 ap->state = ANEG_STATE_AN_ENABLE;
2921
2922 /* fallthru */
2923 case ANEG_STATE_AN_ENABLE:
2924 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2925 if (ap->flags & MR_AN_ENABLE) {
2926 ap->link_time = 0;
2927 ap->cur_time = 0;
2928 ap->ability_match_cfg = 0;
2929 ap->ability_match_count = 0;
2930 ap->ability_match = 0;
2931 ap->idle_match = 0;
2932 ap->ack_match = 0;
2933
2934 ap->state = ANEG_STATE_RESTART_INIT;
2935 } else {
2936 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2937 }
2938 break;
2939
2940 case ANEG_STATE_RESTART_INIT:
2941 ap->link_time = ap->cur_time;
2942 ap->flags &= ~(MR_NP_LOADED);
2943 ap->txconfig = 0;
2944 tw32(MAC_TX_AUTO_NEG, 0);
2945 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2946 tw32_f(MAC_MODE, tp->mac_mode);
2947 udelay(40);
2948
2949 ret = ANEG_TIMER_ENAB;
2950 ap->state = ANEG_STATE_RESTART;
2951
2952 /* fallthru */
2953 case ANEG_STATE_RESTART:
2954 delta = ap->cur_time - ap->link_time;
2955 if (delta > ANEG_STATE_SETTLE_TIME) {
2956 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2957 } else {
2958 ret = ANEG_TIMER_ENAB;
2959 }
2960 break;
2961
2962 case ANEG_STATE_DISABLE_LINK_OK:
2963 ret = ANEG_DONE;
2964 break;
2965
2966 case ANEG_STATE_ABILITY_DETECT_INIT:
2967 ap->flags &= ~(MR_TOGGLE_TX);
2968 ap->txconfig = ANEG_CFG_FD;
2969 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2970 if (flowctrl & ADVERTISE_1000XPAUSE)
2971 ap->txconfig |= ANEG_CFG_PS1;
2972 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2973 ap->txconfig |= ANEG_CFG_PS2;
2974 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2975 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2976 tw32_f(MAC_MODE, tp->mac_mode);
2977 udelay(40);
2978
2979 ap->state = ANEG_STATE_ABILITY_DETECT;
2980 break;
2981
2982 case ANEG_STATE_ABILITY_DETECT:
2983 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2984 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2985 }
2986 break;
2987
2988 case ANEG_STATE_ACK_DETECT_INIT:
2989 ap->txconfig |= ANEG_CFG_ACK;
2990 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2991 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2992 tw32_f(MAC_MODE, tp->mac_mode);
2993 udelay(40);
2994
2995 ap->state = ANEG_STATE_ACK_DETECT;
2996
2997 /* fallthru */
2998 case ANEG_STATE_ACK_DETECT:
2999 if (ap->ack_match != 0) {
3000 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3001 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3002 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3003 } else {
3004 ap->state = ANEG_STATE_AN_ENABLE;
3005 }
3006 } else if (ap->ability_match != 0 &&
3007 ap->rxconfig == 0) {
3008 ap->state = ANEG_STATE_AN_ENABLE;
3009 }
3010 break;
3011
3012 case ANEG_STATE_COMPLETE_ACK_INIT:
3013 if (ap->rxconfig & ANEG_CFG_INVAL) {
3014 ret = ANEG_FAILED;
3015 break;
3016 }
3017 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3018 MR_LP_ADV_HALF_DUPLEX |
3019 MR_LP_ADV_SYM_PAUSE |
3020 MR_LP_ADV_ASYM_PAUSE |
3021 MR_LP_ADV_REMOTE_FAULT1 |
3022 MR_LP_ADV_REMOTE_FAULT2 |
3023 MR_LP_ADV_NEXT_PAGE |
3024 MR_TOGGLE_RX |
3025 MR_NP_RX);
3026 if (ap->rxconfig & ANEG_CFG_FD)
3027 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3028 if (ap->rxconfig & ANEG_CFG_HD)
3029 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3030 if (ap->rxconfig & ANEG_CFG_PS1)
3031 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3032 if (ap->rxconfig & ANEG_CFG_PS2)
3033 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3034 if (ap->rxconfig & ANEG_CFG_RF1)
3035 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3036 if (ap->rxconfig & ANEG_CFG_RF2)
3037 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3038 if (ap->rxconfig & ANEG_CFG_NP)
3039 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3040
3041 ap->link_time = ap->cur_time;
3042
3043 ap->flags ^= (MR_TOGGLE_TX);
3044 if (ap->rxconfig & 0x0008)
3045 ap->flags |= MR_TOGGLE_RX;
3046 if (ap->rxconfig & ANEG_CFG_NP)
3047 ap->flags |= MR_NP_RX;
3048 ap->flags |= MR_PAGE_RX;
3049
3050 ap->state = ANEG_STATE_COMPLETE_ACK;
3051 ret = ANEG_TIMER_ENAB;
3052 break;
3053
3054 case ANEG_STATE_COMPLETE_ACK:
3055 if (ap->ability_match != 0 &&
3056 ap->rxconfig == 0) {
3057 ap->state = ANEG_STATE_AN_ENABLE;
3058 break;
3059 }
3060 delta = ap->cur_time - ap->link_time;
3061 if (delta > ANEG_STATE_SETTLE_TIME) {
3062 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3063 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3064 } else {
3065 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3066 !(ap->flags & MR_NP_RX)) {
3067 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3068 } else {
3069 ret = ANEG_FAILED;
3070 }
3071 }
3072 }
3073 break;
3074
3075 case ANEG_STATE_IDLE_DETECT_INIT:
3076 ap->link_time = ap->cur_time;
3077 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3078 tw32_f(MAC_MODE, tp->mac_mode);
3079 udelay(40);
3080
3081 ap->state = ANEG_STATE_IDLE_DETECT;
3082 ret = ANEG_TIMER_ENAB;
3083 break;
3084
3085 case ANEG_STATE_IDLE_DETECT:
3086 if (ap->ability_match != 0 &&
3087 ap->rxconfig == 0) {
3088 ap->state = ANEG_STATE_AN_ENABLE;
3089 break;
3090 }
3091 delta = ap->cur_time - ap->link_time;
3092 if (delta > ANEG_STATE_SETTLE_TIME) {
3093 /* XXX another gem from the Broadcom driver :( */
3094 ap->state = ANEG_STATE_LINK_OK;
3095 }
3096 break;
3097
3098 case ANEG_STATE_LINK_OK:
3099 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3100 ret = ANEG_DONE;
3101 break;
3102
3103 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3104 /* ??? unimplemented */
3105 break;
3106
3107 case ANEG_STATE_NEXT_PAGE_WAIT:
3108 /* ??? unimplemented */
3109 break;
3110
3111 default:
3112 ret = ANEG_FAILED;
3113 break;
3114 }
3115
3116 return ret;
3117}
3118
3119static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3120{
3121 int res = 0;
3122 struct tg3_fiber_aneginfo aninfo;
3123 int status = ANEG_FAILED;
3124 unsigned int tick;
3125 u32 tmp;
3126
3127 tw32_f(MAC_TX_AUTO_NEG, 0);
3128
3129 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3130 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3131 udelay(40);
3132
3133 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3134 udelay(40);
3135
3136 memset(&aninfo, 0, sizeof(aninfo));
3137 aninfo.flags |= MR_AN_ENABLE;
3138 aninfo.state = ANEG_STATE_UNKNOWN;
3139 aninfo.cur_time = 0;
3140 tick = 0;
3141 while (++tick < 195000) {
3142 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3143 if (status == ANEG_DONE || status == ANEG_FAILED)
3144 break;
3145
3146 udelay(1);
3147 }
3148
3149 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3150 tw32_f(MAC_MODE, tp->mac_mode);
3151 udelay(40);
3152
3153 *txflags = aninfo.txconfig;
3154 *rxflags = aninfo.flags;
3155
3156 if (status == ANEG_DONE &&
3157 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3158 MR_LP_ADV_FULL_DUPLEX)))
3159 res = 1;
3160
3161 return res;
3162}
3163
3164static void tg3_init_bcm8002(struct tg3 *tp)
3165{
3166 u32 mac_status = tr32(MAC_STATUS);
3167 int i;
3168
3169 /* Reset when initting first time or we have a link. */
3170 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3171 !(mac_status & MAC_STATUS_PCS_SYNCED))
3172 return;
3173
3174 /* Set PLL lock range. */
3175 tg3_writephy(tp, 0x16, 0x8007);
3176
3177 /* SW reset */
3178 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3179
3180 /* Wait for reset to complete. */
3181 /* XXX schedule_timeout() ... */
3182 for (i = 0; i < 500; i++)
3183 udelay(10);
3184
3185 /* Config mode; select PMA/Ch 1 regs. */
3186 tg3_writephy(tp, 0x10, 0x8411);
3187
3188 /* Enable auto-lock and comdet, select txclk for tx. */
3189 tg3_writephy(tp, 0x11, 0x0a10);
3190
3191 tg3_writephy(tp, 0x18, 0x00a0);
3192 tg3_writephy(tp, 0x16, 0x41ff);
3193
3194 /* Assert and deassert POR. */
3195 tg3_writephy(tp, 0x13, 0x0400);
3196 udelay(40);
3197 tg3_writephy(tp, 0x13, 0x0000);
3198
3199 tg3_writephy(tp, 0x11, 0x0a50);
3200 udelay(40);
3201 tg3_writephy(tp, 0x11, 0x0a10);
3202
3203 /* Wait for signal to stabilize */
3204 /* XXX schedule_timeout() ... */
3205 for (i = 0; i < 15000; i++)
3206 udelay(10);
3207
3208 /* Deselect the channel register so we can read the PHYID
3209 * later.
3210 */
3211 tg3_writephy(tp, 0x10, 0x8011);
3212}
3213
3214static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3215{
3216 u16 flowctrl;
3217 u32 sg_dig_ctrl, sg_dig_status;
3218 u32 serdes_cfg, expected_sg_dig_ctrl;
3219 int workaround, port_a;
3220 int current_link_up;
3221
3222 serdes_cfg = 0;
3223 expected_sg_dig_ctrl = 0;
3224 workaround = 0;
3225 port_a = 1;
3226 current_link_up = 0;
3227
3228 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3229 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3230 workaround = 1;
3231 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3232 port_a = 0;
3233
3234 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3235 /* preserve bits 20-23 for voltage regulator */
3236 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3237 }
3238
3239 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3240
3241 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3242 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3243 if (workaround) {
3244 u32 val = serdes_cfg;
3245
3246 if (port_a)
3247 val |= 0xc010000;
3248 else
3249 val |= 0x4010000;
3250 tw32_f(MAC_SERDES_CFG, val);
3251 }
3252
3253 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3254 }
3255 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3256 tg3_setup_flow_control(tp, 0, 0);
3257 current_link_up = 1;
3258 }
3259 goto out;
3260 }
3261
3262 /* Want auto-negotiation. */
3263 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3264
3265 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3266 if (flowctrl & ADVERTISE_1000XPAUSE)
3267 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3268 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3269 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3270
3271 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3272 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3273 tp->serdes_counter &&
3274 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3275 MAC_STATUS_RCVD_CFG)) ==
3276 MAC_STATUS_PCS_SYNCED)) {
3277 tp->serdes_counter--;
3278 current_link_up = 1;
3279 goto out;
3280 }
3281restart_autoneg:
3282 if (workaround)
3283 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3284 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3285 udelay(5);
3286 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3287
3288 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3289 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3290 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3291 MAC_STATUS_SIGNAL_DET)) {
3292 sg_dig_status = tr32(SG_DIG_STATUS);
3293 mac_status = tr32(MAC_STATUS);
3294
3295 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3296 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3297 u32 local_adv = 0, remote_adv = 0;
3298
3299 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3300 local_adv |= ADVERTISE_1000XPAUSE;
3301 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3302 local_adv |= ADVERTISE_1000XPSE_ASYM;
3303
3304 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3305 remote_adv |= LPA_1000XPAUSE;
3306 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3307 remote_adv |= LPA_1000XPAUSE_ASYM;
3308
3309 tg3_setup_flow_control(tp, local_adv, remote_adv);
3310 current_link_up = 1;
3311 tp->serdes_counter = 0;
3312 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3313 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3314 if (tp->serdes_counter)
3315 tp->serdes_counter--;
3316 else {
3317 if (workaround) {
3318 u32 val = serdes_cfg;
3319
3320 if (port_a)
3321 val |= 0xc010000;
3322 else
3323 val |= 0x4010000;
3324
3325 tw32_f(MAC_SERDES_CFG, val);
3326 }
3327
3328 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3329 udelay(40);
3330
3331 /* Link parallel detection - link is up */
3332 /* only if we have PCS_SYNC and not */
3333 /* receiving config code words */
3334 mac_status = tr32(MAC_STATUS);
3335 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3336 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3337 tg3_setup_flow_control(tp, 0, 0);
3338 current_link_up = 1;
3339 tp->tg3_flags2 |=
3340 TG3_FLG2_PARALLEL_DETECT;
3341 tp->serdes_counter =
3342 SERDES_PARALLEL_DET_TIMEOUT;
3343 } else
3344 goto restart_autoneg;
3345 }
3346 }
3347 } else {
3348 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3349 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3350 }
3351
3352out:
3353 return current_link_up;
3354}
3355
3356static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3357{
3358 int current_link_up = 0;
3359
3360 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3361 goto out;
3362
3363 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3364 u32 txflags, rxflags;
3365 int i;
3366
3367 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3368 u32 local_adv = 0, remote_adv = 0;
3369
3370 if (txflags & ANEG_CFG_PS1)
3371 local_adv |= ADVERTISE_1000XPAUSE;
3372 if (txflags & ANEG_CFG_PS2)
3373 local_adv |= ADVERTISE_1000XPSE_ASYM;
3374
3375 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3376 remote_adv |= LPA_1000XPAUSE;
3377 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3378 remote_adv |= LPA_1000XPAUSE_ASYM;
3379
3380 tg3_setup_flow_control(tp, local_adv, remote_adv);
3381
3382 current_link_up = 1;
3383 }
3384 for (i = 0; i < 30; i++) {
3385 udelay(20);
3386 tw32_f(MAC_STATUS,
3387 (MAC_STATUS_SYNC_CHANGED |
3388 MAC_STATUS_CFG_CHANGED));
3389 udelay(40);
3390 if ((tr32(MAC_STATUS) &
3391 (MAC_STATUS_SYNC_CHANGED |
3392 MAC_STATUS_CFG_CHANGED)) == 0)
3393 break;
3394 }
3395
3396 mac_status = tr32(MAC_STATUS);
3397 if (current_link_up == 0 &&
3398 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3399 !(mac_status & MAC_STATUS_RCVD_CFG))
3400 current_link_up = 1;
3401 } else {
3402 tg3_setup_flow_control(tp, 0, 0);
3403
3404 /* Forcing 1000FD link up. */
3405 current_link_up = 1;
3406
3407 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3408 udelay(40);
3409
3410 tw32_f(MAC_MODE, tp->mac_mode);
3411 udelay(40);
3412 }
3413
3414out:
3415 return current_link_up;
3416}
3417
3418static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3419{
3420 u32 orig_pause_cfg;
3421 u16 orig_active_speed;
3422 u8 orig_active_duplex;
3423 u32 mac_status;
3424 int current_link_up;
3425 int i;
3426
3427 orig_pause_cfg = tp->link_config.active_flowctrl;
3428 orig_active_speed = tp->link_config.active_speed;
3429 orig_active_duplex = tp->link_config.active_duplex;
3430
3431 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3432 netif_carrier_ok(tp->dev) &&
3433 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3434 mac_status = tr32(MAC_STATUS);
3435 mac_status &= (MAC_STATUS_PCS_SYNCED |
3436 MAC_STATUS_SIGNAL_DET |
3437 MAC_STATUS_CFG_CHANGED |
3438 MAC_STATUS_RCVD_CFG);
3439 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3440 MAC_STATUS_SIGNAL_DET)) {
3441 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3442 MAC_STATUS_CFG_CHANGED));
3443 return 0;
3444 }
3445 }
3446
3447 tw32_f(MAC_TX_AUTO_NEG, 0);
3448
3449 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3450 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3451 tw32_f(MAC_MODE, tp->mac_mode);
3452 udelay(40);
3453
3454 if (tp->phy_id == PHY_ID_BCM8002)
3455 tg3_init_bcm8002(tp);
3456
3457 /* Enable link change event even when serdes polling. */
3458 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3459 udelay(40);
3460
3461 current_link_up = 0;
3462 mac_status = tr32(MAC_STATUS);
3463
3464 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3465 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3466 else
3467 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3468
3469 tp->hw_status->status =
3470 (SD_STATUS_UPDATED |
3471 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3472
3473 for (i = 0; i < 100; i++) {
3474 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3475 MAC_STATUS_CFG_CHANGED));
3476 udelay(5);
3477 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3478 MAC_STATUS_CFG_CHANGED |
3479 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3480 break;
3481 }
3482
3483 mac_status = tr32(MAC_STATUS);
3484 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3485 current_link_up = 0;
3486 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3487 tp->serdes_counter == 0) {
3488 tw32_f(MAC_MODE, (tp->mac_mode |
3489 MAC_MODE_SEND_CONFIGS));
3490 udelay(1);
3491 tw32_f(MAC_MODE, tp->mac_mode);
3492 }
3493 }
3494
3495 if (current_link_up == 1) {
3496 tp->link_config.active_speed = SPEED_1000;
3497 tp->link_config.active_duplex = DUPLEX_FULL;
3498 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3499 LED_CTRL_LNKLED_OVERRIDE |
3500 LED_CTRL_1000MBPS_ON));
3501 } else {
3502 tp->link_config.active_speed = SPEED_INVALID;
3503 tp->link_config.active_duplex = DUPLEX_INVALID;
3504 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3505 LED_CTRL_LNKLED_OVERRIDE |
3506 LED_CTRL_TRAFFIC_OVERRIDE));
3507 }
3508
3509 if (current_link_up != netif_carrier_ok(tp->dev)) {
3510 if (current_link_up)
3511 netif_carrier_on(tp->dev);
3512 else
3513 netif_carrier_off(tp->dev);
3514 tg3_link_report(tp);
3515 } else {
3516 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3517 if (orig_pause_cfg != now_pause_cfg ||
3518 orig_active_speed != tp->link_config.active_speed ||
3519 orig_active_duplex != tp->link_config.active_duplex)
3520 tg3_link_report(tp);
3521 }
3522
3523 return 0;
3524}
3525
3526static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3527{
3528 int current_link_up, err = 0;
3529 u32 bmsr, bmcr;
3530 u16 current_speed;
3531 u8 current_duplex;
3532 u32 local_adv, remote_adv;
3533
3534 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3535 tw32_f(MAC_MODE, tp->mac_mode);
3536 udelay(40);
3537
3538 tw32(MAC_EVENT, 0);
3539
3540 tw32_f(MAC_STATUS,
3541 (MAC_STATUS_SYNC_CHANGED |
3542 MAC_STATUS_CFG_CHANGED |
3543 MAC_STATUS_MI_COMPLETION |
3544 MAC_STATUS_LNKSTATE_CHANGED));
3545 udelay(40);
3546
3547 if (force_reset)
3548 tg3_phy_reset(tp);
3549
3550 current_link_up = 0;
3551 current_speed = SPEED_INVALID;
3552 current_duplex = DUPLEX_INVALID;
3553
3554 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3555 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3557 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3558 bmsr |= BMSR_LSTATUS;
3559 else
3560 bmsr &= ~BMSR_LSTATUS;
3561 }
3562
3563 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3564
3565 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3566 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3567 /* do nothing, just check for link up at the end */
3568 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3569 u32 adv, new_adv;
3570
3571 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3572 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3573 ADVERTISE_1000XPAUSE |
3574 ADVERTISE_1000XPSE_ASYM |
3575 ADVERTISE_SLCT);
3576
3577 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3578
3579 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3580 new_adv |= ADVERTISE_1000XHALF;
3581 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3582 new_adv |= ADVERTISE_1000XFULL;
3583
3584 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3585 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3586 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3587 tg3_writephy(tp, MII_BMCR, bmcr);
3588
3589 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3590 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3591 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3592
3593 return err;
3594 }
3595 } else {
3596 u32 new_bmcr;
3597
3598 bmcr &= ~BMCR_SPEED1000;
3599 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3600
3601 if (tp->link_config.duplex == DUPLEX_FULL)
3602 new_bmcr |= BMCR_FULLDPLX;
3603
3604 if (new_bmcr != bmcr) {
3605 /* BMCR_SPEED1000 is a reserved bit that needs
3606 * to be set on write.
3607 */
3608 new_bmcr |= BMCR_SPEED1000;
3609
3610 /* Force a linkdown */
3611 if (netif_carrier_ok(tp->dev)) {
3612 u32 adv;
3613
3614 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3615 adv &= ~(ADVERTISE_1000XFULL |
3616 ADVERTISE_1000XHALF |
3617 ADVERTISE_SLCT);
3618 tg3_writephy(tp, MII_ADVERTISE, adv);
3619 tg3_writephy(tp, MII_BMCR, bmcr |
3620 BMCR_ANRESTART |
3621 BMCR_ANENABLE);
3622 udelay(10);
3623 netif_carrier_off(tp->dev);
3624 }
3625 tg3_writephy(tp, MII_BMCR, new_bmcr);
3626 bmcr = new_bmcr;
3627 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3628 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3629 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3630 ASIC_REV_5714) {
3631 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3632 bmsr |= BMSR_LSTATUS;
3633 else
3634 bmsr &= ~BMSR_LSTATUS;
3635 }
3636 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3637 }
3638 }
3639
3640 if (bmsr & BMSR_LSTATUS) {
3641 current_speed = SPEED_1000;
3642 current_link_up = 1;
3643 if (bmcr & BMCR_FULLDPLX)
3644 current_duplex = DUPLEX_FULL;
3645 else
3646 current_duplex = DUPLEX_HALF;
3647
3648 local_adv = 0;
3649 remote_adv = 0;
3650
3651 if (bmcr & BMCR_ANENABLE) {
3652 u32 common;
3653
3654 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3655 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3656 common = local_adv & remote_adv;
3657 if (common & (ADVERTISE_1000XHALF |
3658 ADVERTISE_1000XFULL)) {
3659 if (common & ADVERTISE_1000XFULL)
3660 current_duplex = DUPLEX_FULL;
3661 else
3662 current_duplex = DUPLEX_HALF;
3663 }
3664 else
3665 current_link_up = 0;
3666 }
3667 }
3668
3669 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3670 tg3_setup_flow_control(tp, local_adv, remote_adv);
3671
3672 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3673 if (tp->link_config.active_duplex == DUPLEX_HALF)
3674 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3675
3676 tw32_f(MAC_MODE, tp->mac_mode);
3677 udelay(40);
3678
3679 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3680
3681 tp->link_config.active_speed = current_speed;
3682 tp->link_config.active_duplex = current_duplex;
3683
3684 if (current_link_up != netif_carrier_ok(tp->dev)) {
3685 if (current_link_up)
3686 netif_carrier_on(tp->dev);
3687 else {
3688 netif_carrier_off(tp->dev);
3689 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3690 }
3691 tg3_link_report(tp);
3692 }
3693 return err;
3694}
3695
3696static void tg3_serdes_parallel_detect(struct tg3 *tp)
3697{
3698 if (tp->serdes_counter) {
3699 /* Give autoneg time to complete. */
3700 tp->serdes_counter--;
3701 return;
3702 }
3703 if (!netif_carrier_ok(tp->dev) &&
3704 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3705 u32 bmcr;
3706
3707 tg3_readphy(tp, MII_BMCR, &bmcr);
3708 if (bmcr & BMCR_ANENABLE) {
3709 u32 phy1, phy2;
3710
3711 /* Select shadow register 0x1f */
3712 tg3_writephy(tp, 0x1c, 0x7c00);
3713 tg3_readphy(tp, 0x1c, &phy1);
3714
3715 /* Select expansion interrupt status register */
3716 tg3_writephy(tp, 0x17, 0x0f01);
3717 tg3_readphy(tp, 0x15, &phy2);
3718 tg3_readphy(tp, 0x15, &phy2);
3719
3720 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3721 /* We have signal detect and not receiving
3722 * config code words, link is up by parallel
3723 * detection.
3724 */
3725
3726 bmcr &= ~BMCR_ANENABLE;
3727 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3728 tg3_writephy(tp, MII_BMCR, bmcr);
3729 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3730 }
3731 }
3732 }
3733 else if (netif_carrier_ok(tp->dev) &&
3734 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3735 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3736 u32 phy2;
3737
3738 /* Select expansion interrupt status register */
3739 tg3_writephy(tp, 0x17, 0x0f01);
3740 tg3_readphy(tp, 0x15, &phy2);
3741 if (phy2 & 0x20) {
3742 u32 bmcr;
3743
3744 /* Config code words received, turn on autoneg. */
3745 tg3_readphy(tp, MII_BMCR, &bmcr);
3746 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3747
3748 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3749
3750 }
3751 }
3752}
3753
3754static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3755{
3756 int err;
3757
3758 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3759 err = tg3_setup_fiber_phy(tp, force_reset);
3760 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3761 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3762 } else {
3763 err = tg3_setup_copper_phy(tp, force_reset);
3764 }
3765
3766 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3767 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3768 u32 val, scale;
3769
3770 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3771 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3772 scale = 65;
3773 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3774 scale = 6;
3775 else
3776 scale = 12;
3777
3778 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3779 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3780 tw32(GRC_MISC_CFG, val);
3781 }
3782
3783 if (tp->link_config.active_speed == SPEED_1000 &&
3784 tp->link_config.active_duplex == DUPLEX_HALF)
3785 tw32(MAC_TX_LENGTHS,
3786 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3787 (6 << TX_LENGTHS_IPG_SHIFT) |
3788 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3789 else
3790 tw32(MAC_TX_LENGTHS,
3791 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3792 (6 << TX_LENGTHS_IPG_SHIFT) |
3793 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3794
3795 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3796 if (netif_carrier_ok(tp->dev)) {
3797 tw32(HOSTCC_STAT_COAL_TICKS,
3798 tp->coal.stats_block_coalesce_usecs);
3799 } else {
3800 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3801 }
3802 }
3803
3804 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3805 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3806 if (!netif_carrier_ok(tp->dev))
3807 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3808 tp->pwrmgmt_thresh;
3809 else
3810 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3811 tw32(PCIE_PWR_MGMT_THRESH, val);
3812 }
3813
3814 return err;
3815}
3816
3817/* This is called whenever we suspect that the system chipset is re-
3818 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3819 * is bogus tx completions. We try to recover by setting the
3820 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3821 * in the workqueue.
3822 */
3823static void tg3_tx_recover(struct tg3 *tp)
3824{
3825 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3826 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3827
3828 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3829 "mapped I/O cycles to the network device, attempting to "
3830 "recover. Please report the problem to the driver maintainer "
3831 "and include system chipset information.\n", tp->dev->name);
3832
3833 spin_lock(&tp->lock);
3834 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3835 spin_unlock(&tp->lock);
3836}
3837
3838static inline u32 tg3_tx_avail(struct tg3 *tp)
3839{
3840 smp_mb();
3841 return (tp->tx_pending -
3842 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3843}
3844
3845/* Tigon3 never reports partial packet sends. So we do not
3846 * need special logic to handle SKBs that have not had all
3847 * of their frags sent yet, like SunGEM does.
3848 */
3849static void tg3_tx(struct tg3 *tp)
3850{
3851 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3852 u32 sw_idx = tp->tx_cons;
3853
3854 while (sw_idx != hw_idx) {
3855 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3856 struct sk_buff *skb = ri->skb;
3857 int i, tx_bug = 0;
3858
3859 if (unlikely(skb == NULL)) {
3860 tg3_tx_recover(tp);
3861 return;
3862 }
3863
3864 pci_unmap_single(tp->pdev,
3865 pci_unmap_addr(ri, mapping),
3866 skb_headlen(skb),
3867 PCI_DMA_TODEVICE);
3868
3869 ri->skb = NULL;
3870
3871 sw_idx = NEXT_TX(sw_idx);
3872
3873 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3874 ri = &tp->tx_buffers[sw_idx];
3875 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3876 tx_bug = 1;
3877
3878 pci_unmap_page(tp->pdev,
3879 pci_unmap_addr(ri, mapping),
3880 skb_shinfo(skb)->frags[i].size,
3881 PCI_DMA_TODEVICE);
3882
3883 sw_idx = NEXT_TX(sw_idx);
3884 }
3885
3886 dev_kfree_skb(skb);
3887
3888 if (unlikely(tx_bug)) {
3889 tg3_tx_recover(tp);
3890 return;
3891 }
3892 }
3893
3894 tp->tx_cons = sw_idx;
3895
3896 /* Need to make the tx_cons update visible to tg3_start_xmit()
3897 * before checking for netif_queue_stopped(). Without the
3898 * memory barrier, there is a small possibility that tg3_start_xmit()
3899 * will miss it and cause the queue to be stopped forever.
3900 */
3901 smp_mb();
3902
3903 if (unlikely(netif_queue_stopped(tp->dev) &&
3904 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3905 netif_tx_lock(tp->dev);
3906 if (netif_queue_stopped(tp->dev) &&
3907 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3908 netif_wake_queue(tp->dev);
3909 netif_tx_unlock(tp->dev);
3910 }
3911}
3912
3913/* Returns size of skb allocated or < 0 on error.
3914 *
3915 * We only need to fill in the address because the other members
3916 * of the RX descriptor are invariant, see tg3_init_rings.
3917 *
3918 * Note the purposeful assymetry of cpu vs. chip accesses. For
3919 * posting buffers we only dirty the first cache line of the RX
3920 * descriptor (containing the address). Whereas for the RX status
3921 * buffers the cpu only reads the last cacheline of the RX descriptor
3922 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3923 */
3924static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3925 int src_idx, u32 dest_idx_unmasked)
3926{
3927 struct tg3_rx_buffer_desc *desc;
3928 struct ring_info *map, *src_map;
3929 struct sk_buff *skb;
3930 dma_addr_t mapping;
3931 int skb_size, dest_idx;
3932
3933 src_map = NULL;
3934 switch (opaque_key) {
3935 case RXD_OPAQUE_RING_STD:
3936 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3937 desc = &tp->rx_std[dest_idx];
3938 map = &tp->rx_std_buffers[dest_idx];
3939 if (src_idx >= 0)
3940 src_map = &tp->rx_std_buffers[src_idx];
3941 skb_size = tp->rx_pkt_buf_sz;
3942 break;
3943
3944 case RXD_OPAQUE_RING_JUMBO:
3945 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3946 desc = &tp->rx_jumbo[dest_idx];
3947 map = &tp->rx_jumbo_buffers[dest_idx];
3948 if (src_idx >= 0)
3949 src_map = &tp->rx_jumbo_buffers[src_idx];
3950 skb_size = RX_JUMBO_PKT_BUF_SZ;
3951 break;
3952
3953 default:
3954 return -EINVAL;
3955 }
3956
3957 /* Do not overwrite any of the map or rp information
3958 * until we are sure we can commit to a new buffer.
3959 *
3960 * Callers depend upon this behavior and assume that
3961 * we leave everything unchanged if we fail.
3962 */
3963 skb = netdev_alloc_skb(tp->dev, skb_size);
3964 if (skb == NULL)
3965 return -ENOMEM;
3966
3967 skb_reserve(skb, tp->rx_offset);
3968
3969 mapping = pci_map_single(tp->pdev, skb->data,
3970 skb_size - tp->rx_offset,
3971 PCI_DMA_FROMDEVICE);
3972
3973 map->skb = skb;
3974 pci_unmap_addr_set(map, mapping, mapping);
3975
3976 if (src_map != NULL)
3977 src_map->skb = NULL;
3978
3979 desc->addr_hi = ((u64)mapping >> 32);
3980 desc->addr_lo = ((u64)mapping & 0xffffffff);
3981
3982 return skb_size;
3983}
3984
3985/* We only need to move over in the address because the other
3986 * members of the RX descriptor are invariant. See notes above
3987 * tg3_alloc_rx_skb for full details.
3988 */
3989static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3990 int src_idx, u32 dest_idx_unmasked)
3991{
3992 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3993 struct ring_info *src_map, *dest_map;
3994 int dest_idx;
3995
3996 switch (opaque_key) {
3997 case RXD_OPAQUE_RING_STD:
3998 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3999 dest_desc = &tp->rx_std[dest_idx];
4000 dest_map = &tp->rx_std_buffers[dest_idx];
4001 src_desc = &tp->rx_std[src_idx];
4002 src_map = &tp->rx_std_buffers[src_idx];
4003 break;
4004
4005 case RXD_OPAQUE_RING_JUMBO:
4006 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4007 dest_desc = &tp->rx_jumbo[dest_idx];
4008 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4009 src_desc = &tp->rx_jumbo[src_idx];
4010 src_map = &tp->rx_jumbo_buffers[src_idx];
4011 break;
4012
4013 default:
4014 return;
4015 }
4016
4017 dest_map->skb = src_map->skb;
4018 pci_unmap_addr_set(dest_map, mapping,
4019 pci_unmap_addr(src_map, mapping));
4020 dest_desc->addr_hi = src_desc->addr_hi;
4021 dest_desc->addr_lo = src_desc->addr_lo;
4022
4023 src_map->skb = NULL;
4024}
4025
4026#if TG3_VLAN_TAG_USED
4027static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4028{
4029 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4030}
4031#endif
4032
4033/* The RX ring scheme is composed of multiple rings which post fresh
4034 * buffers to the chip, and one special ring the chip uses to report
4035 * status back to the host.
4036 *
4037 * The special ring reports the status of received packets to the
4038 * host. The chip does not write into the original descriptor the
4039 * RX buffer was obtained from. The chip simply takes the original
4040 * descriptor as provided by the host, updates the status and length
4041 * field, then writes this into the next status ring entry.
4042 *
4043 * Each ring the host uses to post buffers to the chip is described
4044 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4045 * it is first placed into the on-chip ram. When the packet's length
4046 * is known, it walks down the TG3_BDINFO entries to select the ring.
4047 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4048 * which is within the range of the new packet's length is chosen.
4049 *
4050 * The "separate ring for rx status" scheme may sound queer, but it makes
4051 * sense from a cache coherency perspective. If only the host writes
4052 * to the buffer post rings, and only the chip writes to the rx status
4053 * rings, then cache lines never move beyond shared-modified state.
4054 * If both the host and chip were to write into the same ring, cache line
4055 * eviction could occur since both entities want it in an exclusive state.
4056 */
4057static int tg3_rx(struct tg3 *tp, int budget)
4058{
4059 u32 work_mask, rx_std_posted = 0;
4060 u32 sw_idx = tp->rx_rcb_ptr;
4061 u16 hw_idx;
4062 int received;
4063
4064 hw_idx = tp->hw_status->idx[0].rx_producer;
4065 /*
4066 * We need to order the read of hw_idx and the read of
4067 * the opaque cookie.
4068 */
4069 rmb();
4070 work_mask = 0;
4071 received = 0;
4072 while (sw_idx != hw_idx && budget > 0) {
4073 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4074 unsigned int len;
4075 struct sk_buff *skb;
4076 dma_addr_t dma_addr;
4077 u32 opaque_key, desc_idx, *post_ptr;
4078
4079 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4080 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4081 if (opaque_key == RXD_OPAQUE_RING_STD) {
4082 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4083 mapping);
4084 skb = tp->rx_std_buffers[desc_idx].skb;
4085 post_ptr = &tp->rx_std_ptr;
4086 rx_std_posted++;
4087 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4088 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4089 mapping);
4090 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4091 post_ptr = &tp->rx_jumbo_ptr;
4092 }
4093 else {
4094 goto next_pkt_nopost;
4095 }
4096
4097 work_mask |= opaque_key;
4098
4099 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4100 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4101 drop_it:
4102 tg3_recycle_rx(tp, opaque_key,
4103 desc_idx, *post_ptr);
4104 drop_it_no_recycle:
4105 /* Other statistics kept track of by card. */
4106 tp->net_stats.rx_dropped++;
4107 goto next_pkt;
4108 }
4109
4110 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4111
4112 if (len > RX_COPY_THRESHOLD
4113 && tp->rx_offset == 2
4114 /* rx_offset != 2 iff this is a 5701 card running
4115 * in PCI-X mode [see tg3_get_invariants()] */
4116 ) {
4117 int skb_size;
4118
4119 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4120 desc_idx, *post_ptr);
4121 if (skb_size < 0)
4122 goto drop_it;
4123
4124 pci_unmap_single(tp->pdev, dma_addr,
4125 skb_size - tp->rx_offset,
4126 PCI_DMA_FROMDEVICE);
4127
4128 skb_put(skb, len);
4129 } else {
4130 struct sk_buff *copy_skb;
4131
4132 tg3_recycle_rx(tp, opaque_key,
4133 desc_idx, *post_ptr);
4134
4135 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4136 if (copy_skb == NULL)
4137 goto drop_it_no_recycle;
4138
4139 skb_reserve(copy_skb, 2);
4140 skb_put(copy_skb, len);
4141 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4142 skb_copy_from_linear_data(skb, copy_skb->data, len);
4143 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4144
4145 /* We'll reuse the original ring buffer. */
4146 skb = copy_skb;
4147 }
4148
4149 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4150 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4151 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4152 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4153 skb->ip_summed = CHECKSUM_UNNECESSARY;
4154 else
4155 skb->ip_summed = CHECKSUM_NONE;
4156
4157 skb->protocol = eth_type_trans(skb, tp->dev);
4158#if TG3_VLAN_TAG_USED
4159 if (tp->vlgrp != NULL &&
4160 desc->type_flags & RXD_FLAG_VLAN) {
4161 tg3_vlan_rx(tp, skb,
4162 desc->err_vlan & RXD_VLAN_MASK);
4163 } else
4164#endif
4165 netif_receive_skb(skb);
4166
4167 tp->dev->last_rx = jiffies;
4168 received++;
4169 budget--;
4170
4171next_pkt:
4172 (*post_ptr)++;
4173
4174 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4175 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4176
4177 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4178 TG3_64BIT_REG_LOW, idx);
4179 work_mask &= ~RXD_OPAQUE_RING_STD;
4180 rx_std_posted = 0;
4181 }
4182next_pkt_nopost:
4183 sw_idx++;
4184 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4185
4186 /* Refresh hw_idx to see if there is new work */
4187 if (sw_idx == hw_idx) {
4188 hw_idx = tp->hw_status->idx[0].rx_producer;
4189 rmb();
4190 }
4191 }
4192
4193 /* ACK the status ring. */
4194 tp->rx_rcb_ptr = sw_idx;
4195 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4196
4197 /* Refill RX ring(s). */
4198 if (work_mask & RXD_OPAQUE_RING_STD) {
4199 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4200 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4201 sw_idx);
4202 }
4203 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4204 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4205 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4206 sw_idx);
4207 }
4208 mmiowb();
4209
4210 return received;
4211}
4212
4213static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4214{
4215 struct tg3_hw_status *sblk = tp->hw_status;
4216
4217 /* handle link change and other phy events */
4218 if (!(tp->tg3_flags &
4219 (TG3_FLAG_USE_LINKCHG_REG |
4220 TG3_FLAG_POLL_SERDES))) {
4221 if (sblk->status & SD_STATUS_LINK_CHG) {
4222 sblk->status = SD_STATUS_UPDATED |
4223 (sblk->status & ~SD_STATUS_LINK_CHG);
4224 spin_lock(&tp->lock);
4225 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4226 tw32_f(MAC_STATUS,
4227 (MAC_STATUS_SYNC_CHANGED |
4228 MAC_STATUS_CFG_CHANGED |
4229 MAC_STATUS_MI_COMPLETION |
4230 MAC_STATUS_LNKSTATE_CHANGED));
4231 udelay(40);
4232 } else
4233 tg3_setup_phy(tp, 0);
4234 spin_unlock(&tp->lock);
4235 }
4236 }
4237
4238 /* run TX completion thread */
4239 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4240 tg3_tx(tp);
4241 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4242 return work_done;
4243 }
4244
4245 /* run RX thread, within the bounds set by NAPI.
4246 * All RX "locking" is done by ensuring outside
4247 * code synchronizes with tg3->napi.poll()
4248 */
4249 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4250 work_done += tg3_rx(tp, budget - work_done);
4251
4252 return work_done;
4253}
4254
4255static int tg3_poll(struct napi_struct *napi, int budget)
4256{
4257 struct tg3 *tp = container_of(napi, struct tg3, napi);
4258 int work_done = 0;
4259 struct tg3_hw_status *sblk = tp->hw_status;
4260
4261 while (1) {
4262 work_done = tg3_poll_work(tp, work_done, budget);
4263
4264 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4265 goto tx_recovery;
4266
4267 if (unlikely(work_done >= budget))
4268 break;
4269
4270 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4271 /* tp->last_tag is used in tg3_restart_ints() below
4272 * to tell the hw how much work has been processed,
4273 * so we must read it before checking for more work.
4274 */
4275 tp->last_tag = sblk->status_tag;
4276 rmb();
4277 } else
4278 sblk->status &= ~SD_STATUS_UPDATED;
4279
4280 if (likely(!tg3_has_work(tp))) {
4281 netif_rx_complete(tp->dev, napi);
4282 tg3_restart_ints(tp);
4283 break;
4284 }
4285 }
4286
4287 return work_done;
4288
4289tx_recovery:
4290 /* work_done is guaranteed to be less than budget. */
4291 netif_rx_complete(tp->dev, napi);
4292 schedule_work(&tp->reset_task);
4293 return work_done;
4294}
4295
4296static void tg3_irq_quiesce(struct tg3 *tp)
4297{
4298 BUG_ON(tp->irq_sync);
4299
4300 tp->irq_sync = 1;
4301 smp_mb();
4302
4303 synchronize_irq(tp->pdev->irq);
4304}
4305
4306static inline int tg3_irq_sync(struct tg3 *tp)
4307{
4308 return tp->irq_sync;
4309}
4310
4311/* Fully shutdown all tg3 driver activity elsewhere in the system.
4312 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4313 * with as well. Most of the time, this is not necessary except when
4314 * shutting down the device.
4315 */
4316static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4317{
4318 spin_lock_bh(&tp->lock);
4319 if (irq_sync)
4320 tg3_irq_quiesce(tp);
4321}
4322
4323static inline void tg3_full_unlock(struct tg3 *tp)
4324{
4325 spin_unlock_bh(&tp->lock);
4326}
4327
4328/* One-shot MSI handler - Chip automatically disables interrupt
4329 * after sending MSI so driver doesn't have to do it.
4330 */
4331static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4332{
4333 struct net_device *dev = dev_id;
4334 struct tg3 *tp = netdev_priv(dev);
4335
4336 prefetch(tp->hw_status);
4337 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4338
4339 if (likely(!tg3_irq_sync(tp)))
4340 netif_rx_schedule(dev, &tp->napi);
4341
4342 return IRQ_HANDLED;
4343}
4344
4345/* MSI ISR - No need to check for interrupt sharing and no need to
4346 * flush status block and interrupt mailbox. PCI ordering rules
4347 * guarantee that MSI will arrive after the status block.
4348 */
4349static irqreturn_t tg3_msi(int irq, void *dev_id)
4350{
4351 struct net_device *dev = dev_id;
4352 struct tg3 *tp = netdev_priv(dev);
4353
4354 prefetch(tp->hw_status);
4355 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4356 /*
4357 * Writing any value to intr-mbox-0 clears PCI INTA# and
4358 * chip-internal interrupt pending events.
4359 * Writing non-zero to intr-mbox-0 additional tells the
4360 * NIC to stop sending us irqs, engaging "in-intr-handler"
4361 * event coalescing.
4362 */
4363 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4364 if (likely(!tg3_irq_sync(tp)))
4365 netif_rx_schedule(dev, &tp->napi);
4366
4367 return IRQ_RETVAL(1);
4368}
4369
4370static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4371{
4372 struct net_device *dev = dev_id;
4373 struct tg3 *tp = netdev_priv(dev);
4374 struct tg3_hw_status *sblk = tp->hw_status;
4375 unsigned int handled = 1;
4376
4377 /* In INTx mode, it is possible for the interrupt to arrive at
4378 * the CPU before the status block posted prior to the interrupt.
4379 * Reading the PCI State register will confirm whether the
4380 * interrupt is ours and will flush the status block.
4381 */
4382 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4383 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4384 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4385 handled = 0;
4386 goto out;
4387 }
4388 }
4389
4390 /*
4391 * Writing any value to intr-mbox-0 clears PCI INTA# and
4392 * chip-internal interrupt pending events.
4393 * Writing non-zero to intr-mbox-0 additional tells the
4394 * NIC to stop sending us irqs, engaging "in-intr-handler"
4395 * event coalescing.
4396 *
4397 * Flush the mailbox to de-assert the IRQ immediately to prevent
4398 * spurious interrupts. The flush impacts performance but
4399 * excessive spurious interrupts can be worse in some cases.
4400 */
4401 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4402 if (tg3_irq_sync(tp))
4403 goto out;
4404 sblk->status &= ~SD_STATUS_UPDATED;
4405 if (likely(tg3_has_work(tp))) {
4406 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4407 netif_rx_schedule(dev, &tp->napi);
4408 } else {
4409 /* No work, shared interrupt perhaps? re-enable
4410 * interrupts, and flush that PCI write
4411 */
4412 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4413 0x00000000);
4414 }
4415out:
4416 return IRQ_RETVAL(handled);
4417}
4418
4419static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4420{
4421 struct net_device *dev = dev_id;
4422 struct tg3 *tp = netdev_priv(dev);
4423 struct tg3_hw_status *sblk = tp->hw_status;
4424 unsigned int handled = 1;
4425
4426 /* In INTx mode, it is possible for the interrupt to arrive at
4427 * the CPU before the status block posted prior to the interrupt.
4428 * Reading the PCI State register will confirm whether the
4429 * interrupt is ours and will flush the status block.
4430 */
4431 if (unlikely(sblk->status_tag == tp->last_tag)) {
4432 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4433 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4434 handled = 0;
4435 goto out;
4436 }
4437 }
4438
4439 /*
4440 * writing any value to intr-mbox-0 clears PCI INTA# and
4441 * chip-internal interrupt pending events.
4442 * writing non-zero to intr-mbox-0 additional tells the
4443 * NIC to stop sending us irqs, engaging "in-intr-handler"
4444 * event coalescing.
4445 *
4446 * Flush the mailbox to de-assert the IRQ immediately to prevent
4447 * spurious interrupts. The flush impacts performance but
4448 * excessive spurious interrupts can be worse in some cases.
4449 */
4450 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4451 if (tg3_irq_sync(tp))
4452 goto out;
4453 if (netif_rx_schedule_prep(dev, &tp->napi)) {
4454 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4455 /* Update last_tag to mark that this status has been
4456 * seen. Because interrupt may be shared, we may be
4457 * racing with tg3_poll(), so only update last_tag
4458 * if tg3_poll() is not scheduled.
4459 */
4460 tp->last_tag = sblk->status_tag;
4461 __netif_rx_schedule(dev, &tp->napi);
4462 }
4463out:
4464 return IRQ_RETVAL(handled);
4465}
4466
4467/* ISR for interrupt test */
4468static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4469{
4470 struct net_device *dev = dev_id;
4471 struct tg3 *tp = netdev_priv(dev);
4472 struct tg3_hw_status *sblk = tp->hw_status;
4473
4474 if ((sblk->status & SD_STATUS_UPDATED) ||
4475 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4476 tg3_disable_ints(tp);
4477 return IRQ_RETVAL(1);
4478 }
4479 return IRQ_RETVAL(0);
4480}
4481
4482static int tg3_init_hw(struct tg3 *, int);
4483static int tg3_halt(struct tg3 *, int, int);
4484
4485/* Restart hardware after configuration changes, self-test, etc.
4486 * Invoked with tp->lock held.
4487 */
4488static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4489 __releases(tp->lock)
4490 __acquires(tp->lock)
4491{
4492 int err;
4493
4494 err = tg3_init_hw(tp, reset_phy);
4495 if (err) {
4496 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4497 "aborting.\n", tp->dev->name);
4498 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4499 tg3_full_unlock(tp);
4500 del_timer_sync(&tp->timer);
4501 tp->irq_sync = 0;
4502 napi_enable(&tp->napi);
4503 dev_close(tp->dev);
4504 tg3_full_lock(tp, 0);
4505 }
4506 return err;
4507}
4508
4509#ifdef CONFIG_NET_POLL_CONTROLLER
4510static void tg3_poll_controller(struct net_device *dev)
4511{
4512 struct tg3 *tp = netdev_priv(dev);
4513
4514 tg3_interrupt(tp->pdev->irq, dev);
4515}
4516#endif
4517
4518static void tg3_reset_task(struct work_struct *work)
4519{
4520 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4521 int err;
4522 unsigned int restart_timer;
4523
4524 tg3_full_lock(tp, 0);
4525
4526 if (!netif_running(tp->dev)) {
4527 tg3_full_unlock(tp);
4528 return;
4529 }
4530
4531 tg3_full_unlock(tp);
4532
4533 tg3_phy_stop(tp);
4534
4535 tg3_netif_stop(tp);
4536
4537 tg3_full_lock(tp, 1);
4538
4539 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4540 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4541
4542 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4543 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4544 tp->write32_rx_mbox = tg3_write_flush_reg32;
4545 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4546 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4547 }
4548
4549 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4550 err = tg3_init_hw(tp, 1);
4551 if (err)
4552 goto out;
4553
4554 tg3_netif_start(tp);
4555
4556 if (restart_timer)
4557 mod_timer(&tp->timer, jiffies + 1);
4558
4559out:
4560 tg3_full_unlock(tp);
4561
4562 if (!err)
4563 tg3_phy_start(tp);
4564}
4565
4566static void tg3_dump_short_state(struct tg3 *tp)
4567{
4568 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4569 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4570 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4571 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4572}
4573
4574static void tg3_tx_timeout(struct net_device *dev)
4575{
4576 struct tg3 *tp = netdev_priv(dev);
4577
4578 if (netif_msg_tx_err(tp)) {
4579 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4580 dev->name);
4581 tg3_dump_short_state(tp);
4582 }
4583
4584 schedule_work(&tp->reset_task);
4585}
4586
4587/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4588static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4589{
4590 u32 base = (u32) mapping & 0xffffffff;
4591
4592 return ((base > 0xffffdcc0) &&
4593 (base + len + 8 < base));
4594}
4595
4596/* Test for DMA addresses > 40-bit */
4597static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4598 int len)
4599{
4600#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4601 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4602 return (((u64) mapping + len) > DMA_40BIT_MASK);
4603 return 0;
4604#else
4605 return 0;
4606#endif
4607}
4608
4609static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4610
4611/* Workaround 4GB and 40-bit hardware DMA bugs. */
4612static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4613 u32 last_plus_one, u32 *start,
4614 u32 base_flags, u32 mss)
4615{
4616 struct sk_buff *new_skb;
4617 dma_addr_t new_addr = 0;
4618 u32 entry = *start;
4619 int i, ret = 0;
4620
4621 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4622 new_skb = skb_copy(skb, GFP_ATOMIC);
4623 else {
4624 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4625
4626 new_skb = skb_copy_expand(skb,
4627 skb_headroom(skb) + more_headroom,
4628 skb_tailroom(skb), GFP_ATOMIC);
4629 }
4630
4631 if (!new_skb) {
4632 ret = -1;
4633 } else {
4634 /* New SKB is guaranteed to be linear. */
4635 entry = *start;
4636 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4637 PCI_DMA_TODEVICE);
4638 /* Make sure new skb does not cross any 4G boundaries.
4639 * Drop the packet if it does.
4640 */
4641 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4642 ret = -1;
4643 dev_kfree_skb(new_skb);
4644 new_skb = NULL;
4645 } else {
4646 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4647 base_flags, 1 | (mss << 1));
4648 *start = NEXT_TX(entry);
4649 }
4650 }
4651
4652 /* Now clean up the sw ring entries. */
4653 i = 0;
4654 while (entry != last_plus_one) {
4655 int len;
4656
4657 if (i == 0)
4658 len = skb_headlen(skb);
4659 else
4660 len = skb_shinfo(skb)->frags[i-1].size;
4661 pci_unmap_single(tp->pdev,
4662 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4663 len, PCI_DMA_TODEVICE);
4664 if (i == 0) {
4665 tp->tx_buffers[entry].skb = new_skb;
4666 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4667 } else {
4668 tp->tx_buffers[entry].skb = NULL;
4669 }
4670 entry = NEXT_TX(entry);
4671 i++;
4672 }
4673
4674 dev_kfree_skb(skb);
4675
4676 return ret;
4677}
4678
4679static void tg3_set_txd(struct tg3 *tp, int entry,
4680 dma_addr_t mapping, int len, u32 flags,
4681 u32 mss_and_is_end)
4682{
4683 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4684 int is_end = (mss_and_is_end & 0x1);
4685 u32 mss = (mss_and_is_end >> 1);
4686 u32 vlan_tag = 0;
4687
4688 if (is_end)
4689 flags |= TXD_FLAG_END;
4690 if (flags & TXD_FLAG_VLAN) {
4691 vlan_tag = flags >> 16;
4692 flags &= 0xffff;
4693 }
4694 vlan_tag |= (mss << TXD_MSS_SHIFT);
4695
4696 txd->addr_hi = ((u64) mapping >> 32);
4697 txd->addr_lo = ((u64) mapping & 0xffffffff);
4698 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4699 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4700}
4701
4702/* hard_start_xmit for devices that don't have any bugs and
4703 * support TG3_FLG2_HW_TSO_2 only.
4704 */
4705static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4706{
4707 struct tg3 *tp = netdev_priv(dev);
4708 dma_addr_t mapping;
4709 u32 len, entry, base_flags, mss;
4710
4711 len = skb_headlen(skb);
4712
4713 /* We are running in BH disabled context with netif_tx_lock
4714 * and TX reclaim runs via tp->napi.poll inside of a software
4715 * interrupt. Furthermore, IRQ processing runs lockless so we have
4716 * no IRQ context deadlocks to worry about either. Rejoice!
4717 */
4718 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4719 if (!netif_queue_stopped(dev)) {
4720 netif_stop_queue(dev);
4721
4722 /* This is a hard error, log it. */
4723 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4724 "queue awake!\n", dev->name);
4725 }
4726 return NETDEV_TX_BUSY;
4727 }
4728
4729 entry = tp->tx_prod;
4730 base_flags = 0;
4731 mss = 0;
4732 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4733 int tcp_opt_len, ip_tcp_len;
4734
4735 if (skb_header_cloned(skb) &&
4736 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4737 dev_kfree_skb(skb);
4738 goto out_unlock;
4739 }
4740
4741 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4742 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4743 else {
4744 struct iphdr *iph = ip_hdr(skb);
4745
4746 tcp_opt_len = tcp_optlen(skb);
4747 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4748
4749 iph->check = 0;
4750 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4751 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4752 }
4753
4754 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4755 TXD_FLAG_CPU_POST_DMA);
4756
4757 tcp_hdr(skb)->check = 0;
4758
4759 }
4760 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4761 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4762#if TG3_VLAN_TAG_USED
4763 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4764 base_flags |= (TXD_FLAG_VLAN |
4765 (vlan_tx_tag_get(skb) << 16));
4766#endif
4767
4768 /* Queue skb data, a.k.a. the main skb fragment. */
4769 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4770
4771 tp->tx_buffers[entry].skb = skb;
4772 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4773
4774 tg3_set_txd(tp, entry, mapping, len, base_flags,
4775 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4776
4777 entry = NEXT_TX(entry);
4778
4779 /* Now loop through additional data fragments, and queue them. */
4780 if (skb_shinfo(skb)->nr_frags > 0) {
4781 unsigned int i, last;
4782
4783 last = skb_shinfo(skb)->nr_frags - 1;
4784 for (i = 0; i <= last; i++) {
4785 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4786
4787 len = frag->size;
4788 mapping = pci_map_page(tp->pdev,
4789 frag->page,
4790 frag->page_offset,
4791 len, PCI_DMA_TODEVICE);
4792
4793 tp->tx_buffers[entry].skb = NULL;
4794 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4795
4796 tg3_set_txd(tp, entry, mapping, len,
4797 base_flags, (i == last) | (mss << 1));
4798
4799 entry = NEXT_TX(entry);
4800 }
4801 }
4802
4803 /* Packets are ready, update Tx producer idx local and on card. */
4804 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4805
4806 tp->tx_prod = entry;
4807 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4808 netif_stop_queue(dev);
4809 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4810 netif_wake_queue(tp->dev);
4811 }
4812
4813out_unlock:
4814 mmiowb();
4815
4816 dev->trans_start = jiffies;
4817
4818 return NETDEV_TX_OK;
4819}
4820
4821static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4822
4823/* Use GSO to workaround a rare TSO bug that may be triggered when the
4824 * TSO header is greater than 80 bytes.
4825 */
4826static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4827{
4828 struct sk_buff *segs, *nskb;
4829
4830 /* Estimate the number of fragments in the worst case */
4831 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4832 netif_stop_queue(tp->dev);
4833 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4834 return NETDEV_TX_BUSY;
4835
4836 netif_wake_queue(tp->dev);
4837 }
4838
4839 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4840 if (IS_ERR(segs))
4841 goto tg3_tso_bug_end;
4842
4843 do {
4844 nskb = segs;
4845 segs = segs->next;
4846 nskb->next = NULL;
4847 tg3_start_xmit_dma_bug(nskb, tp->dev);
4848 } while (segs);
4849
4850tg3_tso_bug_end:
4851 dev_kfree_skb(skb);
4852
4853 return NETDEV_TX_OK;
4854}
4855
4856/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4857 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4858 */
4859static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4860{
4861 struct tg3 *tp = netdev_priv(dev);
4862 dma_addr_t mapping;
4863 u32 len, entry, base_flags, mss;
4864 int would_hit_hwbug;
4865
4866 len = skb_headlen(skb);
4867
4868 /* We are running in BH disabled context with netif_tx_lock
4869 * and TX reclaim runs via tp->napi.poll inside of a software
4870 * interrupt. Furthermore, IRQ processing runs lockless so we have
4871 * no IRQ context deadlocks to worry about either. Rejoice!
4872 */
4873 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4874 if (!netif_queue_stopped(dev)) {
4875 netif_stop_queue(dev);
4876
4877 /* This is a hard error, log it. */
4878 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4879 "queue awake!\n", dev->name);
4880 }
4881 return NETDEV_TX_BUSY;
4882 }
4883
4884 entry = tp->tx_prod;
4885 base_flags = 0;
4886 if (skb->ip_summed == CHECKSUM_PARTIAL)
4887 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4888 mss = 0;
4889 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4890 struct iphdr *iph;
4891 int tcp_opt_len, ip_tcp_len, hdr_len;
4892
4893 if (skb_header_cloned(skb) &&
4894 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4895 dev_kfree_skb(skb);
4896 goto out_unlock;
4897 }
4898
4899 tcp_opt_len = tcp_optlen(skb);
4900 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4901
4902 hdr_len = ip_tcp_len + tcp_opt_len;
4903 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4904 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4905 return (tg3_tso_bug(tp, skb));
4906
4907 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4908 TXD_FLAG_CPU_POST_DMA);
4909
4910 iph = ip_hdr(skb);
4911 iph->check = 0;
4912 iph->tot_len = htons(mss + hdr_len);
4913 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4914 tcp_hdr(skb)->check = 0;
4915 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4916 } else
4917 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4918 iph->daddr, 0,
4919 IPPROTO_TCP,
4920 0);
4921
4922 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4923 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4924 if (tcp_opt_len || iph->ihl > 5) {
4925 int tsflags;
4926
4927 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4928 mss |= (tsflags << 11);
4929 }
4930 } else {
4931 if (tcp_opt_len || iph->ihl > 5) {
4932 int tsflags;
4933
4934 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4935 base_flags |= tsflags << 12;
4936 }
4937 }
4938 }
4939#if TG3_VLAN_TAG_USED
4940 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4941 base_flags |= (TXD_FLAG_VLAN |
4942 (vlan_tx_tag_get(skb) << 16));
4943#endif
4944
4945 /* Queue skb data, a.k.a. the main skb fragment. */
4946 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4947
4948 tp->tx_buffers[entry].skb = skb;
4949 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4950
4951 would_hit_hwbug = 0;
4952
4953 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4954 would_hit_hwbug = 1;
4955 else if (tg3_4g_overflow_test(mapping, len))
4956 would_hit_hwbug = 1;
4957
4958 tg3_set_txd(tp, entry, mapping, len, base_flags,
4959 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4960
4961 entry = NEXT_TX(entry);
4962
4963 /* Now loop through additional data fragments, and queue them. */
4964 if (skb_shinfo(skb)->nr_frags > 0) {
4965 unsigned int i, last;
4966
4967 last = skb_shinfo(skb)->nr_frags - 1;
4968 for (i = 0; i <= last; i++) {
4969 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4970
4971 len = frag->size;
4972 mapping = pci_map_page(tp->pdev,
4973 frag->page,
4974 frag->page_offset,
4975 len, PCI_DMA_TODEVICE);
4976
4977 tp->tx_buffers[entry].skb = NULL;
4978 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4979
4980 if (tg3_4g_overflow_test(mapping, len))
4981 would_hit_hwbug = 1;
4982
4983 if (tg3_40bit_overflow_test(tp, mapping, len))
4984 would_hit_hwbug = 1;
4985
4986 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4987 tg3_set_txd(tp, entry, mapping, len,
4988 base_flags, (i == last)|(mss << 1));
4989 else
4990 tg3_set_txd(tp, entry, mapping, len,
4991 base_flags, (i == last));
4992
4993 entry = NEXT_TX(entry);
4994 }
4995 }
4996
4997 if (would_hit_hwbug) {
4998 u32 last_plus_one = entry;
4999 u32 start;
5000
5001 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5002 start &= (TG3_TX_RING_SIZE - 1);
5003
5004 /* If the workaround fails due to memory/mapping
5005 * failure, silently drop this packet.
5006 */
5007 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5008 &start, base_flags, mss))
5009 goto out_unlock;
5010
5011 entry = start;
5012 }
5013
5014 /* Packets are ready, update Tx producer idx local and on card. */
5015 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5016
5017 tp->tx_prod = entry;
5018 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5019 netif_stop_queue(dev);
5020 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5021 netif_wake_queue(tp->dev);
5022 }
5023
5024out_unlock:
5025 mmiowb();
5026
5027 dev->trans_start = jiffies;
5028
5029 return NETDEV_TX_OK;
5030}
5031
5032static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5033 int new_mtu)
5034{
5035 dev->mtu = new_mtu;
5036
5037 if (new_mtu > ETH_DATA_LEN) {
5038 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5039 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5040 ethtool_op_set_tso(dev, 0);
5041 }
5042 else
5043 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5044 } else {
5045 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5046 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5047 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5048 }
5049}
5050
5051static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5052{
5053 struct tg3 *tp = netdev_priv(dev);
5054 int err;
5055
5056 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5057 return -EINVAL;
5058
5059 if (!netif_running(dev)) {
5060 /* We'll just catch it later when the
5061 * device is up'd.
5062 */
5063 tg3_set_mtu(dev, tp, new_mtu);
5064 return 0;
5065 }
5066
5067 tg3_phy_stop(tp);
5068
5069 tg3_netif_stop(tp);
5070
5071 tg3_full_lock(tp, 1);
5072
5073 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5074
5075 tg3_set_mtu(dev, tp, new_mtu);
5076
5077 err = tg3_restart_hw(tp, 0);
5078
5079 if (!err)
5080 tg3_netif_start(tp);
5081
5082 tg3_full_unlock(tp);
5083
5084 if (!err)
5085 tg3_phy_start(tp);
5086
5087 return err;
5088}
5089
5090/* Free up pending packets in all rx/tx rings.
5091 *
5092 * The chip has been shut down and the driver detached from
5093 * the networking, so no interrupts or new tx packets will
5094 * end up in the driver. tp->{tx,}lock is not held and we are not
5095 * in an interrupt context and thus may sleep.
5096 */
5097static void tg3_free_rings(struct tg3 *tp)
5098{
5099 struct ring_info *rxp;
5100 int i;
5101
5102 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5103 rxp = &tp->rx_std_buffers[i];
5104
5105 if (rxp->skb == NULL)
5106 continue;
5107 pci_unmap_single(tp->pdev,
5108 pci_unmap_addr(rxp, mapping),
5109 tp->rx_pkt_buf_sz - tp->rx_offset,
5110 PCI_DMA_FROMDEVICE);
5111 dev_kfree_skb_any(rxp->skb);
5112 rxp->skb = NULL;
5113 }
5114
5115 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5116 rxp = &tp->rx_jumbo_buffers[i];
5117
5118 if (rxp->skb == NULL)
5119 continue;
5120 pci_unmap_single(tp->pdev,
5121 pci_unmap_addr(rxp, mapping),
5122 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5123 PCI_DMA_FROMDEVICE);
5124 dev_kfree_skb_any(rxp->skb);
5125 rxp->skb = NULL;
5126 }
5127
5128 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5129 struct tx_ring_info *txp;
5130 struct sk_buff *skb;
5131 int j;
5132
5133 txp = &tp->tx_buffers[i];
5134 skb = txp->skb;
5135
5136 if (skb == NULL) {
5137 i++;
5138 continue;
5139 }
5140
5141 pci_unmap_single(tp->pdev,
5142 pci_unmap_addr(txp, mapping),
5143 skb_headlen(skb),
5144 PCI_DMA_TODEVICE);
5145 txp->skb = NULL;
5146
5147 i++;
5148
5149 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5150 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5151 pci_unmap_page(tp->pdev,
5152 pci_unmap_addr(txp, mapping),
5153 skb_shinfo(skb)->frags[j].size,
5154 PCI_DMA_TODEVICE);
5155 i++;
5156 }
5157
5158 dev_kfree_skb_any(skb);
5159 }
5160}
5161
5162/* Initialize tx/rx rings for packet processing.
5163 *
5164 * The chip has been shut down and the driver detached from
5165 * the networking, so no interrupts or new tx packets will
5166 * end up in the driver. tp->{tx,}lock are held and thus
5167 * we may not sleep.
5168 */
5169static int tg3_init_rings(struct tg3 *tp)
5170{
5171 u32 i;
5172
5173 /* Free up all the SKBs. */
5174 tg3_free_rings(tp);
5175
5176 /* Zero out all descriptors. */
5177 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5178 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5179 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5180 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5181
5182 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5183 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5184 (tp->dev->mtu > ETH_DATA_LEN))
5185 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5186
5187 /* Initialize invariants of the rings, we only set this
5188 * stuff once. This works because the card does not
5189 * write into the rx buffer posting rings.
5190 */
5191 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5192 struct tg3_rx_buffer_desc *rxd;
5193
5194 rxd = &tp->rx_std[i];
5195 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5196 << RXD_LEN_SHIFT;
5197 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5198 rxd->opaque = (RXD_OPAQUE_RING_STD |
5199 (i << RXD_OPAQUE_INDEX_SHIFT));
5200 }
5201
5202 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5203 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5204 struct tg3_rx_buffer_desc *rxd;
5205
5206 rxd = &tp->rx_jumbo[i];
5207 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5208 << RXD_LEN_SHIFT;
5209 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5210 RXD_FLAG_JUMBO;
5211 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5212 (i << RXD_OPAQUE_INDEX_SHIFT));
5213 }
5214 }
5215
5216 /* Now allocate fresh SKBs for each rx ring. */
5217 for (i = 0; i < tp->rx_pending; i++) {
5218 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5219 printk(KERN_WARNING PFX
5220 "%s: Using a smaller RX standard ring, "
5221 "only %d out of %d buffers were allocated "
5222 "successfully.\n",
5223 tp->dev->name, i, tp->rx_pending);
5224 if (i == 0)
5225 return -ENOMEM;
5226 tp->rx_pending = i;
5227 break;
5228 }
5229 }
5230
5231 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5232 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5233 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5234 -1, i) < 0) {
5235 printk(KERN_WARNING PFX
5236 "%s: Using a smaller RX jumbo ring, "
5237 "only %d out of %d buffers were "
5238 "allocated successfully.\n",
5239 tp->dev->name, i, tp->rx_jumbo_pending);
5240 if (i == 0) {
5241 tg3_free_rings(tp);
5242 return -ENOMEM;
5243 }
5244 tp->rx_jumbo_pending = i;
5245 break;
5246 }
5247 }
5248 }
5249 return 0;
5250}
5251
5252/*
5253 * Must not be invoked with interrupt sources disabled and
5254 * the hardware shutdown down.
5255 */
5256static void tg3_free_consistent(struct tg3 *tp)
5257{
5258 kfree(tp->rx_std_buffers);
5259 tp->rx_std_buffers = NULL;
5260 if (tp->rx_std) {
5261 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5262 tp->rx_std, tp->rx_std_mapping);
5263 tp->rx_std = NULL;
5264 }
5265 if (tp->rx_jumbo) {
5266 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5267 tp->rx_jumbo, tp->rx_jumbo_mapping);
5268 tp->rx_jumbo = NULL;
5269 }
5270 if (tp->rx_rcb) {
5271 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5272 tp->rx_rcb, tp->rx_rcb_mapping);
5273 tp->rx_rcb = NULL;
5274 }
5275 if (tp->tx_ring) {
5276 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5277 tp->tx_ring, tp->tx_desc_mapping);
5278 tp->tx_ring = NULL;
5279 }
5280 if (tp->hw_status) {
5281 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5282 tp->hw_status, tp->status_mapping);
5283 tp->hw_status = NULL;
5284 }
5285 if (tp->hw_stats) {
5286 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5287 tp->hw_stats, tp->stats_mapping);
5288 tp->hw_stats = NULL;
5289 }
5290}
5291
5292/*
5293 * Must not be invoked with interrupt sources disabled and
5294 * the hardware shutdown down. Can sleep.
5295 */
5296static int tg3_alloc_consistent(struct tg3 *tp)
5297{
5298 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5299 (TG3_RX_RING_SIZE +
5300 TG3_RX_JUMBO_RING_SIZE)) +
5301 (sizeof(struct tx_ring_info) *
5302 TG3_TX_RING_SIZE),
5303 GFP_KERNEL);
5304 if (!tp->rx_std_buffers)
5305 return -ENOMEM;
5306
5307 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5308 tp->tx_buffers = (struct tx_ring_info *)
5309 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5310
5311 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5312 &tp->rx_std_mapping);
5313 if (!tp->rx_std)
5314 goto err_out;
5315
5316 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5317 &tp->rx_jumbo_mapping);
5318
5319 if (!tp->rx_jumbo)
5320 goto err_out;
5321
5322 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5323 &tp->rx_rcb_mapping);
5324 if (!tp->rx_rcb)
5325 goto err_out;
5326
5327 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5328 &tp->tx_desc_mapping);
5329 if (!tp->tx_ring)
5330 goto err_out;
5331
5332 tp->hw_status = pci_alloc_consistent(tp->pdev,
5333 TG3_HW_STATUS_SIZE,
5334 &tp->status_mapping);
5335 if (!tp->hw_status)
5336 goto err_out;
5337
5338 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5339 sizeof(struct tg3_hw_stats),
5340 &tp->stats_mapping);
5341 if (!tp->hw_stats)
5342 goto err_out;
5343
5344 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5345 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5346
5347 return 0;
5348
5349err_out:
5350 tg3_free_consistent(tp);
5351 return -ENOMEM;
5352}
5353
5354#define MAX_WAIT_CNT 1000
5355
5356/* To stop a block, clear the enable bit and poll till it
5357 * clears. tp->lock is held.
5358 */
5359static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5360{
5361 unsigned int i;
5362 u32 val;
5363
5364 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5365 switch (ofs) {
5366 case RCVLSC_MODE:
5367 case DMAC_MODE:
5368 case MBFREE_MODE:
5369 case BUFMGR_MODE:
5370 case MEMARB_MODE:
5371 /* We can't enable/disable these bits of the
5372 * 5705/5750, just say success.
5373 */
5374 return 0;
5375
5376 default:
5377 break;
5378 }
5379 }
5380
5381 val = tr32(ofs);
5382 val &= ~enable_bit;
5383 tw32_f(ofs, val);
5384
5385 for (i = 0; i < MAX_WAIT_CNT; i++) {
5386 udelay(100);
5387 val = tr32(ofs);
5388 if ((val & enable_bit) == 0)
5389 break;
5390 }
5391
5392 if (i == MAX_WAIT_CNT && !silent) {
5393 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5394 "ofs=%lx enable_bit=%x\n",
5395 ofs, enable_bit);
5396 return -ENODEV;
5397 }
5398
5399 return 0;
5400}
5401
5402/* tp->lock is held. */
5403static int tg3_abort_hw(struct tg3 *tp, int silent)
5404{
5405 int i, err;
5406
5407 tg3_disable_ints(tp);
5408
5409 tp->rx_mode &= ~RX_MODE_ENABLE;
5410 tw32_f(MAC_RX_MODE, tp->rx_mode);
5411 udelay(10);
5412
5413 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5414 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5415 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5416 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5417 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5418 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5419
5420 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5421 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5422 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5423 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5424 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5425 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5426 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5427
5428 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5429 tw32_f(MAC_MODE, tp->mac_mode);
5430 udelay(40);
5431
5432 tp->tx_mode &= ~TX_MODE_ENABLE;
5433 tw32_f(MAC_TX_MODE, tp->tx_mode);
5434
5435 for (i = 0; i < MAX_WAIT_CNT; i++) {
5436 udelay(100);
5437 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5438 break;
5439 }
5440 if (i >= MAX_WAIT_CNT) {
5441 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5442 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5443 tp->dev->name, tr32(MAC_TX_MODE));
5444 err |= -ENODEV;
5445 }
5446
5447 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5448 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5449 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5450
5451 tw32(FTQ_RESET, 0xffffffff);
5452 tw32(FTQ_RESET, 0x00000000);
5453
5454 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5455 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5456
5457 if (tp->hw_status)
5458 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5459 if (tp->hw_stats)
5460 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5461
5462 return err;
5463}
5464
5465/* tp->lock is held. */
5466static int tg3_nvram_lock(struct tg3 *tp)
5467{
5468 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5469 int i;
5470
5471 if (tp->nvram_lock_cnt == 0) {
5472 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5473 for (i = 0; i < 8000; i++) {
5474 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5475 break;
5476 udelay(20);
5477 }
5478 if (i == 8000) {
5479 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5480 return -ENODEV;
5481 }
5482 }
5483 tp->nvram_lock_cnt++;
5484 }
5485 return 0;
5486}
5487
5488/* tp->lock is held. */
5489static void tg3_nvram_unlock(struct tg3 *tp)
5490{
5491 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5492 if (tp->nvram_lock_cnt > 0)
5493 tp->nvram_lock_cnt--;
5494 if (tp->nvram_lock_cnt == 0)
5495 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5496 }
5497}
5498
5499/* tp->lock is held. */
5500static void tg3_enable_nvram_access(struct tg3 *tp)
5501{
5502 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5503 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5504 u32 nvaccess = tr32(NVRAM_ACCESS);
5505
5506 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5507 }
5508}
5509
5510/* tp->lock is held. */
5511static void tg3_disable_nvram_access(struct tg3 *tp)
5512{
5513 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5514 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5515 u32 nvaccess = tr32(NVRAM_ACCESS);
5516
5517 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5518 }
5519}
5520
5521static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5522{
5523 int i;
5524 u32 apedata;
5525
5526 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5527 if (apedata != APE_SEG_SIG_MAGIC)
5528 return;
5529
5530 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5531 if (!(apedata & APE_FW_STATUS_READY))
5532 return;
5533
5534 /* Wait for up to 1 millisecond for APE to service previous event. */
5535 for (i = 0; i < 10; i++) {
5536 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5537 return;
5538
5539 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5540
5541 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5542 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5543 event | APE_EVENT_STATUS_EVENT_PENDING);
5544
5545 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5546
5547 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5548 break;
5549
5550 udelay(100);
5551 }
5552
5553 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5554 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5555}
5556
5557static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5558{
5559 u32 event;
5560 u32 apedata;
5561
5562 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5563 return;
5564
5565 switch (kind) {
5566 case RESET_KIND_INIT:
5567 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5568 APE_HOST_SEG_SIG_MAGIC);
5569 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5570 APE_HOST_SEG_LEN_MAGIC);
5571 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5572 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5573 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5574 APE_HOST_DRIVER_ID_MAGIC);
5575 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5576 APE_HOST_BEHAV_NO_PHYLOCK);
5577
5578 event = APE_EVENT_STATUS_STATE_START;
5579 break;
5580 case RESET_KIND_SHUTDOWN:
5581 event = APE_EVENT_STATUS_STATE_UNLOAD;
5582 break;
5583 case RESET_KIND_SUSPEND:
5584 event = APE_EVENT_STATUS_STATE_SUSPEND;
5585 break;
5586 default:
5587 return;
5588 }
5589
5590 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5591
5592 tg3_ape_send_event(tp, event);
5593}
5594
5595/* tp->lock is held. */
5596static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5597{
5598 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5599 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5600
5601 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5602 switch (kind) {
5603 case RESET_KIND_INIT:
5604 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5605 DRV_STATE_START);
5606 break;
5607
5608 case RESET_KIND_SHUTDOWN:
5609 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5610 DRV_STATE_UNLOAD);
5611 break;
5612
5613 case RESET_KIND_SUSPEND:
5614 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5615 DRV_STATE_SUSPEND);
5616 break;
5617
5618 default:
5619 break;
5620 }
5621 }
5622
5623 if (kind == RESET_KIND_INIT ||
5624 kind == RESET_KIND_SUSPEND)
5625 tg3_ape_driver_state_change(tp, kind);
5626}
5627
5628/* tp->lock is held. */
5629static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5630{
5631 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5632 switch (kind) {
5633 case RESET_KIND_INIT:
5634 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5635 DRV_STATE_START_DONE);
5636 break;
5637
5638 case RESET_KIND_SHUTDOWN:
5639 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5640 DRV_STATE_UNLOAD_DONE);
5641 break;
5642
5643 default:
5644 break;
5645 }
5646 }
5647
5648 if (kind == RESET_KIND_SHUTDOWN)
5649 tg3_ape_driver_state_change(tp, kind);
5650}
5651
5652/* tp->lock is held. */
5653static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5654{
5655 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5656 switch (kind) {
5657 case RESET_KIND_INIT:
5658 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5659 DRV_STATE_START);
5660 break;
5661
5662 case RESET_KIND_SHUTDOWN:
5663 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5664 DRV_STATE_UNLOAD);
5665 break;
5666
5667 case RESET_KIND_SUSPEND:
5668 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5669 DRV_STATE_SUSPEND);
5670 break;
5671
5672 default:
5673 break;
5674 }
5675 }
5676}
5677
5678static int tg3_poll_fw(struct tg3 *tp)
5679{
5680 int i;
5681 u32 val;
5682
5683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5684 /* Wait up to 20ms for init done. */
5685 for (i = 0; i < 200; i++) {
5686 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5687 return 0;
5688 udelay(100);
5689 }
5690 return -ENODEV;
5691 }
5692
5693 /* Wait for firmware initialization to complete. */
5694 for (i = 0; i < 100000; i++) {
5695 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5696 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5697 break;
5698 udelay(10);
5699 }
5700
5701 /* Chip might not be fitted with firmware. Some Sun onboard
5702 * parts are configured like that. So don't signal the timeout
5703 * of the above loop as an error, but do report the lack of
5704 * running firmware once.
5705 */
5706 if (i >= 100000 &&
5707 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5708 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5709
5710 printk(KERN_INFO PFX "%s: No firmware running.\n",
5711 tp->dev->name);
5712 }
5713
5714 return 0;
5715}
5716
5717/* Save PCI command register before chip reset */
5718static void tg3_save_pci_state(struct tg3 *tp)
5719{
5720 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5721}
5722
5723/* Restore PCI state after chip reset */
5724static void tg3_restore_pci_state(struct tg3 *tp)
5725{
5726 u32 val;
5727
5728 /* Re-enable indirect register accesses. */
5729 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5730 tp->misc_host_ctrl);
5731
5732 /* Set MAX PCI retry to zero. */
5733 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5734 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5735 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5736 val |= PCISTATE_RETRY_SAME_DMA;
5737 /* Allow reads and writes to the APE register and memory space. */
5738 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5739 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5740 PCISTATE_ALLOW_APE_SHMEM_WR;
5741 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5742
5743 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5744
5745 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5746 pcie_set_readrq(tp->pdev, 4096);
5747 else {
5748 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5749 tp->pci_cacheline_sz);
5750 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5751 tp->pci_lat_timer);
5752 }
5753
5754 /* Make sure PCI-X relaxed ordering bit is clear. */
5755 if (tp->pcix_cap) {
5756 u16 pcix_cmd;
5757
5758 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5759 &pcix_cmd);
5760 pcix_cmd &= ~PCI_X_CMD_ERO;
5761 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5762 pcix_cmd);
5763 }
5764
5765 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5766
5767 /* Chip reset on 5780 will reset MSI enable bit,
5768 * so need to restore it.
5769 */
5770 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5771 u16 ctrl;
5772
5773 pci_read_config_word(tp->pdev,
5774 tp->msi_cap + PCI_MSI_FLAGS,
5775 &ctrl);
5776 pci_write_config_word(tp->pdev,
5777 tp->msi_cap + PCI_MSI_FLAGS,
5778 ctrl | PCI_MSI_FLAGS_ENABLE);
5779 val = tr32(MSGINT_MODE);
5780 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5781 }
5782 }
5783}
5784
5785static void tg3_stop_fw(struct tg3 *);
5786
5787/* tp->lock is held. */
5788static int tg3_chip_reset(struct tg3 *tp)
5789{
5790 u32 val;
5791 void (*write_op)(struct tg3 *, u32, u32);
5792 int err;
5793
5794 tg3_nvram_lock(tp);
5795
5796 tg3_mdio_stop(tp);
5797
5798 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5799
5800 /* No matching tg3_nvram_unlock() after this because
5801 * chip reset below will undo the nvram lock.
5802 */
5803 tp->nvram_lock_cnt = 0;
5804
5805 /* GRC_MISC_CFG core clock reset will clear the memory
5806 * enable bit in PCI register 4 and the MSI enable bit
5807 * on some chips, so we save relevant registers here.
5808 */
5809 tg3_save_pci_state(tp);
5810
5811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5812 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5815 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5816 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5817 tw32(GRC_FASTBOOT_PC, 0);
5818
5819 /*
5820 * We must avoid the readl() that normally takes place.
5821 * It locks machines, causes machine checks, and other
5822 * fun things. So, temporarily disable the 5701
5823 * hardware workaround, while we do the reset.
5824 */
5825 write_op = tp->write32;
5826 if (write_op == tg3_write_flush_reg32)
5827 tp->write32 = tg3_write32;
5828
5829 /* Prevent the irq handler from reading or writing PCI registers
5830 * during chip reset when the memory enable bit in the PCI command
5831 * register may be cleared. The chip does not generate interrupt
5832 * at this time, but the irq handler may still be called due to irq
5833 * sharing or irqpoll.
5834 */
5835 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5836 if (tp->hw_status) {
5837 tp->hw_status->status = 0;
5838 tp->hw_status->status_tag = 0;
5839 }
5840 tp->last_tag = 0;
5841 smp_mb();
5842 synchronize_irq(tp->pdev->irq);
5843
5844 /* do the reset */
5845 val = GRC_MISC_CFG_CORECLK_RESET;
5846
5847 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5848 if (tr32(0x7e2c) == 0x60) {
5849 tw32(0x7e2c, 0x20);
5850 }
5851 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5852 tw32(GRC_MISC_CFG, (1 << 29));
5853 val |= (1 << 29);
5854 }
5855 }
5856
5857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5858 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5859 tw32(GRC_VCPU_EXT_CTRL,
5860 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5861 }
5862
5863 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5864 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5865 tw32(GRC_MISC_CFG, val);
5866
5867 /* restore 5701 hardware bug workaround write method */
5868 tp->write32 = write_op;
5869
5870 /* Unfortunately, we have to delay before the PCI read back.
5871 * Some 575X chips even will not respond to a PCI cfg access
5872 * when the reset command is given to the chip.
5873 *
5874 * How do these hardware designers expect things to work
5875 * properly if the PCI write is posted for a long period
5876 * of time? It is always necessary to have some method by
5877 * which a register read back can occur to push the write
5878 * out which does the reset.
5879 *
5880 * For most tg3 variants the trick below was working.
5881 * Ho hum...
5882 */
5883 udelay(120);
5884
5885 /* Flush PCI posted writes. The normal MMIO registers
5886 * are inaccessible at this time so this is the only
5887 * way to make this reliably (actually, this is no longer
5888 * the case, see above). I tried to use indirect
5889 * register read/write but this upset some 5701 variants.
5890 */
5891 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5892
5893 udelay(120);
5894
5895 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5896 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5897 int i;
5898 u32 cfg_val;
5899
5900 /* Wait for link training to complete. */
5901 for (i = 0; i < 5000; i++)
5902 udelay(100);
5903
5904 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5905 pci_write_config_dword(tp->pdev, 0xc4,
5906 cfg_val | (1 << 15));
5907 }
5908 /* Set PCIE max payload size and clear error status. */
5909 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5910 }
5911
5912 tg3_restore_pci_state(tp);
5913
5914 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5915
5916 val = 0;
5917 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5918 val = tr32(MEMARB_MODE);
5919 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5920
5921 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5922 tg3_stop_fw(tp);
5923 tw32(0x5000, 0x400);
5924 }
5925
5926 tw32(GRC_MODE, tp->grc_mode);
5927
5928 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5929 val = tr32(0xc4);
5930
5931 tw32(0xc4, val | (1 << 15));
5932 }
5933
5934 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5936 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5937 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5938 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5939 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5940 }
5941
5942 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5943 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5944 tw32_f(MAC_MODE, tp->mac_mode);
5945 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5946 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5947 tw32_f(MAC_MODE, tp->mac_mode);
5948 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
5949 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
5950 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
5951 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
5952 tw32_f(MAC_MODE, tp->mac_mode);
5953 } else
5954 tw32_f(MAC_MODE, 0);
5955 udelay(40);
5956
5957 tg3_mdio_start(tp);
5958
5959 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
5960
5961 err = tg3_poll_fw(tp);
5962 if (err)
5963 return err;
5964
5965 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5966 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5967 val = tr32(0x7c00);
5968
5969 tw32(0x7c00, val | (1 << 25));
5970 }
5971
5972 /* Reprobe ASF enable state. */
5973 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5974 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5975 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5976 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5977 u32 nic_cfg;
5978
5979 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5980 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5981 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5982 tp->last_event_jiffies = jiffies;
5983 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5984 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5985 }
5986 }
5987
5988 return 0;
5989}
5990
5991/* tp->lock is held. */
5992static void tg3_stop_fw(struct tg3 *tp)
5993{
5994 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5995 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5996 /* Wait for RX cpu to ACK the previous event. */
5997 tg3_wait_for_event_ack(tp);
5998
5999 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6000
6001 tg3_generate_fw_event(tp);
6002
6003 /* Wait for RX cpu to ACK this event. */
6004 tg3_wait_for_event_ack(tp);
6005 }
6006}
6007
6008/* tp->lock is held. */
6009static int tg3_halt(struct tg3 *tp, int kind, int silent)
6010{
6011 int err;
6012
6013 tg3_stop_fw(tp);
6014
6015 tg3_write_sig_pre_reset(tp, kind);
6016
6017 tg3_abort_hw(tp, silent);
6018 err = tg3_chip_reset(tp);
6019
6020 tg3_write_sig_legacy(tp, kind);
6021 tg3_write_sig_post_reset(tp, kind);
6022
6023 if (err)
6024 return err;
6025
6026 return 0;
6027}
6028
6029#define TG3_FW_RELEASE_MAJOR 0x0
6030#define TG3_FW_RELASE_MINOR 0x0
6031#define TG3_FW_RELEASE_FIX 0x0
6032#define TG3_FW_START_ADDR 0x08000000
6033#define TG3_FW_TEXT_ADDR 0x08000000
6034#define TG3_FW_TEXT_LEN 0x9c0
6035#define TG3_FW_RODATA_ADDR 0x080009c0
6036#define TG3_FW_RODATA_LEN 0x60
6037#define TG3_FW_DATA_ADDR 0x08000a40
6038#define TG3_FW_DATA_LEN 0x20
6039#define TG3_FW_SBSS_ADDR 0x08000a60
6040#define TG3_FW_SBSS_LEN 0xc
6041#define TG3_FW_BSS_ADDR 0x08000a70
6042#define TG3_FW_BSS_LEN 0x10
6043
6044static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
6045 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6046 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6047 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6048 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6049 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6050 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6051 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6052 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6053 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6054 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6055 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6056 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6057 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6058 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6059 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6060 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6061 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6062 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6063 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6064 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6065 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6066 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6067 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6068 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6069 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6070 0, 0, 0, 0, 0, 0,
6071 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6072 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6073 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6074 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6075 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6076 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6077 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6078 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6079 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6080 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6081 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6082 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6083 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6084 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6085 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6086 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6087 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6088 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6089 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6090 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6091 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6092 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6093 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6094 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6095 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6096 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6097 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6098 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6099 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6100 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6101 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6102 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6103 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6104 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6105 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6106 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6107 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6108 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6109 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6110 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6111 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6112 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6113 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6114 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6115 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6116 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6117 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6118 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6119 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6120 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6121 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6122 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6123 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6124 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6125 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6126 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6127 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6128 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6129 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6130 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6131 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6132 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6133 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6134 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6135 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6136};
6137
6138static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6139 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6140 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6141 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6142 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6143 0x00000000
6144};
6145
6146#if 0 /* All zeros, don't eat up space with it. */
6147u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6148 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6149 0x00000000, 0x00000000, 0x00000000, 0x00000000
6150};
6151#endif
6152
6153#define RX_CPU_SCRATCH_BASE 0x30000
6154#define RX_CPU_SCRATCH_SIZE 0x04000
6155#define TX_CPU_SCRATCH_BASE 0x34000
6156#define TX_CPU_SCRATCH_SIZE 0x04000
6157
6158/* tp->lock is held. */
6159static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6160{
6161 int i;
6162
6163 BUG_ON(offset == TX_CPU_BASE &&
6164 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6165
6166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6167 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6168
6169 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6170 return 0;
6171 }
6172 if (offset == RX_CPU_BASE) {
6173 for (i = 0; i < 10000; i++) {
6174 tw32(offset + CPU_STATE, 0xffffffff);
6175 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6176 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6177 break;
6178 }
6179
6180 tw32(offset + CPU_STATE, 0xffffffff);
6181 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6182 udelay(10);
6183 } else {
6184 for (i = 0; i < 10000; i++) {
6185 tw32(offset + CPU_STATE, 0xffffffff);
6186 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6187 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6188 break;
6189 }
6190 }
6191
6192 if (i >= 10000) {
6193 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6194 "and %s CPU\n",
6195 tp->dev->name,
6196 (offset == RX_CPU_BASE ? "RX" : "TX"));
6197 return -ENODEV;
6198 }
6199
6200 /* Clear firmware's nvram arbitration. */
6201 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6202 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6203 return 0;
6204}
6205
6206struct fw_info {
6207 unsigned int text_base;
6208 unsigned int text_len;
6209 const u32 *text_data;
6210 unsigned int rodata_base;
6211 unsigned int rodata_len;
6212 const u32 *rodata_data;
6213 unsigned int data_base;
6214 unsigned int data_len;
6215 const u32 *data_data;
6216};
6217
6218/* tp->lock is held. */
6219static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6220 int cpu_scratch_size, struct fw_info *info)
6221{
6222 int err, lock_err, i;
6223 void (*write_op)(struct tg3 *, u32, u32);
6224
6225 if (cpu_base == TX_CPU_BASE &&
6226 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6227 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6228 "TX cpu firmware on %s which is 5705.\n",
6229 tp->dev->name);
6230 return -EINVAL;
6231 }
6232
6233 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6234 write_op = tg3_write_mem;
6235 else
6236 write_op = tg3_write_indirect_reg32;
6237
6238 /* It is possible that bootcode is still loading at this point.
6239 * Get the nvram lock first before halting the cpu.
6240 */
6241 lock_err = tg3_nvram_lock(tp);
6242 err = tg3_halt_cpu(tp, cpu_base);
6243 if (!lock_err)
6244 tg3_nvram_unlock(tp);
6245 if (err)
6246 goto out;
6247
6248 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6249 write_op(tp, cpu_scratch_base + i, 0);
6250 tw32(cpu_base + CPU_STATE, 0xffffffff);
6251 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6252 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6253 write_op(tp, (cpu_scratch_base +
6254 (info->text_base & 0xffff) +
6255 (i * sizeof(u32))),
6256 (info->text_data ?
6257 info->text_data[i] : 0));
6258 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6259 write_op(tp, (cpu_scratch_base +
6260 (info->rodata_base & 0xffff) +
6261 (i * sizeof(u32))),
6262 (info->rodata_data ?
6263 info->rodata_data[i] : 0));
6264 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6265 write_op(tp, (cpu_scratch_base +
6266 (info->data_base & 0xffff) +
6267 (i * sizeof(u32))),
6268 (info->data_data ?
6269 info->data_data[i] : 0));
6270
6271 err = 0;
6272
6273out:
6274 return err;
6275}
6276
6277/* tp->lock is held. */
6278static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6279{
6280 struct fw_info info;
6281 int err, i;
6282
6283 info.text_base = TG3_FW_TEXT_ADDR;
6284 info.text_len = TG3_FW_TEXT_LEN;
6285 info.text_data = &tg3FwText[0];
6286 info.rodata_base = TG3_FW_RODATA_ADDR;
6287 info.rodata_len = TG3_FW_RODATA_LEN;
6288 info.rodata_data = &tg3FwRodata[0];
6289 info.data_base = TG3_FW_DATA_ADDR;
6290 info.data_len = TG3_FW_DATA_LEN;
6291 info.data_data = NULL;
6292
6293 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6294 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6295 &info);
6296 if (err)
6297 return err;
6298
6299 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6300 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6301 &info);
6302 if (err)
6303 return err;
6304
6305 /* Now startup only the RX cpu. */
6306 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6307 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6308
6309 for (i = 0; i < 5; i++) {
6310 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6311 break;
6312 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6313 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6314 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
6315 udelay(1000);
6316 }
6317 if (i >= 5) {
6318 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6319 "to set RX CPU PC, is %08x should be %08x\n",
6320 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6321 TG3_FW_TEXT_ADDR);
6322 return -ENODEV;
6323 }
6324 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6325 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6326
6327 return 0;
6328}
6329
6330
6331#define TG3_TSO_FW_RELEASE_MAJOR 0x1
6332#define TG3_TSO_FW_RELASE_MINOR 0x6
6333#define TG3_TSO_FW_RELEASE_FIX 0x0
6334#define TG3_TSO_FW_START_ADDR 0x08000000
6335#define TG3_TSO_FW_TEXT_ADDR 0x08000000
6336#define TG3_TSO_FW_TEXT_LEN 0x1aa0
6337#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
6338#define TG3_TSO_FW_RODATA_LEN 0x60
6339#define TG3_TSO_FW_DATA_ADDR 0x08001b20
6340#define TG3_TSO_FW_DATA_LEN 0x30
6341#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
6342#define TG3_TSO_FW_SBSS_LEN 0x2c
6343#define TG3_TSO_FW_BSS_ADDR 0x08001b80
6344#define TG3_TSO_FW_BSS_LEN 0x894
6345
6346static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6347 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6348 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6349 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6350 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6351 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6352 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6353 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6354 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6355 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6356 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6357 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6358 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6359 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6360 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6361 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6362 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6363 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6364 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6365 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6366 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6367 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6368 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6369 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6370 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6371 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6372 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6373 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6374 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6375 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6376 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6377 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6378 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6379 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6380 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6381 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6382 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6383 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6384 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6385 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6386 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6387 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6388 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6389 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6390 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6391 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6392 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6393 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6394 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6395 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6396 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6397 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6398 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6399 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6400 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6401 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6402 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6403 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6404 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6405 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6406 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6407 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6408 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6409 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6410 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6411 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6412 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6413 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6414 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6415 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6416 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6417 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6418 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6419 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6420 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6421 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6422 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6423 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6424 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6425 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6426 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6427 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6428 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6429 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6430 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6431 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6432 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6433 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6434 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6435 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6436 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6437 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6438 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6439 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6440 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6441 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6442 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6443 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6444 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6445 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6446 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6447 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6448 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6449 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6450 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6451 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6452 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6453 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6454 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6455 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6456 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6457 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6458 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6459 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6460 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6461 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6462 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6463 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6464 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6465 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6466 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6467 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6468 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6469 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6470 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6471 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6472 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6473 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6474 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6475 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6476 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6477 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6478 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6479 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6480 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6481 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6482 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6483 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6484 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6485 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6486 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6487 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6488 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6489 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6490 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6491 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6492 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6493 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6494 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6495 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6496 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6497 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6498 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6499 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6500 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6501 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6502 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6503 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6504 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6505 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6506 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6507 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6508 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6509 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6510 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6511 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6512 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6513 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6514 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6515 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6516 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6517 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6518 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6519 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6520 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6521 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6522 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6523 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6524 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6525 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6526 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6527 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6528 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6529 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6530 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6531 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6532 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6533 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6534 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6535 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6536 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6537 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6538 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6539 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6540 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6541 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6542 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6543 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6544 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6545 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6546 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6547 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6548 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6549 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6550 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6551 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6552 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6553 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6554 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6555 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6556 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6557 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6558 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6559 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6560 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6561 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6562 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6563 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6564 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6565 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6566 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6567 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6568 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6569 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6570 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6571 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6572 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6573 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6574 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6575 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6576 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6577 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6578 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6579 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6580 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6581 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6582 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6583 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6584 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6585 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6586 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6587 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6588 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6589 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6590 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6591 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6592 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6593 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6594 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6595 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6596 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6597 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6598 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6599 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6600 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6601 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6602 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6603 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6604 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6605 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6606 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6607 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6608 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6609 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6610 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6611 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6612 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6613 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6614 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6615 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6616 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6617 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6618 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6619 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6620 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6621 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6622 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6623 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6624 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6625 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6626 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6627 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6628 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6629 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6630 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6631};
6632
6633static const u32 tg3TsoFwRodata[] = {
6634 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6635 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6636 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6637 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6638 0x00000000,
6639};
6640
6641static const u32 tg3TsoFwData[] = {
6642 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6643 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6644 0x00000000,
6645};
6646
6647/* 5705 needs a special version of the TSO firmware. */
6648#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6649#define TG3_TSO5_FW_RELASE_MINOR 0x2
6650#define TG3_TSO5_FW_RELEASE_FIX 0x0
6651#define TG3_TSO5_FW_START_ADDR 0x00010000
6652#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6653#define TG3_TSO5_FW_TEXT_LEN 0xe90
6654#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6655#define TG3_TSO5_FW_RODATA_LEN 0x50
6656#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6657#define TG3_TSO5_FW_DATA_LEN 0x20
6658#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6659#define TG3_TSO5_FW_SBSS_LEN 0x28
6660#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6661#define TG3_TSO5_FW_BSS_LEN 0x88
6662
6663static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6664 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6665 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6666 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6667 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6668 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6669 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6670 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6671 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6672 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6673 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6674 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6675 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6676 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6677 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6678 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6679 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6680 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6681 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6682 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6683 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6684 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6685 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6686 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6687 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6688 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6689 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6690 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6691 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6692 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6693 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6694 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6695 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6696 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6697 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6698 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6699 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6700 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6701 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6702 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6703 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6704 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6705 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6706 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6707 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6708 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6709 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6710 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6711 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6712 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6713 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6714 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6715 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6716 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6717 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6718 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6719 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6720 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6721 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6722 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6723 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6724 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6725 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6726 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6727 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6728 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6729 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6730 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6731 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6732 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6733 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6734 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6735 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6736 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6737 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6738 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6739 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6740 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6741 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6742 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6743 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6744 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6745 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6746 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6747 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6748 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6749 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6750 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6751 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6752 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6753 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6754 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6755 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6756 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6757 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6758 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6759 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6760 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6761 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6762 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6763 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6764 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6765 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6766 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6767 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6768 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6769 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6770 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6771 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6772 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6773 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6774 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6775 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6776 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6777 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6778 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6779 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6780 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6781 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6782 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6783 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6784 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6785 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6786 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6787 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6788 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6789 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6790 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6791 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6792 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6793 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6794 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6795 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6796 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6797 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6798 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6799 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6800 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6801 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6802 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6803 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6804 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6805 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6806 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6807 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6808 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6809 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6810 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6811 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6812 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6813 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6814 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6815 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6816 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6817 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6818 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6819 0x00000000, 0x00000000, 0x00000000,
6820};
6821
6822static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6823 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6824 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6825 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6826 0x00000000, 0x00000000, 0x00000000,
6827};
6828
6829static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6830 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6831 0x00000000, 0x00000000, 0x00000000,
6832};
6833
6834/* tp->lock is held. */
6835static int tg3_load_tso_firmware(struct tg3 *tp)
6836{
6837 struct fw_info info;
6838 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6839 int err, i;
6840
6841 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6842 return 0;
6843
6844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6845 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6846 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6847 info.text_data = &tg3Tso5FwText[0];
6848 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6849 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6850 info.rodata_data = &tg3Tso5FwRodata[0];
6851 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6852 info.data_len = TG3_TSO5_FW_DATA_LEN;
6853 info.data_data = &tg3Tso5FwData[0];
6854 cpu_base = RX_CPU_BASE;
6855 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6856 cpu_scratch_size = (info.text_len +
6857 info.rodata_len +
6858 info.data_len +
6859 TG3_TSO5_FW_SBSS_LEN +
6860 TG3_TSO5_FW_BSS_LEN);
6861 } else {
6862 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6863 info.text_len = TG3_TSO_FW_TEXT_LEN;
6864 info.text_data = &tg3TsoFwText[0];
6865 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6866 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6867 info.rodata_data = &tg3TsoFwRodata[0];
6868 info.data_base = TG3_TSO_FW_DATA_ADDR;
6869 info.data_len = TG3_TSO_FW_DATA_LEN;
6870 info.data_data = &tg3TsoFwData[0];
6871 cpu_base = TX_CPU_BASE;
6872 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6873 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6874 }
6875
6876 err = tg3_load_firmware_cpu(tp, cpu_base,
6877 cpu_scratch_base, cpu_scratch_size,
6878 &info);
6879 if (err)
6880 return err;
6881
6882 /* Now startup the cpu. */
6883 tw32(cpu_base + CPU_STATE, 0xffffffff);
6884 tw32_f(cpu_base + CPU_PC, info.text_base);
6885
6886 for (i = 0; i < 5; i++) {
6887 if (tr32(cpu_base + CPU_PC) == info.text_base)
6888 break;
6889 tw32(cpu_base + CPU_STATE, 0xffffffff);
6890 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6891 tw32_f(cpu_base + CPU_PC, info.text_base);
6892 udelay(1000);
6893 }
6894 if (i >= 5) {
6895 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6896 "to set CPU PC, is %08x should be %08x\n",
6897 tp->dev->name, tr32(cpu_base + CPU_PC),
6898 info.text_base);
6899 return -ENODEV;
6900 }
6901 tw32(cpu_base + CPU_STATE, 0xffffffff);
6902 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6903 return 0;
6904}
6905
6906
6907/* tp->lock is held. */
6908static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6909{
6910 u32 addr_high, addr_low;
6911 int i;
6912
6913 addr_high = ((tp->dev->dev_addr[0] << 8) |
6914 tp->dev->dev_addr[1]);
6915 addr_low = ((tp->dev->dev_addr[2] << 24) |
6916 (tp->dev->dev_addr[3] << 16) |
6917 (tp->dev->dev_addr[4] << 8) |
6918 (tp->dev->dev_addr[5] << 0));
6919 for (i = 0; i < 4; i++) {
6920 if (i == 1 && skip_mac_1)
6921 continue;
6922 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6923 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6924 }
6925
6926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6928 for (i = 0; i < 12; i++) {
6929 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6930 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6931 }
6932 }
6933
6934 addr_high = (tp->dev->dev_addr[0] +
6935 tp->dev->dev_addr[1] +
6936 tp->dev->dev_addr[2] +
6937 tp->dev->dev_addr[3] +
6938 tp->dev->dev_addr[4] +
6939 tp->dev->dev_addr[5]) &
6940 TX_BACKOFF_SEED_MASK;
6941 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6942}
6943
6944static int tg3_set_mac_addr(struct net_device *dev, void *p)
6945{
6946 struct tg3 *tp = netdev_priv(dev);
6947 struct sockaddr *addr = p;
6948 int err = 0, skip_mac_1 = 0;
6949
6950 if (!is_valid_ether_addr(addr->sa_data))
6951 return -EINVAL;
6952
6953 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6954
6955 if (!netif_running(dev))
6956 return 0;
6957
6958 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6959 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6960
6961 addr0_high = tr32(MAC_ADDR_0_HIGH);
6962 addr0_low = tr32(MAC_ADDR_0_LOW);
6963 addr1_high = tr32(MAC_ADDR_1_HIGH);
6964 addr1_low = tr32(MAC_ADDR_1_LOW);
6965
6966 /* Skip MAC addr 1 if ASF is using it. */
6967 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6968 !(addr1_high == 0 && addr1_low == 0))
6969 skip_mac_1 = 1;
6970 }
6971 spin_lock_bh(&tp->lock);
6972 __tg3_set_mac_addr(tp, skip_mac_1);
6973 spin_unlock_bh(&tp->lock);
6974
6975 return err;
6976}
6977
6978/* tp->lock is held. */
6979static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6980 dma_addr_t mapping, u32 maxlen_flags,
6981 u32 nic_addr)
6982{
6983 tg3_write_mem(tp,
6984 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6985 ((u64) mapping >> 32));
6986 tg3_write_mem(tp,
6987 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6988 ((u64) mapping & 0xffffffff));
6989 tg3_write_mem(tp,
6990 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6991 maxlen_flags);
6992
6993 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6994 tg3_write_mem(tp,
6995 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6996 nic_addr);
6997}
6998
6999static void __tg3_set_rx_mode(struct net_device *);
7000static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7001{
7002 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7003 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7004 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7005 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7006 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7007 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7008 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7009 }
7010 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7011 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7012 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7013 u32 val = ec->stats_block_coalesce_usecs;
7014
7015 if (!netif_carrier_ok(tp->dev))
7016 val = 0;
7017
7018 tw32(HOSTCC_STAT_COAL_TICKS, val);
7019 }
7020}
7021
7022/* tp->lock is held. */
7023static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7024{
7025 u32 val, rdmac_mode;
7026 int i, err, limit;
7027
7028 tg3_disable_ints(tp);
7029
7030 tg3_stop_fw(tp);
7031
7032 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7033
7034 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7035 tg3_abort_hw(tp, 1);
7036 }
7037
7038 if (reset_phy &&
7039 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7040 tg3_phy_reset(tp);
7041
7042 err = tg3_chip_reset(tp);
7043 if (err)
7044 return err;
7045
7046 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7047
7048 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
7049 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7050 val = tr32(TG3_CPMU_CTRL);
7051 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7052 tw32(TG3_CPMU_CTRL, val);
7053
7054 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7055 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7056 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7057 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7058
7059 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7060 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7061 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7062 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7063
7064 val = tr32(TG3_CPMU_HST_ACC);
7065 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7066 val |= CPMU_HST_ACC_MACCLK_6_25;
7067 tw32(TG3_CPMU_HST_ACC, val);
7068 }
7069
7070 /* This works around an issue with Athlon chipsets on
7071 * B3 tigon3 silicon. This bit has no effect on any
7072 * other revision. But do not set this on PCI Express
7073 * chips and don't even touch the clocks if the CPMU is present.
7074 */
7075 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7076 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7077 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7078 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7079 }
7080
7081 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7082 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7083 val = tr32(TG3PCI_PCISTATE);
7084 val |= PCISTATE_RETRY_SAME_DMA;
7085 tw32(TG3PCI_PCISTATE, val);
7086 }
7087
7088 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7089 /* Allow reads and writes to the
7090 * APE register and memory space.
7091 */
7092 val = tr32(TG3PCI_PCISTATE);
7093 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7094 PCISTATE_ALLOW_APE_SHMEM_WR;
7095 tw32(TG3PCI_PCISTATE, val);
7096 }
7097
7098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7099 /* Enable some hw fixes. */
7100 val = tr32(TG3PCI_MSI_DATA);
7101 val |= (1 << 26) | (1 << 28) | (1 << 29);
7102 tw32(TG3PCI_MSI_DATA, val);
7103 }
7104
7105 /* Descriptor ring init may make accesses to the
7106 * NIC SRAM area to setup the TX descriptors, so we
7107 * can only do this after the hardware has been
7108 * successfully reset.
7109 */
7110 err = tg3_init_rings(tp);
7111 if (err)
7112 return err;
7113
7114 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7115 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7116 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7117 /* This value is determined during the probe time DMA
7118 * engine test, tg3_test_dma.
7119 */
7120 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7121 }
7122
7123 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7124 GRC_MODE_4X_NIC_SEND_RINGS |
7125 GRC_MODE_NO_TX_PHDR_CSUM |
7126 GRC_MODE_NO_RX_PHDR_CSUM);
7127 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7128
7129 /* Pseudo-header checksum is done by hardware logic and not
7130 * the offload processers, so make the chip do the pseudo-
7131 * header checksums on receive. For transmit it is more
7132 * convenient to do the pseudo-header checksum in software
7133 * as Linux does that on transmit for us in all cases.
7134 */
7135 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7136
7137 tw32(GRC_MODE,
7138 tp->grc_mode |
7139 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7140
7141 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7142 val = tr32(GRC_MISC_CFG);
7143 val &= ~0xff;
7144 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7145 tw32(GRC_MISC_CFG, val);
7146
7147 /* Initialize MBUF/DESC pool. */
7148 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7149 /* Do nothing. */
7150 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7151 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7153 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7154 else
7155 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7156 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7157 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7158 }
7159 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7160 int fw_len;
7161
7162 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7163 TG3_TSO5_FW_RODATA_LEN +
7164 TG3_TSO5_FW_DATA_LEN +
7165 TG3_TSO5_FW_SBSS_LEN +
7166 TG3_TSO5_FW_BSS_LEN);
7167 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7168 tw32(BUFMGR_MB_POOL_ADDR,
7169 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7170 tw32(BUFMGR_MB_POOL_SIZE,
7171 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7172 }
7173
7174 if (tp->dev->mtu <= ETH_DATA_LEN) {
7175 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7176 tp->bufmgr_config.mbuf_read_dma_low_water);
7177 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7178 tp->bufmgr_config.mbuf_mac_rx_low_water);
7179 tw32(BUFMGR_MB_HIGH_WATER,
7180 tp->bufmgr_config.mbuf_high_water);
7181 } else {
7182 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7183 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7184 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7185 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7186 tw32(BUFMGR_MB_HIGH_WATER,
7187 tp->bufmgr_config.mbuf_high_water_jumbo);
7188 }
7189 tw32(BUFMGR_DMA_LOW_WATER,
7190 tp->bufmgr_config.dma_low_water);
7191 tw32(BUFMGR_DMA_HIGH_WATER,
7192 tp->bufmgr_config.dma_high_water);
7193
7194 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7195 for (i = 0; i < 2000; i++) {
7196 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7197 break;
7198 udelay(10);
7199 }
7200 if (i >= 2000) {
7201 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7202 tp->dev->name);
7203 return -ENODEV;
7204 }
7205
7206 /* Setup replenish threshold. */
7207 val = tp->rx_pending / 8;
7208 if (val == 0)
7209 val = 1;
7210 else if (val > tp->rx_std_max_post)
7211 val = tp->rx_std_max_post;
7212 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7213 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7214 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7215
7216 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7217 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7218 }
7219
7220 tw32(RCVBDI_STD_THRESH, val);
7221
7222 /* Initialize TG3_BDINFO's at:
7223 * RCVDBDI_STD_BD: standard eth size rx ring
7224 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7225 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7226 *
7227 * like so:
7228 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7229 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7230 * ring attribute flags
7231 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7232 *
7233 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7234 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7235 *
7236 * The size of each ring is fixed in the firmware, but the location is
7237 * configurable.
7238 */
7239 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7240 ((u64) tp->rx_std_mapping >> 32));
7241 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7242 ((u64) tp->rx_std_mapping & 0xffffffff));
7243 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7244 NIC_SRAM_RX_BUFFER_DESC);
7245
7246 /* Don't even try to program the JUMBO/MINI buffer descriptor
7247 * configs on 5705.
7248 */
7249 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7250 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7251 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7252 } else {
7253 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7254 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7255
7256 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7257 BDINFO_FLAGS_DISABLED);
7258
7259 /* Setup replenish threshold. */
7260 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7261
7262 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7263 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7264 ((u64) tp->rx_jumbo_mapping >> 32));
7265 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7266 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7267 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7268 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7269 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7270 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7271 } else {
7272 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7273 BDINFO_FLAGS_DISABLED);
7274 }
7275
7276 }
7277
7278 /* There is only one send ring on 5705/5750, no need to explicitly
7279 * disable the others.
7280 */
7281 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7282 /* Clear out send RCB ring in SRAM. */
7283 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7284 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7285 BDINFO_FLAGS_DISABLED);
7286 }
7287
7288 tp->tx_prod = 0;
7289 tp->tx_cons = 0;
7290 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7291 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7292
7293 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7294 tp->tx_desc_mapping,
7295 (TG3_TX_RING_SIZE <<
7296 BDINFO_FLAGS_MAXLEN_SHIFT),
7297 NIC_SRAM_TX_BUFFER_DESC);
7298
7299 /* There is only one receive return ring on 5705/5750, no need
7300 * to explicitly disable the others.
7301 */
7302 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7303 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7304 i += TG3_BDINFO_SIZE) {
7305 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7306 BDINFO_FLAGS_DISABLED);
7307 }
7308 }
7309
7310 tp->rx_rcb_ptr = 0;
7311 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7312
7313 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7314 tp->rx_rcb_mapping,
7315 (TG3_RX_RCB_RING_SIZE(tp) <<
7316 BDINFO_FLAGS_MAXLEN_SHIFT),
7317 0);
7318
7319 tp->rx_std_ptr = tp->rx_pending;
7320 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7321 tp->rx_std_ptr);
7322
7323 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7324 tp->rx_jumbo_pending : 0;
7325 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7326 tp->rx_jumbo_ptr);
7327
7328 /* Initialize MAC address and backoff seed. */
7329 __tg3_set_mac_addr(tp, 0);
7330
7331 /* MTU + ethernet header + FCS + optional VLAN tag */
7332 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7333
7334 /* The slot time is changed by tg3_setup_phy if we
7335 * run at gigabit with half duplex.
7336 */
7337 tw32(MAC_TX_LENGTHS,
7338 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7339 (6 << TX_LENGTHS_IPG_SHIFT) |
7340 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7341
7342 /* Receive rules. */
7343 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7344 tw32(RCVLPC_CONFIG, 0x0181);
7345
7346 /* Calculate RDMAC_MODE setting early, we need it to determine
7347 * the RCVLPC_STATE_ENABLE mask.
7348 */
7349 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7350 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7351 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7352 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7353 RDMAC_MODE_LNGREAD_ENAB);
7354
7355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7357 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7358 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7359 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7360
7361 /* If statement applies to 5705 and 5750 PCI devices only */
7362 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7363 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7364 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7365 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7367 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7368 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7369 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7370 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7371 }
7372 }
7373
7374 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7375 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7376
7377 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7378 rdmac_mode |= (1 << 27);
7379
7380 /* Receive/send statistics. */
7381 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7382 val = tr32(RCVLPC_STATS_ENABLE);
7383 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7384 tw32(RCVLPC_STATS_ENABLE, val);
7385 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7386 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7387 val = tr32(RCVLPC_STATS_ENABLE);
7388 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7389 tw32(RCVLPC_STATS_ENABLE, val);
7390 } else {
7391 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7392 }
7393 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7394 tw32(SNDDATAI_STATSENAB, 0xffffff);
7395 tw32(SNDDATAI_STATSCTRL,
7396 (SNDDATAI_SCTRL_ENABLE |
7397 SNDDATAI_SCTRL_FASTUPD));
7398
7399 /* Setup host coalescing engine. */
7400 tw32(HOSTCC_MODE, 0);
7401 for (i = 0; i < 2000; i++) {
7402 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7403 break;
7404 udelay(10);
7405 }
7406
7407 __tg3_set_coalesce(tp, &tp->coal);
7408
7409 /* set status block DMA address */
7410 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7411 ((u64) tp->status_mapping >> 32));
7412 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7413 ((u64) tp->status_mapping & 0xffffffff));
7414
7415 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7416 /* Status/statistics block address. See tg3_timer,
7417 * the tg3_periodic_fetch_stats call there, and
7418 * tg3_get_stats to see how this works for 5705/5750 chips.
7419 */
7420 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7421 ((u64) tp->stats_mapping >> 32));
7422 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7423 ((u64) tp->stats_mapping & 0xffffffff));
7424 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7425 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7426 }
7427
7428 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7429
7430 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7431 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7432 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7433 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7434
7435 /* Clear statistics/status block in chip, and status block in ram. */
7436 for (i = NIC_SRAM_STATS_BLK;
7437 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7438 i += sizeof(u32)) {
7439 tg3_write_mem(tp, i, 0);
7440 udelay(40);
7441 }
7442 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7443
7444 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7445 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7446 /* reset to prevent losing 1st rx packet intermittently */
7447 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7448 udelay(10);
7449 }
7450
7451 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7452 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7453 else
7454 tp->mac_mode = 0;
7455 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7456 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7457 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7458 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7459 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7460 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7461 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7462 udelay(40);
7463
7464 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7465 * If TG3_FLG2_IS_NIC is zero, we should read the
7466 * register to preserve the GPIO settings for LOMs. The GPIOs,
7467 * whether used as inputs or outputs, are set by boot code after
7468 * reset.
7469 */
7470 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7471 u32 gpio_mask;
7472
7473 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7474 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7475 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7476
7477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7478 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7479 GRC_LCLCTRL_GPIO_OUTPUT3;
7480
7481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7482 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7483
7484 tp->grc_local_ctrl &= ~gpio_mask;
7485 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7486
7487 /* GPIO1 must be driven high for eeprom write protect */
7488 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7489 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7490 GRC_LCLCTRL_GPIO_OUTPUT1);
7491 }
7492 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7493 udelay(100);
7494
7495 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7496 tp->last_tag = 0;
7497
7498 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7499 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7500 udelay(40);
7501 }
7502
7503 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7504 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7505 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7506 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7507 WDMAC_MODE_LNGREAD_ENAB);
7508
7509 /* If statement applies to 5705 and 5750 PCI devices only */
7510 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7511 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7513 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7514 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7515 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7516 /* nothing */
7517 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7518 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7519 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7520 val |= WDMAC_MODE_RX_ACCEL;
7521 }
7522 }
7523
7524 /* Enable host coalescing bug fix */
7525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7526 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7527 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7528 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7529 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7530 val |= WDMAC_MODE_STATUS_TAG_FIX;
7531
7532 tw32_f(WDMAC_MODE, val);
7533 udelay(40);
7534
7535 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7536 u16 pcix_cmd;
7537
7538 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7539 &pcix_cmd);
7540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7541 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7542 pcix_cmd |= PCI_X_CMD_READ_2K;
7543 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7544 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7545 pcix_cmd |= PCI_X_CMD_READ_2K;
7546 }
7547 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7548 pcix_cmd);
7549 }
7550
7551 tw32_f(RDMAC_MODE, rdmac_mode);
7552 udelay(40);
7553
7554 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7555 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7556 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7557
7558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7559 tw32(SNDDATAC_MODE,
7560 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7561 else
7562 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7563
7564 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7565 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7566 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7567 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7568 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7569 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7570 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7571 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7572
7573 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7574 err = tg3_load_5701_a0_firmware_fix(tp);
7575 if (err)
7576 return err;
7577 }
7578
7579 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7580 err = tg3_load_tso_firmware(tp);
7581 if (err)
7582 return err;
7583 }
7584
7585 tp->tx_mode = TX_MODE_ENABLE;
7586 tw32_f(MAC_TX_MODE, tp->tx_mode);
7587 udelay(100);
7588
7589 tp->rx_mode = RX_MODE_ENABLE;
7590 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7591 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7592 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7594 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7595
7596 tw32_f(MAC_RX_MODE, tp->rx_mode);
7597 udelay(10);
7598
7599 tw32(MAC_LED_CTRL, tp->led_ctrl);
7600
7601 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7602 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7603 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7604 udelay(10);
7605 }
7606 tw32_f(MAC_RX_MODE, tp->rx_mode);
7607 udelay(10);
7608
7609 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7610 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7611 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7612 /* Set drive transmission level to 1.2V */
7613 /* only if the signal pre-emphasis bit is not set */
7614 val = tr32(MAC_SERDES_CFG);
7615 val &= 0xfffff000;
7616 val |= 0x880;
7617 tw32(MAC_SERDES_CFG, val);
7618 }
7619 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7620 tw32(MAC_SERDES_CFG, 0x616000);
7621 }
7622
7623 /* Prevent chip from dropping frames when flow control
7624 * is enabled.
7625 */
7626 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7627
7628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7629 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7630 /* Use hardware link auto-negotiation */
7631 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7632 }
7633
7634 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7635 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7636 u32 tmp;
7637
7638 tmp = tr32(SERDES_RX_CTRL);
7639 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7640 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7641 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7642 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7643 }
7644
7645 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7646 if (tp->link_config.phy_is_low_power) {
7647 tp->link_config.phy_is_low_power = 0;
7648 tp->link_config.speed = tp->link_config.orig_speed;
7649 tp->link_config.duplex = tp->link_config.orig_duplex;
7650 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7651 }
7652
7653 err = tg3_setup_phy(tp, 0);
7654 if (err)
7655 return err;
7656
7657 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7658 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7659 u32 tmp;
7660
7661 /* Clear CRC stats. */
7662 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7663 tg3_writephy(tp, MII_TG3_TEST1,
7664 tmp | MII_TG3_TEST1_CRC_EN);
7665 tg3_readphy(tp, 0x14, &tmp);
7666 }
7667 }
7668 }
7669
7670 __tg3_set_rx_mode(tp->dev);
7671
7672 /* Initialize receive rules. */
7673 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7674 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7675 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7676 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7677
7678 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7679 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7680 limit = 8;
7681 else
7682 limit = 16;
7683 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7684 limit -= 4;
7685 switch (limit) {
7686 case 16:
7687 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7688 case 15:
7689 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7690 case 14:
7691 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7692 case 13:
7693 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7694 case 12:
7695 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7696 case 11:
7697 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7698 case 10:
7699 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7700 case 9:
7701 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7702 case 8:
7703 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7704 case 7:
7705 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7706 case 6:
7707 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7708 case 5:
7709 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7710 case 4:
7711 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7712 case 3:
7713 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7714 case 2:
7715 case 1:
7716
7717 default:
7718 break;
7719 }
7720
7721 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7722 /* Write our heartbeat update interval to APE. */
7723 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7724 APE_HOST_HEARTBEAT_INT_DISABLE);
7725
7726 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7727
7728 return 0;
7729}
7730
7731/* Called at device open time to get the chip ready for
7732 * packet processing. Invoked with tp->lock held.
7733 */
7734static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7735{
7736 tg3_switch_clocks(tp);
7737
7738 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7739
7740 return tg3_reset_hw(tp, reset_phy);
7741}
7742
7743#define TG3_STAT_ADD32(PSTAT, REG) \
7744do { u32 __val = tr32(REG); \
7745 (PSTAT)->low += __val; \
7746 if ((PSTAT)->low < __val) \
7747 (PSTAT)->high += 1; \
7748} while (0)
7749
7750static void tg3_periodic_fetch_stats(struct tg3 *tp)
7751{
7752 struct tg3_hw_stats *sp = tp->hw_stats;
7753
7754 if (!netif_carrier_ok(tp->dev))
7755 return;
7756
7757 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7758 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7759 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7760 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7761 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7762 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7763 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7764 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7765 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7766 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7767 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7768 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7769 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7770
7771 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7772 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7773 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7774 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7775 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7776 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7777 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7778 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7779 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7780 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7781 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7782 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7783 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7784 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7785
7786 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7787 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7788 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7789}
7790
7791static void tg3_timer(unsigned long __opaque)
7792{
7793 struct tg3 *tp = (struct tg3 *) __opaque;
7794
7795 if (tp->irq_sync)
7796 goto restart_timer;
7797
7798 spin_lock(&tp->lock);
7799
7800 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7801 /* All of this garbage is because when using non-tagged
7802 * IRQ status the mailbox/status_block protocol the chip
7803 * uses with the cpu is race prone.
7804 */
7805 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7806 tw32(GRC_LOCAL_CTRL,
7807 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7808 } else {
7809 tw32(HOSTCC_MODE, tp->coalesce_mode |
7810 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7811 }
7812
7813 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7814 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7815 spin_unlock(&tp->lock);
7816 schedule_work(&tp->reset_task);
7817 return;
7818 }
7819 }
7820
7821 /* This part only runs once per second. */
7822 if (!--tp->timer_counter) {
7823 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7824 tg3_periodic_fetch_stats(tp);
7825
7826 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7827 u32 mac_stat;
7828 int phy_event;
7829
7830 mac_stat = tr32(MAC_STATUS);
7831
7832 phy_event = 0;
7833 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7834 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7835 phy_event = 1;
7836 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7837 phy_event = 1;
7838
7839 if (phy_event)
7840 tg3_setup_phy(tp, 0);
7841 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7842 u32 mac_stat = tr32(MAC_STATUS);
7843 int need_setup = 0;
7844
7845 if (netif_carrier_ok(tp->dev) &&
7846 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7847 need_setup = 1;
7848 }
7849 if (! netif_carrier_ok(tp->dev) &&
7850 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7851 MAC_STATUS_SIGNAL_DET))) {
7852 need_setup = 1;
7853 }
7854 if (need_setup) {
7855 if (!tp->serdes_counter) {
7856 tw32_f(MAC_MODE,
7857 (tp->mac_mode &
7858 ~MAC_MODE_PORT_MODE_MASK));
7859 udelay(40);
7860 tw32_f(MAC_MODE, tp->mac_mode);
7861 udelay(40);
7862 }
7863 tg3_setup_phy(tp, 0);
7864 }
7865 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7866 tg3_serdes_parallel_detect(tp);
7867
7868 tp->timer_counter = tp->timer_multiplier;
7869 }
7870
7871 /* Heartbeat is only sent once every 2 seconds.
7872 *
7873 * The heartbeat is to tell the ASF firmware that the host
7874 * driver is still alive. In the event that the OS crashes,
7875 * ASF needs to reset the hardware to free up the FIFO space
7876 * that may be filled with rx packets destined for the host.
7877 * If the FIFO is full, ASF will no longer function properly.
7878 *
7879 * Unintended resets have been reported on real time kernels
7880 * where the timer doesn't run on time. Netpoll will also have
7881 * same problem.
7882 *
7883 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7884 * to check the ring condition when the heartbeat is expiring
7885 * before doing the reset. This will prevent most unintended
7886 * resets.
7887 */
7888 if (!--tp->asf_counter) {
7889 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7890 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7891 tg3_wait_for_event_ack(tp);
7892
7893 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7894 FWCMD_NICDRV_ALIVE3);
7895 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7896 /* 5 seconds timeout */
7897 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7898
7899 tg3_generate_fw_event(tp);
7900 }
7901 tp->asf_counter = tp->asf_multiplier;
7902 }
7903
7904 spin_unlock(&tp->lock);
7905
7906restart_timer:
7907 tp->timer.expires = jiffies + tp->timer_offset;
7908 add_timer(&tp->timer);
7909}
7910
7911static int tg3_request_irq(struct tg3 *tp)
7912{
7913 irq_handler_t fn;
7914 unsigned long flags;
7915 struct net_device *dev = tp->dev;
7916
7917 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7918 fn = tg3_msi;
7919 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7920 fn = tg3_msi_1shot;
7921 flags = IRQF_SAMPLE_RANDOM;
7922 } else {
7923 fn = tg3_interrupt;
7924 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7925 fn = tg3_interrupt_tagged;
7926 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7927 }
7928 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7929}
7930
7931static int tg3_test_interrupt(struct tg3 *tp)
7932{
7933 struct net_device *dev = tp->dev;
7934 int err, i, intr_ok = 0;
7935
7936 if (!netif_running(dev))
7937 return -ENODEV;
7938
7939 tg3_disable_ints(tp);
7940
7941 free_irq(tp->pdev->irq, dev);
7942
7943 err = request_irq(tp->pdev->irq, tg3_test_isr,
7944 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7945 if (err)
7946 return err;
7947
7948 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7949 tg3_enable_ints(tp);
7950
7951 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7952 HOSTCC_MODE_NOW);
7953
7954 for (i = 0; i < 5; i++) {
7955 u32 int_mbox, misc_host_ctrl;
7956
7957 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7958 TG3_64BIT_REG_LOW);
7959 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7960
7961 if ((int_mbox != 0) ||
7962 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7963 intr_ok = 1;
7964 break;
7965 }
7966
7967 msleep(10);
7968 }
7969
7970 tg3_disable_ints(tp);
7971
7972 free_irq(tp->pdev->irq, dev);
7973
7974 err = tg3_request_irq(tp);
7975
7976 if (err)
7977 return err;
7978
7979 if (intr_ok)
7980 return 0;
7981
7982 return -EIO;
7983}
7984
7985/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7986 * successfully restored
7987 */
7988static int tg3_test_msi(struct tg3 *tp)
7989{
7990 struct net_device *dev = tp->dev;
7991 int err;
7992 u16 pci_cmd;
7993
7994 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7995 return 0;
7996
7997 /* Turn off SERR reporting in case MSI terminates with Master
7998 * Abort.
7999 */
8000 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8001 pci_write_config_word(tp->pdev, PCI_COMMAND,
8002 pci_cmd & ~PCI_COMMAND_SERR);
8003
8004 err = tg3_test_interrupt(tp);
8005
8006 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8007
8008 if (!err)
8009 return 0;
8010
8011 /* other failures */
8012 if (err != -EIO)
8013 return err;
8014
8015 /* MSI test failed, go back to INTx mode */
8016 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8017 "switching to INTx mode. Please report this failure to "
8018 "the PCI maintainer and include system chipset information.\n",
8019 tp->dev->name);
8020
8021 free_irq(tp->pdev->irq, dev);
8022 pci_disable_msi(tp->pdev);
8023
8024 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8025
8026 err = tg3_request_irq(tp);
8027 if (err)
8028 return err;
8029
8030 /* Need to reset the chip because the MSI cycle may have terminated
8031 * with Master Abort.
8032 */
8033 tg3_full_lock(tp, 1);
8034
8035 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8036 err = tg3_init_hw(tp, 1);
8037
8038 tg3_full_unlock(tp);
8039
8040 if (err)
8041 free_irq(tp->pdev->irq, dev);
8042
8043 return err;
8044}
8045
8046static int tg3_open(struct net_device *dev)
8047{
8048 struct tg3 *tp = netdev_priv(dev);
8049 int err;
8050
8051 netif_carrier_off(tp->dev);
8052
8053 err = tg3_set_power_state(tp, PCI_D0);
8054 if (err)
8055 return err;
8056
8057 tg3_full_lock(tp, 0);
8058
8059 tg3_disable_ints(tp);
8060 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8061
8062 tg3_full_unlock(tp);
8063
8064 /* The placement of this call is tied
8065 * to the setup and use of Host TX descriptors.
8066 */
8067 err = tg3_alloc_consistent(tp);
8068 if (err)
8069 return err;
8070
8071 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
8072 /* All MSI supporting chips should support tagged
8073 * status. Assert that this is the case.
8074 */
8075 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8076 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8077 "Not using MSI.\n", tp->dev->name);
8078 } else if (pci_enable_msi(tp->pdev) == 0) {
8079 u32 msi_mode;
8080
8081 msi_mode = tr32(MSGINT_MODE);
8082 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8083 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8084 }
8085 }
8086 err = tg3_request_irq(tp);
8087
8088 if (err) {
8089 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8090 pci_disable_msi(tp->pdev);
8091 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8092 }
8093 tg3_free_consistent(tp);
8094 return err;
8095 }
8096
8097 napi_enable(&tp->napi);
8098
8099 tg3_full_lock(tp, 0);
8100
8101 err = tg3_init_hw(tp, 1);
8102 if (err) {
8103 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8104 tg3_free_rings(tp);
8105 } else {
8106 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8107 tp->timer_offset = HZ;
8108 else
8109 tp->timer_offset = HZ / 10;
8110
8111 BUG_ON(tp->timer_offset > HZ);
8112 tp->timer_counter = tp->timer_multiplier =
8113 (HZ / tp->timer_offset);
8114 tp->asf_counter = tp->asf_multiplier =
8115 ((HZ / tp->timer_offset) * 2);
8116
8117 init_timer(&tp->timer);
8118 tp->timer.expires = jiffies + tp->timer_offset;
8119 tp->timer.data = (unsigned long) tp;
8120 tp->timer.function = tg3_timer;
8121 }
8122
8123 tg3_full_unlock(tp);
8124
8125 if (err) {
8126 napi_disable(&tp->napi);
8127 free_irq(tp->pdev->irq, dev);
8128 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8129 pci_disable_msi(tp->pdev);
8130 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8131 }
8132 tg3_free_consistent(tp);
8133 return err;
8134 }
8135
8136 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8137 err = tg3_test_msi(tp);
8138
8139 if (err) {
8140 tg3_full_lock(tp, 0);
8141
8142 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8143 pci_disable_msi(tp->pdev);
8144 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8145 }
8146 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8147 tg3_free_rings(tp);
8148 tg3_free_consistent(tp);
8149
8150 tg3_full_unlock(tp);
8151
8152 napi_disable(&tp->napi);
8153
8154 return err;
8155 }
8156
8157 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8158 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8159 u32 val = tr32(PCIE_TRANSACTION_CFG);
8160
8161 tw32(PCIE_TRANSACTION_CFG,
8162 val | PCIE_TRANS_CFG_1SHOT_MSI);
8163 }
8164 }
8165 }
8166
8167 tg3_phy_start(tp);
8168
8169 tg3_full_lock(tp, 0);
8170
8171 add_timer(&tp->timer);
8172 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8173 tg3_enable_ints(tp);
8174
8175 tg3_full_unlock(tp);
8176
8177 netif_start_queue(dev);
8178
8179 return 0;
8180}
8181
8182#if 0
8183/*static*/ void tg3_dump_state(struct tg3 *tp)
8184{
8185 u32 val32, val32_2, val32_3, val32_4, val32_5;
8186 u16 val16;
8187 int i;
8188
8189 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8190 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8191 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8192 val16, val32);
8193
8194 /* MAC block */
8195 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8196 tr32(MAC_MODE), tr32(MAC_STATUS));
8197 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8198 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8199 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8200 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8201 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8202 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8203
8204 /* Send data initiator control block */
8205 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8206 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8207 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8208 tr32(SNDDATAI_STATSCTRL));
8209
8210 /* Send data completion control block */
8211 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8212
8213 /* Send BD ring selector block */
8214 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8215 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8216
8217 /* Send BD initiator control block */
8218 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8219 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8220
8221 /* Send BD completion control block */
8222 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8223
8224 /* Receive list placement control block */
8225 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8226 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8227 printk(" RCVLPC_STATSCTRL[%08x]\n",
8228 tr32(RCVLPC_STATSCTRL));
8229
8230 /* Receive data and receive BD initiator control block */
8231 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8232 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8233
8234 /* Receive data completion control block */
8235 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8236 tr32(RCVDCC_MODE));
8237
8238 /* Receive BD initiator control block */
8239 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8240 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8241
8242 /* Receive BD completion control block */
8243 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8244 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8245
8246 /* Receive list selector control block */
8247 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8248 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8249
8250 /* Mbuf cluster free block */
8251 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8252 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8253
8254 /* Host coalescing control block */
8255 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8256 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8257 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8258 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8259 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8260 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8261 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8262 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8263 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8264 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8265 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8266 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8267
8268 /* Memory arbiter control block */
8269 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8270 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8271
8272 /* Buffer manager control block */
8273 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8274 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8275 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8276 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8277 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8278 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8279 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8280 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8281
8282 /* Read DMA control block */
8283 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8284 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8285
8286 /* Write DMA control block */
8287 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8288 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8289
8290 /* DMA completion block */
8291 printk("DEBUG: DMAC_MODE[%08x]\n",
8292 tr32(DMAC_MODE));
8293
8294 /* GRC block */
8295 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8296 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8297 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8298 tr32(GRC_LOCAL_CTRL));
8299
8300 /* TG3_BDINFOs */
8301 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8302 tr32(RCVDBDI_JUMBO_BD + 0x0),
8303 tr32(RCVDBDI_JUMBO_BD + 0x4),
8304 tr32(RCVDBDI_JUMBO_BD + 0x8),
8305 tr32(RCVDBDI_JUMBO_BD + 0xc));
8306 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8307 tr32(RCVDBDI_STD_BD + 0x0),
8308 tr32(RCVDBDI_STD_BD + 0x4),
8309 tr32(RCVDBDI_STD_BD + 0x8),
8310 tr32(RCVDBDI_STD_BD + 0xc));
8311 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8312 tr32(RCVDBDI_MINI_BD + 0x0),
8313 tr32(RCVDBDI_MINI_BD + 0x4),
8314 tr32(RCVDBDI_MINI_BD + 0x8),
8315 tr32(RCVDBDI_MINI_BD + 0xc));
8316
8317 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8318 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8319 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8320 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8321 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8322 val32, val32_2, val32_3, val32_4);
8323
8324 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8325 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8326 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8327 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8328 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8329 val32, val32_2, val32_3, val32_4);
8330
8331 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8332 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8333 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8334 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8335 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8336 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8337 val32, val32_2, val32_3, val32_4, val32_5);
8338
8339 /* SW status block */
8340 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8341 tp->hw_status->status,
8342 tp->hw_status->status_tag,
8343 tp->hw_status->rx_jumbo_consumer,
8344 tp->hw_status->rx_consumer,
8345 tp->hw_status->rx_mini_consumer,
8346 tp->hw_status->idx[0].rx_producer,
8347 tp->hw_status->idx[0].tx_consumer);
8348
8349 /* SW statistics block */
8350 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8351 ((u32 *)tp->hw_stats)[0],
8352 ((u32 *)tp->hw_stats)[1],
8353 ((u32 *)tp->hw_stats)[2],
8354 ((u32 *)tp->hw_stats)[3]);
8355
8356 /* Mailboxes */
8357 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8358 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8359 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8360 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8361 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8362
8363 /* NIC side send descriptors. */
8364 for (i = 0; i < 6; i++) {
8365 unsigned long txd;
8366
8367 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8368 + (i * sizeof(struct tg3_tx_buffer_desc));
8369 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8370 i,
8371 readl(txd + 0x0), readl(txd + 0x4),
8372 readl(txd + 0x8), readl(txd + 0xc));
8373 }
8374
8375 /* NIC side RX descriptors. */
8376 for (i = 0; i < 6; i++) {
8377 unsigned long rxd;
8378
8379 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8380 + (i * sizeof(struct tg3_rx_buffer_desc));
8381 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8382 i,
8383 readl(rxd + 0x0), readl(rxd + 0x4),
8384 readl(rxd + 0x8), readl(rxd + 0xc));
8385 rxd += (4 * sizeof(u32));
8386 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8387 i,
8388 readl(rxd + 0x0), readl(rxd + 0x4),
8389 readl(rxd + 0x8), readl(rxd + 0xc));
8390 }
8391
8392 for (i = 0; i < 6; i++) {
8393 unsigned long rxd;
8394
8395 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8396 + (i * sizeof(struct tg3_rx_buffer_desc));
8397 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8398 i,
8399 readl(rxd + 0x0), readl(rxd + 0x4),
8400 readl(rxd + 0x8), readl(rxd + 0xc));
8401 rxd += (4 * sizeof(u32));
8402 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8403 i,
8404 readl(rxd + 0x0), readl(rxd + 0x4),
8405 readl(rxd + 0x8), readl(rxd + 0xc));
8406 }
8407}
8408#endif
8409
8410static struct net_device_stats *tg3_get_stats(struct net_device *);
8411static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8412
8413static int tg3_close(struct net_device *dev)
8414{
8415 struct tg3 *tp = netdev_priv(dev);
8416
8417 napi_disable(&tp->napi);
8418 cancel_work_sync(&tp->reset_task);
8419
8420 netif_stop_queue(dev);
8421
8422 del_timer_sync(&tp->timer);
8423
8424 tg3_full_lock(tp, 1);
8425#if 0
8426 tg3_dump_state(tp);
8427#endif
8428
8429 tg3_disable_ints(tp);
8430
8431 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8432 tg3_free_rings(tp);
8433 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8434
8435 tg3_full_unlock(tp);
8436
8437 free_irq(tp->pdev->irq, dev);
8438 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8439 pci_disable_msi(tp->pdev);
8440 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8441 }
8442
8443 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8444 sizeof(tp->net_stats_prev));
8445 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8446 sizeof(tp->estats_prev));
8447
8448 tg3_free_consistent(tp);
8449
8450 tg3_set_power_state(tp, PCI_D3hot);
8451
8452 netif_carrier_off(tp->dev);
8453
8454 return 0;
8455}
8456
8457static inline unsigned long get_stat64(tg3_stat64_t *val)
8458{
8459 unsigned long ret;
8460
8461#if (BITS_PER_LONG == 32)
8462 ret = val->low;
8463#else
8464 ret = ((u64)val->high << 32) | ((u64)val->low);
8465#endif
8466 return ret;
8467}
8468
8469static unsigned long calc_crc_errors(struct tg3 *tp)
8470{
8471 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8472
8473 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8474 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8476 u32 val;
8477
8478 spin_lock_bh(&tp->lock);
8479 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8480 tg3_writephy(tp, MII_TG3_TEST1,
8481 val | MII_TG3_TEST1_CRC_EN);
8482 tg3_readphy(tp, 0x14, &val);
8483 } else
8484 val = 0;
8485 spin_unlock_bh(&tp->lock);
8486
8487 tp->phy_crc_errors += val;
8488
8489 return tp->phy_crc_errors;
8490 }
8491
8492 return get_stat64(&hw_stats->rx_fcs_errors);
8493}
8494
8495#define ESTAT_ADD(member) \
8496 estats->member = old_estats->member + \
8497 get_stat64(&hw_stats->member)
8498
8499static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8500{
8501 struct tg3_ethtool_stats *estats = &tp->estats;
8502 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8503 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8504
8505 if (!hw_stats)
8506 return old_estats;
8507
8508 ESTAT_ADD(rx_octets);
8509 ESTAT_ADD(rx_fragments);
8510 ESTAT_ADD(rx_ucast_packets);
8511 ESTAT_ADD(rx_mcast_packets);
8512 ESTAT_ADD(rx_bcast_packets);
8513 ESTAT_ADD(rx_fcs_errors);
8514 ESTAT_ADD(rx_align_errors);
8515 ESTAT_ADD(rx_xon_pause_rcvd);
8516 ESTAT_ADD(rx_xoff_pause_rcvd);
8517 ESTAT_ADD(rx_mac_ctrl_rcvd);
8518 ESTAT_ADD(rx_xoff_entered);
8519 ESTAT_ADD(rx_frame_too_long_errors);
8520 ESTAT_ADD(rx_jabbers);
8521 ESTAT_ADD(rx_undersize_packets);
8522 ESTAT_ADD(rx_in_length_errors);
8523 ESTAT_ADD(rx_out_length_errors);
8524 ESTAT_ADD(rx_64_or_less_octet_packets);
8525 ESTAT_ADD(rx_65_to_127_octet_packets);
8526 ESTAT_ADD(rx_128_to_255_octet_packets);
8527 ESTAT_ADD(rx_256_to_511_octet_packets);
8528 ESTAT_ADD(rx_512_to_1023_octet_packets);
8529 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8530 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8531 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8532 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8533 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8534
8535 ESTAT_ADD(tx_octets);
8536 ESTAT_ADD(tx_collisions);
8537 ESTAT_ADD(tx_xon_sent);
8538 ESTAT_ADD(tx_xoff_sent);
8539 ESTAT_ADD(tx_flow_control);
8540 ESTAT_ADD(tx_mac_errors);
8541 ESTAT_ADD(tx_single_collisions);
8542 ESTAT_ADD(tx_mult_collisions);
8543 ESTAT_ADD(tx_deferred);
8544 ESTAT_ADD(tx_excessive_collisions);
8545 ESTAT_ADD(tx_late_collisions);
8546 ESTAT_ADD(tx_collide_2times);
8547 ESTAT_ADD(tx_collide_3times);
8548 ESTAT_ADD(tx_collide_4times);
8549 ESTAT_ADD(tx_collide_5times);
8550 ESTAT_ADD(tx_collide_6times);
8551 ESTAT_ADD(tx_collide_7times);
8552 ESTAT_ADD(tx_collide_8times);
8553 ESTAT_ADD(tx_collide_9times);
8554 ESTAT_ADD(tx_collide_10times);
8555 ESTAT_ADD(tx_collide_11times);
8556 ESTAT_ADD(tx_collide_12times);
8557 ESTAT_ADD(tx_collide_13times);
8558 ESTAT_ADD(tx_collide_14times);
8559 ESTAT_ADD(tx_collide_15times);
8560 ESTAT_ADD(tx_ucast_packets);
8561 ESTAT_ADD(tx_mcast_packets);
8562 ESTAT_ADD(tx_bcast_packets);
8563 ESTAT_ADD(tx_carrier_sense_errors);
8564 ESTAT_ADD(tx_discards);
8565 ESTAT_ADD(tx_errors);
8566
8567 ESTAT_ADD(dma_writeq_full);
8568 ESTAT_ADD(dma_write_prioq_full);
8569 ESTAT_ADD(rxbds_empty);
8570 ESTAT_ADD(rx_discards);
8571 ESTAT_ADD(rx_errors);
8572 ESTAT_ADD(rx_threshold_hit);
8573
8574 ESTAT_ADD(dma_readq_full);
8575 ESTAT_ADD(dma_read_prioq_full);
8576 ESTAT_ADD(tx_comp_queue_full);
8577
8578 ESTAT_ADD(ring_set_send_prod_index);
8579 ESTAT_ADD(ring_status_update);
8580 ESTAT_ADD(nic_irqs);
8581 ESTAT_ADD(nic_avoided_irqs);
8582 ESTAT_ADD(nic_tx_threshold_hit);
8583
8584 return estats;
8585}
8586
8587static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8588{
8589 struct tg3 *tp = netdev_priv(dev);
8590 struct net_device_stats *stats = &tp->net_stats;
8591 struct net_device_stats *old_stats = &tp->net_stats_prev;
8592 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8593
8594 if (!hw_stats)
8595 return old_stats;
8596
8597 stats->rx_packets = old_stats->rx_packets +
8598 get_stat64(&hw_stats->rx_ucast_packets) +
8599 get_stat64(&hw_stats->rx_mcast_packets) +
8600 get_stat64(&hw_stats->rx_bcast_packets);
8601
8602 stats->tx_packets = old_stats->tx_packets +
8603 get_stat64(&hw_stats->tx_ucast_packets) +
8604 get_stat64(&hw_stats->tx_mcast_packets) +
8605 get_stat64(&hw_stats->tx_bcast_packets);
8606
8607 stats->rx_bytes = old_stats->rx_bytes +
8608 get_stat64(&hw_stats->rx_octets);
8609 stats->tx_bytes = old_stats->tx_bytes +
8610 get_stat64(&hw_stats->tx_octets);
8611
8612 stats->rx_errors = old_stats->rx_errors +
8613 get_stat64(&hw_stats->rx_errors);
8614 stats->tx_errors = old_stats->tx_errors +
8615 get_stat64(&hw_stats->tx_errors) +
8616 get_stat64(&hw_stats->tx_mac_errors) +
8617 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8618 get_stat64(&hw_stats->tx_discards);
8619
8620 stats->multicast = old_stats->multicast +
8621 get_stat64(&hw_stats->rx_mcast_packets);
8622 stats->collisions = old_stats->collisions +
8623 get_stat64(&hw_stats->tx_collisions);
8624
8625 stats->rx_length_errors = old_stats->rx_length_errors +
8626 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8627 get_stat64(&hw_stats->rx_undersize_packets);
8628
8629 stats->rx_over_errors = old_stats->rx_over_errors +
8630 get_stat64(&hw_stats->rxbds_empty);
8631 stats->rx_frame_errors = old_stats->rx_frame_errors +
8632 get_stat64(&hw_stats->rx_align_errors);
8633 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8634 get_stat64(&hw_stats->tx_discards);
8635 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8636 get_stat64(&hw_stats->tx_carrier_sense_errors);
8637
8638 stats->rx_crc_errors = old_stats->rx_crc_errors +
8639 calc_crc_errors(tp);
8640
8641 stats->rx_missed_errors = old_stats->rx_missed_errors +
8642 get_stat64(&hw_stats->rx_discards);
8643
8644 return stats;
8645}
8646
8647static inline u32 calc_crc(unsigned char *buf, int len)
8648{
8649 u32 reg;
8650 u32 tmp;
8651 int j, k;
8652
8653 reg = 0xffffffff;
8654
8655 for (j = 0; j < len; j++) {
8656 reg ^= buf[j];
8657
8658 for (k = 0; k < 8; k++) {
8659 tmp = reg & 0x01;
8660
8661 reg >>= 1;
8662
8663 if (tmp) {
8664 reg ^= 0xedb88320;
8665 }
8666 }
8667 }
8668
8669 return ~reg;
8670}
8671
8672static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8673{
8674 /* accept or reject all multicast frames */
8675 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8676 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8677 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8678 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8679}
8680
8681static void __tg3_set_rx_mode(struct net_device *dev)
8682{
8683 struct tg3 *tp = netdev_priv(dev);
8684 u32 rx_mode;
8685
8686 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8687 RX_MODE_KEEP_VLAN_TAG);
8688
8689 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8690 * flag clear.
8691 */
8692#if TG3_VLAN_TAG_USED
8693 if (!tp->vlgrp &&
8694 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8695 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8696#else
8697 /* By definition, VLAN is disabled always in this
8698 * case.
8699 */
8700 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8701 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8702#endif
8703
8704 if (dev->flags & IFF_PROMISC) {
8705 /* Promiscuous mode. */
8706 rx_mode |= RX_MODE_PROMISC;
8707 } else if (dev->flags & IFF_ALLMULTI) {
8708 /* Accept all multicast. */
8709 tg3_set_multi (tp, 1);
8710 } else if (dev->mc_count < 1) {
8711 /* Reject all multicast. */
8712 tg3_set_multi (tp, 0);
8713 } else {
8714 /* Accept one or more multicast(s). */
8715 struct dev_mc_list *mclist;
8716 unsigned int i;
8717 u32 mc_filter[4] = { 0, };
8718 u32 regidx;
8719 u32 bit;
8720 u32 crc;
8721
8722 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8723 i++, mclist = mclist->next) {
8724
8725 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8726 bit = ~crc & 0x7f;
8727 regidx = (bit & 0x60) >> 5;
8728 bit &= 0x1f;
8729 mc_filter[regidx] |= (1 << bit);
8730 }
8731
8732 tw32(MAC_HASH_REG_0, mc_filter[0]);
8733 tw32(MAC_HASH_REG_1, mc_filter[1]);
8734 tw32(MAC_HASH_REG_2, mc_filter[2]);
8735 tw32(MAC_HASH_REG_3, mc_filter[3]);
8736 }
8737
8738 if (rx_mode != tp->rx_mode) {
8739 tp->rx_mode = rx_mode;
8740 tw32_f(MAC_RX_MODE, rx_mode);
8741 udelay(10);
8742 }
8743}
8744
8745static void tg3_set_rx_mode(struct net_device *dev)
8746{
8747 struct tg3 *tp = netdev_priv(dev);
8748
8749 if (!netif_running(dev))
8750 return;
8751
8752 tg3_full_lock(tp, 0);
8753 __tg3_set_rx_mode(dev);
8754 tg3_full_unlock(tp);
8755}
8756
8757#define TG3_REGDUMP_LEN (32 * 1024)
8758
8759static int tg3_get_regs_len(struct net_device *dev)
8760{
8761 return TG3_REGDUMP_LEN;
8762}
8763
8764static void tg3_get_regs(struct net_device *dev,
8765 struct ethtool_regs *regs, void *_p)
8766{
8767 u32 *p = _p;
8768 struct tg3 *tp = netdev_priv(dev);
8769 u8 *orig_p = _p;
8770 int i;
8771
8772 regs->version = 0;
8773
8774 memset(p, 0, TG3_REGDUMP_LEN);
8775
8776 if (tp->link_config.phy_is_low_power)
8777 return;
8778
8779 tg3_full_lock(tp, 0);
8780
8781#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8782#define GET_REG32_LOOP(base,len) \
8783do { p = (u32 *)(orig_p + (base)); \
8784 for (i = 0; i < len; i += 4) \
8785 __GET_REG32((base) + i); \
8786} while (0)
8787#define GET_REG32_1(reg) \
8788do { p = (u32 *)(orig_p + (reg)); \
8789 __GET_REG32((reg)); \
8790} while (0)
8791
8792 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8793 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8794 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8795 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8796 GET_REG32_1(SNDDATAC_MODE);
8797 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8798 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8799 GET_REG32_1(SNDBDC_MODE);
8800 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8801 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8802 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8803 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8804 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8805 GET_REG32_1(RCVDCC_MODE);
8806 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8807 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8808 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8809 GET_REG32_1(MBFREE_MODE);
8810 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8811 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8812 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8813 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8814 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8815 GET_REG32_1(RX_CPU_MODE);
8816 GET_REG32_1(RX_CPU_STATE);
8817 GET_REG32_1(RX_CPU_PGMCTR);
8818 GET_REG32_1(RX_CPU_HWBKPT);
8819 GET_REG32_1(TX_CPU_MODE);
8820 GET_REG32_1(TX_CPU_STATE);
8821 GET_REG32_1(TX_CPU_PGMCTR);
8822 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8823 GET_REG32_LOOP(FTQ_RESET, 0x120);
8824 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8825 GET_REG32_1(DMAC_MODE);
8826 GET_REG32_LOOP(GRC_MODE, 0x4c);
8827 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8828 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8829
8830#undef __GET_REG32
8831#undef GET_REG32_LOOP
8832#undef GET_REG32_1
8833
8834 tg3_full_unlock(tp);
8835}
8836
8837static int tg3_get_eeprom_len(struct net_device *dev)
8838{
8839 struct tg3 *tp = netdev_priv(dev);
8840
8841 return tp->nvram_size;
8842}
8843
8844static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8845static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8846static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8847
8848static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8849{
8850 struct tg3 *tp = netdev_priv(dev);
8851 int ret;
8852 u8 *pd;
8853 u32 i, offset, len, b_offset, b_count;
8854 __le32 val;
8855
8856 if (tp->link_config.phy_is_low_power)
8857 return -EAGAIN;
8858
8859 offset = eeprom->offset;
8860 len = eeprom->len;
8861 eeprom->len = 0;
8862
8863 eeprom->magic = TG3_EEPROM_MAGIC;
8864
8865 if (offset & 3) {
8866 /* adjustments to start on required 4 byte boundary */
8867 b_offset = offset & 3;
8868 b_count = 4 - b_offset;
8869 if (b_count > len) {
8870 /* i.e. offset=1 len=2 */
8871 b_count = len;
8872 }
8873 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8874 if (ret)
8875 return ret;
8876 memcpy(data, ((char*)&val) + b_offset, b_count);
8877 len -= b_count;
8878 offset += b_count;
8879 eeprom->len += b_count;
8880 }
8881
8882 /* read bytes upto the last 4 byte boundary */
8883 pd = &data[eeprom->len];
8884 for (i = 0; i < (len - (len & 3)); i += 4) {
8885 ret = tg3_nvram_read_le(tp, offset + i, &val);
8886 if (ret) {
8887 eeprom->len += i;
8888 return ret;
8889 }
8890 memcpy(pd + i, &val, 4);
8891 }
8892 eeprom->len += i;
8893
8894 if (len & 3) {
8895 /* read last bytes not ending on 4 byte boundary */
8896 pd = &data[eeprom->len];
8897 b_count = len & 3;
8898 b_offset = offset + len - b_count;
8899 ret = tg3_nvram_read_le(tp, b_offset, &val);
8900 if (ret)
8901 return ret;
8902 memcpy(pd, &val, b_count);
8903 eeprom->len += b_count;
8904 }
8905 return 0;
8906}
8907
8908static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8909
8910static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8911{
8912 struct tg3 *tp = netdev_priv(dev);
8913 int ret;
8914 u32 offset, len, b_offset, odd_len;
8915 u8 *buf;
8916 __le32 start, end;
8917
8918 if (tp->link_config.phy_is_low_power)
8919 return -EAGAIN;
8920
8921 if (eeprom->magic != TG3_EEPROM_MAGIC)
8922 return -EINVAL;
8923
8924 offset = eeprom->offset;
8925 len = eeprom->len;
8926
8927 if ((b_offset = (offset & 3))) {
8928 /* adjustments to start on required 4 byte boundary */
8929 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8930 if (ret)
8931 return ret;
8932 len += b_offset;
8933 offset &= ~3;
8934 if (len < 4)
8935 len = 4;
8936 }
8937
8938 odd_len = 0;
8939 if (len & 3) {
8940 /* adjustments to end on required 4 byte boundary */
8941 odd_len = 1;
8942 len = (len + 3) & ~3;
8943 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8944 if (ret)
8945 return ret;
8946 }
8947
8948 buf = data;
8949 if (b_offset || odd_len) {
8950 buf = kmalloc(len, GFP_KERNEL);
8951 if (!buf)
8952 return -ENOMEM;
8953 if (b_offset)
8954 memcpy(buf, &start, 4);
8955 if (odd_len)
8956 memcpy(buf+len-4, &end, 4);
8957 memcpy(buf + b_offset, data, eeprom->len);
8958 }
8959
8960 ret = tg3_nvram_write_block(tp, offset, len, buf);
8961
8962 if (buf != data)
8963 kfree(buf);
8964
8965 return ret;
8966}
8967
8968static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8969{
8970 struct tg3 *tp = netdev_priv(dev);
8971
8972 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8973 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8974 return -EAGAIN;
8975 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8976 }
8977
8978 cmd->supported = (SUPPORTED_Autoneg);
8979
8980 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8981 cmd->supported |= (SUPPORTED_1000baseT_Half |
8982 SUPPORTED_1000baseT_Full);
8983
8984 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8985 cmd->supported |= (SUPPORTED_100baseT_Half |
8986 SUPPORTED_100baseT_Full |
8987 SUPPORTED_10baseT_Half |
8988 SUPPORTED_10baseT_Full |
8989 SUPPORTED_TP);
8990 cmd->port = PORT_TP;
8991 } else {
8992 cmd->supported |= SUPPORTED_FIBRE;
8993 cmd->port = PORT_FIBRE;
8994 }
8995
8996 cmd->advertising = tp->link_config.advertising;
8997 if (netif_running(dev)) {
8998 cmd->speed = tp->link_config.active_speed;
8999 cmd->duplex = tp->link_config.active_duplex;
9000 }
9001 cmd->phy_address = PHY_ADDR;
9002 cmd->transceiver = 0;
9003 cmd->autoneg = tp->link_config.autoneg;
9004 cmd->maxtxpkt = 0;
9005 cmd->maxrxpkt = 0;
9006 return 0;
9007}
9008
9009static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9010{
9011 struct tg3 *tp = netdev_priv(dev);
9012
9013 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9014 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9015 return -EAGAIN;
9016 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
9017 }
9018
9019 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9020 /* These are the only valid advertisement bits allowed. */
9021 if (cmd->autoneg == AUTONEG_ENABLE &&
9022 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
9023 ADVERTISED_1000baseT_Full |
9024 ADVERTISED_Autoneg |
9025 ADVERTISED_FIBRE)))
9026 return -EINVAL;
9027 /* Fiber can only do SPEED_1000. */
9028 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9029 (cmd->speed != SPEED_1000))
9030 return -EINVAL;
9031 /* Copper cannot force SPEED_1000. */
9032 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9033 (cmd->speed == SPEED_1000))
9034 return -EINVAL;
9035 else if ((cmd->speed == SPEED_1000) &&
9036 (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9037 return -EINVAL;
9038
9039 tg3_full_lock(tp, 0);
9040
9041 tp->link_config.autoneg = cmd->autoneg;
9042 if (cmd->autoneg == AUTONEG_ENABLE) {
9043 tp->link_config.advertising = (cmd->advertising |
9044 ADVERTISED_Autoneg);
9045 tp->link_config.speed = SPEED_INVALID;
9046 tp->link_config.duplex = DUPLEX_INVALID;
9047 } else {
9048 tp->link_config.advertising = 0;
9049 tp->link_config.speed = cmd->speed;
9050 tp->link_config.duplex = cmd->duplex;
9051 }
9052
9053 tp->link_config.orig_speed = tp->link_config.speed;
9054 tp->link_config.orig_duplex = tp->link_config.duplex;
9055 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9056
9057 if (netif_running(dev))
9058 tg3_setup_phy(tp, 1);
9059
9060 tg3_full_unlock(tp);
9061
9062 return 0;
9063}
9064
9065static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9066{
9067 struct tg3 *tp = netdev_priv(dev);
9068
9069 strcpy(info->driver, DRV_MODULE_NAME);
9070 strcpy(info->version, DRV_MODULE_VERSION);
9071 strcpy(info->fw_version, tp->fw_ver);
9072 strcpy(info->bus_info, pci_name(tp->pdev));
9073}
9074
9075static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9076{
9077 struct tg3 *tp = netdev_priv(dev);
9078
9079 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9080 device_can_wakeup(&tp->pdev->dev))
9081 wol->supported = WAKE_MAGIC;
9082 else
9083 wol->supported = 0;
9084 wol->wolopts = 0;
9085 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
9086 wol->wolopts = WAKE_MAGIC;
9087 memset(&wol->sopass, 0, sizeof(wol->sopass));
9088}
9089
9090static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9091{
9092 struct tg3 *tp = netdev_priv(dev);
9093 struct device *dp = &tp->pdev->dev;
9094
9095 if (wol->wolopts & ~WAKE_MAGIC)
9096 return -EINVAL;
9097 if ((wol->wolopts & WAKE_MAGIC) &&
9098 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9099 return -EINVAL;
9100
9101 spin_lock_bh(&tp->lock);
9102 if (wol->wolopts & WAKE_MAGIC) {
9103 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9104 device_set_wakeup_enable(dp, true);
9105 } else {
9106 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9107 device_set_wakeup_enable(dp, false);
9108 }
9109 spin_unlock_bh(&tp->lock);
9110
9111 return 0;
9112}
9113
9114static u32 tg3_get_msglevel(struct net_device *dev)
9115{
9116 struct tg3 *tp = netdev_priv(dev);
9117 return tp->msg_enable;
9118}
9119
9120static void tg3_set_msglevel(struct net_device *dev, u32 value)
9121{
9122 struct tg3 *tp = netdev_priv(dev);
9123 tp->msg_enable = value;
9124}
9125
9126static int tg3_set_tso(struct net_device *dev, u32 value)
9127{
9128 struct tg3 *tp = netdev_priv(dev);
9129
9130 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9131 if (value)
9132 return -EINVAL;
9133 return 0;
9134 }
9135 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9136 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9137 if (value) {
9138 dev->features |= NETIF_F_TSO6;
9139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9140 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9141 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9142 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9143 dev->features |= NETIF_F_TSO_ECN;
9144 } else
9145 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9146 }
9147 return ethtool_op_set_tso(dev, value);
9148}
9149
9150static int tg3_nway_reset(struct net_device *dev)
9151{
9152 struct tg3 *tp = netdev_priv(dev);
9153 int r;
9154
9155 if (!netif_running(dev))
9156 return -EAGAIN;
9157
9158 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9159 return -EINVAL;
9160
9161 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9162 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9163 return -EAGAIN;
9164 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9165 } else {
9166 u32 bmcr;
9167
9168 spin_lock_bh(&tp->lock);
9169 r = -EINVAL;
9170 tg3_readphy(tp, MII_BMCR, &bmcr);
9171 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9172 ((bmcr & BMCR_ANENABLE) ||
9173 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9174 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9175 BMCR_ANENABLE);
9176 r = 0;
9177 }
9178 spin_unlock_bh(&tp->lock);
9179 }
9180
9181 return r;
9182}
9183
9184static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9185{
9186 struct tg3 *tp = netdev_priv(dev);
9187
9188 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9189 ering->rx_mini_max_pending = 0;
9190 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9191 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9192 else
9193 ering->rx_jumbo_max_pending = 0;
9194
9195 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9196
9197 ering->rx_pending = tp->rx_pending;
9198 ering->rx_mini_pending = 0;
9199 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9200 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9201 else
9202 ering->rx_jumbo_pending = 0;
9203
9204 ering->tx_pending = tp->tx_pending;
9205}
9206
9207static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9208{
9209 struct tg3 *tp = netdev_priv(dev);
9210 int irq_sync = 0, err = 0;
9211
9212 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9213 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9214 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9215 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9216 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9217 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9218 return -EINVAL;
9219
9220 if (netif_running(dev)) {
9221 tg3_phy_stop(tp);
9222 tg3_netif_stop(tp);
9223 irq_sync = 1;
9224 }
9225
9226 tg3_full_lock(tp, irq_sync);
9227
9228 tp->rx_pending = ering->rx_pending;
9229
9230 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9231 tp->rx_pending > 63)
9232 tp->rx_pending = 63;
9233 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9234 tp->tx_pending = ering->tx_pending;
9235
9236 if (netif_running(dev)) {
9237 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9238 err = tg3_restart_hw(tp, 1);
9239 if (!err)
9240 tg3_netif_start(tp);
9241 }
9242
9243 tg3_full_unlock(tp);
9244
9245 if (irq_sync && !err)
9246 tg3_phy_start(tp);
9247
9248 return err;
9249}
9250
9251static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9252{
9253 struct tg3 *tp = netdev_priv(dev);
9254
9255 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9256
9257 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9258 epause->rx_pause = 1;
9259 else
9260 epause->rx_pause = 0;
9261
9262 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9263 epause->tx_pause = 1;
9264 else
9265 epause->tx_pause = 0;
9266}
9267
9268static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9269{
9270 struct tg3 *tp = netdev_priv(dev);
9271 int err = 0;
9272
9273 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9274 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9275 return -EAGAIN;
9276
9277 if (epause->autoneg) {
9278 u32 newadv;
9279 struct phy_device *phydev;
9280
9281 phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9282
9283 if (epause->rx_pause) {
9284 if (epause->tx_pause)
9285 newadv = ADVERTISED_Pause;
9286 else
9287 newadv = ADVERTISED_Pause |
9288 ADVERTISED_Asym_Pause;
9289 } else if (epause->tx_pause) {
9290 newadv = ADVERTISED_Asym_Pause;
9291 } else
9292 newadv = 0;
9293
9294 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9295 u32 oldadv = phydev->advertising &
9296 (ADVERTISED_Pause |
9297 ADVERTISED_Asym_Pause);
9298 if (oldadv != newadv) {
9299 phydev->advertising &=
9300 ~(ADVERTISED_Pause |
9301 ADVERTISED_Asym_Pause);
9302 phydev->advertising |= newadv;
9303 err = phy_start_aneg(phydev);
9304 }
9305 } else {
9306 tp->link_config.advertising &=
9307 ~(ADVERTISED_Pause |
9308 ADVERTISED_Asym_Pause);
9309 tp->link_config.advertising |= newadv;
9310 }
9311 } else {
9312 if (epause->rx_pause)
9313 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9314 else
9315 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9316
9317 if (epause->tx_pause)
9318 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9319 else
9320 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9321
9322 if (netif_running(dev))
9323 tg3_setup_flow_control(tp, 0, 0);
9324 }
9325 } else {
9326 int irq_sync = 0;
9327
9328 if (netif_running(dev)) {
9329 tg3_netif_stop(tp);
9330 irq_sync = 1;
9331 }
9332
9333 tg3_full_lock(tp, irq_sync);
9334
9335 if (epause->autoneg)
9336 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9337 else
9338 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9339 if (epause->rx_pause)
9340 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9341 else
9342 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9343 if (epause->tx_pause)
9344 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9345 else
9346 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9347
9348 if (netif_running(dev)) {
9349 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9350 err = tg3_restart_hw(tp, 1);
9351 if (!err)
9352 tg3_netif_start(tp);
9353 }
9354
9355 tg3_full_unlock(tp);
9356 }
9357
9358 return err;
9359}
9360
9361static u32 tg3_get_rx_csum(struct net_device *dev)
9362{
9363 struct tg3 *tp = netdev_priv(dev);
9364 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9365}
9366
9367static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9368{
9369 struct tg3 *tp = netdev_priv(dev);
9370
9371 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9372 if (data != 0)
9373 return -EINVAL;
9374 return 0;
9375 }
9376
9377 spin_lock_bh(&tp->lock);
9378 if (data)
9379 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9380 else
9381 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9382 spin_unlock_bh(&tp->lock);
9383
9384 return 0;
9385}
9386
9387static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9388{
9389 struct tg3 *tp = netdev_priv(dev);
9390
9391 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9392 if (data != 0)
9393 return -EINVAL;
9394 return 0;
9395 }
9396
9397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9400 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9401 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9402 ethtool_op_set_tx_ipv6_csum(dev, data);
9403 else
9404 ethtool_op_set_tx_csum(dev, data);
9405
9406 return 0;
9407}
9408
9409static int tg3_get_sset_count (struct net_device *dev, int sset)
9410{
9411 switch (sset) {
9412 case ETH_SS_TEST:
9413 return TG3_NUM_TEST;
9414 case ETH_SS_STATS:
9415 return TG3_NUM_STATS;
9416 default:
9417 return -EOPNOTSUPP;
9418 }
9419}
9420
9421static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9422{
9423 switch (stringset) {
9424 case ETH_SS_STATS:
9425 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9426 break;
9427 case ETH_SS_TEST:
9428 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9429 break;
9430 default:
9431 WARN_ON(1); /* we need a WARN() */
9432 break;
9433 }
9434}
9435
9436static int tg3_phys_id(struct net_device *dev, u32 data)
9437{
9438 struct tg3 *tp = netdev_priv(dev);
9439 int i;
9440
9441 if (!netif_running(tp->dev))
9442 return -EAGAIN;
9443
9444 if (data == 0)
9445 data = UINT_MAX / 2;
9446
9447 for (i = 0; i < (data * 2); i++) {
9448 if ((i % 2) == 0)
9449 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9450 LED_CTRL_1000MBPS_ON |
9451 LED_CTRL_100MBPS_ON |
9452 LED_CTRL_10MBPS_ON |
9453 LED_CTRL_TRAFFIC_OVERRIDE |
9454 LED_CTRL_TRAFFIC_BLINK |
9455 LED_CTRL_TRAFFIC_LED);
9456
9457 else
9458 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9459 LED_CTRL_TRAFFIC_OVERRIDE);
9460
9461 if (msleep_interruptible(500))
9462 break;
9463 }
9464 tw32(MAC_LED_CTRL, tp->led_ctrl);
9465 return 0;
9466}
9467
9468static void tg3_get_ethtool_stats (struct net_device *dev,
9469 struct ethtool_stats *estats, u64 *tmp_stats)
9470{
9471 struct tg3 *tp = netdev_priv(dev);
9472 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9473}
9474
9475#define NVRAM_TEST_SIZE 0x100
9476#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9477#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9478#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9479#define NVRAM_SELFBOOT_HW_SIZE 0x20
9480#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9481
9482static int tg3_test_nvram(struct tg3 *tp)
9483{
9484 u32 csum, magic;
9485 __le32 *buf;
9486 int i, j, k, err = 0, size;
9487
9488 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9489 return -EIO;
9490
9491 if (magic == TG3_EEPROM_MAGIC)
9492 size = NVRAM_TEST_SIZE;
9493 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9494 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9495 TG3_EEPROM_SB_FORMAT_1) {
9496 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9497 case TG3_EEPROM_SB_REVISION_0:
9498 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9499 break;
9500 case TG3_EEPROM_SB_REVISION_2:
9501 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9502 break;
9503 case TG3_EEPROM_SB_REVISION_3:
9504 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9505 break;
9506 default:
9507 return 0;
9508 }
9509 } else
9510 return 0;
9511 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9512 size = NVRAM_SELFBOOT_HW_SIZE;
9513 else
9514 return -EIO;
9515
9516 buf = kmalloc(size, GFP_KERNEL);
9517 if (buf == NULL)
9518 return -ENOMEM;
9519
9520 err = -EIO;
9521 for (i = 0, j = 0; i < size; i += 4, j++) {
9522 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9523 break;
9524 }
9525 if (i < size)
9526 goto out;
9527
9528 /* Selfboot format */
9529 magic = swab32(le32_to_cpu(buf[0]));
9530 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9531 TG3_EEPROM_MAGIC_FW) {
9532 u8 *buf8 = (u8 *) buf, csum8 = 0;
9533
9534 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9535 TG3_EEPROM_SB_REVISION_2) {
9536 /* For rev 2, the csum doesn't include the MBA. */
9537 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9538 csum8 += buf8[i];
9539 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9540 csum8 += buf8[i];
9541 } else {
9542 for (i = 0; i < size; i++)
9543 csum8 += buf8[i];
9544 }
9545
9546 if (csum8 == 0) {
9547 err = 0;
9548 goto out;
9549 }
9550
9551 err = -EIO;
9552 goto out;
9553 }
9554
9555 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9556 TG3_EEPROM_MAGIC_HW) {
9557 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9558 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9559 u8 *buf8 = (u8 *) buf;
9560
9561 /* Separate the parity bits and the data bytes. */
9562 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9563 if ((i == 0) || (i == 8)) {
9564 int l;
9565 u8 msk;
9566
9567 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9568 parity[k++] = buf8[i] & msk;
9569 i++;
9570 }
9571 else if (i == 16) {
9572 int l;
9573 u8 msk;
9574
9575 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9576 parity[k++] = buf8[i] & msk;
9577 i++;
9578
9579 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9580 parity[k++] = buf8[i] & msk;
9581 i++;
9582 }
9583 data[j++] = buf8[i];
9584 }
9585
9586 err = -EIO;
9587 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9588 u8 hw8 = hweight8(data[i]);
9589
9590 if ((hw8 & 0x1) && parity[i])
9591 goto out;
9592 else if (!(hw8 & 0x1) && !parity[i])
9593 goto out;
9594 }
9595 err = 0;
9596 goto out;
9597 }
9598
9599 /* Bootstrap checksum at offset 0x10 */
9600 csum = calc_crc((unsigned char *) buf, 0x10);
9601 if(csum != le32_to_cpu(buf[0x10/4]))
9602 goto out;
9603
9604 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9605 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9606 if (csum != le32_to_cpu(buf[0xfc/4]))
9607 goto out;
9608
9609 err = 0;
9610
9611out:
9612 kfree(buf);
9613 return err;
9614}
9615
9616#define TG3_SERDES_TIMEOUT_SEC 2
9617#define TG3_COPPER_TIMEOUT_SEC 6
9618
9619static int tg3_test_link(struct tg3 *tp)
9620{
9621 int i, max;
9622
9623 if (!netif_running(tp->dev))
9624 return -ENODEV;
9625
9626 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9627 max = TG3_SERDES_TIMEOUT_SEC;
9628 else
9629 max = TG3_COPPER_TIMEOUT_SEC;
9630
9631 for (i = 0; i < max; i++) {
9632 if (netif_carrier_ok(tp->dev))
9633 return 0;
9634
9635 if (msleep_interruptible(1000))
9636 break;
9637 }
9638
9639 return -EIO;
9640}
9641
9642/* Only test the commonly used registers */
9643static int tg3_test_registers(struct tg3 *tp)
9644{
9645 int i, is_5705, is_5750;
9646 u32 offset, read_mask, write_mask, val, save_val, read_val;
9647 static struct {
9648 u16 offset;
9649 u16 flags;
9650#define TG3_FL_5705 0x1
9651#define TG3_FL_NOT_5705 0x2
9652#define TG3_FL_NOT_5788 0x4
9653#define TG3_FL_NOT_5750 0x8
9654 u32 read_mask;
9655 u32 write_mask;
9656 } reg_tbl[] = {
9657 /* MAC Control Registers */
9658 { MAC_MODE, TG3_FL_NOT_5705,
9659 0x00000000, 0x00ef6f8c },
9660 { MAC_MODE, TG3_FL_5705,
9661 0x00000000, 0x01ef6b8c },
9662 { MAC_STATUS, TG3_FL_NOT_5705,
9663 0x03800107, 0x00000000 },
9664 { MAC_STATUS, TG3_FL_5705,
9665 0x03800100, 0x00000000 },
9666 { MAC_ADDR_0_HIGH, 0x0000,
9667 0x00000000, 0x0000ffff },
9668 { MAC_ADDR_0_LOW, 0x0000,
9669 0x00000000, 0xffffffff },
9670 { MAC_RX_MTU_SIZE, 0x0000,
9671 0x00000000, 0x0000ffff },
9672 { MAC_TX_MODE, 0x0000,
9673 0x00000000, 0x00000070 },
9674 { MAC_TX_LENGTHS, 0x0000,
9675 0x00000000, 0x00003fff },
9676 { MAC_RX_MODE, TG3_FL_NOT_5705,
9677 0x00000000, 0x000007fc },
9678 { MAC_RX_MODE, TG3_FL_5705,
9679 0x00000000, 0x000007dc },
9680 { MAC_HASH_REG_0, 0x0000,
9681 0x00000000, 0xffffffff },
9682 { MAC_HASH_REG_1, 0x0000,
9683 0x00000000, 0xffffffff },
9684 { MAC_HASH_REG_2, 0x0000,
9685 0x00000000, 0xffffffff },
9686 { MAC_HASH_REG_3, 0x0000,
9687 0x00000000, 0xffffffff },
9688
9689 /* Receive Data and Receive BD Initiator Control Registers. */
9690 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9691 0x00000000, 0xffffffff },
9692 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9693 0x00000000, 0xffffffff },
9694 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9695 0x00000000, 0x00000003 },
9696 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9697 0x00000000, 0xffffffff },
9698 { RCVDBDI_STD_BD+0, 0x0000,
9699 0x00000000, 0xffffffff },
9700 { RCVDBDI_STD_BD+4, 0x0000,
9701 0x00000000, 0xffffffff },
9702 { RCVDBDI_STD_BD+8, 0x0000,
9703 0x00000000, 0xffff0002 },
9704 { RCVDBDI_STD_BD+0xc, 0x0000,
9705 0x00000000, 0xffffffff },
9706
9707 /* Receive BD Initiator Control Registers. */
9708 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9709 0x00000000, 0xffffffff },
9710 { RCVBDI_STD_THRESH, TG3_FL_5705,
9711 0x00000000, 0x000003ff },
9712 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9713 0x00000000, 0xffffffff },
9714
9715 /* Host Coalescing Control Registers. */
9716 { HOSTCC_MODE, TG3_FL_NOT_5705,
9717 0x00000000, 0x00000004 },
9718 { HOSTCC_MODE, TG3_FL_5705,
9719 0x00000000, 0x000000f6 },
9720 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9721 0x00000000, 0xffffffff },
9722 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9723 0x00000000, 0x000003ff },
9724 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9725 0x00000000, 0xffffffff },
9726 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9727 0x00000000, 0x000003ff },
9728 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9729 0x00000000, 0xffffffff },
9730 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9731 0x00000000, 0x000000ff },
9732 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9733 0x00000000, 0xffffffff },
9734 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9735 0x00000000, 0x000000ff },
9736 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9737 0x00000000, 0xffffffff },
9738 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9739 0x00000000, 0xffffffff },
9740 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9741 0x00000000, 0xffffffff },
9742 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9743 0x00000000, 0x000000ff },
9744 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9745 0x00000000, 0xffffffff },
9746 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9747 0x00000000, 0x000000ff },
9748 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9749 0x00000000, 0xffffffff },
9750 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9751 0x00000000, 0xffffffff },
9752 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9753 0x00000000, 0xffffffff },
9754 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9755 0x00000000, 0xffffffff },
9756 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9757 0x00000000, 0xffffffff },
9758 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9759 0xffffffff, 0x00000000 },
9760 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9761 0xffffffff, 0x00000000 },
9762
9763 /* Buffer Manager Control Registers. */
9764 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9765 0x00000000, 0x007fff80 },
9766 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9767 0x00000000, 0x007fffff },
9768 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9769 0x00000000, 0x0000003f },
9770 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9771 0x00000000, 0x000001ff },
9772 { BUFMGR_MB_HIGH_WATER, 0x0000,
9773 0x00000000, 0x000001ff },
9774 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9775 0xffffffff, 0x00000000 },
9776 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9777 0xffffffff, 0x00000000 },
9778
9779 /* Mailbox Registers */
9780 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9781 0x00000000, 0x000001ff },
9782 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9783 0x00000000, 0x000001ff },
9784 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9785 0x00000000, 0x000007ff },
9786 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9787 0x00000000, 0x000001ff },
9788
9789 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9790 };
9791
9792 is_5705 = is_5750 = 0;
9793 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9794 is_5705 = 1;
9795 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9796 is_5750 = 1;
9797 }
9798
9799 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9800 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9801 continue;
9802
9803 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9804 continue;
9805
9806 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9807 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9808 continue;
9809
9810 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9811 continue;
9812
9813 offset = (u32) reg_tbl[i].offset;
9814 read_mask = reg_tbl[i].read_mask;
9815 write_mask = reg_tbl[i].write_mask;
9816
9817 /* Save the original register content */
9818 save_val = tr32(offset);
9819
9820 /* Determine the read-only value. */
9821 read_val = save_val & read_mask;
9822
9823 /* Write zero to the register, then make sure the read-only bits
9824 * are not changed and the read/write bits are all zeros.
9825 */
9826 tw32(offset, 0);
9827
9828 val = tr32(offset);
9829
9830 /* Test the read-only and read/write bits. */
9831 if (((val & read_mask) != read_val) || (val & write_mask))
9832 goto out;
9833
9834 /* Write ones to all the bits defined by RdMask and WrMask, then
9835 * make sure the read-only bits are not changed and the
9836 * read/write bits are all ones.
9837 */
9838 tw32(offset, read_mask | write_mask);
9839
9840 val = tr32(offset);
9841
9842 /* Test the read-only bits. */
9843 if ((val & read_mask) != read_val)
9844 goto out;
9845
9846 /* Test the read/write bits. */
9847 if ((val & write_mask) != write_mask)
9848 goto out;
9849
9850 tw32(offset, save_val);
9851 }
9852
9853 return 0;
9854
9855out:
9856 if (netif_msg_hw(tp))
9857 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9858 offset);
9859 tw32(offset, save_val);
9860 return -EIO;
9861}
9862
9863static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9864{
9865 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9866 int i;
9867 u32 j;
9868
9869 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9870 for (j = 0; j < len; j += 4) {
9871 u32 val;
9872
9873 tg3_write_mem(tp, offset + j, test_pattern[i]);
9874 tg3_read_mem(tp, offset + j, &val);
9875 if (val != test_pattern[i])
9876 return -EIO;
9877 }
9878 }
9879 return 0;
9880}
9881
9882static int tg3_test_memory(struct tg3 *tp)
9883{
9884 static struct mem_entry {
9885 u32 offset;
9886 u32 len;
9887 } mem_tbl_570x[] = {
9888 { 0x00000000, 0x00b50},
9889 { 0x00002000, 0x1c000},
9890 { 0xffffffff, 0x00000}
9891 }, mem_tbl_5705[] = {
9892 { 0x00000100, 0x0000c},
9893 { 0x00000200, 0x00008},
9894 { 0x00004000, 0x00800},
9895 { 0x00006000, 0x01000},
9896 { 0x00008000, 0x02000},
9897 { 0x00010000, 0x0e000},
9898 { 0xffffffff, 0x00000}
9899 }, mem_tbl_5755[] = {
9900 { 0x00000200, 0x00008},
9901 { 0x00004000, 0x00800},
9902 { 0x00006000, 0x00800},
9903 { 0x00008000, 0x02000},
9904 { 0x00010000, 0x0c000},
9905 { 0xffffffff, 0x00000}
9906 }, mem_tbl_5906[] = {
9907 { 0x00000200, 0x00008},
9908 { 0x00004000, 0x00400},
9909 { 0x00006000, 0x00400},
9910 { 0x00008000, 0x01000},
9911 { 0x00010000, 0x01000},
9912 { 0xffffffff, 0x00000}
9913 };
9914 struct mem_entry *mem_tbl;
9915 int err = 0;
9916 int i;
9917
9918 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9924 mem_tbl = mem_tbl_5755;
9925 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9926 mem_tbl = mem_tbl_5906;
9927 else
9928 mem_tbl = mem_tbl_5705;
9929 } else
9930 mem_tbl = mem_tbl_570x;
9931
9932 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9933 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9934 mem_tbl[i].len)) != 0)
9935 break;
9936 }
9937
9938 return err;
9939}
9940
9941#define TG3_MAC_LOOPBACK 0
9942#define TG3_PHY_LOOPBACK 1
9943
9944static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9945{
9946 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9947 u32 desc_idx;
9948 struct sk_buff *skb, *rx_skb;
9949 u8 *tx_data;
9950 dma_addr_t map;
9951 int num_pkts, tx_len, rx_len, i, err;
9952 struct tg3_rx_buffer_desc *desc;
9953
9954 if (loopback_mode == TG3_MAC_LOOPBACK) {
9955 /* HW errata - mac loopback fails in some cases on 5780.
9956 * Normal traffic and PHY loopback are not affected by
9957 * errata.
9958 */
9959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9960 return 0;
9961
9962 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9963 MAC_MODE_PORT_INT_LPBACK;
9964 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9965 mac_mode |= MAC_MODE_LINK_POLARITY;
9966 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9967 mac_mode |= MAC_MODE_PORT_MODE_MII;
9968 else
9969 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9970 tw32(MAC_MODE, mac_mode);
9971 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9972 u32 val;
9973
9974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9975 u32 phytest;
9976
9977 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9978 u32 phy;
9979
9980 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9981 phytest | MII_TG3_EPHY_SHADOW_EN);
9982 if (!tg3_readphy(tp, 0x1b, &phy))
9983 tg3_writephy(tp, 0x1b, phy & ~0x20);
9984 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9985 }
9986 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9987 } else
9988 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9989
9990 tg3_phy_toggle_automdix(tp, 0);
9991
9992 tg3_writephy(tp, MII_BMCR, val);
9993 udelay(40);
9994
9995 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9997 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9998 mac_mode |= MAC_MODE_PORT_MODE_MII;
9999 } else
10000 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10001
10002 /* reset to prevent losing 1st rx packet intermittently */
10003 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10004 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10005 udelay(10);
10006 tw32_f(MAC_RX_MODE, tp->rx_mode);
10007 }
10008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10009 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10010 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10011 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10012 mac_mode |= MAC_MODE_LINK_POLARITY;
10013 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10014 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10015 }
10016 tw32(MAC_MODE, mac_mode);
10017 }
10018 else
10019 return -EINVAL;
10020
10021 err = -EIO;
10022
10023 tx_len = 1514;
10024 skb = netdev_alloc_skb(tp->dev, tx_len);
10025 if (!skb)
10026 return -ENOMEM;
10027
10028 tx_data = skb_put(skb, tx_len);
10029 memcpy(tx_data, tp->dev->dev_addr, 6);
10030 memset(tx_data + 6, 0x0, 8);
10031
10032 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10033
10034 for (i = 14; i < tx_len; i++)
10035 tx_data[i] = (u8) (i & 0xff);
10036
10037 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10038
10039 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10040 HOSTCC_MODE_NOW);
10041
10042 udelay(10);
10043
10044 rx_start_idx = tp->hw_status->idx[0].rx_producer;
10045
10046 num_pkts = 0;
10047
10048 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
10049
10050 tp->tx_prod++;
10051 num_pkts++;
10052
10053 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10054 tp->tx_prod);
10055 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
10056
10057 udelay(10);
10058
10059 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10060 for (i = 0; i < 25; i++) {
10061 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10062 HOSTCC_MODE_NOW);
10063
10064 udelay(10);
10065
10066 tx_idx = tp->hw_status->idx[0].tx_consumer;
10067 rx_idx = tp->hw_status->idx[0].rx_producer;
10068 if ((tx_idx == tp->tx_prod) &&
10069 (rx_idx == (rx_start_idx + num_pkts)))
10070 break;
10071 }
10072
10073 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10074 dev_kfree_skb(skb);
10075
10076 if (tx_idx != tp->tx_prod)
10077 goto out;
10078
10079 if (rx_idx != rx_start_idx + num_pkts)
10080 goto out;
10081
10082 desc = &tp->rx_rcb[rx_start_idx];
10083 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10084 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10085 if (opaque_key != RXD_OPAQUE_RING_STD)
10086 goto out;
10087
10088 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10089 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10090 goto out;
10091
10092 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10093 if (rx_len != tx_len)
10094 goto out;
10095
10096 rx_skb = tp->rx_std_buffers[desc_idx].skb;
10097
10098 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10099 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10100
10101 for (i = 14; i < tx_len; i++) {
10102 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10103 goto out;
10104 }
10105 err = 0;
10106
10107 /* tg3_free_rings will unmap and free the rx_skb */
10108out:
10109 return err;
10110}
10111
10112#define TG3_MAC_LOOPBACK_FAILED 1
10113#define TG3_PHY_LOOPBACK_FAILED 2
10114#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10115 TG3_PHY_LOOPBACK_FAILED)
10116
10117static int tg3_test_loopback(struct tg3 *tp)
10118{
10119 int err = 0;
10120 u32 cpmuctrl = 0;
10121
10122 if (!netif_running(tp->dev))
10123 return TG3_LOOPBACK_FAILED;
10124
10125 err = tg3_reset_hw(tp, 1);
10126 if (err)
10127 return TG3_LOOPBACK_FAILED;
10128
10129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10132 int i;
10133 u32 status;
10134
10135 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10136
10137 /* Wait for up to 40 microseconds to acquire lock. */
10138 for (i = 0; i < 4; i++) {
10139 status = tr32(TG3_CPMU_MUTEX_GNT);
10140 if (status == CPMU_MUTEX_GNT_DRIVER)
10141 break;
10142 udelay(10);
10143 }
10144
10145 if (status != CPMU_MUTEX_GNT_DRIVER)
10146 return TG3_LOOPBACK_FAILED;
10147
10148 /* Turn off link-based power management. */
10149 cpmuctrl = tr32(TG3_CPMU_CTRL);
10150 tw32(TG3_CPMU_CTRL,
10151 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10152 CPMU_CTRL_LINK_AWARE_MODE));
10153 }
10154
10155 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10156 err |= TG3_MAC_LOOPBACK_FAILED;
10157
10158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10161 tw32(TG3_CPMU_CTRL, cpmuctrl);
10162
10163 /* Release the mutex */
10164 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10165 }
10166
10167 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10168 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10169 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10170 err |= TG3_PHY_LOOPBACK_FAILED;
10171 }
10172
10173 return err;
10174}
10175
10176static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10177 u64 *data)
10178{
10179 struct tg3 *tp = netdev_priv(dev);
10180
10181 if (tp->link_config.phy_is_low_power)
10182 tg3_set_power_state(tp, PCI_D0);
10183
10184 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10185
10186 if (tg3_test_nvram(tp) != 0) {
10187 etest->flags |= ETH_TEST_FL_FAILED;
10188 data[0] = 1;
10189 }
10190 if (tg3_test_link(tp) != 0) {
10191 etest->flags |= ETH_TEST_FL_FAILED;
10192 data[1] = 1;
10193 }
10194 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10195 int err, err2 = 0, irq_sync = 0;
10196
10197 if (netif_running(dev)) {
10198 tg3_phy_stop(tp);
10199 tg3_netif_stop(tp);
10200 irq_sync = 1;
10201 }
10202
10203 tg3_full_lock(tp, irq_sync);
10204
10205 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10206 err = tg3_nvram_lock(tp);
10207 tg3_halt_cpu(tp, RX_CPU_BASE);
10208 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10209 tg3_halt_cpu(tp, TX_CPU_BASE);
10210 if (!err)
10211 tg3_nvram_unlock(tp);
10212
10213 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10214 tg3_phy_reset(tp);
10215
10216 if (tg3_test_registers(tp) != 0) {
10217 etest->flags |= ETH_TEST_FL_FAILED;
10218 data[2] = 1;
10219 }
10220 if (tg3_test_memory(tp) != 0) {
10221 etest->flags |= ETH_TEST_FL_FAILED;
10222 data[3] = 1;
10223 }
10224 if ((data[4] = tg3_test_loopback(tp)) != 0)
10225 etest->flags |= ETH_TEST_FL_FAILED;
10226
10227 tg3_full_unlock(tp);
10228
10229 if (tg3_test_interrupt(tp) != 0) {
10230 etest->flags |= ETH_TEST_FL_FAILED;
10231 data[5] = 1;
10232 }
10233
10234 tg3_full_lock(tp, 0);
10235
10236 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10237 if (netif_running(dev)) {
10238 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10239 err2 = tg3_restart_hw(tp, 1);
10240 if (!err2)
10241 tg3_netif_start(tp);
10242 }
10243
10244 tg3_full_unlock(tp);
10245
10246 if (irq_sync && !err2)
10247 tg3_phy_start(tp);
10248 }
10249 if (tp->link_config.phy_is_low_power)
10250 tg3_set_power_state(tp, PCI_D3hot);
10251
10252}
10253
10254static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10255{
10256 struct mii_ioctl_data *data = if_mii(ifr);
10257 struct tg3 *tp = netdev_priv(dev);
10258 int err;
10259
10260 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10261 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10262 return -EAGAIN;
10263 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10264 }
10265
10266 switch(cmd) {
10267 case SIOCGMIIPHY:
10268 data->phy_id = PHY_ADDR;
10269
10270 /* fallthru */
10271 case SIOCGMIIREG: {
10272 u32 mii_regval;
10273
10274 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10275 break; /* We have no PHY */
10276
10277 if (tp->link_config.phy_is_low_power)
10278 return -EAGAIN;
10279
10280 spin_lock_bh(&tp->lock);
10281 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10282 spin_unlock_bh(&tp->lock);
10283
10284 data->val_out = mii_regval;
10285
10286 return err;
10287 }
10288
10289 case SIOCSMIIREG:
10290 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10291 break; /* We have no PHY */
10292
10293 if (!capable(CAP_NET_ADMIN))
10294 return -EPERM;
10295
10296 if (tp->link_config.phy_is_low_power)
10297 return -EAGAIN;
10298
10299 spin_lock_bh(&tp->lock);
10300 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10301 spin_unlock_bh(&tp->lock);
10302
10303 return err;
10304
10305 default:
10306 /* do nothing */
10307 break;
10308 }
10309 return -EOPNOTSUPP;
10310}
10311
10312#if TG3_VLAN_TAG_USED
10313static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10314{
10315 struct tg3 *tp = netdev_priv(dev);
10316
10317 if (netif_running(dev))
10318 tg3_netif_stop(tp);
10319
10320 tg3_full_lock(tp, 0);
10321
10322 tp->vlgrp = grp;
10323
10324 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10325 __tg3_set_rx_mode(dev);
10326
10327 if (netif_running(dev))
10328 tg3_netif_start(tp);
10329
10330 tg3_full_unlock(tp);
10331}
10332#endif
10333
10334static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10335{
10336 struct tg3 *tp = netdev_priv(dev);
10337
10338 memcpy(ec, &tp->coal, sizeof(*ec));
10339 return 0;
10340}
10341
10342static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10343{
10344 struct tg3 *tp = netdev_priv(dev);
10345 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10346 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10347
10348 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10349 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10350 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10351 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10352 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10353 }
10354
10355 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10356 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10357 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10358 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10359 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10360 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10361 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10362 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10363 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10364 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10365 return -EINVAL;
10366
10367 /* No rx interrupts will be generated if both are zero */
10368 if ((ec->rx_coalesce_usecs == 0) &&
10369 (ec->rx_max_coalesced_frames == 0))
10370 return -EINVAL;
10371
10372 /* No tx interrupts will be generated if both are zero */
10373 if ((ec->tx_coalesce_usecs == 0) &&
10374 (ec->tx_max_coalesced_frames == 0))
10375 return -EINVAL;
10376
10377 /* Only copy relevant parameters, ignore all others. */
10378 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10379 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10380 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10381 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10382 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10383 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10384 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10385 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10386 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10387
10388 if (netif_running(dev)) {
10389 tg3_full_lock(tp, 0);
10390 __tg3_set_coalesce(tp, &tp->coal);
10391 tg3_full_unlock(tp);
10392 }
10393 return 0;
10394}
10395
10396static const struct ethtool_ops tg3_ethtool_ops = {
10397 .get_settings = tg3_get_settings,
10398 .set_settings = tg3_set_settings,
10399 .get_drvinfo = tg3_get_drvinfo,
10400 .get_regs_len = tg3_get_regs_len,
10401 .get_regs = tg3_get_regs,
10402 .get_wol = tg3_get_wol,
10403 .set_wol = tg3_set_wol,
10404 .get_msglevel = tg3_get_msglevel,
10405 .set_msglevel = tg3_set_msglevel,
10406 .nway_reset = tg3_nway_reset,
10407 .get_link = ethtool_op_get_link,
10408 .get_eeprom_len = tg3_get_eeprom_len,
10409 .get_eeprom = tg3_get_eeprom,
10410 .set_eeprom = tg3_set_eeprom,
10411 .get_ringparam = tg3_get_ringparam,
10412 .set_ringparam = tg3_set_ringparam,
10413 .get_pauseparam = tg3_get_pauseparam,
10414 .set_pauseparam = tg3_set_pauseparam,
10415 .get_rx_csum = tg3_get_rx_csum,
10416 .set_rx_csum = tg3_set_rx_csum,
10417 .set_tx_csum = tg3_set_tx_csum,
10418 .set_sg = ethtool_op_set_sg,
10419 .set_tso = tg3_set_tso,
10420 .self_test = tg3_self_test,
10421 .get_strings = tg3_get_strings,
10422 .phys_id = tg3_phys_id,
10423 .get_ethtool_stats = tg3_get_ethtool_stats,
10424 .get_coalesce = tg3_get_coalesce,
10425 .set_coalesce = tg3_set_coalesce,
10426 .get_sset_count = tg3_get_sset_count,
10427};
10428
10429static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10430{
10431 u32 cursize, val, magic;
10432
10433 tp->nvram_size = EEPROM_CHIP_SIZE;
10434
10435 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10436 return;
10437
10438 if ((magic != TG3_EEPROM_MAGIC) &&
10439 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10440 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10441 return;
10442
10443 /*
10444 * Size the chip by reading offsets at increasing powers of two.
10445 * When we encounter our validation signature, we know the addressing
10446 * has wrapped around, and thus have our chip size.
10447 */
10448 cursize = 0x10;
10449
10450 while (cursize < tp->nvram_size) {
10451 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10452 return;
10453
10454 if (val == magic)
10455 break;
10456
10457 cursize <<= 1;
10458 }
10459
10460 tp->nvram_size = cursize;
10461}
10462
10463static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10464{
10465 u32 val;
10466
10467 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10468 return;
10469
10470 /* Selfboot format */
10471 if (val != TG3_EEPROM_MAGIC) {
10472 tg3_get_eeprom_size(tp);
10473 return;
10474 }
10475
10476 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10477 if (val != 0) {
10478 tp->nvram_size = (val >> 16) * 1024;
10479 return;
10480 }
10481 }
10482 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10483}
10484
10485static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10486{
10487 u32 nvcfg1;
10488
10489 nvcfg1 = tr32(NVRAM_CFG1);
10490 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10491 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10492 }
10493 else {
10494 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10495 tw32(NVRAM_CFG1, nvcfg1);
10496 }
10497
10498 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10499 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10500 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10501 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10502 tp->nvram_jedecnum = JEDEC_ATMEL;
10503 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10504 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10505 break;
10506 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10507 tp->nvram_jedecnum = JEDEC_ATMEL;
10508 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10509 break;
10510 case FLASH_VENDOR_ATMEL_EEPROM:
10511 tp->nvram_jedecnum = JEDEC_ATMEL;
10512 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10513 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10514 break;
10515 case FLASH_VENDOR_ST:
10516 tp->nvram_jedecnum = JEDEC_ST;
10517 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10518 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519 break;
10520 case FLASH_VENDOR_SAIFUN:
10521 tp->nvram_jedecnum = JEDEC_SAIFUN;
10522 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10523 break;
10524 case FLASH_VENDOR_SST_SMALL:
10525 case FLASH_VENDOR_SST_LARGE:
10526 tp->nvram_jedecnum = JEDEC_SST;
10527 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10528 break;
10529 }
10530 }
10531 else {
10532 tp->nvram_jedecnum = JEDEC_ATMEL;
10533 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10534 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10535 }
10536}
10537
10538static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10539{
10540 u32 nvcfg1;
10541
10542 nvcfg1 = tr32(NVRAM_CFG1);
10543
10544 /* NVRAM protection for TPM */
10545 if (nvcfg1 & (1 << 27))
10546 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10547
10548 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10549 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10550 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10551 tp->nvram_jedecnum = JEDEC_ATMEL;
10552 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10553 break;
10554 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10555 tp->nvram_jedecnum = JEDEC_ATMEL;
10556 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10557 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10558 break;
10559 case FLASH_5752VENDOR_ST_M45PE10:
10560 case FLASH_5752VENDOR_ST_M45PE20:
10561 case FLASH_5752VENDOR_ST_M45PE40:
10562 tp->nvram_jedecnum = JEDEC_ST;
10563 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10564 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10565 break;
10566 }
10567
10568 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10569 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10570 case FLASH_5752PAGE_SIZE_256:
10571 tp->nvram_pagesize = 256;
10572 break;
10573 case FLASH_5752PAGE_SIZE_512:
10574 tp->nvram_pagesize = 512;
10575 break;
10576 case FLASH_5752PAGE_SIZE_1K:
10577 tp->nvram_pagesize = 1024;
10578 break;
10579 case FLASH_5752PAGE_SIZE_2K:
10580 tp->nvram_pagesize = 2048;
10581 break;
10582 case FLASH_5752PAGE_SIZE_4K:
10583 tp->nvram_pagesize = 4096;
10584 break;
10585 case FLASH_5752PAGE_SIZE_264:
10586 tp->nvram_pagesize = 264;
10587 break;
10588 }
10589 }
10590 else {
10591 /* For eeprom, set pagesize to maximum eeprom size */
10592 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10593
10594 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10595 tw32(NVRAM_CFG1, nvcfg1);
10596 }
10597}
10598
10599static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10600{
10601 u32 nvcfg1, protect = 0;
10602
10603 nvcfg1 = tr32(NVRAM_CFG1);
10604
10605 /* NVRAM protection for TPM */
10606 if (nvcfg1 & (1 << 27)) {
10607 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10608 protect = 1;
10609 }
10610
10611 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10612 switch (nvcfg1) {
10613 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10614 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10615 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10616 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10617 tp->nvram_jedecnum = JEDEC_ATMEL;
10618 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10619 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10620 tp->nvram_pagesize = 264;
10621 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10622 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10623 tp->nvram_size = (protect ? 0x3e200 :
10624 TG3_NVRAM_SIZE_512KB);
10625 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10626 tp->nvram_size = (protect ? 0x1f200 :
10627 TG3_NVRAM_SIZE_256KB);
10628 else
10629 tp->nvram_size = (protect ? 0x1f200 :
10630 TG3_NVRAM_SIZE_128KB);
10631 break;
10632 case FLASH_5752VENDOR_ST_M45PE10:
10633 case FLASH_5752VENDOR_ST_M45PE20:
10634 case FLASH_5752VENDOR_ST_M45PE40:
10635 tp->nvram_jedecnum = JEDEC_ST;
10636 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10637 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10638 tp->nvram_pagesize = 256;
10639 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10640 tp->nvram_size = (protect ?
10641 TG3_NVRAM_SIZE_64KB :
10642 TG3_NVRAM_SIZE_128KB);
10643 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10644 tp->nvram_size = (protect ?
10645 TG3_NVRAM_SIZE_64KB :
10646 TG3_NVRAM_SIZE_256KB);
10647 else
10648 tp->nvram_size = (protect ?
10649 TG3_NVRAM_SIZE_128KB :
10650 TG3_NVRAM_SIZE_512KB);
10651 break;
10652 }
10653}
10654
10655static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10656{
10657 u32 nvcfg1;
10658
10659 nvcfg1 = tr32(NVRAM_CFG1);
10660
10661 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10662 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10663 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10664 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10665 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10666 tp->nvram_jedecnum = JEDEC_ATMEL;
10667 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10668 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10669
10670 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10671 tw32(NVRAM_CFG1, nvcfg1);
10672 break;
10673 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10674 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10675 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10676 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10677 tp->nvram_jedecnum = JEDEC_ATMEL;
10678 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10679 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10680 tp->nvram_pagesize = 264;
10681 break;
10682 case FLASH_5752VENDOR_ST_M45PE10:
10683 case FLASH_5752VENDOR_ST_M45PE20:
10684 case FLASH_5752VENDOR_ST_M45PE40:
10685 tp->nvram_jedecnum = JEDEC_ST;
10686 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10687 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10688 tp->nvram_pagesize = 256;
10689 break;
10690 }
10691}
10692
10693static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10694{
10695 u32 nvcfg1, protect = 0;
10696
10697 nvcfg1 = tr32(NVRAM_CFG1);
10698
10699 /* NVRAM protection for TPM */
10700 if (nvcfg1 & (1 << 27)) {
10701 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10702 protect = 1;
10703 }
10704
10705 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10706 switch (nvcfg1) {
10707 case FLASH_5761VENDOR_ATMEL_ADB021D:
10708 case FLASH_5761VENDOR_ATMEL_ADB041D:
10709 case FLASH_5761VENDOR_ATMEL_ADB081D:
10710 case FLASH_5761VENDOR_ATMEL_ADB161D:
10711 case FLASH_5761VENDOR_ATMEL_MDB021D:
10712 case FLASH_5761VENDOR_ATMEL_MDB041D:
10713 case FLASH_5761VENDOR_ATMEL_MDB081D:
10714 case FLASH_5761VENDOR_ATMEL_MDB161D:
10715 tp->nvram_jedecnum = JEDEC_ATMEL;
10716 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10717 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10718 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10719 tp->nvram_pagesize = 256;
10720 break;
10721 case FLASH_5761VENDOR_ST_A_M45PE20:
10722 case FLASH_5761VENDOR_ST_A_M45PE40:
10723 case FLASH_5761VENDOR_ST_A_M45PE80:
10724 case FLASH_5761VENDOR_ST_A_M45PE16:
10725 case FLASH_5761VENDOR_ST_M_M45PE20:
10726 case FLASH_5761VENDOR_ST_M_M45PE40:
10727 case FLASH_5761VENDOR_ST_M_M45PE80:
10728 case FLASH_5761VENDOR_ST_M_M45PE16:
10729 tp->nvram_jedecnum = JEDEC_ST;
10730 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10731 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10732 tp->nvram_pagesize = 256;
10733 break;
10734 }
10735
10736 if (protect) {
10737 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10738 } else {
10739 switch (nvcfg1) {
10740 case FLASH_5761VENDOR_ATMEL_ADB161D:
10741 case FLASH_5761VENDOR_ATMEL_MDB161D:
10742 case FLASH_5761VENDOR_ST_A_M45PE16:
10743 case FLASH_5761VENDOR_ST_M_M45PE16:
10744 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10745 break;
10746 case FLASH_5761VENDOR_ATMEL_ADB081D:
10747 case FLASH_5761VENDOR_ATMEL_MDB081D:
10748 case FLASH_5761VENDOR_ST_A_M45PE80:
10749 case FLASH_5761VENDOR_ST_M_M45PE80:
10750 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10751 break;
10752 case FLASH_5761VENDOR_ATMEL_ADB041D:
10753 case FLASH_5761VENDOR_ATMEL_MDB041D:
10754 case FLASH_5761VENDOR_ST_A_M45PE40:
10755 case FLASH_5761VENDOR_ST_M_M45PE40:
10756 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10757 break;
10758 case FLASH_5761VENDOR_ATMEL_ADB021D:
10759 case FLASH_5761VENDOR_ATMEL_MDB021D:
10760 case FLASH_5761VENDOR_ST_A_M45PE20:
10761 case FLASH_5761VENDOR_ST_M_M45PE20:
10762 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10763 break;
10764 }
10765 }
10766}
10767
10768static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10769{
10770 tp->nvram_jedecnum = JEDEC_ATMEL;
10771 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10772 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10773}
10774
10775/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10776static void __devinit tg3_nvram_init(struct tg3 *tp)
10777{
10778 tw32_f(GRC_EEPROM_ADDR,
10779 (EEPROM_ADDR_FSM_RESET |
10780 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10781 EEPROM_ADDR_CLKPERD_SHIFT)));
10782
10783 msleep(1);
10784
10785 /* Enable seeprom accesses. */
10786 tw32_f(GRC_LOCAL_CTRL,
10787 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10788 udelay(100);
10789
10790 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10791 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10792 tp->tg3_flags |= TG3_FLAG_NVRAM;
10793
10794 if (tg3_nvram_lock(tp)) {
10795 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10796 "tg3_nvram_init failed.\n", tp->dev->name);
10797 return;
10798 }
10799 tg3_enable_nvram_access(tp);
10800
10801 tp->nvram_size = 0;
10802
10803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10804 tg3_get_5752_nvram_info(tp);
10805 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10806 tg3_get_5755_nvram_info(tp);
10807 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10808 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10809 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10810 tg3_get_5787_nvram_info(tp);
10811 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10812 tg3_get_5761_nvram_info(tp);
10813 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10814 tg3_get_5906_nvram_info(tp);
10815 else
10816 tg3_get_nvram_info(tp);
10817
10818 if (tp->nvram_size == 0)
10819 tg3_get_nvram_size(tp);
10820
10821 tg3_disable_nvram_access(tp);
10822 tg3_nvram_unlock(tp);
10823
10824 } else {
10825 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10826
10827 tg3_get_eeprom_size(tp);
10828 }
10829}
10830
10831static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10832 u32 offset, u32 *val)
10833{
10834 u32 tmp;
10835 int i;
10836
10837 if (offset > EEPROM_ADDR_ADDR_MASK ||
10838 (offset % 4) != 0)
10839 return -EINVAL;
10840
10841 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10842 EEPROM_ADDR_DEVID_MASK |
10843 EEPROM_ADDR_READ);
10844 tw32(GRC_EEPROM_ADDR,
10845 tmp |
10846 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10847 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10848 EEPROM_ADDR_ADDR_MASK) |
10849 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10850
10851 for (i = 0; i < 1000; i++) {
10852 tmp = tr32(GRC_EEPROM_ADDR);
10853
10854 if (tmp & EEPROM_ADDR_COMPLETE)
10855 break;
10856 msleep(1);
10857 }
10858 if (!(tmp & EEPROM_ADDR_COMPLETE))
10859 return -EBUSY;
10860
10861 *val = tr32(GRC_EEPROM_DATA);
10862 return 0;
10863}
10864
10865#define NVRAM_CMD_TIMEOUT 10000
10866
10867static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10868{
10869 int i;
10870
10871 tw32(NVRAM_CMD, nvram_cmd);
10872 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10873 udelay(10);
10874 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10875 udelay(10);
10876 break;
10877 }
10878 }
10879 if (i == NVRAM_CMD_TIMEOUT) {
10880 return -EBUSY;
10881 }
10882 return 0;
10883}
10884
10885static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10886{
10887 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10888 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10889 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10890 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10891 (tp->nvram_jedecnum == JEDEC_ATMEL))
10892
10893 addr = ((addr / tp->nvram_pagesize) <<
10894 ATMEL_AT45DB0X1B_PAGE_POS) +
10895 (addr % tp->nvram_pagesize);
10896
10897 return addr;
10898}
10899
10900static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10901{
10902 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10903 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10904 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10905 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10906 (tp->nvram_jedecnum == JEDEC_ATMEL))
10907
10908 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10909 tp->nvram_pagesize) +
10910 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10911
10912 return addr;
10913}
10914
10915static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10916{
10917 int ret;
10918
10919 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10920 return tg3_nvram_read_using_eeprom(tp, offset, val);
10921
10922 offset = tg3_nvram_phys_addr(tp, offset);
10923
10924 if (offset > NVRAM_ADDR_MSK)
10925 return -EINVAL;
10926
10927 ret = tg3_nvram_lock(tp);
10928 if (ret)
10929 return ret;
10930
10931 tg3_enable_nvram_access(tp);
10932
10933 tw32(NVRAM_ADDR, offset);
10934 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10935 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10936
10937 if (ret == 0)
10938 *val = swab32(tr32(NVRAM_RDDATA));
10939
10940 tg3_disable_nvram_access(tp);
10941
10942 tg3_nvram_unlock(tp);
10943
10944 return ret;
10945}
10946
10947static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10948{
10949 u32 v;
10950 int res = tg3_nvram_read(tp, offset, &v);
10951 if (!res)
10952 *val = cpu_to_le32(v);
10953 return res;
10954}
10955
10956static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10957{
10958 int err;
10959 u32 tmp;
10960
10961 err = tg3_nvram_read(tp, offset, &tmp);
10962 *val = swab32(tmp);
10963 return err;
10964}
10965
10966static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10967 u32 offset, u32 len, u8 *buf)
10968{
10969 int i, j, rc = 0;
10970 u32 val;
10971
10972 for (i = 0; i < len; i += 4) {
10973 u32 addr;
10974 __le32 data;
10975
10976 addr = offset + i;
10977
10978 memcpy(&data, buf + i, 4);
10979
10980 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10981
10982 val = tr32(GRC_EEPROM_ADDR);
10983 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10984
10985 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10986 EEPROM_ADDR_READ);
10987 tw32(GRC_EEPROM_ADDR, val |
10988 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10989 (addr & EEPROM_ADDR_ADDR_MASK) |
10990 EEPROM_ADDR_START |
10991 EEPROM_ADDR_WRITE);
10992
10993 for (j = 0; j < 1000; j++) {
10994 val = tr32(GRC_EEPROM_ADDR);
10995
10996 if (val & EEPROM_ADDR_COMPLETE)
10997 break;
10998 msleep(1);
10999 }
11000 if (!(val & EEPROM_ADDR_COMPLETE)) {
11001 rc = -EBUSY;
11002 break;
11003 }
11004 }
11005
11006 return rc;
11007}
11008
11009/* offset and length are dword aligned */
11010static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11011 u8 *buf)
11012{
11013 int ret = 0;
11014 u32 pagesize = tp->nvram_pagesize;
11015 u32 pagemask = pagesize - 1;
11016 u32 nvram_cmd;
11017 u8 *tmp;
11018
11019 tmp = kmalloc(pagesize, GFP_KERNEL);
11020 if (tmp == NULL)
11021 return -ENOMEM;
11022
11023 while (len) {
11024 int j;
11025 u32 phy_addr, page_off, size;
11026
11027 phy_addr = offset & ~pagemask;
11028
11029 for (j = 0; j < pagesize; j += 4) {
11030 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
11031 (__le32 *) (tmp + j))))
11032 break;
11033 }
11034 if (ret)
11035 break;
11036
11037 page_off = offset & pagemask;
11038 size = pagesize;
11039 if (len < size)
11040 size = len;
11041
11042 len -= size;
11043
11044 memcpy(tmp + page_off, buf, size);
11045
11046 offset = offset + (pagesize - page_off);
11047
11048 tg3_enable_nvram_access(tp);
11049
11050 /*
11051 * Before we can erase the flash page, we need
11052 * to issue a special "write enable" command.
11053 */
11054 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11055
11056 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11057 break;
11058
11059 /* Erase the target page */
11060 tw32(NVRAM_ADDR, phy_addr);
11061
11062 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11063 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11064
11065 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11066 break;
11067
11068 /* Issue another write enable to start the write. */
11069 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11070
11071 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11072 break;
11073
11074 for (j = 0; j < pagesize; j += 4) {
11075 __be32 data;
11076
11077 data = *((__be32 *) (tmp + j));
11078 /* swab32(le32_to_cpu(data)), actually */
11079 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11080
11081 tw32(NVRAM_ADDR, phy_addr + j);
11082
11083 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11084 NVRAM_CMD_WR;
11085
11086 if (j == 0)
11087 nvram_cmd |= NVRAM_CMD_FIRST;
11088 else if (j == (pagesize - 4))
11089 nvram_cmd |= NVRAM_CMD_LAST;
11090
11091 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11092 break;
11093 }
11094 if (ret)
11095 break;
11096 }
11097
11098 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11099 tg3_nvram_exec_cmd(tp, nvram_cmd);
11100
11101 kfree(tmp);
11102
11103 return ret;
11104}
11105
11106/* offset and length are dword aligned */
11107static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11108 u8 *buf)
11109{
11110 int i, ret = 0;
11111
11112 for (i = 0; i < len; i += 4, offset += 4) {
11113 u32 page_off, phy_addr, nvram_cmd;
11114 __be32 data;
11115
11116 memcpy(&data, buf + i, 4);
11117 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11118
11119 page_off = offset % tp->nvram_pagesize;
11120
11121 phy_addr = tg3_nvram_phys_addr(tp, offset);
11122
11123 tw32(NVRAM_ADDR, phy_addr);
11124
11125 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11126
11127 if ((page_off == 0) || (i == 0))
11128 nvram_cmd |= NVRAM_CMD_FIRST;
11129 if (page_off == (tp->nvram_pagesize - 4))
11130 nvram_cmd |= NVRAM_CMD_LAST;
11131
11132 if (i == (len - 4))
11133 nvram_cmd |= NVRAM_CMD_LAST;
11134
11135 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11136 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11137 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11138 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11139 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11140 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11141 (tp->nvram_jedecnum == JEDEC_ST) &&
11142 (nvram_cmd & NVRAM_CMD_FIRST)) {
11143
11144 if ((ret = tg3_nvram_exec_cmd(tp,
11145 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11146 NVRAM_CMD_DONE)))
11147
11148 break;
11149 }
11150 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11151 /* We always do complete word writes to eeprom. */
11152 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11153 }
11154
11155 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11156 break;
11157 }
11158 return ret;
11159}
11160
11161/* offset and length are dword aligned */
11162static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11163{
11164 int ret;
11165
11166 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11167 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11168 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11169 udelay(40);
11170 }
11171
11172 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11173 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11174 }
11175 else {
11176 u32 grc_mode;
11177
11178 ret = tg3_nvram_lock(tp);
11179 if (ret)
11180 return ret;
11181
11182 tg3_enable_nvram_access(tp);
11183 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11184 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11185 tw32(NVRAM_WRITE1, 0x406);
11186
11187 grc_mode = tr32(GRC_MODE);
11188 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11189
11190 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11191 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11192
11193 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11194 buf);
11195 }
11196 else {
11197 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11198 buf);
11199 }
11200
11201 grc_mode = tr32(GRC_MODE);
11202 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11203
11204 tg3_disable_nvram_access(tp);
11205 tg3_nvram_unlock(tp);
11206 }
11207
11208 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11209 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11210 udelay(40);
11211 }
11212
11213 return ret;
11214}
11215
11216struct subsys_tbl_ent {
11217 u16 subsys_vendor, subsys_devid;
11218 u32 phy_id;
11219};
11220
11221static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11222 /* Broadcom boards. */
11223 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11224 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11225 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11226 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11227 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11228 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11229 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11230 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11231 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11232 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11233 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11234
11235 /* 3com boards. */
11236 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11237 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11238 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11239 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11240 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11241
11242 /* DELL boards. */
11243 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11244 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11245 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11246 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11247
11248 /* Compaq boards. */
11249 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11250 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11251 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11252 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11253 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11254
11255 /* IBM boards. */
11256 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11257};
11258
11259static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11260{
11261 int i;
11262
11263 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11264 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11265 tp->pdev->subsystem_vendor) &&
11266 (subsys_id_to_phy_id[i].subsys_devid ==
11267 tp->pdev->subsystem_device))
11268 return &subsys_id_to_phy_id[i];
11269 }
11270 return NULL;
11271}
11272
11273static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11274{
11275 u32 val;
11276 u16 pmcsr;
11277
11278 /* On some early chips the SRAM cannot be accessed in D3hot state,
11279 * so need make sure we're in D0.
11280 */
11281 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11282 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11283 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11284 msleep(1);
11285
11286 /* Make sure register accesses (indirect or otherwise)
11287 * will function correctly.
11288 */
11289 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11290 tp->misc_host_ctrl);
11291
11292 /* The memory arbiter has to be enabled in order for SRAM accesses
11293 * to succeed. Normally on powerup the tg3 chip firmware will make
11294 * sure it is enabled, but other entities such as system netboot
11295 * code might disable it.
11296 */
11297 val = tr32(MEMARB_MODE);
11298 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11299
11300 tp->phy_id = PHY_ID_INVALID;
11301 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11302
11303 /* Assume an onboard device and WOL capable by default. */
11304 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11305
11306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11307 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11308 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11309 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11310 }
11311 val = tr32(VCPU_CFGSHDW);
11312 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11313 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11314 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11315 (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11316 device_may_wakeup(&tp->pdev->dev))
11317 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11318 return;
11319 }
11320
11321 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11322 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11323 u32 nic_cfg, led_cfg;
11324 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11325 int eeprom_phy_serdes = 0;
11326
11327 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11328 tp->nic_sram_data_cfg = nic_cfg;
11329
11330 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11331 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11332 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11333 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11334 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11335 (ver > 0) && (ver < 0x100))
11336 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11337
11338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11339 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11340
11341 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11342 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11343 eeprom_phy_serdes = 1;
11344
11345 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11346 if (nic_phy_id != 0) {
11347 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11348 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11349
11350 eeprom_phy_id = (id1 >> 16) << 10;
11351 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11352 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11353 } else
11354 eeprom_phy_id = 0;
11355
11356 tp->phy_id = eeprom_phy_id;
11357 if (eeprom_phy_serdes) {
11358 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11359 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11360 else
11361 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11362 }
11363
11364 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11365 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11366 SHASTA_EXT_LED_MODE_MASK);
11367 else
11368 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11369
11370 switch (led_cfg) {
11371 default:
11372 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11373 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11374 break;
11375
11376 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11377 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11378 break;
11379
11380 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11381 tp->led_ctrl = LED_CTRL_MODE_MAC;
11382
11383 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11384 * read on some older 5700/5701 bootcode.
11385 */
11386 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11387 ASIC_REV_5700 ||
11388 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11389 ASIC_REV_5701)
11390 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11391
11392 break;
11393
11394 case SHASTA_EXT_LED_SHARED:
11395 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11396 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11397 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11398 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11399 LED_CTRL_MODE_PHY_2);
11400 break;
11401
11402 case SHASTA_EXT_LED_MAC:
11403 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11404 break;
11405
11406 case SHASTA_EXT_LED_COMBO:
11407 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11408 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11409 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11410 LED_CTRL_MODE_PHY_2);
11411 break;
11412
11413 }
11414
11415 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11417 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11418 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11419
11420 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11421 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11422
11423 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11424 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11425 if ((tp->pdev->subsystem_vendor ==
11426 PCI_VENDOR_ID_ARIMA) &&
11427 (tp->pdev->subsystem_device == 0x205a ||
11428 tp->pdev->subsystem_device == 0x2063))
11429 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11430 } else {
11431 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11432 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11433 }
11434
11435 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11436 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11437 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11438 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11439 }
11440 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11441 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11442 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11443 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11444 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11445
11446 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11447 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) &&
11448 device_may_wakeup(&tp->pdev->dev))
11449 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11450
11451 if (cfg2 & (1 << 17))
11452 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11453
11454 /* serdes signal pre-emphasis in register 0x590 set by */
11455 /* bootcode if bit 18 is set */
11456 if (cfg2 & (1 << 18))
11457 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11458
11459 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11460 u32 cfg3;
11461
11462 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11463 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11464 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11465 }
11466
11467 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11468 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11469 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11470 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11471 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11472 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11473 }
11474}
11475
11476static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11477{
11478 int i;
11479 u32 val;
11480
11481 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11482 tw32(OTP_CTRL, cmd);
11483
11484 /* Wait for up to 1 ms for command to execute. */
11485 for (i = 0; i < 100; i++) {
11486 val = tr32(OTP_STATUS);
11487 if (val & OTP_STATUS_CMD_DONE)
11488 break;
11489 udelay(10);
11490 }
11491
11492 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11493}
11494
11495/* Read the gphy configuration from the OTP region of the chip. The gphy
11496 * configuration is a 32-bit value that straddles the alignment boundary.
11497 * We do two 32-bit reads and then shift and merge the results.
11498 */
11499static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11500{
11501 u32 bhalf_otp, thalf_otp;
11502
11503 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11504
11505 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11506 return 0;
11507
11508 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11509
11510 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11511 return 0;
11512
11513 thalf_otp = tr32(OTP_READ_DATA);
11514
11515 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11516
11517 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11518 return 0;
11519
11520 bhalf_otp = tr32(OTP_READ_DATA);
11521
11522 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11523}
11524
11525static int __devinit tg3_phy_probe(struct tg3 *tp)
11526{
11527 u32 hw_phy_id_1, hw_phy_id_2;
11528 u32 hw_phy_id, hw_phy_id_masked;
11529 int err;
11530
11531 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11532 return tg3_phy_init(tp);
11533
11534 /* Reading the PHY ID register can conflict with ASF
11535 * firwmare access to the PHY hardware.
11536 */
11537 err = 0;
11538 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11539 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11540 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11541 } else {
11542 /* Now read the physical PHY_ID from the chip and verify
11543 * that it is sane. If it doesn't look good, we fall back
11544 * to either the hard-coded table based PHY_ID and failing
11545 * that the value found in the eeprom area.
11546 */
11547 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11548 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11549
11550 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11551 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11552 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11553
11554 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11555 }
11556
11557 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11558 tp->phy_id = hw_phy_id;
11559 if (hw_phy_id_masked == PHY_ID_BCM8002)
11560 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11561 else
11562 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11563 } else {
11564 if (tp->phy_id != PHY_ID_INVALID) {
11565 /* Do nothing, phy ID already set up in
11566 * tg3_get_eeprom_hw_cfg().
11567 */
11568 } else {
11569 struct subsys_tbl_ent *p;
11570
11571 /* No eeprom signature? Try the hardcoded
11572 * subsys device table.
11573 */
11574 p = lookup_by_subsys(tp);
11575 if (!p)
11576 return -ENODEV;
11577
11578 tp->phy_id = p->phy_id;
11579 if (!tp->phy_id ||
11580 tp->phy_id == PHY_ID_BCM8002)
11581 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11582 }
11583 }
11584
11585 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11586 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11587 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11588 u32 bmsr, adv_reg, tg3_ctrl, mask;
11589
11590 tg3_readphy(tp, MII_BMSR, &bmsr);
11591 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11592 (bmsr & BMSR_LSTATUS))
11593 goto skip_phy_reset;
11594
11595 err = tg3_phy_reset(tp);
11596 if (err)
11597 return err;
11598
11599 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11600 ADVERTISE_100HALF | ADVERTISE_100FULL |
11601 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11602 tg3_ctrl = 0;
11603 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11604 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11605 MII_TG3_CTRL_ADV_1000_FULL);
11606 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11607 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11608 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11609 MII_TG3_CTRL_ENABLE_AS_MASTER);
11610 }
11611
11612 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11613 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11614 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11615 if (!tg3_copper_is_advertising_all(tp, mask)) {
11616 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11617
11618 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11619 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11620
11621 tg3_writephy(tp, MII_BMCR,
11622 BMCR_ANENABLE | BMCR_ANRESTART);
11623 }
11624 tg3_phy_set_wirespeed(tp);
11625
11626 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11627 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11628 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11629 }
11630
11631skip_phy_reset:
11632 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11633 err = tg3_init_5401phy_dsp(tp);
11634 if (err)
11635 return err;
11636 }
11637
11638 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11639 err = tg3_init_5401phy_dsp(tp);
11640 }
11641
11642 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11643 tp->link_config.advertising =
11644 (ADVERTISED_1000baseT_Half |
11645 ADVERTISED_1000baseT_Full |
11646 ADVERTISED_Autoneg |
11647 ADVERTISED_FIBRE);
11648 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11649 tp->link_config.advertising &=
11650 ~(ADVERTISED_1000baseT_Half |
11651 ADVERTISED_1000baseT_Full);
11652
11653 return err;
11654}
11655
11656static void __devinit tg3_read_partno(struct tg3 *tp)
11657{
11658 unsigned char vpd_data[256];
11659 unsigned int i;
11660 u32 magic;
11661
11662 if (tg3_nvram_read_swab(tp, 0x0, &magic))
11663 goto out_not_found;
11664
11665 if (magic == TG3_EEPROM_MAGIC) {
11666 for (i = 0; i < 256; i += 4) {
11667 u32 tmp;
11668
11669 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11670 goto out_not_found;
11671
11672 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11673 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11674 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11675 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11676 }
11677 } else {
11678 int vpd_cap;
11679
11680 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11681 for (i = 0; i < 256; i += 4) {
11682 u32 tmp, j = 0;
11683 __le32 v;
11684 u16 tmp16;
11685
11686 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11687 i);
11688 while (j++ < 100) {
11689 pci_read_config_word(tp->pdev, vpd_cap +
11690 PCI_VPD_ADDR, &tmp16);
11691 if (tmp16 & 0x8000)
11692 break;
11693 msleep(1);
11694 }
11695 if (!(tmp16 & 0x8000))
11696 goto out_not_found;
11697
11698 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11699 &tmp);
11700 v = cpu_to_le32(tmp);
11701 memcpy(&vpd_data[i], &v, 4);
11702 }
11703 }
11704
11705 /* Now parse and find the part number. */
11706 for (i = 0; i < 254; ) {
11707 unsigned char val = vpd_data[i];
11708 unsigned int block_end;
11709
11710 if (val == 0x82 || val == 0x91) {
11711 i = (i + 3 +
11712 (vpd_data[i + 1] +
11713 (vpd_data[i + 2] << 8)));
11714 continue;
11715 }
11716
11717 if (val != 0x90)
11718 goto out_not_found;
11719
11720 block_end = (i + 3 +
11721 (vpd_data[i + 1] +
11722 (vpd_data[i + 2] << 8)));
11723 i += 3;
11724
11725 if (block_end > 256)
11726 goto out_not_found;
11727
11728 while (i < (block_end - 2)) {
11729 if (vpd_data[i + 0] == 'P' &&
11730 vpd_data[i + 1] == 'N') {
11731 int partno_len = vpd_data[i + 2];
11732
11733 i += 3;
11734 if (partno_len > 24 || (partno_len + i) > 256)
11735 goto out_not_found;
11736
11737 memcpy(tp->board_part_number,
11738 &vpd_data[i], partno_len);
11739
11740 /* Success. */
11741 return;
11742 }
11743 i += 3 + vpd_data[i + 2];
11744 }
11745
11746 /* Part number not found. */
11747 goto out_not_found;
11748 }
11749
11750out_not_found:
11751 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11752 strcpy(tp->board_part_number, "BCM95906");
11753 else
11754 strcpy(tp->board_part_number, "none");
11755}
11756
11757static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11758{
11759 u32 val;
11760
11761 if (tg3_nvram_read_swab(tp, offset, &val) ||
11762 (val & 0xfc000000) != 0x0c000000 ||
11763 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11764 val != 0)
11765 return 0;
11766
11767 return 1;
11768}
11769
11770static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11771{
11772 u32 val, offset, start;
11773 u32 ver_offset;
11774 int i, bcnt;
11775
11776 if (tg3_nvram_read_swab(tp, 0, &val))
11777 return;
11778
11779 if (val != TG3_EEPROM_MAGIC)
11780 return;
11781
11782 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11783 tg3_nvram_read_swab(tp, 0x4, &start))
11784 return;
11785
11786 offset = tg3_nvram_logical_addr(tp, offset);
11787
11788 if (!tg3_fw_img_is_valid(tp, offset) ||
11789 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11790 return;
11791
11792 offset = offset + ver_offset - start;
11793 for (i = 0; i < 16; i += 4) {
11794 __le32 v;
11795 if (tg3_nvram_read_le(tp, offset + i, &v))
11796 return;
11797
11798 memcpy(tp->fw_ver + i, &v, 4);
11799 }
11800
11801 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11802 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11803 return;
11804
11805 for (offset = TG3_NVM_DIR_START;
11806 offset < TG3_NVM_DIR_END;
11807 offset += TG3_NVM_DIRENT_SIZE) {
11808 if (tg3_nvram_read_swab(tp, offset, &val))
11809 return;
11810
11811 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11812 break;
11813 }
11814
11815 if (offset == TG3_NVM_DIR_END)
11816 return;
11817
11818 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11819 start = 0x08000000;
11820 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11821 return;
11822
11823 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11824 !tg3_fw_img_is_valid(tp, offset) ||
11825 tg3_nvram_read_swab(tp, offset + 8, &val))
11826 return;
11827
11828 offset += val - start;
11829
11830 bcnt = strlen(tp->fw_ver);
11831
11832 tp->fw_ver[bcnt++] = ',';
11833 tp->fw_ver[bcnt++] = ' ';
11834
11835 for (i = 0; i < 4; i++) {
11836 __le32 v;
11837 if (tg3_nvram_read_le(tp, offset, &v))
11838 return;
11839
11840 offset += sizeof(v);
11841
11842 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11843 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11844 break;
11845 }
11846
11847 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11848 bcnt += sizeof(v);
11849 }
11850
11851 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11852}
11853
11854static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11855
11856static int __devinit tg3_get_invariants(struct tg3 *tp)
11857{
11858 static struct pci_device_id write_reorder_chipsets[] = {
11859 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11860 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11861 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11862 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11863 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11864 PCI_DEVICE_ID_VIA_8385_0) },
11865 { },
11866 };
11867 u32 misc_ctrl_reg;
11868 u32 cacheline_sz_reg;
11869 u32 pci_state_reg, grc_misc_cfg;
11870 u32 val;
11871 u16 pci_cmd;
11872 int err, pcie_cap;
11873
11874 /* Force memory write invalidate off. If we leave it on,
11875 * then on 5700_BX chips we have to enable a workaround.
11876 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11877 * to match the cacheline size. The Broadcom driver have this
11878 * workaround but turns MWI off all the times so never uses
11879 * it. This seems to suggest that the workaround is insufficient.
11880 */
11881 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11882 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11883 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11884
11885 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11886 * has the register indirect write enable bit set before
11887 * we try to access any of the MMIO registers. It is also
11888 * critical that the PCI-X hw workaround situation is decided
11889 * before that as well.
11890 */
11891 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11892 &misc_ctrl_reg);
11893
11894 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11895 MISC_HOST_CTRL_CHIPREV_SHIFT);
11896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11897 u32 prod_id_asic_rev;
11898
11899 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11900 &prod_id_asic_rev);
11901 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11902 }
11903
11904 /* Wrong chip ID in 5752 A0. This code can be removed later
11905 * as A0 is not in production.
11906 */
11907 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11908 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11909
11910 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11911 * we need to disable memory and use config. cycles
11912 * only to access all registers. The 5702/03 chips
11913 * can mistakenly decode the special cycles from the
11914 * ICH chipsets as memory write cycles, causing corruption
11915 * of register and memory space. Only certain ICH bridges
11916 * will drive special cycles with non-zero data during the
11917 * address phase which can fall within the 5703's address
11918 * range. This is not an ICH bug as the PCI spec allows
11919 * non-zero address during special cycles. However, only
11920 * these ICH bridges are known to drive non-zero addresses
11921 * during special cycles.
11922 *
11923 * Since special cycles do not cross PCI bridges, we only
11924 * enable this workaround if the 5703 is on the secondary
11925 * bus of these ICH bridges.
11926 */
11927 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11928 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11929 static struct tg3_dev_id {
11930 u32 vendor;
11931 u32 device;
11932 u32 rev;
11933 } ich_chipsets[] = {
11934 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11935 PCI_ANY_ID },
11936 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11937 PCI_ANY_ID },
11938 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11939 0xa },
11940 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11941 PCI_ANY_ID },
11942 { },
11943 };
11944 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11945 struct pci_dev *bridge = NULL;
11946
11947 while (pci_id->vendor != 0) {
11948 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11949 bridge);
11950 if (!bridge) {
11951 pci_id++;
11952 continue;
11953 }
11954 if (pci_id->rev != PCI_ANY_ID) {
11955 if (bridge->revision > pci_id->rev)
11956 continue;
11957 }
11958 if (bridge->subordinate &&
11959 (bridge->subordinate->number ==
11960 tp->pdev->bus->number)) {
11961
11962 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11963 pci_dev_put(bridge);
11964 break;
11965 }
11966 }
11967 }
11968
11969 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11970 static struct tg3_dev_id {
11971 u32 vendor;
11972 u32 device;
11973 } bridge_chipsets[] = {
11974 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11975 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11976 { },
11977 };
11978 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11979 struct pci_dev *bridge = NULL;
11980
11981 while (pci_id->vendor != 0) {
11982 bridge = pci_get_device(pci_id->vendor,
11983 pci_id->device,
11984 bridge);
11985 if (!bridge) {
11986 pci_id++;
11987 continue;
11988 }
11989 if (bridge->subordinate &&
11990 (bridge->subordinate->number <=
11991 tp->pdev->bus->number) &&
11992 (bridge->subordinate->subordinate >=
11993 tp->pdev->bus->number)) {
11994 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11995 pci_dev_put(bridge);
11996 break;
11997 }
11998 }
11999 }
12000
12001 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12002 * DMA addresses > 40-bit. This bridge may have other additional
12003 * 57xx devices behind it in some 4-port NIC designs for example.
12004 * Any tg3 device found behind the bridge will also need the 40-bit
12005 * DMA workaround.
12006 */
12007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12009 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12010 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12011 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12012 }
12013 else {
12014 struct pci_dev *bridge = NULL;
12015
12016 do {
12017 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12018 PCI_DEVICE_ID_SERVERWORKS_EPB,
12019 bridge);
12020 if (bridge && bridge->subordinate &&
12021 (bridge->subordinate->number <=
12022 tp->pdev->bus->number) &&
12023 (bridge->subordinate->subordinate >=
12024 tp->pdev->bus->number)) {
12025 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12026 pci_dev_put(bridge);
12027 break;
12028 }
12029 } while (bridge);
12030 }
12031
12032 /* Initialize misc host control in PCI block. */
12033 tp->misc_host_ctrl |= (misc_ctrl_reg &
12034 MISC_HOST_CTRL_CHIPREV);
12035 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12036 tp->misc_host_ctrl);
12037
12038 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12039 &cacheline_sz_reg);
12040
12041 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
12042 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
12043 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
12044 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
12045
12046 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12047 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12048 tp->pdev_peer = tg3_find_peer(tp);
12049
12050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12058 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12059 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12060
12061 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12062 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12063 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12064
12065 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12066 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12067 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12068 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12069 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12070 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12071 tp->pdev_peer == tp->pdev))
12072 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12073
12074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12080 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12081 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12082 } else {
12083 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12084 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12085 ASIC_REV_5750 &&
12086 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12087 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12088 }
12089 }
12090
12091 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12092 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12093 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12094
12095 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12096 if (pcie_cap != 0) {
12097 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12098
12099 pcie_set_readrq(tp->pdev, 4096);
12100
12101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12102 u16 lnkctl;
12103
12104 pci_read_config_word(tp->pdev,
12105 pcie_cap + PCI_EXP_LNKCTL,
12106 &lnkctl);
12107 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
12108 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12109 }
12110 }
12111
12112 /* If we have an AMD 762 or VIA K8T800 chipset, write
12113 * reordering to the mailbox registers done by the host
12114 * controller can cause major troubles. We read back from
12115 * every mailbox register write to force the writes to be
12116 * posted to the chip in order.
12117 */
12118 if (pci_dev_present(write_reorder_chipsets) &&
12119 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12120 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12121
12122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12123 tp->pci_lat_timer < 64) {
12124 tp->pci_lat_timer = 64;
12125
12126 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
12127 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
12128 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
12129 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
12130
12131 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12132 cacheline_sz_reg);
12133 }
12134
12135 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12136 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12137 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12138 if (!tp->pcix_cap) {
12139 printk(KERN_ERR PFX "Cannot find PCI-X "
12140 "capability, aborting.\n");
12141 return -EIO;
12142 }
12143 }
12144
12145 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12146 &pci_state_reg);
12147
12148 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12149 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12150
12151 /* If this is a 5700 BX chipset, and we are in PCI-X
12152 * mode, enable register write workaround.
12153 *
12154 * The workaround is to use indirect register accesses
12155 * for all chip writes not to mailbox registers.
12156 */
12157 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12158 u32 pm_reg;
12159
12160 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12161
12162 /* The chip can have it's power management PCI config
12163 * space registers clobbered due to this bug.
12164 * So explicitly force the chip into D0 here.
12165 */
12166 pci_read_config_dword(tp->pdev,
12167 tp->pm_cap + PCI_PM_CTRL,
12168 &pm_reg);
12169 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12170 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12171 pci_write_config_dword(tp->pdev,
12172 tp->pm_cap + PCI_PM_CTRL,
12173 pm_reg);
12174
12175 /* Also, force SERR#/PERR# in PCI command. */
12176 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12177 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12178 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12179 }
12180 }
12181
12182 /* 5700 BX chips need to have their TX producer index mailboxes
12183 * written twice to workaround a bug.
12184 */
12185 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12186 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12187
12188 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12189 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12190 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12191 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12192
12193 /* Chip-specific fixup from Broadcom driver */
12194 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12195 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12196 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12197 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12198 }
12199
12200 /* Default fast path register access methods */
12201 tp->read32 = tg3_read32;
12202 tp->write32 = tg3_write32;
12203 tp->read32_mbox = tg3_read32;
12204 tp->write32_mbox = tg3_write32;
12205 tp->write32_tx_mbox = tg3_write32;
12206 tp->write32_rx_mbox = tg3_write32;
12207
12208 /* Various workaround register access methods */
12209 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12210 tp->write32 = tg3_write_indirect_reg32;
12211 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12212 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12213 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12214 /*
12215 * Back to back register writes can cause problems on these
12216 * chips, the workaround is to read back all reg writes
12217 * except those to mailbox regs.
12218 *
12219 * See tg3_write_indirect_reg32().
12220 */
12221 tp->write32 = tg3_write_flush_reg32;
12222 }
12223
12224
12225 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12226 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12227 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12228 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12229 tp->write32_rx_mbox = tg3_write_flush_reg32;
12230 }
12231
12232 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12233 tp->read32 = tg3_read_indirect_reg32;
12234 tp->write32 = tg3_write_indirect_reg32;
12235 tp->read32_mbox = tg3_read_indirect_mbox;
12236 tp->write32_mbox = tg3_write_indirect_mbox;
12237 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12238 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12239
12240 iounmap(tp->regs);
12241 tp->regs = NULL;
12242
12243 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12244 pci_cmd &= ~PCI_COMMAND_MEMORY;
12245 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12246 }
12247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12248 tp->read32_mbox = tg3_read32_mbox_5906;
12249 tp->write32_mbox = tg3_write32_mbox_5906;
12250 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12251 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12252 }
12253
12254 if (tp->write32 == tg3_write_indirect_reg32 ||
12255 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12256 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12257 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12258 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12259
12260 /* Get eeprom hw config before calling tg3_set_power_state().
12261 * In particular, the TG3_FLG2_IS_NIC flag must be
12262 * determined before calling tg3_set_power_state() so that
12263 * we know whether or not to switch out of Vaux power.
12264 * When the flag is set, it means that GPIO1 is used for eeprom
12265 * write protect and also implies that it is a LOM where GPIOs
12266 * are not used to switch power.
12267 */
12268 tg3_get_eeprom_hw_cfg(tp);
12269
12270 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12271 /* Allow reads and writes to the
12272 * APE register and memory space.
12273 */
12274 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12275 PCISTATE_ALLOW_APE_SHMEM_WR;
12276 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12277 pci_state_reg);
12278 }
12279
12280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12281 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12283 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12284
12285 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12286 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12287 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12288 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12289 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12290 }
12291
12292 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12293 * GPIO1 driven high will bring 5700's external PHY out of reset.
12294 * It is also used as eeprom write protect on LOMs.
12295 */
12296 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12297 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12298 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12299 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12300 GRC_LCLCTRL_GPIO_OUTPUT1);
12301 /* Unused GPIO3 must be driven as output on 5752 because there
12302 * are no pull-up resistors on unused GPIO pins.
12303 */
12304 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12305 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12306
12307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12308 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12309
12310 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12311 /* Turn off the debug UART. */
12312 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12313 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12314 /* Keep VMain power. */
12315 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12316 GRC_LCLCTRL_GPIO_OUTPUT0;
12317 }
12318
12319 /* Force the chip into D0. */
12320 err = tg3_set_power_state(tp, PCI_D0);
12321 if (err) {
12322 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12323 pci_name(tp->pdev));
12324 return err;
12325 }
12326
12327 /* 5700 B0 chips do not support checksumming correctly due
12328 * to hardware bugs.
12329 */
12330 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12331 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12332
12333 /* Derive initial jumbo mode from MTU assigned in
12334 * ether_setup() via the alloc_etherdev() call
12335 */
12336 if (tp->dev->mtu > ETH_DATA_LEN &&
12337 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12338 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12339
12340 /* Determine WakeOnLan speed to use. */
12341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12342 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12343 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12344 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12345 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12346 } else {
12347 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12348 }
12349
12350 /* A few boards don't want Ethernet@WireSpeed phy feature */
12351 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12352 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12353 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12354 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12355 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12356 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12357 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12358
12359 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12360 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12361 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12362 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12363 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12364
12365 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12366 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12369 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12370 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12371 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12372 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12373 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12374 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12375 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12376 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12377 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12378 }
12379
12380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12381 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12382 tp->phy_otp = tg3_read_otp_phycfg(tp);
12383 if (tp->phy_otp == 0)
12384 tp->phy_otp = TG3_OTP_DEFAULT;
12385 }
12386
12387 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12388 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12389 else
12390 tp->mi_mode = MAC_MI_MODE_BASE;
12391
12392 tp->coalesce_mode = 0;
12393 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12394 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12395 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12396
12397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12398 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12399
12400 err = tg3_mdio_init(tp);
12401 if (err)
12402 return err;
12403
12404 /* Initialize data/descriptor byte/word swapping. */
12405 val = tr32(GRC_MODE);
12406 val &= GRC_MODE_HOST_STACKUP;
12407 tw32(GRC_MODE, val | tp->grc_mode);
12408
12409 tg3_switch_clocks(tp);
12410
12411 /* Clear this out for sanity. */
12412 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12413
12414 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12415 &pci_state_reg);
12416 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12417 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12418 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12419
12420 if (chiprevid == CHIPREV_ID_5701_A0 ||
12421 chiprevid == CHIPREV_ID_5701_B0 ||
12422 chiprevid == CHIPREV_ID_5701_B2 ||
12423 chiprevid == CHIPREV_ID_5701_B5) {
12424 void __iomem *sram_base;
12425
12426 /* Write some dummy words into the SRAM status block
12427 * area, see if it reads back correctly. If the return
12428 * value is bad, force enable the PCIX workaround.
12429 */
12430 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12431
12432 writel(0x00000000, sram_base);
12433 writel(0x00000000, sram_base + 4);
12434 writel(0xffffffff, sram_base + 4);
12435 if (readl(sram_base) != 0x00000000)
12436 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12437 }
12438 }
12439
12440 udelay(50);
12441 tg3_nvram_init(tp);
12442
12443 grc_misc_cfg = tr32(GRC_MISC_CFG);
12444 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12445
12446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12447 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12448 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12449 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12450
12451 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12452 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12453 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12454 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12455 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12456 HOSTCC_MODE_CLRTICK_TXBD);
12457
12458 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12459 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12460 tp->misc_host_ctrl);
12461 }
12462
12463 /* Preserve the APE MAC_MODE bits */
12464 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12465 tp->mac_mode = tr32(MAC_MODE) |
12466 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12467 else
12468 tp->mac_mode = TG3_DEF_MAC_MODE;
12469
12470 /* these are limited to 10/100 only */
12471 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12472 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12473 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12474 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12475 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12476 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12477 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12478 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12479 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12480 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12481 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12483 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12484
12485 err = tg3_phy_probe(tp);
12486 if (err) {
12487 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12488 pci_name(tp->pdev), err);
12489 /* ... but do not return immediately ... */
12490 tg3_mdio_fini(tp);
12491 }
12492
12493 tg3_read_partno(tp);
12494 tg3_read_fw_ver(tp);
12495
12496 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12497 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12498 } else {
12499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12500 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12501 else
12502 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12503 }
12504
12505 /* 5700 {AX,BX} chips have a broken status block link
12506 * change bit implementation, so we must use the
12507 * status register in those cases.
12508 */
12509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12510 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12511 else
12512 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12513
12514 /* The led_ctrl is set during tg3_phy_probe, here we might
12515 * have to force the link status polling mechanism based
12516 * upon subsystem IDs.
12517 */
12518 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12519 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12520 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12521 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12522 TG3_FLAG_USE_LINKCHG_REG);
12523 }
12524
12525 /* For all SERDES we poll the MAC status register. */
12526 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12527 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12528 else
12529 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12530
12531 /* All chips before 5787 can get confused if TX buffers
12532 * straddle the 4GB address boundary in some cases.
12533 */
12534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12539 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12540 tp->dev->hard_start_xmit = tg3_start_xmit;
12541 else
12542 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12543
12544 tp->rx_offset = 2;
12545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12546 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12547 tp->rx_offset = 0;
12548
12549 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12550
12551 /* Increment the rx prod index on the rx std ring by at most
12552 * 8 for these chips to workaround hw errata.
12553 */
12554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12555 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12556 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12557 tp->rx_std_max_post = 8;
12558
12559 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12560 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12561 PCIE_PWR_MGMT_L1_THRESH_MSK;
12562
12563 return err;
12564}
12565
12566#ifdef CONFIG_SPARC
12567static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12568{
12569 struct net_device *dev = tp->dev;
12570 struct pci_dev *pdev = tp->pdev;
12571 struct device_node *dp = pci_device_to_OF_node(pdev);
12572 const unsigned char *addr;
12573 int len;
12574
12575 addr = of_get_property(dp, "local-mac-address", &len);
12576 if (addr && len == 6) {
12577 memcpy(dev->dev_addr, addr, 6);
12578 memcpy(dev->perm_addr, dev->dev_addr, 6);
12579 return 0;
12580 }
12581 return -ENODEV;
12582}
12583
12584static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12585{
12586 struct net_device *dev = tp->dev;
12587
12588 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12589 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12590 return 0;
12591}
12592#endif
12593
12594static int __devinit tg3_get_device_address(struct tg3 *tp)
12595{
12596 struct net_device *dev = tp->dev;
12597 u32 hi, lo, mac_offset;
12598 int addr_ok = 0;
12599
12600#ifdef CONFIG_SPARC
12601 if (!tg3_get_macaddr_sparc(tp))
12602 return 0;
12603#endif
12604
12605 mac_offset = 0x7c;
12606 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12607 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12608 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12609 mac_offset = 0xcc;
12610 if (tg3_nvram_lock(tp))
12611 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12612 else
12613 tg3_nvram_unlock(tp);
12614 }
12615 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12616 mac_offset = 0x10;
12617
12618 /* First try to get it from MAC address mailbox. */
12619 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12620 if ((hi >> 16) == 0x484b) {
12621 dev->dev_addr[0] = (hi >> 8) & 0xff;
12622 dev->dev_addr[1] = (hi >> 0) & 0xff;
12623
12624 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12625 dev->dev_addr[2] = (lo >> 24) & 0xff;
12626 dev->dev_addr[3] = (lo >> 16) & 0xff;
12627 dev->dev_addr[4] = (lo >> 8) & 0xff;
12628 dev->dev_addr[5] = (lo >> 0) & 0xff;
12629
12630 /* Some old bootcode may report a 0 MAC address in SRAM */
12631 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12632 }
12633 if (!addr_ok) {
12634 /* Next, try NVRAM. */
12635 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12636 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12637 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12638 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12639 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12640 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12641 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12642 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12643 }
12644 /* Finally just fetch it out of the MAC control regs. */
12645 else {
12646 hi = tr32(MAC_ADDR_0_HIGH);
12647 lo = tr32(MAC_ADDR_0_LOW);
12648
12649 dev->dev_addr[5] = lo & 0xff;
12650 dev->dev_addr[4] = (lo >> 8) & 0xff;
12651 dev->dev_addr[3] = (lo >> 16) & 0xff;
12652 dev->dev_addr[2] = (lo >> 24) & 0xff;
12653 dev->dev_addr[1] = hi & 0xff;
12654 dev->dev_addr[0] = (hi >> 8) & 0xff;
12655 }
12656 }
12657
12658 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12659#ifdef CONFIG_SPARC
12660 if (!tg3_get_default_macaddr_sparc(tp))
12661 return 0;
12662#endif
12663 return -EINVAL;
12664 }
12665 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12666 return 0;
12667}
12668
12669#define BOUNDARY_SINGLE_CACHELINE 1
12670#define BOUNDARY_MULTI_CACHELINE 2
12671
12672static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12673{
12674 int cacheline_size;
12675 u8 byte;
12676 int goal;
12677
12678 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12679 if (byte == 0)
12680 cacheline_size = 1024;
12681 else
12682 cacheline_size = (int) byte * 4;
12683
12684 /* On 5703 and later chips, the boundary bits have no
12685 * effect.
12686 */
12687 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12688 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12689 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12690 goto out;
12691
12692#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12693 goal = BOUNDARY_MULTI_CACHELINE;
12694#else
12695#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12696 goal = BOUNDARY_SINGLE_CACHELINE;
12697#else
12698 goal = 0;
12699#endif
12700#endif
12701
12702 if (!goal)
12703 goto out;
12704
12705 /* PCI controllers on most RISC systems tend to disconnect
12706 * when a device tries to burst across a cache-line boundary.
12707 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12708 *
12709 * Unfortunately, for PCI-E there are only limited
12710 * write-side controls for this, and thus for reads
12711 * we will still get the disconnects. We'll also waste
12712 * these PCI cycles for both read and write for chips
12713 * other than 5700 and 5701 which do not implement the
12714 * boundary bits.
12715 */
12716 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12717 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12718 switch (cacheline_size) {
12719 case 16:
12720 case 32:
12721 case 64:
12722 case 128:
12723 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12724 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12725 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12726 } else {
12727 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12728 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12729 }
12730 break;
12731
12732 case 256:
12733 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12734 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12735 break;
12736
12737 default:
12738 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12739 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12740 break;
12741 }
12742 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12743 switch (cacheline_size) {
12744 case 16:
12745 case 32:
12746 case 64:
12747 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12748 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12749 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12750 break;
12751 }
12752 /* fallthrough */
12753 case 128:
12754 default:
12755 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12756 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12757 break;
12758 }
12759 } else {
12760 switch (cacheline_size) {
12761 case 16:
12762 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12763 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12764 DMA_RWCTRL_WRITE_BNDRY_16);
12765 break;
12766 }
12767 /* fallthrough */
12768 case 32:
12769 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12770 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12771 DMA_RWCTRL_WRITE_BNDRY_32);
12772 break;
12773 }
12774 /* fallthrough */
12775 case 64:
12776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12777 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12778 DMA_RWCTRL_WRITE_BNDRY_64);
12779 break;
12780 }
12781 /* fallthrough */
12782 case 128:
12783 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12784 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12785 DMA_RWCTRL_WRITE_BNDRY_128);
12786 break;
12787 }
12788 /* fallthrough */
12789 case 256:
12790 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12791 DMA_RWCTRL_WRITE_BNDRY_256);
12792 break;
12793 case 512:
12794 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12795 DMA_RWCTRL_WRITE_BNDRY_512);
12796 break;
12797 case 1024:
12798 default:
12799 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12800 DMA_RWCTRL_WRITE_BNDRY_1024);
12801 break;
12802 }
12803 }
12804
12805out:
12806 return val;
12807}
12808
12809static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12810{
12811 struct tg3_internal_buffer_desc test_desc;
12812 u32 sram_dma_descs;
12813 int i, ret;
12814
12815 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12816
12817 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12818 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12819 tw32(RDMAC_STATUS, 0);
12820 tw32(WDMAC_STATUS, 0);
12821
12822 tw32(BUFMGR_MODE, 0);
12823 tw32(FTQ_RESET, 0);
12824
12825 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12826 test_desc.addr_lo = buf_dma & 0xffffffff;
12827 test_desc.nic_mbuf = 0x00002100;
12828 test_desc.len = size;
12829
12830 /*
12831 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12832 * the *second* time the tg3 driver was getting loaded after an
12833 * initial scan.
12834 *
12835 * Broadcom tells me:
12836 * ...the DMA engine is connected to the GRC block and a DMA
12837 * reset may affect the GRC block in some unpredictable way...
12838 * The behavior of resets to individual blocks has not been tested.
12839 *
12840 * Broadcom noted the GRC reset will also reset all sub-components.
12841 */
12842 if (to_device) {
12843 test_desc.cqid_sqid = (13 << 8) | 2;
12844
12845 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12846 udelay(40);
12847 } else {
12848 test_desc.cqid_sqid = (16 << 8) | 7;
12849
12850 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12851 udelay(40);
12852 }
12853 test_desc.flags = 0x00000005;
12854
12855 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12856 u32 val;
12857
12858 val = *(((u32 *)&test_desc) + i);
12859 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12860 sram_dma_descs + (i * sizeof(u32)));
12861 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12862 }
12863 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12864
12865 if (to_device) {
12866 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12867 } else {
12868 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12869 }
12870
12871 ret = -ENODEV;
12872 for (i = 0; i < 40; i++) {
12873 u32 val;
12874
12875 if (to_device)
12876 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12877 else
12878 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12879 if ((val & 0xffff) == sram_dma_descs) {
12880 ret = 0;
12881 break;
12882 }
12883
12884 udelay(100);
12885 }
12886
12887 return ret;
12888}
12889
12890#define TEST_BUFFER_SIZE 0x2000
12891
12892static int __devinit tg3_test_dma(struct tg3 *tp)
12893{
12894 dma_addr_t buf_dma;
12895 u32 *buf, saved_dma_rwctrl;
12896 int ret;
12897
12898 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12899 if (!buf) {
12900 ret = -ENOMEM;
12901 goto out_nofree;
12902 }
12903
12904 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12905 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12906
12907 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12908
12909 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12910 /* DMA read watermark not used on PCIE */
12911 tp->dma_rwctrl |= 0x00180000;
12912 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12915 tp->dma_rwctrl |= 0x003f0000;
12916 else
12917 tp->dma_rwctrl |= 0x003f000f;
12918 } else {
12919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12921 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12922 u32 read_water = 0x7;
12923
12924 /* If the 5704 is behind the EPB bridge, we can
12925 * do the less restrictive ONE_DMA workaround for
12926 * better performance.
12927 */
12928 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12930 tp->dma_rwctrl |= 0x8000;
12931 else if (ccval == 0x6 || ccval == 0x7)
12932 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12933
12934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12935 read_water = 4;
12936 /* Set bit 23 to enable PCIX hw bug fix */
12937 tp->dma_rwctrl |=
12938 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12939 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12940 (1 << 23);
12941 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12942 /* 5780 always in PCIX mode */
12943 tp->dma_rwctrl |= 0x00144000;
12944 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12945 /* 5714 always in PCIX mode */
12946 tp->dma_rwctrl |= 0x00148000;
12947 } else {
12948 tp->dma_rwctrl |= 0x001b000f;
12949 }
12950 }
12951
12952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12954 tp->dma_rwctrl &= 0xfffffff0;
12955
12956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12957 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12958 /* Remove this if it causes problems for some boards. */
12959 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12960
12961 /* On 5700/5701 chips, we need to set this bit.
12962 * Otherwise the chip will issue cacheline transactions
12963 * to streamable DMA memory with not all the byte
12964 * enables turned on. This is an error on several
12965 * RISC PCI controllers, in particular sparc64.
12966 *
12967 * On 5703/5704 chips, this bit has been reassigned
12968 * a different meaning. In particular, it is used
12969 * on those chips to enable a PCI-X workaround.
12970 */
12971 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12972 }
12973
12974 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12975
12976#if 0
12977 /* Unneeded, already done by tg3_get_invariants. */
12978 tg3_switch_clocks(tp);
12979#endif
12980
12981 ret = 0;
12982 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12983 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12984 goto out;
12985
12986 /* It is best to perform DMA test with maximum write burst size
12987 * to expose the 5700/5701 write DMA bug.
12988 */
12989 saved_dma_rwctrl = tp->dma_rwctrl;
12990 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12991 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12992
12993 while (1) {
12994 u32 *p = buf, i;
12995
12996 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12997 p[i] = i;
12998
12999 /* Send the buffer to the chip. */
13000 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13001 if (ret) {
13002 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13003 break;
13004 }
13005
13006#if 0
13007 /* validate data reached card RAM correctly. */
13008 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13009 u32 val;
13010 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13011 if (le32_to_cpu(val) != p[i]) {
13012 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13013 /* ret = -ENODEV here? */
13014 }
13015 p[i] = 0;
13016 }
13017#endif
13018 /* Now read it back. */
13019 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13020 if (ret) {
13021 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13022
13023 break;
13024 }
13025
13026 /* Verify it. */
13027 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13028 if (p[i] == i)
13029 continue;
13030
13031 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13032 DMA_RWCTRL_WRITE_BNDRY_16) {
13033 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13034 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13035 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13036 break;
13037 } else {
13038 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13039 ret = -ENODEV;
13040 goto out;
13041 }
13042 }
13043
13044 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13045 /* Success. */
13046 ret = 0;
13047 break;
13048 }
13049 }
13050 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13051 DMA_RWCTRL_WRITE_BNDRY_16) {
13052 static struct pci_device_id dma_wait_state_chipsets[] = {
13053 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13054 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13055 { },
13056 };
13057
13058 /* DMA test passed without adjusting DMA boundary,
13059 * now look for chipsets that are known to expose the
13060 * DMA bug without failing the test.
13061 */
13062 if (pci_dev_present(dma_wait_state_chipsets)) {
13063 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13064 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13065 }
13066 else
13067 /* Safe to use the calculated DMA boundary. */
13068 tp->dma_rwctrl = saved_dma_rwctrl;
13069
13070 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13071 }
13072
13073out:
13074 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13075out_nofree:
13076 return ret;
13077}
13078
13079static void __devinit tg3_init_link_config(struct tg3 *tp)
13080{
13081 tp->link_config.advertising =
13082 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13083 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13084 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13085 ADVERTISED_Autoneg | ADVERTISED_MII);
13086 tp->link_config.speed = SPEED_INVALID;
13087 tp->link_config.duplex = DUPLEX_INVALID;
13088 tp->link_config.autoneg = AUTONEG_ENABLE;
13089 tp->link_config.active_speed = SPEED_INVALID;
13090 tp->link_config.active_duplex = DUPLEX_INVALID;
13091 tp->link_config.phy_is_low_power = 0;
13092 tp->link_config.orig_speed = SPEED_INVALID;
13093 tp->link_config.orig_duplex = DUPLEX_INVALID;
13094 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13095}
13096
13097static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13098{
13099 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13100 tp->bufmgr_config.mbuf_read_dma_low_water =
13101 DEFAULT_MB_RDMA_LOW_WATER_5705;
13102 tp->bufmgr_config.mbuf_mac_rx_low_water =
13103 DEFAULT_MB_MACRX_LOW_WATER_5705;
13104 tp->bufmgr_config.mbuf_high_water =
13105 DEFAULT_MB_HIGH_WATER_5705;
13106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13107 tp->bufmgr_config.mbuf_mac_rx_low_water =
13108 DEFAULT_MB_MACRX_LOW_WATER_5906;
13109 tp->bufmgr_config.mbuf_high_water =
13110 DEFAULT_MB_HIGH_WATER_5906;
13111 }
13112
13113 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13114 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13115 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13116 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13117 tp->bufmgr_config.mbuf_high_water_jumbo =
13118 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13119 } else {
13120 tp->bufmgr_config.mbuf_read_dma_low_water =
13121 DEFAULT_MB_RDMA_LOW_WATER;
13122 tp->bufmgr_config.mbuf_mac_rx_low_water =
13123 DEFAULT_MB_MACRX_LOW_WATER;
13124 tp->bufmgr_config.mbuf_high_water =
13125 DEFAULT_MB_HIGH_WATER;
13126
13127 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13128 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13129 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13130 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13131 tp->bufmgr_config.mbuf_high_water_jumbo =
13132 DEFAULT_MB_HIGH_WATER_JUMBO;
13133 }
13134
13135 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13136 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13137}
13138
13139static char * __devinit tg3_phy_string(struct tg3 *tp)
13140{
13141 switch (tp->phy_id & PHY_ID_MASK) {
13142 case PHY_ID_BCM5400: return "5400";
13143 case PHY_ID_BCM5401: return "5401";
13144 case PHY_ID_BCM5411: return "5411";
13145 case PHY_ID_BCM5701: return "5701";
13146 case PHY_ID_BCM5703: return "5703";
13147 case PHY_ID_BCM5704: return "5704";
13148 case PHY_ID_BCM5705: return "5705";
13149 case PHY_ID_BCM5750: return "5750";
13150 case PHY_ID_BCM5752: return "5752";
13151 case PHY_ID_BCM5714: return "5714";
13152 case PHY_ID_BCM5780: return "5780";
13153 case PHY_ID_BCM5755: return "5755";
13154 case PHY_ID_BCM5787: return "5787";
13155 case PHY_ID_BCM5784: return "5784";
13156 case PHY_ID_BCM5756: return "5722/5756";
13157 case PHY_ID_BCM5906: return "5906";
13158 case PHY_ID_BCM5761: return "5761";
13159 case PHY_ID_BCM8002: return "8002/serdes";
13160 case 0: return "serdes";
13161 default: return "unknown";
13162 }
13163}
13164
13165static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13166{
13167 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13168 strcpy(str, "PCI Express");
13169 return str;
13170 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13171 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13172
13173 strcpy(str, "PCIX:");
13174
13175 if ((clock_ctrl == 7) ||
13176 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13177 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13178 strcat(str, "133MHz");
13179 else if (clock_ctrl == 0)
13180 strcat(str, "33MHz");
13181 else if (clock_ctrl == 2)
13182 strcat(str, "50MHz");
13183 else if (clock_ctrl == 4)
13184 strcat(str, "66MHz");
13185 else if (clock_ctrl == 6)
13186 strcat(str, "100MHz");
13187 } else {
13188 strcpy(str, "PCI:");
13189 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13190 strcat(str, "66MHz");
13191 else
13192 strcat(str, "33MHz");
13193 }
13194 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13195 strcat(str, ":32-bit");
13196 else
13197 strcat(str, ":64-bit");
13198 return str;
13199}
13200
13201static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13202{
13203 struct pci_dev *peer;
13204 unsigned int func, devnr = tp->pdev->devfn & ~7;
13205
13206 for (func = 0; func < 8; func++) {
13207 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13208 if (peer && peer != tp->pdev)
13209 break;
13210 pci_dev_put(peer);
13211 }
13212 /* 5704 can be configured in single-port mode, set peer to
13213 * tp->pdev in that case.
13214 */
13215 if (!peer) {
13216 peer = tp->pdev;
13217 return peer;
13218 }
13219
13220 /*
13221 * We don't need to keep the refcount elevated; there's no way
13222 * to remove one half of this device without removing the other
13223 */
13224 pci_dev_put(peer);
13225
13226 return peer;
13227}
13228
13229static void __devinit tg3_init_coal(struct tg3 *tp)
13230{
13231 struct ethtool_coalesce *ec = &tp->coal;
13232
13233 memset(ec, 0, sizeof(*ec));
13234 ec->cmd = ETHTOOL_GCOALESCE;
13235 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13236 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13237 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13238 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13239 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13240 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13241 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13242 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13243 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13244
13245 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13246 HOSTCC_MODE_CLRTICK_TXBD)) {
13247 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13248 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13249 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13250 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13251 }
13252
13253 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13254 ec->rx_coalesce_usecs_irq = 0;
13255 ec->tx_coalesce_usecs_irq = 0;
13256 ec->stats_block_coalesce_usecs = 0;
13257 }
13258}
13259
13260static int __devinit tg3_init_one(struct pci_dev *pdev,
13261 const struct pci_device_id *ent)
13262{
13263 static int tg3_version_printed = 0;
13264 resource_size_t tg3reg_base;
13265 unsigned long tg3reg_len;
13266 struct net_device *dev;
13267 struct tg3 *tp;
13268 int err, pm_cap;
13269 char str[40];
13270 u64 dma_mask, persist_dma_mask;
13271 DECLARE_MAC_BUF(mac);
13272
13273 if (tg3_version_printed++ == 0)
13274 printk(KERN_INFO "%s", version);
13275
13276 err = pci_enable_device(pdev);
13277 if (err) {
13278 printk(KERN_ERR PFX "Cannot enable PCI device, "
13279 "aborting.\n");
13280 return err;
13281 }
13282
13283 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13284 printk(KERN_ERR PFX "Cannot find proper PCI device "
13285 "base address, aborting.\n");
13286 err = -ENODEV;
13287 goto err_out_disable_pdev;
13288 }
13289
13290 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13291 if (err) {
13292 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13293 "aborting.\n");
13294 goto err_out_disable_pdev;
13295 }
13296
13297 pci_set_master(pdev);
13298
13299 /* Find power-management capability. */
13300 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13301 if (pm_cap == 0) {
13302 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13303 "aborting.\n");
13304 err = -EIO;
13305 goto err_out_free_res;
13306 }
13307
13308 tg3reg_base = pci_resource_start(pdev, 0);
13309 tg3reg_len = pci_resource_len(pdev, 0);
13310
13311 dev = alloc_etherdev(sizeof(*tp));
13312 if (!dev) {
13313 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13314 err = -ENOMEM;
13315 goto err_out_free_res;
13316 }
13317
13318 SET_NETDEV_DEV(dev, &pdev->dev);
13319
13320#if TG3_VLAN_TAG_USED
13321 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13322 dev->vlan_rx_register = tg3_vlan_rx_register;
13323#endif
13324
13325 tp = netdev_priv(dev);
13326 tp->pdev = pdev;
13327 tp->dev = dev;
13328 tp->pm_cap = pm_cap;
13329 tp->rx_mode = TG3_DEF_RX_MODE;
13330 tp->tx_mode = TG3_DEF_TX_MODE;
13331
13332 if (tg3_debug > 0)
13333 tp->msg_enable = tg3_debug;
13334 else
13335 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13336
13337 /* The word/byte swap controls here control register access byte
13338 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13339 * setting below.
13340 */
13341 tp->misc_host_ctrl =
13342 MISC_HOST_CTRL_MASK_PCI_INT |
13343 MISC_HOST_CTRL_WORD_SWAP |
13344 MISC_HOST_CTRL_INDIR_ACCESS |
13345 MISC_HOST_CTRL_PCISTATE_RW;
13346
13347 /* The NONFRM (non-frame) byte/word swap controls take effect
13348 * on descriptor entries, anything which isn't packet data.
13349 *
13350 * The StrongARM chips on the board (one for tx, one for rx)
13351 * are running in big-endian mode.
13352 */
13353 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13354 GRC_MODE_WSWAP_NONFRM_DATA);
13355#ifdef __BIG_ENDIAN
13356 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13357#endif
13358 spin_lock_init(&tp->lock);
13359 spin_lock_init(&tp->indirect_lock);
13360 INIT_WORK(&tp->reset_task, tg3_reset_task);
13361
13362 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13363 if (!tp->regs) {
13364 printk(KERN_ERR PFX "Cannot map device registers, "
13365 "aborting.\n");
13366 err = -ENOMEM;
13367 goto err_out_free_dev;
13368 }
13369
13370 tg3_init_link_config(tp);
13371
13372 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13373 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13374 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13375
13376 dev->open = tg3_open;
13377 dev->stop = tg3_close;
13378 dev->get_stats = tg3_get_stats;
13379 dev->set_multicast_list = tg3_set_rx_mode;
13380 dev->set_mac_address = tg3_set_mac_addr;
13381 dev->do_ioctl = tg3_ioctl;
13382 dev->tx_timeout = tg3_tx_timeout;
13383 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13384 dev->ethtool_ops = &tg3_ethtool_ops;
13385 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13386 dev->change_mtu = tg3_change_mtu;
13387 dev->irq = pdev->irq;
13388#ifdef CONFIG_NET_POLL_CONTROLLER
13389 dev->poll_controller = tg3_poll_controller;
13390#endif
13391
13392 err = tg3_get_invariants(tp);
13393 if (err) {
13394 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13395 "aborting.\n");
13396 goto err_out_iounmap;
13397 }
13398
13399 /* The EPB bridge inside 5714, 5715, and 5780 and any
13400 * device behind the EPB cannot support DMA addresses > 40-bit.
13401 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13402 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13403 * do DMA address check in tg3_start_xmit().
13404 */
13405 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13406 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13407 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13408 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13409#ifdef CONFIG_HIGHMEM
13410 dma_mask = DMA_64BIT_MASK;
13411#endif
13412 } else
13413 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13414
13415 /* Configure DMA attributes. */
13416 if (dma_mask > DMA_32BIT_MASK) {
13417 err = pci_set_dma_mask(pdev, dma_mask);
13418 if (!err) {
13419 dev->features |= NETIF_F_HIGHDMA;
13420 err = pci_set_consistent_dma_mask(pdev,
13421 persist_dma_mask);
13422 if (err < 0) {
13423 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13424 "DMA for consistent allocations\n");
13425 goto err_out_iounmap;
13426 }
13427 }
13428 }
13429 if (err || dma_mask == DMA_32BIT_MASK) {
13430 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13431 if (err) {
13432 printk(KERN_ERR PFX "No usable DMA configuration, "
13433 "aborting.\n");
13434 goto err_out_iounmap;
13435 }
13436 }
13437
13438 tg3_init_bufmgr_config(tp);
13439
13440 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13441 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13442 }
13443 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13445 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13446 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13447 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13448 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13449 } else {
13450 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13451 }
13452
13453 /* TSO is on by default on chips that support hardware TSO.
13454 * Firmware TSO on older chips gives lower performance, so it
13455 * is off by default, but can be enabled using ethtool.
13456 */
13457 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13458 dev->features |= NETIF_F_TSO;
13459 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13460 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13461 dev->features |= NETIF_F_TSO6;
13462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13463 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13464 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13466 dev->features |= NETIF_F_TSO_ECN;
13467 }
13468
13469
13470 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13471 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13472 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13473 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13474 tp->rx_pending = 63;
13475 }
13476
13477 err = tg3_get_device_address(tp);
13478 if (err) {
13479 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13480 "aborting.\n");
13481 goto err_out_iounmap;
13482 }
13483
13484 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13485 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13486 printk(KERN_ERR PFX "Cannot find proper PCI device "
13487 "base address for APE, aborting.\n");
13488 err = -ENODEV;
13489 goto err_out_iounmap;
13490 }
13491
13492 tg3reg_base = pci_resource_start(pdev, 2);
13493 tg3reg_len = pci_resource_len(pdev, 2);
13494
13495 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13496 if (!tp->aperegs) {
13497 printk(KERN_ERR PFX "Cannot map APE registers, "
13498 "aborting.\n");
13499 err = -ENOMEM;
13500 goto err_out_iounmap;
13501 }
13502
13503 tg3_ape_lock_init(tp);
13504 }
13505
13506 /*
13507 * Reset chip in case UNDI or EFI driver did not shutdown
13508 * DMA self test will enable WDMAC and we'll see (spurious)
13509 * pending DMA on the PCI bus at that point.
13510 */
13511 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13512 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13513 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13514 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13515 }
13516
13517 err = tg3_test_dma(tp);
13518 if (err) {
13519 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13520 goto err_out_apeunmap;
13521 }
13522
13523 /* Tigon3 can do ipv4 only... and some chips have buggy
13524 * checksumming.
13525 */
13526 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13527 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13529 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13533 dev->features |= NETIF_F_IPV6_CSUM;
13534
13535 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13536 } else
13537 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13538
13539 /* flow control autonegotiation is default behavior */
13540 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13541 tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13542
13543 tg3_init_coal(tp);
13544
13545 pci_set_drvdata(pdev, dev);
13546
13547 err = register_netdev(dev);
13548 if (err) {
13549 printk(KERN_ERR PFX "Cannot register net device, "
13550 "aborting.\n");
13551 goto err_out_apeunmap;
13552 }
13553
13554 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13555 "(%s) %s Ethernet %s\n",
13556 dev->name,
13557 tp->board_part_number,
13558 tp->pci_chip_rev_id,
13559 tg3_phy_string(tp),
13560 tg3_bus_string(tp, str),
13561 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13562 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13563 "10/100/1000Base-T")),
13564 print_mac(mac, dev->dev_addr));
13565
13566 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13567 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13568 dev->name,
13569 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13570 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13571 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13572 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13573 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13574 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13575 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13576 dev->name, tp->dma_rwctrl,
13577 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13578 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13579
13580 return 0;
13581
13582err_out_apeunmap:
13583 if (tp->aperegs) {
13584 iounmap(tp->aperegs);
13585 tp->aperegs = NULL;
13586 }
13587
13588err_out_iounmap:
13589 if (tp->regs) {
13590 iounmap(tp->regs);
13591 tp->regs = NULL;
13592 }
13593
13594err_out_free_dev:
13595 free_netdev(dev);
13596
13597err_out_free_res:
13598 pci_release_regions(pdev);
13599
13600err_out_disable_pdev:
13601 pci_disable_device(pdev);
13602 pci_set_drvdata(pdev, NULL);
13603 return err;
13604}
13605
13606static void __devexit tg3_remove_one(struct pci_dev *pdev)
13607{
13608 struct net_device *dev = pci_get_drvdata(pdev);
13609
13610 if (dev) {
13611 struct tg3 *tp = netdev_priv(dev);
13612
13613 flush_scheduled_work();
13614
13615 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13616 tg3_phy_fini(tp);
13617 tg3_mdio_fini(tp);
13618 }
13619
13620 unregister_netdev(dev);
13621 if (tp->aperegs) {
13622 iounmap(tp->aperegs);
13623 tp->aperegs = NULL;
13624 }
13625 if (tp->regs) {
13626 iounmap(tp->regs);
13627 tp->regs = NULL;
13628 }
13629 free_netdev(dev);
13630 pci_release_regions(pdev);
13631 pci_disable_device(pdev);
13632 pci_set_drvdata(pdev, NULL);
13633 }
13634}
13635
13636static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13637{
13638 struct net_device *dev = pci_get_drvdata(pdev);
13639 struct tg3 *tp = netdev_priv(dev);
13640 pci_power_t target_state;
13641 int err;
13642
13643 /* PCI register 4 needs to be saved whether netif_running() or not.
13644 * MSI address and data need to be saved if using MSI and
13645 * netif_running().
13646 */
13647 pci_save_state(pdev);
13648
13649 if (!netif_running(dev))
13650 return 0;
13651
13652 flush_scheduled_work();
13653 tg3_phy_stop(tp);
13654 tg3_netif_stop(tp);
13655
13656 del_timer_sync(&tp->timer);
13657
13658 tg3_full_lock(tp, 1);
13659 tg3_disable_ints(tp);
13660 tg3_full_unlock(tp);
13661
13662 netif_device_detach(dev);
13663
13664 tg3_full_lock(tp, 0);
13665 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13666 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13667 tg3_full_unlock(tp);
13668
13669 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13670
13671 err = tg3_set_power_state(tp, target_state);
13672 if (err) {
13673 int err2;
13674
13675 tg3_full_lock(tp, 0);
13676
13677 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13678 err2 = tg3_restart_hw(tp, 1);
13679 if (err2)
13680 goto out;
13681
13682 tp->timer.expires = jiffies + tp->timer_offset;
13683 add_timer(&tp->timer);
13684
13685 netif_device_attach(dev);
13686 tg3_netif_start(tp);
13687
13688out:
13689 tg3_full_unlock(tp);
13690
13691 if (!err2)
13692 tg3_phy_start(tp);
13693 }
13694
13695 return err;
13696}
13697
13698static int tg3_resume(struct pci_dev *pdev)
13699{
13700 struct net_device *dev = pci_get_drvdata(pdev);
13701 struct tg3 *tp = netdev_priv(dev);
13702 int err;
13703
13704 pci_restore_state(tp->pdev);
13705
13706 if (!netif_running(dev))
13707 return 0;
13708
13709 err = tg3_set_power_state(tp, PCI_D0);
13710 if (err)
13711 return err;
13712
13713 netif_device_attach(dev);
13714
13715 tg3_full_lock(tp, 0);
13716
13717 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13718 err = tg3_restart_hw(tp, 1);
13719 if (err)
13720 goto out;
13721
13722 tp->timer.expires = jiffies + tp->timer_offset;
13723 add_timer(&tp->timer);
13724
13725 tg3_netif_start(tp);
13726
13727out:
13728 tg3_full_unlock(tp);
13729
13730 if (!err)
13731 tg3_phy_start(tp);
13732
13733 return err;
13734}
13735
13736static struct pci_driver tg3_driver = {
13737 .name = DRV_MODULE_NAME,
13738 .id_table = tg3_pci_tbl,
13739 .probe = tg3_init_one,
13740 .remove = __devexit_p(tg3_remove_one),
13741 .suspend = tg3_suspend,
13742 .resume = tg3_resume
13743};
13744
13745static int __init tg3_init(void)
13746{
13747 return pci_register_driver(&tg3_driver);
13748}
13749
13750static void __exit tg3_cleanup(void)
13751{
13752 pci_unregister_driver(&tg3_driver);
13753}
13754
13755module_init(tg3_init);
13756module_exit(tg3_cleanup);
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