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1 | /* | |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
28 | #include <linux/slab.h> | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "drm_crtc_helper.h" | |
33 | #include "intel_drv.h" | |
34 | #include "i915_drm.h" | |
35 | #include "i915_drv.h" | |
36 | ||
37 | static void intel_crt_dpms(struct drm_encoder *encoder, int mode) | |
38 | { | |
39 | struct drm_device *dev = encoder->dev; | |
40 | struct drm_i915_private *dev_priv = dev->dev_private; | |
41 | u32 temp, reg; | |
42 | ||
43 | if (HAS_PCH_SPLIT(dev)) | |
44 | reg = PCH_ADPA; | |
45 | else | |
46 | reg = ADPA; | |
47 | ||
48 | temp = I915_READ(reg); | |
49 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
50 | temp &= ~ADPA_DAC_ENABLE; | |
51 | ||
52 | switch(mode) { | |
53 | case DRM_MODE_DPMS_ON: | |
54 | temp |= ADPA_DAC_ENABLE; | |
55 | break; | |
56 | case DRM_MODE_DPMS_STANDBY: | |
57 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
58 | break; | |
59 | case DRM_MODE_DPMS_SUSPEND: | |
60 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
61 | break; | |
62 | case DRM_MODE_DPMS_OFF: | |
63 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
64 | break; | |
65 | } | |
66 | ||
67 | I915_WRITE(reg, temp); | |
68 | } | |
69 | ||
70 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
71 | struct drm_display_mode *mode) | |
72 | { | |
73 | struct drm_device *dev = connector->dev; | |
74 | ||
75 | int max_clock = 0; | |
76 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
77 | return MODE_NO_DBLESCAN; | |
78 | ||
79 | if (mode->clock < 25000) | |
80 | return MODE_CLOCK_LOW; | |
81 | ||
82 | if (!IS_I9XX(dev)) | |
83 | max_clock = 350000; | |
84 | else | |
85 | max_clock = 400000; | |
86 | if (mode->clock > max_clock) | |
87 | return MODE_CLOCK_HIGH; | |
88 | ||
89 | return MODE_OK; | |
90 | } | |
91 | ||
92 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, | |
93 | struct drm_display_mode *mode, | |
94 | struct drm_display_mode *adjusted_mode) | |
95 | { | |
96 | return true; | |
97 | } | |
98 | ||
99 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
100 | struct drm_display_mode *mode, | |
101 | struct drm_display_mode *adjusted_mode) | |
102 | { | |
103 | ||
104 | struct drm_device *dev = encoder->dev; | |
105 | struct drm_crtc *crtc = encoder->crtc; | |
106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
108 | int dpll_md_reg; | |
109 | u32 adpa, dpll_md; | |
110 | u32 adpa_reg; | |
111 | ||
112 | if (intel_crtc->pipe == 0) | |
113 | dpll_md_reg = DPLL_A_MD; | |
114 | else | |
115 | dpll_md_reg = DPLL_B_MD; | |
116 | ||
117 | if (HAS_PCH_SPLIT(dev)) | |
118 | adpa_reg = PCH_ADPA; | |
119 | else | |
120 | adpa_reg = ADPA; | |
121 | ||
122 | /* | |
123 | * Disable separate mode multiplier used when cloning SDVO to CRT | |
124 | * XXX this needs to be adjusted when we really are cloning | |
125 | */ | |
126 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { | |
127 | dpll_md = I915_READ(dpll_md_reg); | |
128 | I915_WRITE(dpll_md_reg, | |
129 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | |
130 | } | |
131 | ||
132 | adpa = 0; | |
133 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
134 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
135 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
136 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
137 | ||
138 | if (intel_crtc->pipe == 0) { | |
139 | if (HAS_PCH_CPT(dev)) | |
140 | adpa |= PORT_TRANS_A_SEL_CPT; | |
141 | else | |
142 | adpa |= ADPA_PIPE_A_SELECT; | |
143 | if (!HAS_PCH_SPLIT(dev)) | |
144 | I915_WRITE(BCLRPAT_A, 0); | |
145 | } else { | |
146 | if (HAS_PCH_CPT(dev)) | |
147 | adpa |= PORT_TRANS_B_SEL_CPT; | |
148 | else | |
149 | adpa |= ADPA_PIPE_B_SELECT; | |
150 | if (!HAS_PCH_SPLIT(dev)) | |
151 | I915_WRITE(BCLRPAT_B, 0); | |
152 | } | |
153 | ||
154 | I915_WRITE(adpa_reg, adpa); | |
155 | } | |
156 | ||
157 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) | |
158 | { | |
159 | struct drm_device *dev = connector->dev; | |
160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
161 | u32 adpa, temp; | |
162 | bool ret; | |
163 | bool turn_off_dac = false; | |
164 | ||
165 | temp = adpa = I915_READ(PCH_ADPA); | |
166 | ||
167 | if (HAS_PCH_SPLIT(dev)) | |
168 | turn_off_dac = true; | |
169 | ||
170 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; | |
171 | if (turn_off_dac) | |
172 | adpa &= ~ADPA_DAC_ENABLE; | |
173 | ||
174 | /* disable HPD first */ | |
175 | I915_WRITE(PCH_ADPA, adpa); | |
176 | (void)I915_READ(PCH_ADPA); | |
177 | ||
178 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | | |
179 | ADPA_CRT_HOTPLUG_WARMUP_10MS | | |
180 | ADPA_CRT_HOTPLUG_SAMPLE_4S | | |
181 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */ | |
182 | ADPA_CRT_HOTPLUG_VOLREF_325MV | | |
183 | ADPA_CRT_HOTPLUG_ENABLE | | |
184 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); | |
185 | ||
186 | DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); | |
187 | I915_WRITE(PCH_ADPA, adpa); | |
188 | ||
189 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, | |
190 | 1000, 1)) | |
191 | DRM_ERROR("timed out waiting for FORCE_TRIGGER"); | |
192 | ||
193 | if (turn_off_dac) { | |
194 | I915_WRITE(PCH_ADPA, temp); | |
195 | (void)I915_READ(PCH_ADPA); | |
196 | } | |
197 | ||
198 | /* Check the status to see if both blue and green are on now */ | |
199 | adpa = I915_READ(PCH_ADPA); | |
200 | adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK; | |
201 | if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) || | |
202 | (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO)) | |
203 | ret = true; | |
204 | else | |
205 | ret = false; | |
206 | ||
207 | return ret; | |
208 | } | |
209 | ||
210 | /** | |
211 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
212 | * | |
213 | * Not for i915G/i915GM | |
214 | * | |
215 | * \return true if CRT is connected. | |
216 | * \return false if CRT is disconnected. | |
217 | */ | |
218 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
219 | { | |
220 | struct drm_device *dev = connector->dev; | |
221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
222 | u32 hotplug_en, orig, stat; | |
223 | bool ret = false; | |
224 | int i, tries = 0; | |
225 | ||
226 | if (HAS_PCH_SPLIT(dev)) | |
227 | return intel_ironlake_crt_detect_hotplug(connector); | |
228 | ||
229 | /* | |
230 | * On 4 series desktop, CRT detect sequence need to be done twice | |
231 | * to get a reliable result. | |
232 | */ | |
233 | ||
234 | if (IS_G4X(dev) && !IS_GM45(dev)) | |
235 | tries = 2; | |
236 | else | |
237 | tries = 1; | |
238 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); | |
239 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; | |
240 | ||
241 | for (i = 0; i < tries ; i++) { | |
242 | /* turn on the FORCE_DETECT */ | |
243 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
244 | /* wait for FORCE_DETECT to go off */ | |
245 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & | |
246 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
247 | 1000, 1)) | |
248 | DRM_ERROR("timed out waiting for FORCE_DETECT to go off"); | |
249 | } | |
250 | ||
251 | stat = I915_READ(PORT_HOTPLUG_STAT); | |
252 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
253 | ret = true; | |
254 | ||
255 | /* clear the interrupt we just generated, if any */ | |
256 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
257 | ||
258 | /* and put the bits back */ | |
259 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
260 | ||
261 | return ret; | |
262 | } | |
263 | ||
264 | static bool intel_crt_detect_ddc(struct drm_encoder *encoder) | |
265 | { | |
266 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
267 | ||
268 | /* CRT should always be at 0, but check anyway */ | |
269 | if (intel_encoder->type != INTEL_OUTPUT_ANALOG) | |
270 | return false; | |
271 | ||
272 | return intel_ddc_probe(intel_encoder); | |
273 | } | |
274 | ||
275 | static enum drm_connector_status | |
276 | intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder) | |
277 | { | |
278 | struct drm_encoder *encoder = &intel_encoder->enc; | |
279 | struct drm_device *dev = encoder->dev; | |
280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
282 | uint32_t pipe = intel_crtc->pipe; | |
283 | uint32_t save_bclrpat; | |
284 | uint32_t save_vtotal; | |
285 | uint32_t vtotal, vactive; | |
286 | uint32_t vsample; | |
287 | uint32_t vblank, vblank_start, vblank_end; | |
288 | uint32_t dsl; | |
289 | uint32_t bclrpat_reg; | |
290 | uint32_t vtotal_reg; | |
291 | uint32_t vblank_reg; | |
292 | uint32_t vsync_reg; | |
293 | uint32_t pipeconf_reg; | |
294 | uint32_t pipe_dsl_reg; | |
295 | uint8_t st00; | |
296 | enum drm_connector_status status; | |
297 | ||
298 | if (pipe == 0) { | |
299 | bclrpat_reg = BCLRPAT_A; | |
300 | vtotal_reg = VTOTAL_A; | |
301 | vblank_reg = VBLANK_A; | |
302 | vsync_reg = VSYNC_A; | |
303 | pipeconf_reg = PIPEACONF; | |
304 | pipe_dsl_reg = PIPEADSL; | |
305 | } else { | |
306 | bclrpat_reg = BCLRPAT_B; | |
307 | vtotal_reg = VTOTAL_B; | |
308 | vblank_reg = VBLANK_B; | |
309 | vsync_reg = VSYNC_B; | |
310 | pipeconf_reg = PIPEBCONF; | |
311 | pipe_dsl_reg = PIPEBDSL; | |
312 | } | |
313 | ||
314 | save_bclrpat = I915_READ(bclrpat_reg); | |
315 | save_vtotal = I915_READ(vtotal_reg); | |
316 | vblank = I915_READ(vblank_reg); | |
317 | ||
318 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
319 | vactive = (save_vtotal & 0x7ff) + 1; | |
320 | ||
321 | vblank_start = (vblank & 0xfff) + 1; | |
322 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
323 | ||
324 | /* Set the border color to purple. */ | |
325 | I915_WRITE(bclrpat_reg, 0x500050); | |
326 | ||
327 | if (IS_I9XX(dev)) { | |
328 | uint32_t pipeconf = I915_READ(pipeconf_reg); | |
329 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
330 | /* Wait for next Vblank to substitue | |
331 | * border color for Color info */ | |
332 | intel_wait_for_vblank(dev, pipe); | |
333 | st00 = I915_READ8(VGA_MSR_WRITE); | |
334 | status = ((st00 & (1 << 4)) != 0) ? | |
335 | connector_status_connected : | |
336 | connector_status_disconnected; | |
337 | ||
338 | I915_WRITE(pipeconf_reg, pipeconf); | |
339 | } else { | |
340 | bool restore_vblank = false; | |
341 | int count, detect; | |
342 | ||
343 | /* | |
344 | * If there isn't any border, add some. | |
345 | * Yes, this will flicker | |
346 | */ | |
347 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
348 | uint32_t vsync = I915_READ(vsync_reg); | |
349 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
350 | ||
351 | vblank_start = vsync_start; | |
352 | I915_WRITE(vblank_reg, | |
353 | (vblank_start - 1) | | |
354 | ((vblank_end - 1) << 16)); | |
355 | restore_vblank = true; | |
356 | } | |
357 | /* sample in the vertical border, selecting the larger one */ | |
358 | if (vblank_start - vactive >= vtotal - vblank_end) | |
359 | vsample = (vblank_start + vactive) >> 1; | |
360 | else | |
361 | vsample = (vtotal + vblank_end) >> 1; | |
362 | ||
363 | /* | |
364 | * Wait for the border to be displayed | |
365 | */ | |
366 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
367 | ; | |
368 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
369 | ; | |
370 | /* | |
371 | * Watch ST00 for an entire scanline | |
372 | */ | |
373 | detect = 0; | |
374 | count = 0; | |
375 | do { | |
376 | count++; | |
377 | /* Read the ST00 VGA status register */ | |
378 | st00 = I915_READ8(VGA_MSR_WRITE); | |
379 | if (st00 & (1 << 4)) | |
380 | detect++; | |
381 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
382 | ||
383 | /* restore vblank if necessary */ | |
384 | if (restore_vblank) | |
385 | I915_WRITE(vblank_reg, vblank); | |
386 | /* | |
387 | * If more than 3/4 of the scanline detected a monitor, | |
388 | * then it is assumed to be present. This works even on i830, | |
389 | * where there isn't any way to force the border color across | |
390 | * the screen | |
391 | */ | |
392 | status = detect * 4 > count * 3 ? | |
393 | connector_status_connected : | |
394 | connector_status_disconnected; | |
395 | } | |
396 | ||
397 | /* Restore previous settings */ | |
398 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
399 | ||
400 | return status; | |
401 | } | |
402 | ||
403 | static enum drm_connector_status intel_crt_detect(struct drm_connector *connector) | |
404 | { | |
405 | struct drm_device *dev = connector->dev; | |
406 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
407 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
408 | struct drm_crtc *crtc; | |
409 | int dpms_mode; | |
410 | enum drm_connector_status status; | |
411 | ||
412 | if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) { | |
413 | if (intel_crt_detect_hotplug(connector)) | |
414 | return connector_status_connected; | |
415 | else | |
416 | return connector_status_disconnected; | |
417 | } | |
418 | ||
419 | if (intel_crt_detect_ddc(encoder)) | |
420 | return connector_status_connected; | |
421 | ||
422 | /* for pre-945g platforms use load detect */ | |
423 | if (encoder->crtc && encoder->crtc->enabled) { | |
424 | status = intel_crt_load_detect(encoder->crtc, intel_encoder); | |
425 | } else { | |
426 | crtc = intel_get_load_detect_pipe(intel_encoder, connector, | |
427 | NULL, &dpms_mode); | |
428 | if (crtc) { | |
429 | status = intel_crt_load_detect(crtc, intel_encoder); | |
430 | intel_release_load_detect_pipe(intel_encoder, | |
431 | connector, dpms_mode); | |
432 | } else | |
433 | status = connector_status_unknown; | |
434 | } | |
435 | ||
436 | return status; | |
437 | } | |
438 | ||
439 | static void intel_crt_destroy(struct drm_connector *connector) | |
440 | { | |
441 | drm_sysfs_connector_remove(connector); | |
442 | drm_connector_cleanup(connector); | |
443 | kfree(connector); | |
444 | } | |
445 | ||
446 | static int intel_crt_get_modes(struct drm_connector *connector) | |
447 | { | |
448 | int ret; | |
449 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
450 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
451 | struct i2c_adapter *ddc_bus; | |
452 | struct drm_device *dev = connector->dev; | |
453 | ||
454 | ||
455 | ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); | |
456 | if (ret || !IS_G4X(dev)) | |
457 | goto end; | |
458 | ||
459 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ | |
460 | ddc_bus = intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D"); | |
461 | ||
462 | if (!ddc_bus) { | |
463 | dev_printk(KERN_ERR, &connector->dev->pdev->dev, | |
464 | "DDC bus registration failed for CRTDDC_D.\n"); | |
465 | goto end; | |
466 | } | |
467 | /* Try to get modes by GPIOD port */ | |
468 | ret = intel_ddc_get_modes(connector, ddc_bus); | |
469 | intel_i2c_destroy(ddc_bus); | |
470 | ||
471 | end: | |
472 | return ret; | |
473 | ||
474 | } | |
475 | ||
476 | static int intel_crt_set_property(struct drm_connector *connector, | |
477 | struct drm_property *property, | |
478 | uint64_t value) | |
479 | { | |
480 | return 0; | |
481 | } | |
482 | ||
483 | /* | |
484 | * Routines for controlling stuff on the analog port | |
485 | */ | |
486 | ||
487 | static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = { | |
488 | .dpms = intel_crt_dpms, | |
489 | .mode_fixup = intel_crt_mode_fixup, | |
490 | .prepare = intel_encoder_prepare, | |
491 | .commit = intel_encoder_commit, | |
492 | .mode_set = intel_crt_mode_set, | |
493 | }; | |
494 | ||
495 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
496 | .dpms = drm_helper_connector_dpms, | |
497 | .detect = intel_crt_detect, | |
498 | .fill_modes = drm_helper_probe_single_connector_modes, | |
499 | .destroy = intel_crt_destroy, | |
500 | .set_property = intel_crt_set_property, | |
501 | }; | |
502 | ||
503 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
504 | .mode_valid = intel_crt_mode_valid, | |
505 | .get_modes = intel_crt_get_modes, | |
506 | .best_encoder = intel_attached_encoder, | |
507 | }; | |
508 | ||
509 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { | |
510 | .destroy = intel_encoder_destroy, | |
511 | }; | |
512 | ||
513 | void intel_crt_init(struct drm_device *dev) | |
514 | { | |
515 | struct drm_connector *connector; | |
516 | struct intel_encoder *intel_encoder; | |
517 | struct intel_connector *intel_connector; | |
518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
519 | u32 i2c_reg; | |
520 | ||
521 | intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL); | |
522 | if (!intel_encoder) | |
523 | return; | |
524 | ||
525 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
526 | if (!intel_connector) { | |
527 | kfree(intel_encoder); | |
528 | return; | |
529 | } | |
530 | ||
531 | connector = &intel_connector->base; | |
532 | drm_connector_init(dev, &intel_connector->base, | |
533 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); | |
534 | ||
535 | drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs, | |
536 | DRM_MODE_ENCODER_DAC); | |
537 | ||
538 | drm_mode_connector_attach_encoder(&intel_connector->base, | |
539 | &intel_encoder->enc); | |
540 | ||
541 | /* Set up the DDC bus. */ | |
542 | if (HAS_PCH_SPLIT(dev)) | |
543 | i2c_reg = PCH_GPIOA; | |
544 | else { | |
545 | i2c_reg = GPIOA; | |
546 | /* Use VBT information for CRT DDC if available */ | |
547 | if (dev_priv->crt_ddc_bus != 0) | |
548 | i2c_reg = dev_priv->crt_ddc_bus; | |
549 | } | |
550 | intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); | |
551 | if (!intel_encoder->ddc_bus) { | |
552 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " | |
553 | "failed.\n"); | |
554 | return; | |
555 | } | |
556 | ||
557 | intel_encoder->type = INTEL_OUTPUT_ANALOG; | |
558 | intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
559 | (1 << INTEL_ANALOG_CLONE_BIT) | | |
560 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
561 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
562 | connector->interlace_allowed = 1; | |
563 | connector->doublescan_allowed = 0; | |
564 | ||
565 | drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs); | |
566 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); | |
567 | ||
568 | drm_sysfs_connector_add(connector); | |
569 | ||
570 | if (I915_HAS_HOTPLUG(dev)) | |
571 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
572 | else | |
573 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
574 | ||
575 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; | |
576 | } |