[net-next-2.6.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			ASSERT(redir_index < IOAPIC_NUM_PINS);

			redir_content = ioapic->redirtbl[redir_index].bits;
			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union ioapic_redir_entry *pent;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		int injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}
	if (!pent->fields.trig_mode)
		ioapic->irr &= ~(1 << idx);
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		mask_before = ioapic->redirtbl[index].fields.mask;
		if (ioapic->ioregsel & 1) {
			ioapic->redirtbl[index].bits &= 0xffffffff;
			ioapic->redirtbl[index].bits |= (u64) val << 32;
		} else {
			ioapic->redirtbl[index].bits &= ~0xffffffffULL;
			ioapic->redirtbl[index].bits |= (u32) val;
			ioapic->redirtbl[index].fields.remote_irr = 0;
		}
		mask_after = ioapic->redirtbl[index].fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
		if (ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		break;
	}
}

static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
			   struct kvm_vcpu *vcpu,
			   u8 vector, u8 trig_mode, u8 delivery_mode)
{
	ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
		     delivery_mode);

	ASSERT((delivery_mode == IOAPIC_FIXED) ||
	       (delivery_mode == IOAPIC_LOWEST_PRIORITY));

	return kvm_apic_set_irq(vcpu, vector, trig_mode);
}

static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
{
	kvm_inject_nmi(vcpu);
	kvm_vcpu_kick(vcpu);
}

u32 kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
				    u8 dest_mode)
{
	u32 mask = 0;
	int i;
	struct kvm *kvm = ioapic->kvm;
	struct kvm_vcpu *vcpu;

	ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);

	if (dest_mode == 0) {	/* Physical mode. */
		if (dest == 0xFF) {	/* Broadcast. */
			for (i = 0; i < KVM_MAX_VCPUS; ++i)
				if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
					mask |= 1 << i;
			return mask;
		}
		for (i = 0; i < KVM_MAX_VCPUS; ++i) {
			vcpu = kvm->vcpus[i];
			if (!vcpu)
				continue;
			if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
				if (vcpu->arch.apic)
					mask = 1 << i;
				break;
			}
		}
	} else if (dest != 0)	/* Logical mode, MDA non-zero. */
		for (i = 0; i < KVM_MAX_VCPUS; ++i) {
			vcpu = kvm->vcpus[i];
			if (!vcpu)
				continue;
			if (vcpu->arch.apic &&
			    kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
				mask |= 1 << vcpu->vcpu_id;
		}
	ioapic_debug("mask %x\n", mask);
	return mask;
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	u8 dest = ioapic->redirtbl[irq].fields.dest_id;
	u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
	u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
	u8 vector = ioapic->redirtbl[irq].fields.vector;
	u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
	u32 deliver_bitmask;
	struct kvm_vcpu *vcpu;
	int vcpu_id, r = 0;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     dest, dest_mode, delivery_mode, vector, trig_mode);

	deliver_bitmask = kvm_ioapic_get_delivery_bitmask(ioapic, dest,
							  dest_mode);
	if (!deliver_bitmask) {
		ioapic_debug("no target on destination\n");
		return 0;
	}

	switch (delivery_mode) {
	case IOAPIC_LOWEST_PRIORITY:
		vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
				deliver_bitmask);
#ifdef CONFIG_X86
		if (irq == 0)
			vcpu = ioapic->kvm->vcpus[0];
#endif
		if (vcpu != NULL)
			r = ioapic_inj_irq(ioapic, vcpu, vector,
				       trig_mode, delivery_mode);
		else
			ioapic_debug("null lowest prio vcpu: "
				     "mask=%x vector=%x delivery_mode=%x\n",
				     deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
		break;
	case IOAPIC_FIXED:
#ifdef CONFIG_X86
		if (irq == 0)
			deliver_bitmask = 1;
#endif
		for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
			if (!(deliver_bitmask & (1 << vcpu_id)))
				continue;
			deliver_bitmask &= ~(1 << vcpu_id);
			vcpu = ioapic->kvm->vcpus[vcpu_id];
			if (vcpu) {
				r = ioapic_inj_irq(ioapic, vcpu, vector,
					       trig_mode, delivery_mode);
			}
		}
		break;
	case IOAPIC_NMI:
		for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
			if (!(deliver_bitmask & (1 << vcpu_id)))
				continue;
			deliver_bitmask &= ~(1 << vcpu_id);
			vcpu = ioapic->kvm->vcpus[vcpu_id];
			if (vcpu)
				ioapic_inj_nmi(vcpu);
			else
				ioapic_debug("NMI to vcpu %d failed\n",
						vcpu->vcpu_id);
		}
		break;
	default:
		printk(KERN_WARNING "Unsupported delivery mode %d\n",
		       delivery_mode);
		break;
	}
	return r;
}

void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
{
	u32 old_irr = ioapic->irr;
	u32 mask = 1 << irq;
	union ioapic_redir_entry entry;

	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
		entry = ioapic->redirtbl[irq];
		level ^= entry.fields.polarity;
		if (!level)
			ioapic->irr &= ~mask;
		else {
			ioapic->irr |= mask;
			if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
			    || !entry.fields.remote_irr)
				ioapic_service(ioapic, irq);
		}
	}
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
				    int trigger_mode)
{
	union ioapic_redir_entry *ent;

	ent = &ioapic->redirtbl[pin];

	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);

	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
			ioapic_service(ioapic, pin);
	}
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		if (ioapic->redirtbl[i].fields.vector == vector)
			__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
}

static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
			   int len, int is_write)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;

	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			     void *val)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
	u32 result;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
}

static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			      const void *val)
{
	struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
	u32 data;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */
	if (len == 4 || len == 8)
		data = *(u32 *) val;
	else {
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return;
	}

	addr &= 0xff;
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data;
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
}

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	ioapic->dev.read = ioapic_mmio_read;
	ioapic->dev.write = ioapic_mmio_write;
	ioapic->dev.in_range = ioapic_in_range;
	ioapic->dev.private = ioapic;
	ioapic->kvm = kvm;
	kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
	2	* Copyright (C) 2001 MandrakeSoft S.A.
	3	*
	4	* MandrakeSoft S.A.
	5	* 43, rue d'Aboukir
	6	* 75002 Paris - France
	7	* http://www.linux-mandrake.com/
	8	* http://www.mandrakesoft.com/
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Yunhong Jiang <yunhong.jiang@intel.com>
	25	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	26	* Based on Xen 3.1 code.
	27	*/
	28
edf88417	29	#include <linux/kvm_host.h>
1fd4f2a5 ED	30	#include <linux/kvm.h>
	31	#include <linux/mm.h>
	32	#include <linux/highmem.h>
	33	#include <linux/smp.h>
	34	#include <linux/hrtimer.h>
	35	#include <linux/io.h>
	36	#include <asm/processor.h>
1fd4f2a5 ED	37	#include <asm/page.h>
1fd4f2a5 ED	38	#include <asm/current.h>
82470196 ZX	39
	40	#include "ioapic.h"
	41	#include "lapic.h"
f5244726	42	#include "irq.h"
82470196	43
e25e3ed5 LV	44	#if 0
	45	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	46	#else
1fd4f2a5	47	#define ioapic_debug(fmt, arg...)
e25e3ed5	48	#endif
ff4b9df8	49	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	50
	51	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	52	unsigned long addr,
	53	unsigned long length)
	54	{
	55	unsigned long result = 0;
	56
	57	switch (ioapic->ioregsel) {
	58	case IOAPIC_REG_VERSION:
	59	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	60	\| (IOAPIC_VERSION_ID & 0xff));
	61	break;
	62
	63	case IOAPIC_REG_APIC_ID:
	64	case IOAPIC_REG_ARB_ID:
	65	result = ((ioapic->id & 0xf) << 24);
	66	break;
	67
	68	default:
	69	{
	70	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	71	u64 redir_content;
	72
	73	ASSERT(redir_index < IOAPIC_NUM_PINS);
	74
	75	redir_content = ioapic->redirtbl[redir_index].bits;
	76	result = (ioapic->ioregsel & 0x1) ?
	77	(redir_content >> 32) & 0xffffffff :
	78	redir_content & 0xffffffff;
	79	break;
	80	}
	81	}
	82
	83	return result;
	84	}
	85
	86	static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
	87	{
	88	union ioapic_redir_entry *pent;
	89
	90	pent = &ioapic->redirtbl[idx];
	91
	92	if (!pent->fields.mask) {
ff4b9df8 MT	93	int injected = ioapic_deliver(ioapic, idx);
ff4b9df8 MT	94	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	95	pent->fields.remote_irr = 1;
	96	}
	97	if (!pent->fields.trig_mode)
	98	ioapic->irr &= ~(1 << idx);
	99	}
	100
	101	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	102	{
	103	unsigned index;
75858a84	104	bool mask_before, mask_after;
1fd4f2a5 ED	105
	106	switch (ioapic->ioregsel) {
	107	case IOAPIC_REG_VERSION:
	108	/* Writes are ignored. */
	109	break;
	110
	111	case IOAPIC_REG_APIC_ID:
	112	ioapic->id = (val >> 24) & 0xf;
	113	break;
	114
	115	case IOAPIC_REG_ARB_ID:
	116	break;
	117
	118	default:
	119	index = (ioapic->ioregsel - 0x10) >> 1;
	120
e25e3ed5	121	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	122	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	123	return;
75858a84	124	mask_before = ioapic->redirtbl[index].fields.mask;
1fd4f2a5 ED	125	if (ioapic->ioregsel & 1) {
	126	ioapic->redirtbl[index].bits &= 0xffffffff;
	127	ioapic->redirtbl[index].bits \|= (u64) val << 32;
	128	} else {
	129	ioapic->redirtbl[index].bits &= ~0xffffffffULL;
	130	ioapic->redirtbl[index].bits \|= (u32) val;
	131	ioapic->redirtbl[index].fields.remote_irr = 0;
	132	}
75858a84 AK	133	mask_after = ioapic->redirtbl[index].fields.mask;
	134	if (mask_before != mask_after)
	135	kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
1fd4f2a5 ED	136	if (ioapic->irr & (1 << index))
	137	ioapic_service(ioapic, index);
	138	break;
	139	}
	140	}
	141
ff4b9df8	142	static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
8be5453f	143	struct kvm_vcpu *vcpu,
1fd4f2a5 ED	144	u8 vector, u8 trig_mode, u8 delivery_mode)
1fd4f2a5 ED	145	{
e25e3ed5	146	ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
1fd4f2a5 ED	147	delivery_mode);
1fd4f2a5 ED	148
0c7ac28d ZX	149	ASSERT((delivery_mode == IOAPIC_FIXED) \|\|
0c7ac28d ZX	150	(delivery_mode == IOAPIC_LOWEST_PRIORITY));
1fd4f2a5	151
ff4b9df8	152	return kvm_apic_set_irq(vcpu, vector, trig_mode);
1fd4f2a5 ED	153	}
1fd4f2a5 ED	154
3419ffc8 SY	155	static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
	156	{
	157	kvm_inject_nmi(vcpu);
26df99c6	158	kvm_vcpu_kick(vcpu);
3419ffc8 SY	159	}
3419ffc8 SY	160
68b76f51 SY	161	u32 kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
68b76f51 SY	162	u8 dest_mode)
1fd4f2a5 ED	163	{
	164	u32 mask = 0;
	165	int i;
	166	struct kvm *kvm = ioapic->kvm;
	167	struct kvm_vcpu *vcpu;
	168
e25e3ed5	169	ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
1fd4f2a5 ED	170
	171	if (dest_mode == 0) { /* Physical mode. */
	172	if (dest == 0xFF) { /* Broadcast. */
	173	for (i = 0; i < KVM_MAX_VCPUS; ++i)
ad312c7c	174	if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
1fd4f2a5 ED	175	mask \|= 1 << i;
	176	return mask;
	177	}
	178	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
	179	vcpu = kvm->vcpus[i];
	180	if (!vcpu)
	181	continue;
ad312c7c ZX	182	if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
ad312c7c ZX	183	if (vcpu->arch.apic)
1fd4f2a5 ED	184	mask = 1 << i;
	185	break;
	186	}
	187	}
	188	} else if (dest != 0) /* Logical mode, MDA non-zero. */
	189	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
	190	vcpu = kvm->vcpus[i];
	191	if (!vcpu)
	192	continue;
ad312c7c ZX	193	if (vcpu->arch.apic &&
ad312c7c ZX	194	kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
1fd4f2a5 ED	195	mask \|= 1 << vcpu->vcpu_id;
1fd4f2a5 ED	196	}
e25e3ed5	197	ioapic_debug("mask %x\n", mask);
1fd4f2a5 ED	198	return mask;
	199	}
	200
ff4b9df8	201	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
1fd4f2a5 ED	202	{
	203	u8 dest = ioapic->redirtbl[irq].fields.dest_id;
	204	u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
	205	u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
	206	u8 vector = ioapic->redirtbl[irq].fields.vector;
	207	u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
	208	u32 deliver_bitmask;
1fd4f2a5	209	struct kvm_vcpu *vcpu;
ff4b9df8	210	int vcpu_id, r = 0;
1fd4f2a5 ED	211
1fd4f2a5 ED	212	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
e25e3ed5	213	"vector=%x trig_mode=%x\n",
1fd4f2a5 ED	214	dest, dest_mode, delivery_mode, vector, trig_mode);
1fd4f2a5 ED	215
68b76f51 SY	216	deliver_bitmask = kvm_ioapic_get_delivery_bitmask(ioapic, dest,
68b76f51 SY	217	dest_mode);
1fd4f2a5	218	if (!deliver_bitmask) {
e25e3ed5	219	ioapic_debug("no target on destination\n");
ff4b9df8	220	return 0;
1fd4f2a5 ED	221	}
	222
	223	switch (delivery_mode) {
0c7ac28d	224	case IOAPIC_LOWEST_PRIORITY:
8be5453f ZX	225	vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
8be5453f ZX	226	deliver_bitmask);
8c35f237 AK	227	#ifdef CONFIG_X86
	228	if (irq == 0)
	229	vcpu = ioapic->kvm->vcpus[0];
	230	#endif
8be5453f	231	if (vcpu != NULL)
ff4b9df8	232	r = ioapic_inj_irq(ioapic, vcpu, vector,
1fd4f2a5 ED	233	trig_mode, delivery_mode);
1fd4f2a5 ED	234	else
8be5453f	235	ioapic_debug("null lowest prio vcpu: "
e25e3ed5	236	"mask=%x vector=%x delivery_mode=%x\n",
0c7ac28d	237	deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
1fd4f2a5	238	break;
0c7ac28d	239	case IOAPIC_FIXED:
8c35f237 AK	240	#ifdef CONFIG_X86
	241	if (irq == 0)
	242	deliver_bitmask = 1;
	243	#endif
1fd4f2a5 ED	244	for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
	245	if (!(deliver_bitmask & (1 << vcpu_id)))
	246	continue;
	247	deliver_bitmask &= ~(1 << vcpu_id);
	248	vcpu = ioapic->kvm->vcpus[vcpu_id];
	249	if (vcpu) {
ff4b9df8	250	r = ioapic_inj_irq(ioapic, vcpu, vector,
1fd4f2a5 ED	251	trig_mode, delivery_mode);
	252	}
	253	}
	254	break;
3419ffc8 SY	255	case IOAPIC_NMI:
	256	for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
	257	if (!(deliver_bitmask & (1 << vcpu_id)))
	258	continue;
	259	deliver_bitmask &= ~(1 << vcpu_id);
	260	vcpu = ioapic->kvm->vcpus[vcpu_id];
	261	if (vcpu)
	262	ioapic_inj_nmi(vcpu);
	263	else
	264	ioapic_debug("NMI to vcpu %d failed\n",
	265	vcpu->vcpu_id);
	266	}
	267	break;
1fd4f2a5 ED	268	default:
	269	printk(KERN_WARNING "Unsupported delivery mode %d\n",
	270	delivery_mode);
	271	break;
	272	}
ff4b9df8	273	return r;
1fd4f2a5 ED	274	}
	275
	276	void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
	277	{
	278	u32 old_irr = ioapic->irr;
	279	u32 mask = 1 << irq;
	280	union ioapic_redir_entry entry;
	281
	282	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
	283	entry = ioapic->redirtbl[irq];
	284	level ^= entry.fields.polarity;
	285	if (!level)
	286	ioapic->irr &= ~mask;
	287	else {
	288	ioapic->irr \|= mask;
	289	if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
	290	\|\| !entry.fields.remote_irr)
	291	ioapic_service(ioapic, irq);
	292	}
	293	}
	294	}
	295
44882eed	296	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
f5244726	297	int trigger_mode)
1fd4f2a5	298	{
1fd4f2a5	299	union ioapic_redir_entry *ent;
1fd4f2a5	300
44882eed	301	ent = &ioapic->redirtbl[pin];
1fd4f2a5	302
44882eed	303	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
f5244726 MT	304
	305	if (trigger_mode == IOAPIC_LEVEL_TRIG) {
	306	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
	307	ent->fields.remote_irr = 0;
44882eed MT	308	if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
44882eed MT	309	ioapic_service(ioapic, pin);
f5244726	310	}
1fd4f2a5 ED	311	}
1fd4f2a5 ED	312
f5244726	313	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	314	{
	315	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	316	int i;
	317
	318	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	319	if (ioapic->redirtbl[i].fields.vector == vector)
f5244726	320	__kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
4fa6b9c5 AK	321	}
4fa6b9c5 AK	322
92760499 LV	323	static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	324	int len, int is_write)
1fd4f2a5 ED	325	{
	326	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	327
	328	return ((addr >= ioapic->base_address &&
	329	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	330	}
	331
	332	static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
	333	void *val)
	334	{
	335	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	336	u32 result;
	337
e25e3ed5	338	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	339	ASSERT(!(addr & 0xf)); /* check alignment */
	340
	341	addr &= 0xff;
	342	switch (addr) {
	343	case IOAPIC_REG_SELECT:
	344	result = ioapic->ioregsel;
	345	break;
	346
	347	case IOAPIC_REG_WINDOW:
	348	result = ioapic_read_indirect(ioapic, addr, len);
	349	break;
	350
	351	default:
	352	result = 0;
	353	break;
	354	}
	355	switch (len) {
	356	case 8:
	357	(u64 ) val = result;
	358	break;
	359	case 1:
	360	case 2:
	361	case 4:
	362	memcpy(val, (char *)&result, len);
	363	break;
	364	default:
	365	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	366	}
	367	}
	368
	369	static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
	370	const void *val)
	371	{
	372	struct kvm_ioapic ioapic = (struct kvm_ioapic )this->private;
	373	u32 data;
	374
e25e3ed5 LV	375	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	376	(void*)addr, len, val);
1fd4f2a5 ED	377	ASSERT(!(addr & 0xf)); /* check alignment */
	378	if (len == 4 \|\| len == 8)
	379	data = (u32 ) val;
	380	else {
	381	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
	382	return;
	383	}
	384
	385	addr &= 0xff;
	386	switch (addr) {
	387	case IOAPIC_REG_SELECT:
	388	ioapic->ioregsel = data;
	389	break;
	390
	391	case IOAPIC_REG_WINDOW:
	392	ioapic_write_indirect(ioapic, data);
	393	break;
b1fd3d30 ZX	394	#ifdef CONFIG_IA64
b1fd3d30 ZX	395	case IOAPIC_REG_EOI:
26815a64	396	kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	397	break;
b1fd3d30 ZX	398	#endif
1fd4f2a5 ED	399
	400	default:
	401	break;
	402	}
	403	}
	404
8c392696 ED	405	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	406	{
	407	int i;
	408
	409	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	410	ioapic->redirtbl[i].fields.mask = 1;
	411	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	412	ioapic->ioregsel = 0;
	413	ioapic->irr = 0;
	414	ioapic->id = 0;
	415	}
	416
1fd4f2a5 ED	417	int kvm_ioapic_init(struct kvm *kvm)
	418	{
	419	struct kvm_ioapic *ioapic;
1fd4f2a5 ED	420
	421	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	422	if (!ioapic)
	423	return -ENOMEM;
d7deeeb0	424	kvm->arch.vioapic = ioapic;
8c392696	425	kvm_ioapic_reset(ioapic);
1fd4f2a5 ED	426	ioapic->dev.read = ioapic_mmio_read;
	427	ioapic->dev.write = ioapic_mmio_write;
	428	ioapic->dev.in_range = ioapic_in_range;
	429	ioapic->dev.private = ioapic;
	430	ioapic->kvm = kvm;
	431	kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
	432	return 0;
	433	}
75858a84	434