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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 KM |
21 | |
22 | #define DO_FMT 0x0000 | |
23 | #define DOFF_CTL 0x0004 | |
24 | #define DOFF_ST 0x0008 | |
25 | #define DI_FMT 0x000C | |
26 | #define DIFF_CTL 0x0010 | |
27 | #define DIFF_ST 0x0014 | |
28 | #define CKG1 0x0018 | |
29 | #define CKG2 0x001C | |
30 | #define DIDT 0x0020 | |
31 | #define DODT 0x0024 | |
32 | #define MUTE_ST 0x0028 | |
3bc28070 KM |
33 | #define OUT_SEL 0x0030 |
34 | #define REG_END OUT_SEL | |
cc780d38 | 35 | |
3bc28070 KM |
36 | #define A_MST_CTLR 0x0180 |
37 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
38 | #define CPU_INT_ST 0x01F4 |
39 | #define CPU_IEMSK 0x01F8 | |
40 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
41 | #define INT_ST 0x0200 |
42 | #define IEMSK 0x0204 | |
43 | #define IMSK 0x0208 | |
44 | #define MUTE 0x020C | |
45 | #define CLK_RST 0x0210 | |
46 | #define SOFT_RST 0x0214 | |
4a942b45 | 47 | #define FIFO_SZ 0x0218 |
3bc28070 | 48 | #define MREG_START A_MST_CTLR |
4a942b45 | 49 | #define MREG_END FIFO_SZ |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
a7ffb52b KM |
53 | #define CR_MONO (0x0 << 4) |
54 | #define CR_MONO_D (0x1 << 4) | |
55 | #define CR_PCM (0x2 << 4) | |
56 | #define CR_I2S (0x3 << 4) | |
57 | #define CR_TDM (0x4 << 4) | |
58 | #define CR_TDM_D (0x5 << 4) | |
3bc28070 | 59 | #define CR_SPDIF 0x00100120 |
a4d7d550 KM |
60 | |
61 | /* DOFF_CTL */ | |
62 | /* DIFF_CTL */ | |
63 | #define IRQ_HALF 0x00100000 | |
64 | #define FIFO_CLR 0x00000001 | |
65 | ||
66 | /* DOFF_ST */ | |
67 | #define ERR_OVER 0x00000010 | |
68 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 69 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 70 | |
ccad7b44 KM |
71 | /* CKG1 */ |
72 | #define ACKMD_MASK 0x00007000 | |
73 | #define BPFMD_MASK 0x00000700 | |
74 | ||
3bc28070 KM |
75 | /* A/B MST_CTLR */ |
76 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
77 | #define SE (1 << 0) /* Fix the master clock */ | |
78 | ||
a4d7d550 KM |
79 | /* CLK_RST */ |
80 | #define B_CLK 0x00000010 | |
81 | #define A_CLK 0x00000001 | |
82 | ||
cf6edd00 KM |
83 | /* IO SHIFT / MACRO */ |
84 | #define BI_SHIFT 12 | |
85 | #define BO_SHIFT 8 | |
86 | #define AI_SHIFT 4 | |
87 | #define AO_SHIFT 0 | |
88 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 89 | |
feb58cff KM |
90 | /* SOFT_RST */ |
91 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
92 | #define PASR (1 << 8) /* Port A Software Reset */ | |
93 | #define IR (1 << 4) /* Interrupt Reset */ | |
94 | #define FSISR (1 << 0) /* Software Reset */ | |
95 | ||
4a942b45 | 96 | /* FIFO_SZ */ |
cf6edd00 | 97 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 98 | |
a4d7d550 KM |
99 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
100 | ||
101 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
102 | ||
5bfb9ad0 KM |
103 | /* |
104 | * FSI driver use below type name for variable | |
105 | * | |
106 | * xxx_len : data length | |
107 | * xxx_width : data width | |
108 | * xxx_offset : data offset | |
109 | * xxx_num : number of data | |
110 | */ | |
111 | ||
c8fe2574 KM |
112 | /* |
113 | * struct | |
114 | */ | |
a4d7d550 | 115 | |
93193c2b | 116 | struct fsi_stream { |
a4d7d550 KM |
117 | struct snd_pcm_substream *substream; |
118 | ||
5bfb9ad0 KM |
119 | int fifo_max_num; |
120 | int chan_num; | |
a4d7d550 | 121 | |
5bfb9ad0 KM |
122 | int buff_offset; |
123 | int buff_len; | |
a4d7d550 | 124 | int period_len; |
5bfb9ad0 | 125 | int period_num; |
93193c2b KM |
126 | }; |
127 | ||
128 | struct fsi_priv { | |
129 | void __iomem *base; | |
130 | struct fsi_master *master; | |
131 | ||
132 | struct fsi_stream playback; | |
133 | struct fsi_stream capture; | |
3bc28070 KM |
134 | |
135 | u32 mst_ctrl; | |
a4d7d550 KM |
136 | }; |
137 | ||
73b92c1f KM |
138 | struct fsi_core { |
139 | int ver; | |
140 | ||
cc780d38 KM |
141 | u32 int_st; |
142 | u32 iemsk; | |
143 | u32 imsk; | |
144 | }; | |
145 | ||
a4d7d550 KM |
146 | struct fsi_master { |
147 | void __iomem *base; | |
148 | int irq; | |
a4d7d550 KM |
149 | struct fsi_priv fsia; |
150 | struct fsi_priv fsib; | |
73b92c1f | 151 | struct fsi_core *core; |
a4d7d550 | 152 | struct sh_fsi_platform_info *info; |
8fc176d5 | 153 | spinlock_t lock; |
a4d7d550 KM |
154 | }; |
155 | ||
c8fe2574 KM |
156 | /* |
157 | * basic read write function | |
158 | */ | |
a4d7d550 | 159 | |
0f69d978 | 160 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
161 | { |
162 | /* valid data area is 24bit */ | |
163 | data &= 0x00ffffff; | |
164 | ||
0f69d978 | 165 | __raw_writel(data, reg); |
a4d7d550 KM |
166 | } |
167 | ||
168 | static u32 __fsi_reg_read(u32 reg) | |
169 | { | |
0f69d978 | 170 | return __raw_readl(reg); |
a4d7d550 KM |
171 | } |
172 | ||
0f69d978 | 173 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
174 | { |
175 | u32 val = __fsi_reg_read(reg); | |
176 | ||
177 | val &= ~mask; | |
178 | val |= data & mask; | |
179 | ||
0f69d978 | 180 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
181 | } |
182 | ||
0f69d978 | 183 | static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) |
a4d7d550 | 184 | { |
d7854147 KM |
185 | if (reg > REG_END) { |
186 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 187 | return; |
d7854147 | 188 | } |
a4d7d550 | 189 | |
0f69d978 | 190 | __fsi_reg_write((u32)(fsi->base + reg), data); |
a4d7d550 KM |
191 | } |
192 | ||
193 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
194 | { | |
d7854147 KM |
195 | if (reg > REG_END) { |
196 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 197 | return 0; |
d7854147 | 198 | } |
a4d7d550 KM |
199 | |
200 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
201 | } | |
202 | ||
0f69d978 | 203 | static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) |
a4d7d550 | 204 | { |
d7854147 KM |
205 | if (reg > REG_END) { |
206 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 207 | return; |
d7854147 | 208 | } |
a4d7d550 | 209 | |
0f69d978 | 210 | __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); |
a4d7d550 KM |
211 | } |
212 | ||
0f69d978 | 213 | static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 | 214 | { |
8fc176d5 KM |
215 | unsigned long flags; |
216 | ||
a4d7d550 | 217 | if ((reg < MREG_START) || |
d7854147 KM |
218 | (reg > MREG_END)) { |
219 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 220 | return; |
d7854147 | 221 | } |
a4d7d550 | 222 | |
8fc176d5 | 223 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 224 | __fsi_reg_write((u32)(master->base + reg), data); |
8fc176d5 | 225 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
226 | } |
227 | ||
71f6e064 | 228 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 | 229 | { |
8fc176d5 KM |
230 | u32 ret; |
231 | unsigned long flags; | |
232 | ||
a4d7d550 | 233 | if ((reg < MREG_START) || |
d7854147 KM |
234 | (reg > MREG_END)) { |
235 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 236 | return 0; |
d7854147 | 237 | } |
a4d7d550 | 238 | |
8fc176d5 KM |
239 | spin_lock_irqsave(&master->lock, flags); |
240 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
241 | spin_unlock_irqrestore(&master->lock, flags); | |
242 | ||
243 | return ret; | |
a4d7d550 KM |
244 | } |
245 | ||
0f69d978 | 246 | static void fsi_master_mask_set(struct fsi_master *master, |
71f6e064 | 247 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 248 | { |
8fc176d5 KM |
249 | unsigned long flags; |
250 | ||
a4d7d550 | 251 | if ((reg < MREG_START) || |
d7854147 KM |
252 | (reg > MREG_END)) { |
253 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 254 | return; |
d7854147 | 255 | } |
a4d7d550 | 256 | |
8fc176d5 | 257 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 258 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 259 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
260 | } |
261 | ||
c8fe2574 KM |
262 | /* |
263 | * basic function | |
264 | */ | |
a4d7d550 | 265 | |
71f6e064 | 266 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 267 | { |
71f6e064 | 268 | return fsi->master; |
a4d7d550 KM |
269 | } |
270 | ||
271 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
272 | { | |
71f6e064 KM |
273 | return fsi->master->base == fsi->base; |
274 | } | |
a4d7d550 | 275 | |
142e8174 | 276 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
277 | { |
278 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 279 | |
f0fba2ad | 280 | return rtd->cpu_dai; |
142e8174 KM |
281 | } |
282 | ||
283 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
284 | { | |
285 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
f0fba2ad | 286 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 287 | |
f0fba2ad LG |
288 | if (dai->id == 0) |
289 | return &master->fsia; | |
290 | else | |
291 | return &master->fsib; | |
a4d7d550 KM |
292 | } |
293 | ||
294 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
295 | { | |
296 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 297 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
298 | |
299 | return is_porta ? master->info->porta_flags : | |
300 | master->info->portb_flags; | |
301 | } | |
302 | ||
93193c2b KM |
303 | static inline int fsi_stream_is_play(int stream) |
304 | { | |
305 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
306 | } | |
307 | ||
00545785 KM |
308 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
309 | { | |
93193c2b KM |
310 | return fsi_stream_is_play(substream->stream); |
311 | } | |
312 | ||
313 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
314 | int is_play) | |
315 | { | |
316 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
317 | } |
318 | ||
a4d7d550 KM |
319 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) |
320 | { | |
321 | u32 mode; | |
322 | u32 flags = fsi_get_info_flags(fsi); | |
323 | ||
324 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
325 | ||
326 | /* return | |
327 | * 1 : master mode | |
328 | * 0 : slave mode | |
329 | */ | |
330 | ||
331 | return (mode & flags) != mode; | |
332 | } | |
333 | ||
cf6edd00 | 334 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
335 | { |
336 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 337 | u32 shift; |
a4d7d550 KM |
338 | |
339 | if (is_porta) | |
cf6edd00 | 340 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 341 | else |
cf6edd00 | 342 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 343 | |
cf6edd00 | 344 | return shift; |
a4d7d550 KM |
345 | } |
346 | ||
347 | static void fsi_stream_push(struct fsi_priv *fsi, | |
93193c2b | 348 | int is_play, |
a4d7d550 KM |
349 | struct snd_pcm_substream *substream, |
350 | u32 buffer_len, | |
351 | u32 period_len) | |
352 | { | |
93193c2b KM |
353 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
354 | ||
355 | io->substream = substream; | |
356 | io->buff_len = buffer_len; | |
357 | io->buff_offset = 0; | |
358 | io->period_len = period_len; | |
359 | io->period_num = 0; | |
a4d7d550 KM |
360 | } |
361 | ||
93193c2b | 362 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 363 | { |
93193c2b KM |
364 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
365 | ||
366 | io->substream = NULL; | |
367 | io->buff_len = 0; | |
368 | io->buff_offset = 0; | |
369 | io->period_len = 0; | |
370 | io->period_num = 0; | |
a4d7d550 KM |
371 | } |
372 | ||
5bfb9ad0 | 373 | static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
374 | { |
375 | u32 status; | |
376 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
93193c2b | 377 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
5bfb9ad0 | 378 | int data_num; |
a4d7d550 KM |
379 | |
380 | status = fsi_reg_read(fsi, reg); | |
5bfb9ad0 | 381 | data_num = 0x1ff & (status >> 8); |
93193c2b | 382 | data_num *= io->chan_num; |
5bfb9ad0 KM |
383 | |
384 | return data_num; | |
385 | } | |
a4d7d550 | 386 | |
5bfb9ad0 KM |
387 | static int fsi_len2num(int len, int width) |
388 | { | |
389 | return len / width; | |
390 | } | |
391 | ||
392 | #define fsi_num2offset(a, b) fsi_num2len(a, b) | |
393 | static int fsi_num2len(int num, int width) | |
394 | { | |
395 | return num * width; | |
a4d7d550 KM |
396 | } |
397 | ||
93193c2b | 398 | static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) |
cca1b235 | 399 | { |
93193c2b KM |
400 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
401 | struct snd_pcm_substream *substream = io->substream; | |
cca1b235 KM |
402 | struct snd_pcm_runtime *runtime = substream->runtime; |
403 | ||
93193c2b | 404 | return frames_to_bytes(runtime, 1) / io->chan_num; |
cca1b235 KM |
405 | } |
406 | ||
b9fde18c KM |
407 | /* |
408 | * dma function | |
409 | */ | |
410 | ||
93193c2b | 411 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 412 | { |
93193c2b KM |
413 | int is_play = fsi_stream_is_play(stream); |
414 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
415 | ||
416 | return io->substream->runtime->dma_area + io->buff_offset; | |
c79eab3e KM |
417 | } |
418 | ||
5bfb9ad0 | 419 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
420 | { |
421 | u16 *start; | |
422 | int i; | |
423 | ||
93193c2b | 424 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 425 | |
5bfb9ad0 | 426 | for (i = 0; i < num; i++) |
b9fde18c KM |
427 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
428 | } | |
429 | ||
5bfb9ad0 | 430 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
431 | { |
432 | u16 *start; | |
433 | int i; | |
434 | ||
93193c2b KM |
435 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
436 | ||
b9fde18c | 437 | |
5bfb9ad0 | 438 | for (i = 0; i < num; i++) |
b9fde18c KM |
439 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
440 | } | |
441 | ||
5bfb9ad0 | 442 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
443 | { |
444 | u32 *start; | |
445 | int i; | |
446 | ||
93193c2b KM |
447 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
448 | ||
b9fde18c | 449 | |
5bfb9ad0 | 450 | for (i = 0; i < num; i++) |
b9fde18c KM |
451 | fsi_reg_write(fsi, DODT, *(start + i)); |
452 | } | |
453 | ||
5bfb9ad0 | 454 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
455 | { |
456 | u32 *start; | |
457 | int i; | |
458 | ||
93193c2b | 459 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 460 | |
5bfb9ad0 | 461 | for (i = 0; i < num; i++) |
b9fde18c KM |
462 | *(start + i) = fsi_reg_read(fsi, DIDT); |
463 | } | |
464 | ||
c8fe2574 KM |
465 | /* |
466 | * irq function | |
467 | */ | |
a4d7d550 | 468 | |
a4d7d550 KM |
469 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
470 | { | |
cf6edd00 | 471 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 472 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 473 | |
73b92c1f KM |
474 | fsi_master_mask_set(master, master->core->imsk, data, data); |
475 | fsi_master_mask_set(master, master->core->iemsk, data, data); | |
a4d7d550 KM |
476 | } |
477 | ||
478 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
479 | { | |
cf6edd00 | 480 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 481 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 482 | |
73b92c1f KM |
483 | fsi_master_mask_set(master, master->core->imsk, data, 0); |
484 | fsi_master_mask_set(master, master->core->iemsk, data, 0); | |
a4d7d550 KM |
485 | } |
486 | ||
10ea76cc KM |
487 | static u32 fsi_irq_get_status(struct fsi_master *master) |
488 | { | |
73b92c1f | 489 | return fsi_master_read(master, master->core->int_st); |
10ea76cc KM |
490 | } |
491 | ||
492 | static void fsi_irq_clear_all_status(struct fsi_master *master) | |
493 | { | |
73b92c1f | 494 | fsi_master_write(master, master->core->int_st, 0); |
a4d7d550 KM |
495 | } |
496 | ||
10ea76cc KM |
497 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
498 | { | |
499 | u32 data = 0; | |
500 | struct fsi_master *master = fsi_get_master(fsi); | |
501 | ||
cf6edd00 KM |
502 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
503 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
504 | |
505 | /* clear interrupt factor */ | |
73b92c1f | 506 | fsi_master_mask_set(master, master->core->int_st, data, 0); |
10ea76cc KM |
507 | } |
508 | ||
c8fe2574 KM |
509 | /* |
510 | * SPDIF master clock function | |
511 | * | |
512 | * These functions are used later FSI2 | |
513 | */ | |
3bc28070 KM |
514 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
515 | { | |
516 | struct fsi_master *master = fsi_get_master(fsi); | |
517 | u32 val = BP | SE; | |
518 | ||
519 | if (master->core->ver < 2) { | |
520 | pr_err("fsi: register access err (%s)\n", __func__); | |
521 | return; | |
522 | } | |
523 | ||
524 | if (enable) | |
525 | fsi_master_mask_set(master, fsi->mst_ctrl, val, val); | |
526 | else | |
527 | fsi_master_mask_set(master, fsi->mst_ctrl, val, 0); | |
528 | } | |
529 | ||
c8fe2574 KM |
530 | /* |
531 | * ctrl function | |
532 | */ | |
10ea76cc | 533 | |
a4d7d550 KM |
534 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
535 | { | |
536 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 537 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
538 | |
539 | if (enable) | |
71f6e064 | 540 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 541 | else |
71f6e064 | 542 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
543 | } |
544 | ||
4a942b45 KM |
545 | static void fsi_fifo_init(struct fsi_priv *fsi, |
546 | int is_play, | |
547 | struct snd_soc_dai *dai) | |
a4d7d550 | 548 | { |
4a942b45 | 549 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 550 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
4a942b45 | 551 | u32 ctrl, shift, i; |
a4d7d550 | 552 | |
4a942b45 KM |
553 | /* get on-chip RAM capacity */ |
554 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
555 | shift >>= fsi_get_port_shift(fsi, is_play); |
556 | shift &= FIFO_SZ_MASK; | |
93193c2b KM |
557 | io->fifo_max_num = 256 << shift; |
558 | dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); | |
a4d7d550 | 559 | |
4a942b45 KM |
560 | /* |
561 | * The maximum number of sample data varies depending | |
562 | * on the number of channels selected for the format. | |
563 | * | |
564 | * FIFOs are used in 4-channel units in 3-channel mode | |
565 | * and in 8-channel units in 5- to 7-channel mode | |
566 | * meaning that more FIFOs than the required size of DPRAM | |
567 | * are used. | |
568 | * | |
569 | * ex) if 256 words of DP-RAM is connected | |
570 | * 1 channel: 256 (256 x 1 = 256) | |
571 | * 2 channels: 128 (128 x 2 = 256) | |
572 | * 3 channels: 64 ( 64 x 3 = 192) | |
573 | * 4 channels: 64 ( 64 x 4 = 256) | |
574 | * 5 channels: 32 ( 32 x 5 = 160) | |
575 | * 6 channels: 32 ( 32 x 6 = 192) | |
576 | * 7 channels: 32 ( 32 x 7 = 224) | |
577 | * 8 channels: 32 ( 32 x 8 = 256) | |
578 | */ | |
93193c2b KM |
579 | for (i = 1; i < io->chan_num; i <<= 1) |
580 | io->fifo_max_num >>= 1; | |
5bfb9ad0 | 581 | dev_dbg(dai->dev, "%d channel %d store\n", |
93193c2b | 582 | io->chan_num, io->fifo_max_num); |
a4d7d550 | 583 | |
a4d7d550 | 584 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; |
a4d7d550 KM |
585 | |
586 | /* set interrupt generation factor */ | |
587 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
588 | ||
589 | /* clear FIFO */ | |
590 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
a4d7d550 KM |
591 | } |
592 | ||
71f6e064 | 593 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 594 | { |
a4d7d550 | 595 | /* port AB reset */ |
feb58cff | 596 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
597 | mdelay(10); |
598 | ||
599 | /* soft reset */ | |
feb58cff KM |
600 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
601 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
602 | mdelay(10); |
603 | } | |
604 | ||
93193c2b | 605 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream) |
a4d7d550 KM |
606 | { |
607 | struct snd_pcm_runtime *runtime; | |
608 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
609 | int is_play = fsi_stream_is_play(stream); |
610 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
d8b33534 KM |
611 | u32 status_reg = is_play ? DOFF_ST : DIFF_ST; |
612 | int data_residue_num; | |
613 | int data_num; | |
614 | int data_num_max; | |
5bfb9ad0 | 615 | int ch_width; |
b9fde18c | 616 | int over_period; |
d8b33534 | 617 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
618 | |
619 | if (!fsi || | |
93193c2b KM |
620 | !io->substream || |
621 | !io->substream->runtime) | |
a4d7d550 KM |
622 | return -EINVAL; |
623 | ||
1c418d1f | 624 | over_period = 0; |
93193c2b | 625 | substream = io->substream; |
1c418d1f | 626 | runtime = substream->runtime; |
a4d7d550 KM |
627 | |
628 | /* FSI FIFO has limit. | |
629 | * So, this driver can not send periods data at a time | |
630 | */ | |
93193c2b KM |
631 | if (io->buff_offset >= |
632 | fsi_num2offset(io->period_num + 1, io->period_len)) { | |
a4d7d550 | 633 | |
1c418d1f | 634 | over_period = 1; |
93193c2b | 635 | io->period_num = (io->period_num + 1) % runtime->periods; |
a4d7d550 | 636 | |
93193c2b KM |
637 | if (0 == io->period_num) |
638 | io->buff_offset = 0; | |
a4d7d550 KM |
639 | } |
640 | ||
641 | /* get 1 channel data width */ | |
93193c2b | 642 | ch_width = fsi_get_frame_width(fsi, is_play); |
a4d7d550 | 643 | |
d8b33534 | 644 | /* get residue data number of alsa */ |
93193c2b | 645 | data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, |
d8b33534 KM |
646 | ch_width); |
647 | ||
648 | if (is_play) { | |
649 | /* | |
650 | * for play-back | |
651 | * | |
652 | * data_num_max : number of FSI fifo free space | |
653 | * data_num : number of ALSA residue data | |
654 | */ | |
93193c2b | 655 | data_num_max = io->fifo_max_num * io->chan_num; |
d8b33534 KM |
656 | data_num_max -= fsi_get_fifo_data_num(fsi, is_play); |
657 | ||
658 | data_num = data_residue_num; | |
659 | ||
660 | switch (ch_width) { | |
661 | case 2: | |
662 | fn = fsi_dma_soft_push16; | |
663 | break; | |
664 | case 4: | |
665 | fn = fsi_dma_soft_push32; | |
666 | break; | |
667 | default: | |
668 | return -EINVAL; | |
669 | } | |
670 | } else { | |
671 | /* | |
672 | * for capture | |
673 | * | |
674 | * data_num_max : number of ALSA free space | |
675 | * data_num : number of data in FSI fifo | |
676 | */ | |
677 | data_num_max = data_residue_num; | |
678 | data_num = fsi_get_fifo_data_num(fsi, is_play); | |
679 | ||
680 | switch (ch_width) { | |
681 | case 2: | |
682 | fn = fsi_dma_soft_pop16; | |
683 | break; | |
684 | case 4: | |
685 | fn = fsi_dma_soft_pop32; | |
686 | break; | |
687 | default: | |
688 | return -EINVAL; | |
689 | } | |
690 | } | |
a4d7d550 | 691 | |
d8b33534 | 692 | data_num = min(data_num, data_num_max); |
a4d7d550 | 693 | |
d8b33534 | 694 | fn(fsi, data_num); |
a4d7d550 | 695 | |
d8b33534 | 696 | /* update buff_offset */ |
93193c2b | 697 | io->buff_offset += fsi_num2offset(data_num, ch_width); |
a4d7d550 | 698 | |
d8b33534 | 699 | /* check fifo status */ |
47fc9a0a | 700 | if (!startup) { |
59c3b003 | 701 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
75eda968 | 702 | u32 status = fsi_reg_read(fsi, status_reg); |
47fc9a0a KM |
703 | |
704 | if (status & ERR_OVER) | |
705 | dev_err(dai->dev, "over run\n"); | |
706 | if (status & ERR_UNDER) | |
707 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 708 | } |
d8b33534 | 709 | fsi_reg_write(fsi, status_reg, 0); |
59c3b003 | 710 | |
d8b33534 KM |
711 | /* re-enable irq */ |
712 | fsi_irq_enable(fsi, is_play); | |
a4d7d550 | 713 | |
1c418d1f | 714 | if (over_period) |
a4d7d550 KM |
715 | snd_pcm_period_elapsed(substream); |
716 | ||
47fc9a0a | 717 | return 0; |
a4d7d550 KM |
718 | } |
719 | ||
47fc9a0a | 720 | static int fsi_data_pop(struct fsi_priv *fsi, int startup) |
07102f3c | 721 | { |
93193c2b | 722 | return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 723 | } |
07102f3c | 724 | |
d8b33534 KM |
725 | static int fsi_data_push(struct fsi_priv *fsi, int startup) |
726 | { | |
93193c2b | 727 | return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
728 | } |
729 | ||
a4d7d550 KM |
730 | static irqreturn_t fsi_interrupt(int irq, void *data) |
731 | { | |
71f6e064 | 732 | struct fsi_master *master = data; |
10ea76cc | 733 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
734 | |
735 | /* clear irq status */ | |
feb58cff KM |
736 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
737 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 738 | |
cf6edd00 | 739 | if (int_st & AB_IO(1, AO_SHIFT)) |
47fc9a0a | 740 | fsi_data_push(&master->fsia, 0); |
cf6edd00 | 741 | if (int_st & AB_IO(1, BO_SHIFT)) |
47fc9a0a | 742 | fsi_data_push(&master->fsib, 0); |
cf6edd00 | 743 | if (int_st & AB_IO(1, AI_SHIFT)) |
47fc9a0a | 744 | fsi_data_pop(&master->fsia, 0); |
cf6edd00 | 745 | if (int_st & AB_IO(1, BI_SHIFT)) |
47fc9a0a | 746 | fsi_data_pop(&master->fsib, 0); |
a4d7d550 | 747 | |
10ea76cc | 748 | fsi_irq_clear_all_status(master); |
a4d7d550 KM |
749 | |
750 | return IRQ_HANDLED; | |
751 | } | |
752 | ||
c8fe2574 KM |
753 | /* |
754 | * dai ops | |
755 | */ | |
a4d7d550 | 756 | |
a4d7d550 KM |
757 | static int fsi_dai_startup(struct snd_pcm_substream *substream, |
758 | struct snd_soc_dai *dai) | |
759 | { | |
71f6e064 | 760 | struct fsi_priv *fsi = fsi_get_priv(substream); |
3bc28070 | 761 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b KM |
762 | struct fsi_stream *io; |
763 | u32 flags = fsi_get_info_flags(fsi); | |
a4d7d550 KM |
764 | u32 fmt; |
765 | u32 reg; | |
766 | u32 data; | |
00545785 | 767 | int is_play = fsi_is_play(substream); |
a4d7d550 | 768 | int is_master; |
a4d7d550 | 769 | |
93193c2b KM |
770 | io = fsi_get_stream(fsi, is_play); |
771 | ||
785d1c45 | 772 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
773 | |
774 | /* CKG1 */ | |
775 | data = is_play ? (1 << 0) : (1 << 4); | |
776 | is_master = fsi_is_master_mode(fsi, is_play); | |
777 | if (is_master) | |
778 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
779 | else | |
780 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
781 | ||
782 | /* clock inversion (CKG2) */ | |
783 | data = 0; | |
b427b44c KM |
784 | if (SH_FSI_LRM_INV & flags) |
785 | data |= 1 << 12; | |
786 | if (SH_FSI_BRM_INV & flags) | |
787 | data |= 1 << 8; | |
788 | if (SH_FSI_LRS_INV & flags) | |
789 | data |= 1 << 4; | |
790 | if (SH_FSI_BRS_INV & flags) | |
791 | data |= 1 << 0; | |
792 | ||
a4d7d550 KM |
793 | fsi_reg_write(fsi, CKG2, data); |
794 | ||
795 | /* do fmt, di fmt */ | |
796 | data = 0; | |
797 | reg = is_play ? DO_FMT : DI_FMT; | |
798 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
799 | switch (fmt) { | |
800 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 801 | data = CR_MONO; |
93193c2b | 802 | io->chan_num = 1; |
a4d7d550 KM |
803 | break; |
804 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 805 | data = CR_MONO_D; |
93193c2b | 806 | io->chan_num = 1; |
a4d7d550 KM |
807 | break; |
808 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 809 | data = CR_PCM; |
93193c2b | 810 | io->chan_num = 2; |
a4d7d550 KM |
811 | break; |
812 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 813 | data = CR_I2S; |
93193c2b | 814 | io->chan_num = 2; |
a4d7d550 KM |
815 | break; |
816 | case SH_FSI_FMT_TDM: | |
93193c2b | 817 | io->chan_num = is_play ? |
a4d7d550 | 818 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 819 | data = CR_TDM | (io->chan_num - 1); |
a4d7d550 KM |
820 | break; |
821 | case SH_FSI_FMT_TDM_DELAY: | |
93193c2b | 822 | io->chan_num = is_play ? |
a4d7d550 | 823 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 824 | data = CR_TDM_D | (io->chan_num - 1); |
a4d7d550 | 825 | break; |
3bc28070 KM |
826 | case SH_FSI_FMT_SPDIF: |
827 | if (master->core->ver < 2) { | |
828 | dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
829 | return -EINVAL; | |
830 | } | |
831 | data = CR_SPDIF; | |
93193c2b | 832 | io->chan_num = 2; |
3bc28070 KM |
833 | fsi_spdif_clk_ctrl(fsi, 1); |
834 | fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010); | |
835 | break; | |
a4d7d550 KM |
836 | default: |
837 | dev_err(dai->dev, "unknown format.\n"); | |
838 | return -EINVAL; | |
839 | } | |
a4d7d550 | 840 | fsi_reg_write(fsi, reg, data); |
a4d7d550 | 841 | |
10ea76cc KM |
842 | /* irq clear */ |
843 | fsi_irq_disable(fsi, is_play); | |
844 | fsi_irq_clear_status(fsi); | |
845 | ||
846 | /* fifo init */ | |
4a942b45 | 847 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 | 848 | |
a68a3b4e | 849 | return 0; |
a4d7d550 KM |
850 | } |
851 | ||
852 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
853 | struct snd_soc_dai *dai) | |
854 | { | |
71f6e064 | 855 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 856 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
857 | |
858 | fsi_irq_disable(fsi, is_play); | |
859 | fsi_clk_ctrl(fsi, 0); | |
860 | ||
785d1c45 | 861 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
862 | } |
863 | ||
864 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
865 | struct snd_soc_dai *dai) | |
866 | { | |
71f6e064 | 867 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 868 | struct snd_pcm_runtime *runtime = substream->runtime; |
00545785 | 869 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
870 | int ret = 0; |
871 | ||
a4d7d550 KM |
872 | switch (cmd) { |
873 | case SNDRV_PCM_TRIGGER_START: | |
93193c2b | 874 | fsi_stream_push(fsi, is_play, substream, |
a4d7d550 KM |
875 | frames_to_bytes(runtime, runtime->buffer_size), |
876 | frames_to_bytes(runtime, runtime->period_size)); | |
47fc9a0a | 877 | ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); |
a4d7d550 KM |
878 | break; |
879 | case SNDRV_PCM_TRIGGER_STOP: | |
880 | fsi_irq_disable(fsi, is_play); | |
93193c2b | 881 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
882 | break; |
883 | } | |
884 | ||
885 | return ret; | |
886 | } | |
887 | ||
ccad7b44 KM |
888 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
889 | struct snd_pcm_hw_params *params, | |
890 | struct snd_soc_dai *dai) | |
891 | { | |
892 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
893 | struct fsi_master *master = fsi_get_master(fsi); | |
894 | int (*set_rate)(int is_porta, int rate) = master->info->set_rate; | |
895 | int fsi_ver = master->core->ver; | |
00545785 | 896 | int is_play = fsi_is_play(substream); |
ccad7b44 KM |
897 | int ret; |
898 | ||
899 | /* if slave mode, set_rate is not needed */ | |
900 | if (!fsi_is_master_mode(fsi, is_play)) | |
901 | return 0; | |
902 | ||
903 | /* it is error if no set_rate */ | |
904 | if (!set_rate) | |
905 | return -EIO; | |
906 | ||
ccad7b44 KM |
907 | ret = set_rate(fsi_is_port_a(fsi), params_rate(params)); |
908 | if (ret > 0) { | |
909 | u32 data = 0; | |
910 | ||
911 | switch (ret & SH_FSI_ACKMD_MASK) { | |
912 | default: | |
913 | /* FALL THROUGH */ | |
914 | case SH_FSI_ACKMD_512: | |
915 | data |= (0x0 << 12); | |
916 | break; | |
917 | case SH_FSI_ACKMD_256: | |
918 | data |= (0x1 << 12); | |
919 | break; | |
920 | case SH_FSI_ACKMD_128: | |
921 | data |= (0x2 << 12); | |
922 | break; | |
923 | case SH_FSI_ACKMD_64: | |
924 | data |= (0x3 << 12); | |
925 | break; | |
926 | case SH_FSI_ACKMD_32: | |
927 | if (fsi_ver < 2) | |
928 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
929 | else | |
930 | data |= (0x4 << 12); | |
931 | break; | |
932 | } | |
933 | ||
934 | switch (ret & SH_FSI_BPFMD_MASK) { | |
935 | default: | |
936 | /* FALL THROUGH */ | |
937 | case SH_FSI_BPFMD_32: | |
938 | data |= (0x0 << 8); | |
939 | break; | |
940 | case SH_FSI_BPFMD_64: | |
941 | data |= (0x1 << 8); | |
942 | break; | |
943 | case SH_FSI_BPFMD_128: | |
944 | data |= (0x2 << 8); | |
945 | break; | |
946 | case SH_FSI_BPFMD_256: | |
947 | data |= (0x3 << 8); | |
948 | break; | |
949 | case SH_FSI_BPFMD_512: | |
950 | data |= (0x4 << 8); | |
951 | break; | |
952 | case SH_FSI_BPFMD_16: | |
953 | if (fsi_ver < 2) | |
954 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
955 | else | |
956 | data |= (0x7 << 8); | |
957 | break; | |
958 | } | |
959 | ||
960 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
961 | udelay(10); | |
962 | fsi_clk_ctrl(fsi, 1); | |
963 | ret = 0; | |
964 | } | |
ccad7b44 KM |
965 | |
966 | return ret; | |
967 | ||
968 | } | |
969 | ||
a4d7d550 KM |
970 | static struct snd_soc_dai_ops fsi_dai_ops = { |
971 | .startup = fsi_dai_startup, | |
972 | .shutdown = fsi_dai_shutdown, | |
973 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 974 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
975 | }; |
976 | ||
c8fe2574 KM |
977 | /* |
978 | * pcm ops | |
979 | */ | |
a4d7d550 | 980 | |
a4d7d550 KM |
981 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
982 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
983 | SNDRV_PCM_INFO_MMAP | | |
984 | SNDRV_PCM_INFO_MMAP_VALID | | |
985 | SNDRV_PCM_INFO_PAUSE, | |
986 | .formats = FSI_FMTS, | |
987 | .rates = FSI_RATES, | |
988 | .rate_min = 8000, | |
989 | .rate_max = 192000, | |
990 | .channels_min = 1, | |
991 | .channels_max = 2, | |
992 | .buffer_bytes_max = 64 * 1024, | |
993 | .period_bytes_min = 32, | |
994 | .period_bytes_max = 8192, | |
995 | .periods_min = 1, | |
996 | .periods_max = 32, | |
997 | .fifo_size = 256, | |
998 | }; | |
999 | ||
1000 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1001 | { | |
1002 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1003 | int ret = 0; | |
1004 | ||
1005 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1006 | ||
1007 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1008 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1009 | ||
1010 | return ret; | |
1011 | } | |
1012 | ||
1013 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1014 | struct snd_pcm_hw_params *hw_params) | |
1015 | { | |
1016 | return snd_pcm_lib_malloc_pages(substream, | |
1017 | params_buffer_bytes(hw_params)); | |
1018 | } | |
1019 | ||
1020 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1021 | { | |
1022 | return snd_pcm_lib_free_pages(substream); | |
1023 | } | |
1024 | ||
1025 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1026 | { | |
1027 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 1028 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1029 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
a4d7d550 KM |
1030 | long location; |
1031 | ||
93193c2b | 1032 | location = (io->buff_offset - 1); |
a4d7d550 KM |
1033 | if (location < 0) |
1034 | location = 0; | |
1035 | ||
1036 | return bytes_to_frames(runtime, location); | |
1037 | } | |
1038 | ||
1039 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1040 | .open = fsi_pcm_open, | |
1041 | .ioctl = snd_pcm_lib_ioctl, | |
1042 | .hw_params = fsi_hw_params, | |
1043 | .hw_free = fsi_hw_free, | |
1044 | .pointer = fsi_pointer, | |
1045 | }; | |
1046 | ||
c8fe2574 KM |
1047 | /* |
1048 | * snd_soc_platform | |
1049 | */ | |
a4d7d550 | 1050 | |
a4d7d550 KM |
1051 | #define PREALLOC_BUFFER (32 * 1024) |
1052 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1053 | ||
1054 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1055 | { | |
1056 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1057 | } | |
1058 | ||
1059 | static int fsi_pcm_new(struct snd_card *card, | |
1060 | struct snd_soc_dai *dai, | |
1061 | struct snd_pcm *pcm) | |
1062 | { | |
1063 | /* | |
1064 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1065 | * in MMAP mode (i.e. aplay -M) | |
1066 | */ | |
1067 | return snd_pcm_lib_preallocate_pages_for_all( | |
1068 | pcm, | |
1069 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1070 | snd_dma_continuous_data(GFP_KERNEL), | |
1071 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1072 | } | |
1073 | ||
c8fe2574 KM |
1074 | /* |
1075 | * alsa struct | |
1076 | */ | |
a4d7d550 | 1077 | |
f0fba2ad | 1078 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1079 | { |
f0fba2ad | 1080 | .name = "fsia-dai", |
a4d7d550 KM |
1081 | .playback = { |
1082 | .rates = FSI_RATES, | |
1083 | .formats = FSI_FMTS, | |
1084 | .channels_min = 1, | |
1085 | .channels_max = 8, | |
1086 | }, | |
07102f3c KM |
1087 | .capture = { |
1088 | .rates = FSI_RATES, | |
1089 | .formats = FSI_FMTS, | |
1090 | .channels_min = 1, | |
1091 | .channels_max = 8, | |
1092 | }, | |
a4d7d550 KM |
1093 | .ops = &fsi_dai_ops, |
1094 | }, | |
1095 | { | |
f0fba2ad | 1096 | .name = "fsib-dai", |
a4d7d550 KM |
1097 | .playback = { |
1098 | .rates = FSI_RATES, | |
1099 | .formats = FSI_FMTS, | |
1100 | .channels_min = 1, | |
1101 | .channels_max = 8, | |
1102 | }, | |
07102f3c KM |
1103 | .capture = { |
1104 | .rates = FSI_RATES, | |
1105 | .formats = FSI_FMTS, | |
1106 | .channels_min = 1, | |
1107 | .channels_max = 8, | |
1108 | }, | |
a4d7d550 KM |
1109 | .ops = &fsi_dai_ops, |
1110 | }, | |
1111 | }; | |
a4d7d550 | 1112 | |
f0fba2ad LG |
1113 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1114 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1115 | .pcm_new = fsi_pcm_new, |
1116 | .pcm_free = fsi_pcm_free, | |
1117 | }; | |
a4d7d550 | 1118 | |
c8fe2574 KM |
1119 | /* |
1120 | * platform function | |
1121 | */ | |
a4d7d550 | 1122 | |
a4d7d550 KM |
1123 | static int fsi_probe(struct platform_device *pdev) |
1124 | { | |
71f6e064 | 1125 | struct fsi_master *master; |
cc780d38 | 1126 | const struct platform_device_id *id_entry; |
a4d7d550 | 1127 | struct resource *res; |
a4d7d550 KM |
1128 | unsigned int irq; |
1129 | int ret; | |
1130 | ||
cc780d38 KM |
1131 | id_entry = pdev->id_entry; |
1132 | if (!id_entry) { | |
1133 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1134 | return -ENODEV; | |
1135 | } | |
1136 | ||
a4d7d550 KM |
1137 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1138 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1139 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1140 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1141 | ret = -ENODEV; | |
1142 | goto exit; | |
1143 | } | |
1144 | ||
1145 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1146 | if (!master) { | |
1147 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1148 | ret = -ENOMEM; | |
1149 | goto exit; | |
1150 | } | |
1151 | ||
1152 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1153 | if (!master->base) { | |
1154 | ret = -ENXIO; | |
1155 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1156 | goto exit_kfree; | |
1157 | } | |
1158 | ||
3bc28070 | 1159 | /* master setting */ |
a4d7d550 KM |
1160 | master->irq = irq; |
1161 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1162 | master->core = (struct fsi_core *)id_entry->driver_data; |
1163 | spin_lock_init(&master->lock); | |
1164 | ||
1165 | /* FSI A setting */ | |
a4d7d550 | 1166 | master->fsia.base = master->base; |
71f6e064 | 1167 | master->fsia.master = master; |
3bc28070 KM |
1168 | master->fsia.mst_ctrl = A_MST_CTLR; |
1169 | ||
1170 | /* FSI B setting */ | |
a4d7d550 | 1171 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1172 | master->fsib.master = master; |
3bc28070 | 1173 | master->fsib.mst_ctrl = B_MST_CTLR; |
a4d7d550 | 1174 | |
785d1c45 KM |
1175 | pm_runtime_enable(&pdev->dev); |
1176 | pm_runtime_resume(&pdev->dev); | |
f0fba2ad | 1177 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1178 | |
71f6e064 | 1179 | fsi_soft_all_reset(master); |
a4d7d550 | 1180 | |
cc780d38 KM |
1181 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1182 | id_entry->name, master); | |
a4d7d550 KM |
1183 | if (ret) { |
1184 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1185 | goto exit_iounmap; |
a4d7d550 KM |
1186 | } |
1187 | ||
f0fba2ad | 1188 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1189 | if (ret < 0) { |
1190 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1191 | goto exit_free_irq; | |
1192 | } | |
1193 | ||
f0fba2ad | 1194 | return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
a4d7d550 KM |
1195 | |
1196 | exit_free_irq: | |
1197 | free_irq(irq, master); | |
a4d7d550 KM |
1198 | exit_iounmap: |
1199 | iounmap(master->base); | |
785d1c45 | 1200 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1201 | exit_kfree: |
1202 | kfree(master); | |
1203 | master = NULL; | |
1204 | exit: | |
1205 | return ret; | |
1206 | } | |
1207 | ||
1208 | static int fsi_remove(struct platform_device *pdev) | |
1209 | { | |
71f6e064 KM |
1210 | struct fsi_master *master; |
1211 | ||
f0fba2ad | 1212 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1213 | |
f0fba2ad LG |
1214 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1215 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1216 | |
785d1c45 | 1217 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1218 | |
a4d7d550 KM |
1219 | free_irq(master->irq, master); |
1220 | ||
1221 | iounmap(master->base); | |
1222 | kfree(master); | |
71f6e064 | 1223 | |
a4d7d550 KM |
1224 | return 0; |
1225 | } | |
1226 | ||
785d1c45 KM |
1227 | static int fsi_runtime_nop(struct device *dev) |
1228 | { | |
1229 | /* Runtime PM callback shared between ->runtime_suspend() | |
1230 | * and ->runtime_resume(). Simply returns success. | |
1231 | * | |
1232 | * This driver re-initializes all registers after | |
1233 | * pm_runtime_get_sync() anyway so there is no need | |
1234 | * to save and restore registers here. | |
1235 | */ | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | static struct dev_pm_ops fsi_pm_ops = { | |
1240 | .runtime_suspend = fsi_runtime_nop, | |
1241 | .runtime_resume = fsi_runtime_nop, | |
1242 | }; | |
1243 | ||
73b92c1f KM |
1244 | static struct fsi_core fsi1_core = { |
1245 | .ver = 1, | |
1246 | ||
1247 | /* Interrupt */ | |
cc780d38 KM |
1248 | .int_st = INT_ST, |
1249 | .iemsk = IEMSK, | |
1250 | .imsk = IMSK, | |
1251 | }; | |
1252 | ||
73b92c1f KM |
1253 | static struct fsi_core fsi2_core = { |
1254 | .ver = 2, | |
1255 | ||
1256 | /* Interrupt */ | |
cc780d38 KM |
1257 | .int_st = CPU_INT_ST, |
1258 | .iemsk = CPU_IEMSK, | |
1259 | .imsk = CPU_IMSK, | |
1260 | }; | |
1261 | ||
1262 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1263 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1264 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1265 | {}, |
cc780d38 | 1266 | }; |
d85a6d7b | 1267 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1268 | |
a4d7d550 KM |
1269 | static struct platform_driver fsi_driver = { |
1270 | .driver = { | |
f0fba2ad | 1271 | .name = "fsi-pcm-audio", |
785d1c45 | 1272 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1273 | }, |
1274 | .probe = fsi_probe, | |
1275 | .remove = fsi_remove, | |
cc780d38 | 1276 | .id_table = fsi_id_table, |
a4d7d550 KM |
1277 | }; |
1278 | ||
1279 | static int __init fsi_mobile_init(void) | |
1280 | { | |
1281 | return platform_driver_register(&fsi_driver); | |
1282 | } | |
1283 | ||
1284 | static void __exit fsi_mobile_exit(void) | |
1285 | { | |
1286 | platform_driver_unregister(&fsi_driver); | |
1287 | } | |
d85a6d7b | 1288 | |
a4d7d550 KM |
1289 | module_init(fsi_mobile_init); |
1290 | module_exit(fsi_mobile_exit); | |
1291 | ||
1292 | MODULE_LICENSE("GPL"); | |
1293 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1294 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |