[net-next-2.6.git] / sound / soc / omap / omap-mcbsp.c

/*
 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Jarkko Nikula <jhnikula@gmail.com>
 *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/control.h>
#include <mach/dma.h>
#include <mach/mcbsp.h>
#include "omap-mcbsp.h"
#include "omap-pcm.h"

#define OMAP_MCBSP_RATES	(SNDRV_PCM_RATE_8000_96000)

struct omap_mcbsp_data {
	unsigned int			bus_id;
	struct omap_mcbsp_reg_cfg	regs;
	unsigned int			fmt;
	/*
	 * Flags indicating is the bus already activated and configured by
	 * another substream
	 */
	int				active;
	int				configured;
};

#define to_mcbsp(priv)	container_of((priv), struct omap_mcbsp_data, bus_id)

static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];

/*
 * Stream DMA parameters. DMA request line and port address are set runtime
 * since they are different between OMAP1 and later OMAPs
 */
static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static const int omap1_dma_reqs[][2] = {
	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
};
static const unsigned long omap1_mcbsp_port[][2] = {
	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const int omap1_dma_reqs[][2] = {};
static const unsigned long omap1_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static const int omap24xx_dma_reqs[][2] = {
	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
#endif
};
#else
static const int omap24xx_dma_reqs[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2420)
static const unsigned long omap2420_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2430)
static const unsigned long omap2430_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap2430_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
static const unsigned long omap34xx_mcbsp_port[][2] = {
	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap34xx_mcbsp_port[][2] = {};
#endif

static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
		/*
		 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
		 * Set constraint for minimum buffer size to the same than FIFO
		 * size in order to avoid underruns in playback startup because
		 * HW is keeping the DMA request active until FIFO is filled.
		 */
		snd_pcm_hw_constraint_minmax(substream->runtime,
			SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
	}

	if (!cpu_dai->active)
		err = omap_mcbsp_request(mcbsp_data->bus_id);

	return err;
}

static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	if (!cpu_dai->active) {
		omap_mcbsp_free(mcbsp_data->bus_id);
		mcbsp_data->configured = 0;
	}
}

static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!mcbsp_data->active++)
			omap_mcbsp_start(mcbsp_data->bus_id);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (!--mcbsp_data->active)
			omap_mcbsp_stop(mcbsp_data->bus_id);
		break;
	default:
		err = -EINVAL;
	}

	return err;
}

static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
	int wlen, channels, wpf;
	unsigned long port;
	unsigned int format;

	if (cpu_class_is_omap1()) {
		dma = omap1_dma_reqs[bus_id][substream->stream];
		port = omap1_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2420()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2420_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2430()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2430_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap343x()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap34xx_mcbsp_port[bus_id][substream->stream];
	} else {
		return -ENODEV;
	}
	omap_mcbsp_dai_dma_params[id][substream->stream].name =
		substream->stream ? "Audio Capture" : "Audio Playback";
	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];

	if (mcbsp_data->configured) {
		/* McBSP already configured by another stream */
		return 0;
	}

	format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
	wpf = channels = params_channels(params);
	switch (channels) {
	case 2:
		if (format == SND_SOC_DAIFMT_I2S) {
			/* Use dual-phase frames */
			regs->rcr2	|= RPHASE;
			regs->xcr2	|= XPHASE;
			/* Set 1 word per (McBSP) frame for phase1 and phase2 */
			wpf--;
			regs->rcr2	|= RFRLEN2(wpf - 1);
			regs->xcr2	|= XFRLEN2(wpf - 1);
		}
	case 1:
	case 4:
		/* Set word per (McBSP) frame for phase1 */
		regs->rcr1	|= RFRLEN1(wpf - 1);
		regs->xcr1	|= XFRLEN1(wpf - 1);
		break;
	default:
		/* Unsupported number of channels */
		return -EINVAL;
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		/* Set word lengths */
		wlen = 16;
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
		break;
	default:
		/* Unsupported PCM format */
		return -EINVAL;
	}

	/* Set FS period and length in terms of bit clock periods */
	switch (format) {
	case SND_SOC_DAIFMT_I2S:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(wlen - 1);
		break;
	case SND_SOC_DAIFMT_DSP_A:
	case SND_SOC_DAIFMT_DSP_B:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(0);
		break;
	}

	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	mcbsp_data->configured = 1;

	return 0;
}

/*
 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 * cache is initialized here
 */
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				      unsigned int fmt)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	unsigned int temp_fmt = fmt;

	if (mcbsp_data->configured)
		return 0;

	mcbsp_data->fmt = fmt;
	memset(regs, 0, sizeof(*regs));
	/* Generic McBSP register settings */
	regs->spcr2	|= XINTM(3) | FREE;
	regs->spcr1	|= RINTM(3);
	regs->rcr2	|= RFIG;
	regs->xcr2	|= XFIG;
	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
		regs->xccr = DXENDLY(1) | XDMAEN;
		regs->rccr = RFULL_CYCLE | RDMAEN;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* 1-bit data delay */
		regs->rcr2	|= RDATDLY(1);
		regs->xcr2	|= XDATDLY(1);
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* 1-bit data delay */
		regs->rcr2      |= RDATDLY(1);
		regs->xcr2      |= XDATDLY(1);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* 0-bit data delay */
		regs->rcr2      |= RDATDLY(0);
		regs->xcr2      |= XDATDLY(0);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	default:
		/* Unsupported data format */
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* McBSP master. Set FS and bit clocks as outputs */
		regs->pcr0	|= FSXM | FSRM |
				   CLKXM | CLKRM;
		/* Sample rate generator drives the FS */
		regs->srgr2	|= FSGM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* McBSP slave */
		break;
	default:
		/* Unsupported master/slave configuration */
		return -EINVAL;
	}

	/* Set bit clock (CLKX/CLKR) and FS polarities */
	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/*
		 * Normal BCLK + FS.
		 * FS active low. TX data driven on falling edge of bit clock
		 * and RX data sampled on rising edge of bit clock.
		 */
		regs->pcr0	|= FSXP | FSRP |
				   CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		regs->pcr0	|= CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		regs->pcr0	|= FSXP | FSRP;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
				     int div_id, int div)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	if (div_id != OMAP_MCBSP_CLKGDV)
		return -ENODEV;

	regs->srgr1	|= CLKGDV(div - 1);

	return 0;
}

static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
				       int clk_id)
{
	int sel_bit;
	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;

	if (cpu_class_is_omap1()) {
		/* OMAP1's can use only external source clock */
		if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
			return -EINVAL;
		else
			return 0;
	}

	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
		return -EINVAL;

	if (cpu_is_omap343x())
		reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;

	switch (mcbsp_data->bus_id) {
	case 0:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 2;
		break;
	case 1:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 6;
		break;
	case 2:
		reg = reg_devconf1;
		sel_bit = 0;
		break;
	case 3:
		reg = reg_devconf1;
		sel_bit = 2;
		break;
	case 4:
		reg = reg_devconf1;
		sel_bit = 4;
		break;
	default:
		return -EINVAL;
	}

	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
		omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	else
		omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);

	return 0;
}

static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
					 int clk_id, unsigned int freq,
					 int dir)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int err = 0;

	switch (clk_id) {
	case OMAP_MCBSP_SYSCLK_CLK:
		regs->srgr2	|= CLKSM;
		break;
	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
		err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
		break;

	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
		regs->srgr2	|= CLKSM;
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
		regs->pcr0	|= SCLKME;
		break;
	default:
		err = -ENODEV;
	}

	return err;
}

static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	.startup	= omap_mcbsp_dai_startup,
	.shutdown	= omap_mcbsp_dai_shutdown,
	.trigger	= omap_mcbsp_dai_trigger,
	.hw_params	= omap_mcbsp_dai_hw_params,
	.set_fmt	= omap_mcbsp_dai_set_dai_fmt,
	.set_clkdiv	= omap_mcbsp_dai_set_clkdiv,
	.set_sysclk	= omap_mcbsp_dai_set_dai_sysclk,
};

#define OMAP_MCBSP_DAI_BUILDER(link_id)				\
{								\
	.name = "omap-mcbsp-dai-"#link_id,			\
	.id = (link_id),					\
	.playback = {						\
		.channels_min = 1,				\
		.channels_max = 4,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.capture = {						\
		.channels_min = 1,				\
		.channels_max = 4,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.ops = &omap_mcbsp_dai_ops,				\
	.private_data = &mcbsp_data[(link_id)].bus_id,		\
}

struct snd_soc_dai omap_mcbsp_dai[] = {
	OMAP_MCBSP_DAI_BUILDER(0),
	OMAP_MCBSP_DAI_BUILDER(1),
#if NUM_LINKS >= 3
	OMAP_MCBSP_DAI_BUILDER(2),
#endif
#if NUM_LINKS == 5
	OMAP_MCBSP_DAI_BUILDER(3),
	OMAP_MCBSP_DAI_BUILDER(4),
#endif
};

EXPORT_SYMBOL_GPL(omap_mcbsp_dai);

static int __init snd_omap_mcbsp_init(void)
{
	return snd_soc_register_dais(omap_mcbsp_dai,
				     ARRAY_SIZE(omap_mcbsp_dai));
}
module_init(snd_omap_mcbsp_init);

static void __exit snd_omap_mcbsp_exit(void)
{
	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
}
module_exit(snd_omap_mcbsp_exit);

MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e74796a JN	1	/*
	2	* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
b08f7a62 JN	6	* Contact: Jarkko Nikula <jhnikula@gmail.com>
b08f7a62 JN	7	* Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a JN	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	21	* 02110-1301 USA
	22	*
	23	*/
	24
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/device.h>
	28	#include <sound/core.h>
	29	#include <sound/pcm.h>
	30	#include <sound/pcm_params.h>
	31	#include <sound/initval.h>
	32	#include <sound/soc.h>
	33
a09e64fb RK	34	#include <mach/control.h>
	35	#include <mach/dma.h>
	36	#include <mach/mcbsp.h>
2e74796a JN	37	#include "omap-mcbsp.h"
	38	#include "omap-pcm.h"
	39
0b604856	40	#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a JN	41
	42	struct omap_mcbsp_data {
	43	unsigned int bus_id;
	44	struct omap_mcbsp_reg_cfg regs;
ba9d0fd0	45	unsigned int fmt;
2e74796a JN	46	/*
	47	* Flags indicating is the bus already activated and configured by
	48	* another substream
	49	*/
	50	int active;
	51	int configured;
	52	};
	53
	54	#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
	55
	56	static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
	57
	58	/*
	59	* Stream DMA parameters. DMA request line and port address are set runtime
	60	* since they are different between OMAP1 and later OMAPs
	61	*/
2e89713a	62	static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a JN	63
	64	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX)
	65	static const int omap1_dma_reqs[][2] = {
	66	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	67	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	68	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
	69	};
	70	static const unsigned long omap1_mcbsp_port[][2] = {
	71	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	72	OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	73	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	74	OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	75	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	76	OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
	77	};
	78	#else
	79	static const int omap1_dma_reqs[][2] = {};
	80	static const unsigned long omap1_mcbsp_port[][2] = {};
	81	#endif
406e2c48 JN	82
	83	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
	84	static const int omap24xx_dma_reqs[][2] = {
2e74796a JN	85	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
2e74796a JN	86	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
406e2c48 JN	87	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP34XX)
	88	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	89	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	90	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
	91	#endif
2e74796a	92	};
406e2c48 JN	93	#else
	94	static const int omap24xx_dma_reqs[][2] = {};
	95	#endif
	96
	97	#if defined(CONFIG_ARCH_OMAP2420)
2e74796a JN	98	static const unsigned long omap2420_mcbsp_port[][2] = {
	99	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	100	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	101	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	102	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	103	};
	104	#else
2e74796a JN	105	static const unsigned long omap2420_mcbsp_port[][2] = {};
	106	#endif
	107
406e2c48 JN	108	#if defined(CONFIG_ARCH_OMAP2430)
	109	static const unsigned long omap2430_mcbsp_port[][2] = {
	110	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	111	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	112	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	113	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	114	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	115	OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	116	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	117	OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	118	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	119	OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	120	};
	121	#else
	122	static const unsigned long omap2430_mcbsp_port[][2] = {};
	123	#endif
	124
	125	#if defined(CONFIG_ARCH_OMAP34XX)
	126	static const unsigned long omap34xx_mcbsp_port[][2] = {
	127	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	128	OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	129	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	130	OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	131	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	132	OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	133	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	134	OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	135	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	136	OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	137	};
	138	#else
	139	static const unsigned long omap34xx_mcbsp_port[][2] = {};
	140	#endif
	141
dee89c4d MB	142	static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
dee89c4d MB	143	struct snd_soc_dai *dai)
2e74796a JN	144	{
2e74796a JN	145	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	146	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	147	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	148	int err = 0;
	149
6984992b JN	150	if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
	151	/*
	152	* McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
	153	* Set constraint for minimum buffer size to the same than FIFO
	154	* size in order to avoid underruns in playback startup because
	155	* HW is keeping the DMA request active until FIFO is filled.
	156	*/
	157	snd_pcm_hw_constraint_minmax(substream->runtime,
	158	SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
	159	}
	160
2e74796a JN	161	if (!cpu_dai->active)
	162	err = omap_mcbsp_request(mcbsp_data->bus_id);
	163
	164	return err;
	165	}
	166
dee89c4d MB	167	static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	168	struct snd_soc_dai *dai)
2e74796a JN	169	{
2e74796a JN	170	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	171	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	172	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	173
	174	if (!cpu_dai->active) {
	175	omap_mcbsp_free(mcbsp_data->bus_id);
	176	mcbsp_data->configured = 0;
	177	}
	178	}
	179
dee89c4d MB	180	static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	181	struct snd_soc_dai *dai)
2e74796a JN	182	{
2e74796a JN	183	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	184	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	185	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	186	int err = 0;
	187
	188	switch (cmd) {
	189	case SNDRV_PCM_TRIGGER_START:
	190	case SNDRV_PCM_TRIGGER_RESUME:
	191	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	192	if (!mcbsp_data->active++)
	193	omap_mcbsp_start(mcbsp_data->bus_id);
	194	break;
	195
	196	case SNDRV_PCM_TRIGGER_STOP:
	197	case SNDRV_PCM_TRIGGER_SUSPEND:
	198	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	199	if (!--mcbsp_data->active)
	200	omap_mcbsp_stop(mcbsp_data->bus_id);
	201	break;
	202	default:
	203	err = -EINVAL;
	204	}
	205
	206	return err;
	207	}
	208
	209	static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	210	struct snd_pcm_hw_params *params,
dee89c4d MB	211	struct snd_soc_dai *dai)
2e74796a JN	212	{
2e74796a JN	213	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	214	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	215	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	216	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	217	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
c29b206f	218	int wlen, channels, wpf;
2e74796a	219	unsigned long port;
c29b206f	220	unsigned int format;
2e74796a JN	221
	222	if (cpu_class_is_omap1()) {
	223	dma = omap1_dma_reqs[bus_id][substream->stream];
	224	port = omap1_mcbsp_port[bus_id][substream->stream];
	225	} else if (cpu_is_omap2420()) {
406e2c48	226	dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a	227	port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48 JN	228	} else if (cpu_is_omap2430()) {
	229	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	230	port = omap2430_mcbsp_port[bus_id][substream->stream];
	231	} else if (cpu_is_omap343x()) {
	232	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	233	port = omap34xx_mcbsp_port[bus_id][substream->stream];
2e74796a	234	} else {
2e74796a JN	235	return -ENODEV;
2e74796a JN	236	}
2e89713a JN	237	omap_mcbsp_dai_dma_params[id][substream->stream].name =
2e89713a JN	238	substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a JN	239	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	240	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	241	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
	242
	243	if (mcbsp_data->configured) {
	244	/* McBSP already configured by another stream */
	245	return 0;
	246	}
	247
c29b206f PU	248	format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
c29b206f PU	249	wpf = channels = params_channels(params);
375e8a7c	250	switch (channels) {
2e74796a	251	case 2:
c29b206f PU	252	if (format == SND_SOC_DAIFMT_I2S) {
	253	/* Use dual-phase frames */
	254	regs->rcr2 \|= RPHASE;
	255	regs->xcr2 \|= XPHASE;
	256	/* Set 1 word per (McBSP) frame for phase1 and phase2 */
	257	wpf--;
	258	regs->rcr2 \|= RFRLEN2(wpf - 1);
	259	regs->xcr2 \|= XFRLEN2(wpf - 1);
	260	}
375e8a7c	261	case 1:
31a00c6b	262	case 4:
c29b206f PU	263	/* Set word per (McBSP) frame for phase1 */
	264	regs->rcr1 \|= RFRLEN1(wpf - 1);
	265	regs->xcr1 \|= XFRLEN1(wpf - 1);
2e74796a JN	266	break;
	267	default:
	268	/* Unsupported number of channels */
	269	return -EINVAL;
	270	}
	271
	272	switch (params_format(params)) {
	273	case SNDRV_PCM_FORMAT_S16_LE:
	274	/* Set word lengths */
ba9d0fd0	275	wlen = 16;
2e74796a JN	276	regs->rcr2 \|= RWDLEN2(OMAP_MCBSP_WORD_16);
	277	regs->rcr1 \|= RWDLEN1(OMAP_MCBSP_WORD_16);
	278	regs->xcr2 \|= XWDLEN2(OMAP_MCBSP_WORD_16);
	279	regs->xcr1 \|= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a JN	280	break;
	281	default:
	282	/* Unsupported PCM format */
	283	return -EINVAL;
	284	}
	285
ba9d0fd0	286	/* Set FS period and length in terms of bit clock periods */
c29b206f	287	switch (format) {
ba9d0fd0	288	case SND_SOC_DAIFMT_I2S:
c29b206f	289	regs->srgr2 \|= FPER(wlen * channels - 1);
ba9d0fd0 JN	290	regs->srgr1 \|= FWID(wlen - 1);
ba9d0fd0 JN	291	break;
3ba191ce	292	case SND_SOC_DAIFMT_DSP_A:
bd25867a	293	case SND_SOC_DAIFMT_DSP_B:
375e8a7c	294	regs->srgr2 \|= FPER(wlen * channels - 1);
36ce8582	295	regs->srgr1 \|= FWID(0);
ba9d0fd0 JN	296	break;
	297	}
	298
2e74796a JN	299	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	300	mcbsp_data->configured = 1;
	301
	302	return 0;
	303	}
	304
	305	/*
	306	* This must be called before _set_clkdiv and _set_sysclk since McBSP register
	307	* cache is initialized here
	308	*/
8687eb8b	309	static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a JN	310	unsigned int fmt)
	311	{
	312	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	313	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582	314	unsigned int temp_fmt = fmt;
2e74796a JN	315
	316	if (mcbsp_data->configured)
	317	return 0;
	318
ba9d0fd0	319	mcbsp_data->fmt = fmt;
2e74796a JN	320	memset(regs, 0, sizeof(*regs));
	321	/* Generic McBSP register settings */
	322	regs->spcr2 \|= XINTM(3) \| FREE;
	323	regs->spcr1 \|= RINTM(3);
	324	regs->rcr2 \|= RFIG;
	325	regs->xcr2 \|= XFIG;
ef390c0b MLC	326	if (cpu_is_omap2430() \|\| cpu_is_omap34xx()) {
	327	regs->xccr = DXENDLY(1) \| XDMAEN;
	328	regs->rccr = RFULL_CYCLE \| RDMAEN;
	329	}
2e74796a JN	330
	331	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	332	case SND_SOC_DAIFMT_I2S:
	333	/* 1-bit data delay */
	334	regs->rcr2 \|= RDATDLY(1);
	335	regs->xcr2 \|= XDATDLY(1);
	336	break;
3ba191ce PU	337	case SND_SOC_DAIFMT_DSP_A:
	338	/* 1-bit data delay */
	339	regs->rcr2 \|= RDATDLY(1);
	340	regs->xcr2 \|= XDATDLY(1);
	341	/* Invert FS polarity configuration */
	342	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
	343	break;
bd25867a	344	case SND_SOC_DAIFMT_DSP_B:
3336c5b5 AK	345	/* 0-bit data delay */
	346	regs->rcr2 \|= RDATDLY(0);
	347	regs->xcr2 \|= XDATDLY(0);
36ce8582 JN	348	/* Invert FS polarity configuration */
36ce8582 JN	349	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5	350	break;
2e74796a JN	351	default:
	352	/* Unsupported data format */
	353	return -EINVAL;
	354	}
	355
	356	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	357	case SND_SOC_DAIFMT_CBS_CFS:
	358	/* McBSP master. Set FS and bit clocks as outputs */
	359	regs->pcr0 \|= FSXM \| FSRM \|
	360	CLKXM \| CLKRM;
	361	/* Sample rate generator drives the FS */
	362	regs->srgr2 \|= FSGM;
	363	break;
	364	case SND_SOC_DAIFMT_CBM_CFM:
	365	/* McBSP slave */
	366	break;
	367	default:
	368	/* Unsupported master/slave configuration */
	369	return -EINVAL;
	370	}
	371
	372	/* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582	373	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a JN	374	case SND_SOC_DAIFMT_NB_NF:
	375	/*
	376	* Normal BCLK + FS.
	377	* FS active low. TX data driven on falling edge of bit clock
	378	* and RX data sampled on rising edge of bit clock.
	379	*/
	380	regs->pcr0 \|= FSXP \| FSRP \|
	381	CLKXP \| CLKRP;
	382	break;
	383	case SND_SOC_DAIFMT_NB_IF:
	384	regs->pcr0 \|= CLKXP \| CLKRP;
	385	break;
	386	case SND_SOC_DAIFMT_IB_NF:
	387	regs->pcr0 \|= FSXP \| FSRP;
	388	break;
	389	case SND_SOC_DAIFMT_IB_IF:
	390	break;
	391	default:
	392	return -EINVAL;
	393	}
	394
	395	return 0;
	396	}
	397
8687eb8b	398	static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a JN	399	int div_id, int div)
	400	{
	401	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	402	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	403
	404	if (div_id != OMAP_MCBSP_CLKGDV)
	405	return -ENODEV;
	406
	407	regs->srgr1 \|= CLKGDV(div - 1);
	408
	409	return 0;
	410	}
	411
	412	static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
	413	int clk_id)
	414	{
	415	int sel_bit;
406e2c48	416	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a JN	417
	418	if (cpu_class_is_omap1()) {
	419	/* OMAP1's can use only external source clock */
	420	if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
	421	return -EINVAL;
	422	else
	423	return 0;
	424	}
	425
406e2c48 JN	426	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
	427	return -EINVAL;
	428
	429	if (cpu_is_omap343x())
	430	reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
	431
2e74796a JN	432	switch (mcbsp_data->bus_id) {
	433	case 0:
	434	reg = OMAP2_CONTROL_DEVCONF0;
	435	sel_bit = 2;
	436	break;
	437	case 1:
	438	reg = OMAP2_CONTROL_DEVCONF0;
	439	sel_bit = 6;
	440	break;
406e2c48 JN	441	case 2:
	442	reg = reg_devconf1;
	443	sel_bit = 0;
	444	break;
	445	case 3:
	446	reg = reg_devconf1;
	447	sel_bit = 2;
	448	break;
	449	case 4:
	450	reg = reg_devconf1;
	451	sel_bit = 4;
	452	break;
2e74796a JN	453	default:
	454	return -EINVAL;
	455	}
	456
406e2c48 JN	457	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
	458	omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	459	else
	460	omap_ctrl_writel(omap_ctrl_readl(reg) \| (1 << sel_bit), reg);
2e74796a JN	461
	462	return 0;
	463	}
	464
8687eb8b	465	static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a JN	466	int clk_id, unsigned int freq,
	467	int dir)
	468	{
	469	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	470	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	471	int err = 0;
	472
	473	switch (clk_id) {
	474	case OMAP_MCBSP_SYSCLK_CLK:
	475	regs->srgr2 \|= CLKSM;
	476	break;
	477	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	478	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
	479	err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
	480	break;
	481
	482	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
	483	regs->srgr2 \|= CLKSM;
	484	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
	485	regs->pcr0 \|= SCLKME;
	486	break;
	487	default:
	488	err = -ENODEV;
	489	}
	490
	491	return err;
	492	}
	493
6335d055 EM	494	static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	495	.startup = omap_mcbsp_dai_startup,
	496	.shutdown = omap_mcbsp_dai_shutdown,
	497	.trigger = omap_mcbsp_dai_trigger,
	498	.hw_params = omap_mcbsp_dai_hw_params,
	499	.set_fmt = omap_mcbsp_dai_set_dai_fmt,
	500	.set_clkdiv = omap_mcbsp_dai_set_clkdiv,
	501	.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
	502	};
	503
8def464d JN	504	#define OMAP_MCBSP_DAI_BUILDER(link_id) \
8def464d JN	505	{ \
0c758bdd	506	.name = "omap-mcbsp-dai-"#link_id, \
8def464d	507	.id = (link_id), \
8def464d	508	.playback = { \
375e8a7c	509	.channels_min = 1, \
31a00c6b	510	.channels_max = 4, \
8def464d JN	511	.rates = OMAP_MCBSP_RATES, \
	512	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	513	}, \
	514	.capture = { \
375e8a7c	515	.channels_min = 1, \
31a00c6b	516	.channels_max = 4, \
8def464d JN	517	.rates = OMAP_MCBSP_RATES, \
	518	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	519	}, \
6335d055	520	.ops = &omap_mcbsp_dai_ops, \
8def464d JN	521	.private_data = &mcbsp_data[(link_id)].bus_id, \
	522	}
	523
	524	struct snd_soc_dai omap_mcbsp_dai[] = {
	525	OMAP_MCBSP_DAI_BUILDER(0),
	526	OMAP_MCBSP_DAI_BUILDER(1),
	527	#if NUM_LINKS >= 3
	528	OMAP_MCBSP_DAI_BUILDER(2),
	529	#endif
	530	#if NUM_LINKS == 5
	531	OMAP_MCBSP_DAI_BUILDER(3),
	532	OMAP_MCBSP_DAI_BUILDER(4),
	533	#endif
2e74796a	534	};
8def464d	535
2e74796a JN	536	EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
2e74796a JN	537
f73f2a6a	538	static int __init snd_omap_mcbsp_init(void)
3f4b783c MB	539	{
	540	return snd_soc_register_dais(omap_mcbsp_dai,
	541	ARRAY_SIZE(omap_mcbsp_dai));
	542	}
f73f2a6a	543	module_init(snd_omap_mcbsp_init);
3f4b783c	544
f73f2a6a	545	static void __exit snd_omap_mcbsp_exit(void)
3f4b783c MB	546	{
	547	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
	548	}
f73f2a6a	549	module_exit(snd_omap_mcbsp_exit);
3f4b783c	550
b08f7a62	551	MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a JN	552	MODULE_DESCRIPTION("OMAP I2S SoC Interface");
2e74796a JN	553	MODULE_LICENSE("GPL");