[net-next-2.6.git] / sound / soc / davinci / davinci-i2s.c

/*
 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"


/*
 * NOTE:  terminology here is confusing.
 *
 *  - This driver supports the "Audio Serial Port" (ASP),
 *    found on dm6446, dm355, and other DaVinci chips.
 *
 *  - But it labels it a "Multi-channel Buffered Serial Port"
 *    (McBSP) as on older chips like the dm642 ... which was
 *    backward-compatible, possibly explaining that confusion.
 *
 *  - OMAP chips have a controller called McBSP, which is
 *    incompatible with the DaVinci flavor of McBSP.
 *
 *  - Newer DaVinci chips have a controller called McASP,
 *    incompatible with ASP and with either McBSP.
 *
 * In short:  this uses ASP to implement I2S, not McBSP.
 * And it won't be the only DaVinci implemention of I2S.
 */
#define DAVINCI_MCBSP_DRR_REG	0x00
#define DAVINCI_MCBSP_DXR_REG	0x04
#define DAVINCI_MCBSP_SPCR_REG	0x08
#define DAVINCI_MCBSP_RCR_REG	0x0c
#define DAVINCI_MCBSP_XCR_REG	0x10
#define DAVINCI_MCBSP_SRGR_REG	0x14
#define DAVINCI_MCBSP_PCR_REG	0x24

#define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
#define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
#define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
#define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
#define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
#define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
#define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)

#define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
#define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
#define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
#define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)

#define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
#define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
#define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
#define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
#define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
#define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
#define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
#define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
#define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)

#define MOD_REG_BIT(val, mask, set) do { \
	if (set) { \
		val |= mask; \
	} else { \
		val &= ~mask; \
	} \
} while (0)

enum {
	DAVINCI_MCBSP_WORD_8 = 0,
	DAVINCI_MCBSP_WORD_12,
	DAVINCI_MCBSP_WORD_16,
	DAVINCI_MCBSP_WORD_20,
	DAVINCI_MCBSP_WORD_24,
	DAVINCI_MCBSP_WORD_32,
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	.name = "I2S PCM Stereo out",
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	.name = "I2S PCM Stereo in",
};

struct davinci_mcbsp_dev {
	void __iomem			*base;
	struct clk			*clk;
	struct davinci_pcm_dma_params	*dma_params[2];
};

static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
					   int reg, u32 val)
{
	__raw_writel(val, dev->base + reg);
}

static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
{
	return __raw_readl(dev->base + reg);
}

static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_platform *platform = socdev->card->platform;
	u32 w;
	int ret;

	/* Start the sample generator and enable transmitter/receiver */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		/* Stop the DMA to avoid data loss */
		/* while the transmitter is out of reset to handle XSYNCERR */
		if (platform->pcm_ops->trigger) {
			ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_STOP);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA stop failed\n");
		}

		/* Enable the transmitter */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

		/* wait for any unexpected frame sync error to occur */
		udelay(100);

		/* Disable the transmitter to clear any outstanding XSYNCERR */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

		/* Restart the DMA */
		if (platform->pcm_ops->trigger) {
			ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_START);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA start failed\n");
		}
		/* Enable the transmitter */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	} else {

		/* Enable the reciever */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	}


	/* Start frame sync */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	u32 w;

	/* Reset transmitter/receiver and sample rate/frame sync generators */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
		       DAVINCI_MCBSP_SPCR_FRST, 0);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	else
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static int davinci_i2s_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;

	cpu_dai->dma_data = dev->dma_params[substream->stream];

	return 0;
}

#define DEFAULT_BITPERSAMPLE	16

static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				   unsigned int fmt)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	unsigned int pcr;
	unsigned int srgr;
	unsigned int rcr;
	unsigned int xcr;
	srgr = DAVINCI_MCBSP_SRGR_FSGM |
		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* cpu is master */
		pcr = DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM |
			DAVINCI_MCBSP_PCR_CLKXM |
			DAVINCI_MCBSP_PCR_CLKRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP CLKR pin is the input for the Sample Rate Generator.
		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
		pcr = DAVINCI_MCBSP_PCR_SCLKME |
			DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is master */
		pcr = 0;
		break;
	default:
		printk(KERN_ERR "%s:bad master\n", __func__);
		return -EINVAL;
	}

	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_B:
		break;
	case SND_SOC_DAIFMT_I2S:
		/* Davinci doesn't support TRUE I2S, but some codecs will have
		 * the left and right channels contiguous. This allows
		 * dsp_a mode to be used with an inverted normal frame clk.
		 * If your codec is master and does not have contiguous
		 * channels, then you will have sound on only one channel.
		 * Try using a different mode, or codec as slave.
		 *
		 * The TLV320AIC33 is an example of a codec where this works.
		 * It has a variable bit clock frequency allowing it to have
		 * valid data on every bit clock.
		 *
		 * The TLV320AIC23 is an example of a codec where this does not
		 * work. It has a fixed bit clock frequency with progressively
		 * more empty bit clock slots between channels as the sample
		 * rate is lowered.
		 */
		fmt ^= SND_SOC_DAIFMT_NB_IF;
	case SND_SOC_DAIFMT_DSP_A:
		rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
		xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
		break;
	default:
		printk(KERN_ERR "%s:bad format\n", __func__);
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
			DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		break;
	default:
		return -EINVAL;
	}
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
	return 0;
}

static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_interval *i = NULL;
	int mcbsp_word_length;
	u32 w;

	/* general line settings */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	} else {
		w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	}

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	w = DAVINCI_MCBSP_SRGR_FSGM;
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);

	/* Determine xfer data type */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
		break;
	default:
		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);

	} else {
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);

	}
	return 0;
}

static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		davinci_mcbsp_start(substream);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		davinci_mcbsp_stop(substream);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int davinci_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
	struct davinci_mcbsp_dev *dev;
	struct resource *mem, *ioarea;
	struct evm_snd_platform_data *pdata;
	int ret;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}

	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
				    pdev->name);
	if (!ioarea) {
		dev_err(&pdev->dev, "McBSP region already claimed\n");
		return -EBUSY;
	}

	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err_release_region;
	}

	cpu_dai->private_data = dev;

	dev->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(dev->clk)) {
		ret = -ENODEV;
		goto err_free_mem;
	}
	clk_enable(dev->clk);

	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	pdata = pdev->dev.platform_data;

	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);

	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);

	return 0;

err_free_mem:
	kfree(dev);
err_release_region:
	release_mem_region(mem->start, (mem->end - mem->start) + 1);

	return ret;
}

static void davinci_i2s_remove(struct platform_device *pdev,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	struct resource *mem;

	clk_disable(dev->clk);
	clk_put(dev->clk);
	dev->clk = NULL;

	kfree(dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem->start, (mem->end - mem->start) + 1);
}

#define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000

static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
	.startup	= davinci_i2s_startup,
	.trigger	= davinci_i2s_trigger,
	.hw_params	= davinci_i2s_hw_params,
	.set_fmt	= davinci_i2s_set_dai_fmt,
};

struct snd_soc_dai davinci_i2s_dai = {
	.name = "davinci-i2s",
	.id = 0,
	.probe = davinci_i2s_probe,
	.remove = davinci_i2s_remove,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &davinci_i2s_dai_ops,
};
EXPORT_SYMBOL_GPL(davinci_i2s_dai);

static int __init davinci_i2s_init(void)
{
	return snd_soc_register_dai(&davinci_i2s_dai);
}
module_init(davinci_i2s_init);

static void __exit davinci_i2s_exit(void)
{
	snd_soc_unregister_dai(&davinci_i2s_dai);
}
module_exit(davinci_i2s_exit);

MODULE_AUTHOR("Vladimir Barinov");
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
310355c1 VB	1	/*
	2	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/device.h>
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/clk.h>
	18
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
	24
	25	#include "davinci-pcm.h"
	26
a62114cb DB	27
	28	/*
	29	* NOTE: terminology here is confusing.
	30	*
	31	* - This driver supports the "Audio Serial Port" (ASP),
	32	* found on dm6446, dm355, and other DaVinci chips.
	33	*
	34	* - But it labels it a "Multi-channel Buffered Serial Port"
	35	* (McBSP) as on older chips like the dm642 ... which was
	36	* backward-compatible, possibly explaining that confusion.
	37	*
	38	* - OMAP chips have a controller called McBSP, which is
	39	* incompatible with the DaVinci flavor of McBSP.
	40	*
	41	* - Newer DaVinci chips have a controller called McASP,
	42	* incompatible with ASP and with either McBSP.
	43	*
	44	* In short: this uses ASP to implement I2S, not McBSP.
	45	* And it won't be the only DaVinci implemention of I2S.
	46	*/
310355c1 VB	47	#define DAVINCI_MCBSP_DRR_REG 0x00
	48	#define DAVINCI_MCBSP_DXR_REG 0x04
	49	#define DAVINCI_MCBSP_SPCR_REG 0x08
	50	#define DAVINCI_MCBSP_RCR_REG 0x0c
	51	#define DAVINCI_MCBSP_XCR_REG 0x10
	52	#define DAVINCI_MCBSP_SRGR_REG 0x14
	53	#define DAVINCI_MCBSP_PCR_REG 0x24
	54
	55	#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
	56	#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
	57	#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
	58	#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
	59	#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
	60	#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
	61	#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
	62
	63	#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
	64	#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
	65	#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
	66	#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
	67
	68	#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
	69	#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
	70	#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
	71	#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
	72	#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
	73
	74	#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
	75	#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
	76	#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
	77
	78	#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
	79	#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
	80	#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
	81	#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8	82	#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1 VB	83	#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
	84	#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
	85	#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
	86	#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
	87
	88	#define MOD_REG_BIT(val, mask, set) do { \
	89	if (set) { \
	90	val \|= mask; \
	91	} else { \
	92	val &= ~mask; \
	93	} \
	94	} while (0)
	95
	96	enum {
	97	DAVINCI_MCBSP_WORD_8 = 0,
	98	DAVINCI_MCBSP_WORD_12,
	99	DAVINCI_MCBSP_WORD_16,
	100	DAVINCI_MCBSP_WORD_20,
	101	DAVINCI_MCBSP_WORD_24,
	102	DAVINCI_MCBSP_WORD_32,
	103	};
	104
	105	static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	106	.name = "I2S PCM Stereo out",
	107	};
	108
	109	static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	110	.name = "I2S PCM Stereo in",
	111	};
	112
	113	struct davinci_mcbsp_dev {
	114	void __iomem *base;
	115	struct clk *clk;
	116	struct davinci_pcm_dma_params *dma_params[2];
	117	};
	118
	119	static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
	120	int reg, u32 val)
	121	{
	122	__raw_writel(val, dev->base + reg);
	123	}
	124
	125	static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
	126	{
	127	return __raw_readl(dev->base + reg);
	128	}
	129
	130	static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
	131	{
	132	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	133	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
fb0ef645	134	struct snd_soc_device *socdev = rtd->socdev;
87689d56	135	struct snd_soc_platform *platform = socdev->card->platform;
310355c1	136	u32 w;
fb0ef645	137	int ret;
310355c1 VB	138
	139	/* Start the sample generator and enable transmitter/receiver */
	140	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	141	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
fb0ef645 NM	142	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	143
	144	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	145	/* Stop the DMA to avoid data loss */
	146	/* while the transmitter is out of reset to handle XSYNCERR */
	147	if (platform->pcm_ops->trigger) {
	148	ret = platform->pcm_ops->trigger(substream,
	149	SNDRV_PCM_TRIGGER_STOP);
	150	if (ret < 0)
	151	printk(KERN_DEBUG "Playback DMA stop failed\n");
	152	}
	153
	154	/* Enable the transmitter */
	155	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
310355c1	156	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
fb0ef645 NM	157	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	158
	159	/* wait for any unexpected frame sync error to occur */
	160	udelay(100);
	161
	162	/* Disable the transmitter to clear any outstanding XSYNCERR */
	163	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	164	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	165	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	166
	167	/* Restart the DMA */
	168	if (platform->pcm_ops->trigger) {
	169	ret = platform->pcm_ops->trigger(substream,
	170	SNDRV_PCM_TRIGGER_START);
	171	if (ret < 0)
	172	printk(KERN_DEBUG "Playback DMA start failed\n");
	173	}
	174	/* Enable the transmitter */
	175	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	176	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
	177	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	178
	179	} else {
	180
	181	/* Enable the reciever */
	182	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
310355c1	183	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
fb0ef645 NM	184	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	185	}
	186
310355c1 VB	187
	188	/* Start frame sync */
	189	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	190	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	191	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	192	}
	193
	194	static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
	195	{
	196	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	197	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	198	u32 w;
	199
	200	/* Reset transmitter/receiver and sample rate/frame sync generators */
	201	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	202	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST \|
	203	DAVINCI_MCBSP_SPCR_FRST, 0);
	204	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	205	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	206	else
	207	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	208	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	209	}
	210
dee89c4d MB	211	static int davinci_i2s_startup(struct snd_pcm_substream *substream,
dee89c4d MB	212	struct snd_soc_dai *dai)
310355c1 VB	213	{
310355c1 VB	214	struct snd_soc_pcm_runtime *rtd = substream->private_data;
9cb132d7	215	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
310355c1 VB	216	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	217
	218	cpu_dai->dma_data = dev->dma_params[substream->stream];
	219
	220	return 0;
	221	}
	222
21903c1c TK	223	#define DEFAULT_BITPERSAMPLE 16
21903c1c TK	224
9cb132d7	225	static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1 VB	226	unsigned int fmt)
	227	{
	228	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
21903c1c TK	229	unsigned int pcr;
	230	unsigned int srgr;
	231	unsigned int rcr;
	232	unsigned int xcr;
	233	srgr = DAVINCI_MCBSP_SRGR_FSGM \|
	234	DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) \|
	235	DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
310355c1 VB	236
	237	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	238	case SND_SOC_DAIFMT_CBS_CFS:
21903c1c TK	239	/* cpu is master */
	240	pcr = DAVINCI_MCBSP_PCR_FSXM \|
	241	DAVINCI_MCBSP_PCR_FSRM \|
	242	DAVINCI_MCBSP_PCR_CLKXM \|
	243	DAVINCI_MCBSP_PCR_CLKRM;
310355c1	244	break;
b402dff8 HV	245	case SND_SOC_DAIFMT_CBM_CFS:
	246	/* McBSP CLKR pin is the input for the Sample Rate Generator.
	247	* McBSP FSR and FSX are driven by the Sample Rate Generator. */
21903c1c TK	248	pcr = DAVINCI_MCBSP_PCR_SCLKME \|
	249	DAVINCI_MCBSP_PCR_FSXM \|
	250	DAVINCI_MCBSP_PCR_FSRM;
b402dff8	251	break;
310355c1	252	case SND_SOC_DAIFMT_CBM_CFM:
21903c1c TK	253	/* codec is master */
21903c1c TK	254	pcr = 0;
310355c1 VB	255	break;
310355c1 VB	256	default:
21903c1c	257	printk(KERN_ERR "%s:bad master\n", __func__);
310355c1 VB	258	return -EINVAL;
	259	}
	260
69ab820c TK	261	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	262	xcr = DAVINCI_MCBSP_XCR_XFIG \| DAVINCI_MCBSP_XCR_XFRLEN1(1);
	263	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
07d8d9dc	264	case SND_SOC_DAIFMT_DSP_B:
69ab820c TK	265	break;
69ab820c TK	266	case SND_SOC_DAIFMT_I2S:
07d8d9dc TK	267	/* Davinci doesn't support TRUE I2S, but some codecs will have
	268	* the left and right channels contiguous. This allows
	269	* dsp_a mode to be used with an inverted normal frame clk.
	270	* If your codec is master and does not have contiguous
	271	* channels, then you will have sound on only one channel.
	272	* Try using a different mode, or codec as slave.
	273	*
	274	* The TLV320AIC33 is an example of a codec where this works.
	275	* It has a variable bit clock frequency allowing it to have
	276	* valid data on every bit clock.
	277	*
	278	* The TLV320AIC23 is an example of a codec where this does not
	279	* work. It has a fixed bit clock frequency with progressively
	280	* more empty bit clock slots between channels as the sample
	281	* rate is lowered.
	282	*/
	283	fmt ^= SND_SOC_DAIFMT_NB_IF;
	284	case SND_SOC_DAIFMT_DSP_A:
69ab820c TK	285	rcr \|= DAVINCI_MCBSP_RCR_RDATDLY(1);
	286	xcr \|= DAVINCI_MCBSP_XCR_XDATDLY(1);
	287	break;
	288	default:
	289	printk(KERN_ERR "%s:bad format\n", __func__);
	290	return -EINVAL;
	291	}
	292
310355c1	293	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
9e031624	294	case SND_SOC_DAIFMT_NB_NF:
664b4af8 TK	295	/* CLKRP Receive clock polarity,
	296	* 1 - sampled on rising edge of CLKR
	297	* valid on rising edge
	298	* CLKXP Transmit clock polarity,
	299	* 1 - clocked on falling edge of CLKX
	300	* valid on rising edge
	301	* FSRP Receive frame sync pol, 0 - active high
	302	* FSXP Transmit frame sync pol, 0 - active high
	303	*/
21903c1c	304	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP);
310355c1	305	break;
9e031624	306	case SND_SOC_DAIFMT_IB_IF:
664b4af8 TK	307	/* CLKRP Receive clock polarity,
	308	* 0 - sampled on falling edge of CLKR
	309	* valid on falling edge
	310	* CLKXP Transmit clock polarity,
	311	* 0 - clocked on rising edge of CLKX
	312	* valid on falling edge
	313	* FSRP Receive frame sync pol, 1 - active low
	314	* FSXP Transmit frame sync pol, 1 - active low
	315	*/
21903c1c	316	pcr \|= (DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1	317	break;
9e031624	318	case SND_SOC_DAIFMT_NB_IF:
664b4af8 TK	319	/* CLKRP Receive clock polarity,
	320	* 1 - sampled on rising edge of CLKR
	321	* valid on rising edge
	322	* CLKXP Transmit clock polarity,
	323	* 1 - clocked on falling edge of CLKX
	324	* valid on rising edge
	325	* FSRP Receive frame sync pol, 1 - active low
	326	* FSXP Transmit frame sync pol, 1 - active low
	327	*/
21903c1c TK	328	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP \|
21903c1c TK	329	DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1	330	break;
9e031624	331	case SND_SOC_DAIFMT_IB_NF:
664b4af8 TK	332	/* CLKRP Receive clock polarity,
	333	* 0 - sampled on falling edge of CLKR
	334	* valid on falling edge
	335	* CLKXP Transmit clock polarity,
	336	* 0 - clocked on rising edge of CLKX
	337	* valid on falling edge
	338	* FSRP Receive frame sync pol, 0 - active high
	339	* FSXP Transmit frame sync pol, 0 - active high
	340	*/
310355c1 VB	341	break;
	342	default:
	343	return -EINVAL;
	344	}
21903c1c TK	345	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
	346	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	347	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	348	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
310355c1 VB	349	return 0;
	350	}
	351
	352	static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	353	struct snd_pcm_hw_params *params,
dee89c4d MB	354	struct snd_soc_dai *dai)
310355c1 VB	355	{
	356	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	357	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	358	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	359	struct snd_interval *i = NULL;
	360	int mcbsp_word_length;
	361	u32 w;
	362
	363	/* general line settings */
cb6e2063 NM	364	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	365	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
	366	w \|= DAVINCI_MCBSP_SPCR_RINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
	367	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	368	} else {
	369	w \|= DAVINCI_MCBSP_SPCR_XINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
	370	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	371	}
310355c1 VB	372
310355c1 VB	373	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
21903c1c	374	w = DAVINCI_MCBSP_SRGR_FSGM;
310355c1	375	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
310355c1 VB	376
310355c1 VB	377	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
310355c1 VB	378	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	379	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
	380
	381	/* Determine xfer data type */
	382	switch (params_format(params)) {
	383	case SNDRV_PCM_FORMAT_S8:
	384	dma_params->data_type = 1;
	385	mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
	386	break;
	387	case SNDRV_PCM_FORMAT_S16_LE:
	388	dma_params->data_type = 2;
	389	mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
	390	break;
	391	case SNDRV_PCM_FORMAT_S32_LE:
	392	dma_params->data_type = 4;
	393	mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
	394	break;
	395	default:
9b6e12e4	396	printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1 VB	397	return -EINVAL;
	398	}
	399
cb6e2063 NM	400	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
	401	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	402	MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) \|
	403	DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
	404	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
310355c1	405
cb6e2063 NM	406	} else {
	407	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	408	MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) \|
	409	DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
	410	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
310355c1	411
cb6e2063	412	}
310355c1 VB	413	return 0;
	414	}
	415
dee89c4d MB	416	static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	417	struct snd_soc_dai *dai)
310355c1 VB	418	{
	419	int ret = 0;
	420
	421	switch (cmd) {
	422	case SNDRV_PCM_TRIGGER_START:
	423	case SNDRV_PCM_TRIGGER_RESUME:
	424	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	425	davinci_mcbsp_start(substream);
	426	break;
	427	case SNDRV_PCM_TRIGGER_STOP:
	428	case SNDRV_PCM_TRIGGER_SUSPEND:
	429	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	430	davinci_mcbsp_stop(substream);
	431	break;
	432	default:
	433	ret = -EINVAL;
	434	}
	435
	436	return ret;
	437	}
	438
bdb92876	439	static int davinci_i2s_probe(struct platform_device *pdev,
9cb132d7	440	struct snd_soc_dai *dai)
310355c1 VB	441	{
310355c1 VB	442	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549	443	struct snd_soc_card *card = socdev->card;
a62114cb	444	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
310355c1 VB	445	struct davinci_mcbsp_dev *dev;
	446	struct resource mem, ioarea;
	447	struct evm_snd_platform_data *pdata;
	448	int ret;
	449
	450	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	451	if (!mem) {
	452	dev_err(&pdev->dev, "no mem resource?\n");
	453	return -ENODEV;
	454	}
	455
	456	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
	457	pdev->name);
	458	if (!ioarea) {
	459	dev_err(&pdev->dev, "McBSP region already claimed\n");
	460	return -EBUSY;
	461	}
	462
	463	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	464	if (!dev) {
	465	ret = -ENOMEM;
	466	goto err_release_region;
	467	}
	468
	469	cpu_dai->private_data = dev;
	470
a62114cb	471	dev->clk = clk_get(&pdev->dev, NULL);
310355c1 VB	472	if (IS_ERR(dev->clk)) {
	473	ret = -ENODEV;
	474	goto err_free_mem;
	475	}
	476	clk_enable(dev->clk);
	477
	478	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	479	pdata = pdev->dev.platform_data;
	480
	481	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	482	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	483	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	484	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
	485
	486	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	487	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	488	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	489	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
	490
	491	return 0;
	492
	493	err_free_mem:
	494	kfree(dev);
	495	err_release_region:
	496	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	497
	498	return ret;
	499	}
	500
bdb92876	501	static void davinci_i2s_remove(struct platform_device *pdev,
9cb132d7	502	struct snd_soc_dai *dai)
310355c1 VB	503	{
310355c1 VB	504	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549	505	struct snd_soc_card *card = socdev->card;
a62114cb	506	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
310355c1 VB	507	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	508	struct resource *mem;
	509
	510	clk_disable(dev->clk);
	511	clk_put(dev->clk);
	512	dev->clk = NULL;
	513
	514	kfree(dev);
	515
	516	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	517	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	518	}
	519
	520	#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
	521
6335d055 EM	522	static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
	523	.startup = davinci_i2s_startup,
	524	.trigger = davinci_i2s_trigger,
	525	.hw_params = davinci_i2s_hw_params,
	526	.set_fmt = davinci_i2s_set_dai_fmt,
	527	};
	528
9cb132d7	529	struct snd_soc_dai davinci_i2s_dai = {
310355c1 VB	530	.name = "davinci-i2s",
310355c1 VB	531	.id = 0,
310355c1 VB	532	.probe = davinci_i2s_probe,
	533	.remove = davinci_i2s_remove,
	534	.playback = {
	535	.channels_min = 2,
	536	.channels_max = 2,
	537	.rates = DAVINCI_I2S_RATES,
	538	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	539	.capture = {
	540	.channels_min = 2,
	541	.channels_max = 2,
	542	.rates = DAVINCI_I2S_RATES,
	543	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	544	.ops = &davinci_i2s_dai_ops,
310355c1 VB	545	};
	546	EXPORT_SYMBOL_GPL(davinci_i2s_dai);
	547
c9b3a40f	548	static int __init davinci_i2s_init(void)
3f4b783c MB	549	{
	550	return snd_soc_register_dai(&davinci_i2s_dai);
	551	}
	552	module_init(davinci_i2s_init);
	553
	554	static void __exit davinci_i2s_exit(void)
	555	{
	556	snd_soc_unregister_dai(&davinci_i2s_dai);
	557	}
	558	module_exit(davinci_i2s_exit);
	559
310355c1 VB	560	MODULE_AUTHOR("Vladimir Barinov");
	561	MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
	562	MODULE_LICENSE("GPL");