[net-next-2.6.git] / sound / soc / davinci / davinci-i2s.c

/*
 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"


/*
 * NOTE:  terminology here is confusing.
 *
 *  - This driver supports the "Audio Serial Port" (ASP),
 *    found on dm6446, dm355, and other DaVinci chips.
 *
 *  - But it labels it a "Multi-channel Buffered Serial Port"
 *    (McBSP) as on older chips like the dm642 ... which was
 *    backward-compatible, possibly explaining that confusion.
 *
 *  - OMAP chips have a controller called McBSP, which is
 *    incompatible with the DaVinci flavor of McBSP.
 *
 *  - Newer DaVinci chips have a controller called McASP,
 *    incompatible with ASP and with either McBSP.
 *
 * In short:  this uses ASP to implement I2S, not McBSP.
 * And it won't be the only DaVinci implemention of I2S.
 */
#define DAVINCI_MCBSP_DRR_REG	0x00
#define DAVINCI_MCBSP_DXR_REG	0x04
#define DAVINCI_MCBSP_SPCR_REG	0x08
#define DAVINCI_MCBSP_RCR_REG	0x0c
#define DAVINCI_MCBSP_XCR_REG	0x10
#define DAVINCI_MCBSP_SRGR_REG	0x14
#define DAVINCI_MCBSP_PCR_REG	0x24

#define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
#define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
#define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
#define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
#define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
#define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
#define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)

#define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
#define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
#define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
#define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)

#define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
#define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
#define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
#define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
#define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
#define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
#define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
#define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
#define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)

enum {
	DAVINCI_MCBSP_WORD_8 = 0,
	DAVINCI_MCBSP_WORD_12,
	DAVINCI_MCBSP_WORD_16,
	DAVINCI_MCBSP_WORD_20,
	DAVINCI_MCBSP_WORD_24,
	DAVINCI_MCBSP_WORD_32,
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	.name = "I2S PCM Stereo out",
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	.name = "I2S PCM Stereo in",
};

struct davinci_mcbsp_dev {
	void __iomem			*base;
	u32				pcr;
	struct clk			*clk;
	struct davinci_pcm_dma_params	*dma_params[2];
};

static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
					   int reg, u32 val)
{
	__raw_writel(val, dev->base + reg);
}

static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
{
	return __raw_readl(dev->base + reg);
}

static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
{
	u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
	/* The clock needs to toggle to complete reset.
	 * So, fake it by toggling the clk polarity.
	 */
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
}

static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
		struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_platform *platform = socdev->card->platform;
	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
	u32 spcr;
	u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (spcr & mask) {
		/* start off disabled */
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
				spcr & ~mask);
		toggle_clock(dev, playback);
	}
	if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
			DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
		/* Start the sample generator */
		spcr |= DAVINCI_MCBSP_SPCR_GRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	}

	if (playback) {
		/* Stop the DMA to avoid data loss */
		/* while the transmitter is out of reset to handle XSYNCERR */
		if (platform->pcm_ops->trigger) {
			int ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_STOP);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA stop failed\n");
		}

		/* Enable the transmitter */
		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		spcr |= DAVINCI_MCBSP_SPCR_XRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);

		/* wait for any unexpected frame sync error to occur */
		udelay(100);

		/* Disable the transmitter to clear any outstanding XSYNCERR */
		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
		toggle_clock(dev, playback);

		/* Restart the DMA */
		if (platform->pcm_ops->trigger) {
			int ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_START);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA start failed\n");
		}
	}

	/* Enable transmitter or receiver */
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	spcr |= mask;

	if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
		/* Start frame sync */
		spcr |= DAVINCI_MCBSP_SPCR_FRST;
	}
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
}

static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
{
	u32 spcr;

	/* Reset transmitter/receiver and sample rate/frame sync generators */
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
	spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	toggle_clock(dev, playback);
}

static int davinci_i2s_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *cpu_dai)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	cpu_dai->dma_data = dev->dma_params[substream->stream];
	return 0;
}

#define DEFAULT_BITPERSAMPLE	16

static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				   unsigned int fmt)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	unsigned int pcr;
	unsigned int srgr;
	unsigned int rcr;
	unsigned int xcr;
	srgr = DAVINCI_MCBSP_SRGR_FSGM |
		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* cpu is master */
		pcr = DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM |
			DAVINCI_MCBSP_PCR_CLKXM |
			DAVINCI_MCBSP_PCR_CLKRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP CLKR pin is the input for the Sample Rate Generator.
		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
		pcr = DAVINCI_MCBSP_PCR_SCLKME |
			DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is master */
		pcr = 0;
		break;
	default:
		printk(KERN_ERR "%s:bad master\n", __func__);
		return -EINVAL;
	}

	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_B:
		break;
	case SND_SOC_DAIFMT_I2S:
		/* Davinci doesn't support TRUE I2S, but some codecs will have
		 * the left and right channels contiguous. This allows
		 * dsp_a mode to be used with an inverted normal frame clk.
		 * If your codec is master and does not have contiguous
		 * channels, then you will have sound on only one channel.
		 * Try using a different mode, or codec as slave.
		 *
		 * The TLV320AIC33 is an example of a codec where this works.
		 * It has a variable bit clock frequency allowing it to have
		 * valid data on every bit clock.
		 *
		 * The TLV320AIC23 is an example of a codec where this does not
		 * work. It has a fixed bit clock frequency with progressively
		 * more empty bit clock slots between channels as the sample
		 * rate is lowered.
		 */
		fmt ^= SND_SOC_DAIFMT_NB_IF;
	case SND_SOC_DAIFMT_DSP_A:
		rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
		xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
		break;
	default:
		printk(KERN_ERR "%s:bad format\n", __func__);
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
			DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		break;
	default:
		return -EINVAL;
	}
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
	dev->pcr = pcr;
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
	return 0;
}

static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_interval *i = NULL;
	int mcbsp_word_length;
	unsigned int rcr, xcr, srgr;
	u32 spcr;

	/* general line settings */
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	} else {
		spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	}

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	srgr = DAVINCI_MCBSP_SRGR_FSGM;
	srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);

	/* Determine xfer data type */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
		break;
	default:
		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
		rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);

	} else {
		xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
		xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
				DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);

	}
	return 0;
}

static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	int ret = 0;
	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		davinci_mcbsp_start(dev, substream);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		davinci_mcbsp_stop(dev, playback);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int davinci_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
	struct davinci_mcbsp_dev *dev;
	struct resource *mem, *ioarea;
	struct evm_snd_platform_data *pdata;
	int ret;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}

	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
				    pdev->name);
	if (!ioarea) {
		dev_err(&pdev->dev, "McBSP region already claimed\n");
		return -EBUSY;
	}

	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err_release_region;
	}

	cpu_dai->private_data = dev;

	dev->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(dev->clk)) {
		ret = -ENODEV;
		goto err_free_mem;
	}
	clk_enable(dev->clk);

	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	pdata = pdev->dev.platform_data;

	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);

	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);

	return 0;

err_free_mem:
	kfree(dev);
err_release_region:
	release_mem_region(mem->start, (mem->end - mem->start) + 1);

	return ret;
}

static void davinci_i2s_remove(struct platform_device *pdev,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	struct resource *mem;

	clk_disable(dev->clk);
	clk_put(dev->clk);
	dev->clk = NULL;

	kfree(dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem->start, (mem->end - mem->start) + 1);
}

#define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000

static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
	.startup	= davinci_i2s_startup,
	.trigger	= davinci_i2s_trigger,
	.hw_params	= davinci_i2s_hw_params,
	.set_fmt	= davinci_i2s_set_dai_fmt,
};

struct snd_soc_dai davinci_i2s_dai = {
	.name = "davinci-i2s",
	.id = 0,
	.probe = davinci_i2s_probe,
	.remove = davinci_i2s_remove,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &davinci_i2s_dai_ops,
};
EXPORT_SYMBOL_GPL(davinci_i2s_dai);

static int __init davinci_i2s_init(void)
{
	return snd_soc_register_dai(&davinci_i2s_dai);
}
module_init(davinci_i2s_init);

static void __exit davinci_i2s_exit(void)
{
	snd_soc_unregister_dai(&davinci_i2s_dai);
}
module_exit(davinci_i2s_exit);

MODULE_AUTHOR("Vladimir Barinov");
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
310355c1 VB	1	/*
	2	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/device.h>
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/clk.h>
	18
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
	24
	25	#include "davinci-pcm.h"
	26
a62114cb DB	27
	28	/*
	29	* NOTE: terminology here is confusing.
	30	*
	31	* - This driver supports the "Audio Serial Port" (ASP),
	32	* found on dm6446, dm355, and other DaVinci chips.
	33	*
	34	* - But it labels it a "Multi-channel Buffered Serial Port"
	35	* (McBSP) as on older chips like the dm642 ... which was
	36	* backward-compatible, possibly explaining that confusion.
	37	*
	38	* - OMAP chips have a controller called McBSP, which is
	39	* incompatible with the DaVinci flavor of McBSP.
	40	*
	41	* - Newer DaVinci chips have a controller called McASP,
	42	* incompatible with ASP and with either McBSP.
	43	*
	44	* In short: this uses ASP to implement I2S, not McBSP.
	45	* And it won't be the only DaVinci implemention of I2S.
	46	*/
310355c1 VB	47	#define DAVINCI_MCBSP_DRR_REG 0x00
	48	#define DAVINCI_MCBSP_DXR_REG 0x04
	49	#define DAVINCI_MCBSP_SPCR_REG 0x08
	50	#define DAVINCI_MCBSP_RCR_REG 0x0c
	51	#define DAVINCI_MCBSP_XCR_REG 0x10
	52	#define DAVINCI_MCBSP_SRGR_REG 0x14
	53	#define DAVINCI_MCBSP_PCR_REG 0x24
	54
	55	#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
	56	#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
	57	#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
	58	#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
	59	#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
	60	#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
	61	#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
	62
	63	#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
	64	#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
	65	#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
	66	#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
	67
	68	#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
	69	#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
	70	#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
	71	#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
	72	#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
	73
	74	#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
	75	#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
	76	#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
	77
	78	#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
	79	#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
	80	#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
	81	#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8	82	#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1 VB	83	#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
	84	#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
	85	#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
	86	#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
	87
310355c1 VB	88	enum {
	89	DAVINCI_MCBSP_WORD_8 = 0,
	90	DAVINCI_MCBSP_WORD_12,
	91	DAVINCI_MCBSP_WORD_16,
	92	DAVINCI_MCBSP_WORD_20,
	93	DAVINCI_MCBSP_WORD_24,
	94	DAVINCI_MCBSP_WORD_32,
	95	};
	96
	97	static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	98	.name = "I2S PCM Stereo out",
	99	};
	100
	101	static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	102	.name = "I2S PCM Stereo in",
	103	};
	104
	105	struct davinci_mcbsp_dev {
	106	void __iomem *base;
c392bec7	107	u32 pcr;
310355c1 VB	108	struct clk *clk;
	109	struct davinci_pcm_dma_params *dma_params[2];
	110	};
	111
	112	static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
	113	int reg, u32 val)
	114	{
	115	__raw_writel(val, dev->base + reg);
	116	}
	117
	118	static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
	119	{
	120	return __raw_readl(dev->base + reg);
	121	}
	122
c392bec7 TK	123	static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
	124	{
	125	u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
	126	/* The clock needs to toggle to complete reset.
	127	* So, fake it by toggling the clk polarity.
	128	*/
	129	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
	130	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
	131	}
	132
f9af37cc TK	133	static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
f9af37cc TK	134	struct snd_pcm_substream *substream)
310355c1 VB	135	{
310355c1 VB	136	struct snd_soc_pcm_runtime *rtd = substream->private_data;
fb0ef645	137	struct snd_soc_device *socdev = rtd->socdev;
87689d56	138	struct snd_soc_platform *platform = socdev->card->platform;
c392bec7	139	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
35cf6358	140	u32 spcr;
c392bec7	141	u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
35cf6358	142	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
c392bec7 TK	143	if (spcr & mask) {
	144	/* start off disabled */
	145	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
	146	spcr & ~mask);
	147	toggle_clock(dev, playback);
	148	}
1bef4499 TK	149	if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM \| DAVINCI_MCBSP_PCR_FSRM \|
	150	DAVINCI_MCBSP_PCR_CLKXM \| DAVINCI_MCBSP_PCR_CLKRM)) {
	151	/* Start the sample generator */
	152	spcr \|= DAVINCI_MCBSP_SPCR_GRST;
	153	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	154	}
fb0ef645	155
1bef4499	156	if (playback) {
fb0ef645 NM	157	/* Stop the DMA to avoid data loss */
	158	/* while the transmitter is out of reset to handle XSYNCERR */
	159	if (platform->pcm_ops->trigger) {
eba575c3	160	int ret = platform->pcm_ops->trigger(substream,
fb0ef645 NM	161	SNDRV_PCM_TRIGGER_STOP);
	162	if (ret < 0)
	163	printk(KERN_DEBUG "Playback DMA stop failed\n");
	164	}
	165
	166	/* Enable the transmitter */
35cf6358 TK	167	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	168	spcr \|= DAVINCI_MCBSP_SPCR_XRST;
	169	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645 NM	170
	171	/* wait for any unexpected frame sync error to occur */
	172	udelay(100);
	173
	174	/* Disable the transmitter to clear any outstanding XSYNCERR */
35cf6358 TK	175	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	176	spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
	177	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7	178	toggle_clock(dev, playback);
fb0ef645 NM	179
	180	/* Restart the DMA */
	181	if (platform->pcm_ops->trigger) {
eba575c3	182	int ret = platform->pcm_ops->trigger(substream,
fb0ef645 NM	183	SNDRV_PCM_TRIGGER_START);
	184	if (ret < 0)
	185	printk(KERN_DEBUG "Playback DMA start failed\n");
	186	}
fb0ef645 NM	187	}
fb0ef645 NM	188
1bef4499	189	/* Enable transmitter or receiver */
35cf6358	190	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
1bef4499 TK	191	spcr \|= mask;
	192
	193	if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM \| DAVINCI_MCBSP_PCR_FSRM)) {
	194	/* Start frame sync */
	195	spcr \|= DAVINCI_MCBSP_SPCR_FRST;
	196	}
35cf6358	197	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
310355c1 VB	198	}
310355c1 VB	199
f9af37cc	200	static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
310355c1	201	{
35cf6358	202	u32 spcr;
310355c1 VB	203
310355c1 VB	204	/* Reset transmitter/receiver and sample rate/frame sync generators */
35cf6358 TK	205	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
35cf6358 TK	206	spcr &= ~(DAVINCI_MCBSP_SPCR_GRST \| DAVINCI_MCBSP_SPCR_FRST);
c392bec7	207	spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
35cf6358	208	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7	209	toggle_clock(dev, playback);
310355c1 VB	210	}
310355c1 VB	211
dee89c4d	212	static int davinci_i2s_startup(struct snd_pcm_substream *substream,
9333b594	213	struct snd_soc_dai *cpu_dai)
310355c1	214	{
9333b594	215	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
310355c1	216	cpu_dai->dma_data = dev->dma_params[substream->stream];
310355c1 VB	217	return 0;
	218	}
	219
21903c1c TK	220	#define DEFAULT_BITPERSAMPLE 16
21903c1c TK	221
9cb132d7	222	static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1 VB	223	unsigned int fmt)
	224	{
	225	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
21903c1c TK	226	unsigned int pcr;
	227	unsigned int srgr;
	228	unsigned int rcr;
	229	unsigned int xcr;
	230	srgr = DAVINCI_MCBSP_SRGR_FSGM \|
	231	DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) \|
	232	DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
310355c1 VB	233
	234	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	235	case SND_SOC_DAIFMT_CBS_CFS:
21903c1c TK	236	/* cpu is master */
	237	pcr = DAVINCI_MCBSP_PCR_FSXM \|
	238	DAVINCI_MCBSP_PCR_FSRM \|
	239	DAVINCI_MCBSP_PCR_CLKXM \|
	240	DAVINCI_MCBSP_PCR_CLKRM;
310355c1	241	break;
b402dff8 HV	242	case SND_SOC_DAIFMT_CBM_CFS:
	243	/* McBSP CLKR pin is the input for the Sample Rate Generator.
	244	* McBSP FSR and FSX are driven by the Sample Rate Generator. */
21903c1c TK	245	pcr = DAVINCI_MCBSP_PCR_SCLKME \|
	246	DAVINCI_MCBSP_PCR_FSXM \|
	247	DAVINCI_MCBSP_PCR_FSRM;
b402dff8	248	break;
310355c1	249	case SND_SOC_DAIFMT_CBM_CFM:
21903c1c TK	250	/* codec is master */
21903c1c TK	251	pcr = 0;
310355c1 VB	252	break;
310355c1 VB	253	default:
21903c1c	254	printk(KERN_ERR "%s:bad master\n", __func__);
310355c1 VB	255	return -EINVAL;
	256	}
	257
69ab820c TK	258	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	259	xcr = DAVINCI_MCBSP_XCR_XFIG \| DAVINCI_MCBSP_XCR_XFRLEN1(1);
	260	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
07d8d9dc	261	case SND_SOC_DAIFMT_DSP_B:
69ab820c TK	262	break;
69ab820c TK	263	case SND_SOC_DAIFMT_I2S:
07d8d9dc TK	264	/* Davinci doesn't support TRUE I2S, but some codecs will have
	265	* the left and right channels contiguous. This allows
	266	* dsp_a mode to be used with an inverted normal frame clk.
	267	* If your codec is master and does not have contiguous
	268	* channels, then you will have sound on only one channel.
	269	* Try using a different mode, or codec as slave.
	270	*
	271	* The TLV320AIC33 is an example of a codec where this works.
	272	* It has a variable bit clock frequency allowing it to have
	273	* valid data on every bit clock.
	274	*
	275	* The TLV320AIC23 is an example of a codec where this does not
	276	* work. It has a fixed bit clock frequency with progressively
	277	* more empty bit clock slots between channels as the sample
	278	* rate is lowered.
	279	*/
	280	fmt ^= SND_SOC_DAIFMT_NB_IF;
	281	case SND_SOC_DAIFMT_DSP_A:
69ab820c TK	282	rcr \|= DAVINCI_MCBSP_RCR_RDATDLY(1);
	283	xcr \|= DAVINCI_MCBSP_XCR_XDATDLY(1);
	284	break;
	285	default:
	286	printk(KERN_ERR "%s:bad format\n", __func__);
	287	return -EINVAL;
	288	}
	289
310355c1	290	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
9e031624	291	case SND_SOC_DAIFMT_NB_NF:
664b4af8 TK	292	/* CLKRP Receive clock polarity,
	293	* 1 - sampled on rising edge of CLKR
	294	* valid on rising edge
	295	* CLKXP Transmit clock polarity,
	296	* 1 - clocked on falling edge of CLKX
	297	* valid on rising edge
	298	* FSRP Receive frame sync pol, 0 - active high
	299	* FSXP Transmit frame sync pol, 0 - active high
	300	*/
21903c1c	301	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP);
310355c1	302	break;
9e031624	303	case SND_SOC_DAIFMT_IB_IF:
664b4af8 TK	304	/* CLKRP Receive clock polarity,
	305	* 0 - sampled on falling edge of CLKR
	306	* valid on falling edge
	307	* CLKXP Transmit clock polarity,
	308	* 0 - clocked on rising edge of CLKX
	309	* valid on falling edge
	310	* FSRP Receive frame sync pol, 1 - active low
	311	* FSXP Transmit frame sync pol, 1 - active low
	312	*/
21903c1c	313	pcr \|= (DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1	314	break;
9e031624	315	case SND_SOC_DAIFMT_NB_IF:
664b4af8 TK	316	/* CLKRP Receive clock polarity,
	317	* 1 - sampled on rising edge of CLKR
	318	* valid on rising edge
	319	* CLKXP Transmit clock polarity,
	320	* 1 - clocked on falling edge of CLKX
	321	* valid on rising edge
	322	* FSRP Receive frame sync pol, 1 - active low
	323	* FSXP Transmit frame sync pol, 1 - active low
	324	*/
21903c1c TK	325	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP \|
21903c1c TK	326	DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1	327	break;
9e031624	328	case SND_SOC_DAIFMT_IB_NF:
664b4af8 TK	329	/* CLKRP Receive clock polarity,
	330	* 0 - sampled on falling edge of CLKR
	331	* valid on falling edge
	332	* CLKXP Transmit clock polarity,
	333	* 0 - clocked on rising edge of CLKX
	334	* valid on falling edge
	335	* FSRP Receive frame sync pol, 0 - active high
	336	* FSXP Transmit frame sync pol, 0 - active high
	337	*/
310355c1 VB	338	break;
	339	default:
	340	return -EINVAL;
	341	}
21903c1c	342	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
c392bec7	343	dev->pcr = pcr;
21903c1c TK	344	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	345	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	346	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
310355c1 VB	347	return 0;
	348	}
	349
	350	static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	351	struct snd_pcm_hw_params *params,
dee89c4d MB	352	struct snd_soc_dai *dai)
310355c1 VB	353	{
	354	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	355	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	356	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	357	struct snd_interval *i = NULL;
	358	int mcbsp_word_length;
35cf6358 TK	359	unsigned int rcr, xcr, srgr;
35cf6358 TK	360	u32 spcr;
310355c1 VB	361
310355c1 VB	362	/* general line settings */
35cf6358	363	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
cb6e2063	364	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
35cf6358 TK	365	spcr \|= DAVINCI_MCBSP_SPCR_RINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
35cf6358 TK	366	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063	367	} else {
35cf6358 TK	368	spcr \|= DAVINCI_MCBSP_SPCR_XINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
35cf6358 TK	369	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063	370	}
310355c1 VB	371
310355c1 VB	372	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
35cf6358 TK	373	srgr = DAVINCI_MCBSP_SRGR_FSGM;
35cf6358 TK	374	srgr \|= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
310355c1 VB	375
310355c1 VB	376	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
35cf6358 TK	377	srgr \|= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
35cf6358 TK	378	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
310355c1 VB	379
	380	/* Determine xfer data type */
	381	switch (params_format(params)) {
	382	case SNDRV_PCM_FORMAT_S8:
	383	dma_params->data_type = 1;
	384	mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
	385	break;
	386	case SNDRV_PCM_FORMAT_S16_LE:
	387	dma_params->data_type = 2;
	388	mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
	389	break;
	390	case SNDRV_PCM_FORMAT_S32_LE:
	391	dma_params->data_type = 4;
	392	mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
	393	break;
	394	default:
9b6e12e4	395	printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1 VB	396	return -EINVAL;
	397	}
	398
cb6e2063	399	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
35cf6358 TK	400	rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	401	rcr \|= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) \|
	402	DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
	403	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
310355c1	404
cb6e2063	405	} else {
35cf6358 TK	406	xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	407	xcr \|= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) \|
	408	DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
	409	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
310355c1	410
cb6e2063	411	}
310355c1 VB	412	return 0;
	413	}
	414
dee89c4d MB	415	static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	416	struct snd_soc_dai *dai)
310355c1	417	{
f9af37cc TK	418	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f9af37cc TK	419	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
310355c1	420	int ret = 0;
f9af37cc	421	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
310355c1 VB	422
	423	switch (cmd) {
	424	case SNDRV_PCM_TRIGGER_START:
	425	case SNDRV_PCM_TRIGGER_RESUME:
	426	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
f9af37cc	427	davinci_mcbsp_start(dev, substream);
310355c1 VB	428	break;
	429	case SNDRV_PCM_TRIGGER_STOP:
	430	case SNDRV_PCM_TRIGGER_SUSPEND:
	431	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f9af37cc	432	davinci_mcbsp_stop(dev, playback);
310355c1 VB	433	break;
	434	default:
	435	ret = -EINVAL;
	436	}
	437
	438	return ret;
	439	}
	440
bdb92876	441	static int davinci_i2s_probe(struct platform_device *pdev,
9cb132d7	442	struct snd_soc_dai *dai)
310355c1 VB	443	{
310355c1 VB	444	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549	445	struct snd_soc_card *card = socdev->card;
a62114cb	446	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
310355c1 VB	447	struct davinci_mcbsp_dev *dev;
	448	struct resource mem, ioarea;
	449	struct evm_snd_platform_data *pdata;
	450	int ret;
	451
	452	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	453	if (!mem) {
	454	dev_err(&pdev->dev, "no mem resource?\n");
	455	return -ENODEV;
	456	}
	457
	458	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
	459	pdev->name);
	460	if (!ioarea) {
	461	dev_err(&pdev->dev, "McBSP region already claimed\n");
	462	return -EBUSY;
	463	}
	464
	465	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	466	if (!dev) {
	467	ret = -ENOMEM;
	468	goto err_release_region;
	469	}
	470
	471	cpu_dai->private_data = dev;
	472
a62114cb	473	dev->clk = clk_get(&pdev->dev, NULL);
310355c1 VB	474	if (IS_ERR(dev->clk)) {
	475	ret = -ENODEV;
	476	goto err_free_mem;
	477	}
	478	clk_enable(dev->clk);
	479
	480	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	481	pdata = pdev->dev.platform_data;
	482
	483	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	484	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	485	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	486	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
	487
	488	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	489	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	490	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	491	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
	492
	493	return 0;
	494
	495	err_free_mem:
	496	kfree(dev);
	497	err_release_region:
	498	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	499
	500	return ret;
	501	}
	502
bdb92876	503	static void davinci_i2s_remove(struct platform_device *pdev,
9cb132d7	504	struct snd_soc_dai *dai)
310355c1 VB	505	{
310355c1 VB	506	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549	507	struct snd_soc_card *card = socdev->card;
a62114cb	508	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
310355c1 VB	509	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	510	struct resource *mem;
	511
	512	clk_disable(dev->clk);
	513	clk_put(dev->clk);
	514	dev->clk = NULL;
	515
	516	kfree(dev);
	517
	518	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	519	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	520	}
	521
	522	#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
	523
6335d055 EM	524	static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
	525	.startup = davinci_i2s_startup,
	526	.trigger = davinci_i2s_trigger,
	527	.hw_params = davinci_i2s_hw_params,
	528	.set_fmt = davinci_i2s_set_dai_fmt,
	529	};
	530
9cb132d7	531	struct snd_soc_dai davinci_i2s_dai = {
310355c1 VB	532	.name = "davinci-i2s",
310355c1 VB	533	.id = 0,
310355c1 VB	534	.probe = davinci_i2s_probe,
	535	.remove = davinci_i2s_remove,
	536	.playback = {
	537	.channels_min = 2,
	538	.channels_max = 2,
	539	.rates = DAVINCI_I2S_RATES,
	540	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	541	.capture = {
	542	.channels_min = 2,
	543	.channels_max = 2,
	544	.rates = DAVINCI_I2S_RATES,
	545	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	546	.ops = &davinci_i2s_dai_ops,
310355c1 VB	547	};
	548	EXPORT_SYMBOL_GPL(davinci_i2s_dai);
	549
c9b3a40f	550	static int __init davinci_i2s_init(void)
3f4b783c MB	551	{
	552	return snd_soc_register_dai(&davinci_i2s_dai);
	553	}
	554	module_init(davinci_i2s_init);
	555
	556	static void __exit davinci_i2s_exit(void)
	557	{
	558	snd_soc_unregister_dai(&davinci_i2s_dai);
	559	}
	560	module_exit(davinci_i2s_exit);
	561
310355c1 VB	562	MODULE_AUTHOR("Vladimir Barinov");
	563	MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
	564	MODULE_LICENSE("GPL");