]>
Commit | Line | Data |
---|---|---|
310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/clk.h> | |
18 | ||
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/soc.h> | |
24 | ||
ff7d04b1 MB |
25 | #include <mach/asp.h> |
26 | ||
310355c1 VB |
27 | #include "davinci-pcm.h" |
28 | ||
a62114cb DB |
29 | |
30 | /* | |
31 | * NOTE: terminology here is confusing. | |
32 | * | |
33 | * - This driver supports the "Audio Serial Port" (ASP), | |
34 | * found on dm6446, dm355, and other DaVinci chips. | |
35 | * | |
36 | * - But it labels it a "Multi-channel Buffered Serial Port" | |
37 | * (McBSP) as on older chips like the dm642 ... which was | |
38 | * backward-compatible, possibly explaining that confusion. | |
39 | * | |
40 | * - OMAP chips have a controller called McBSP, which is | |
41 | * incompatible with the DaVinci flavor of McBSP. | |
42 | * | |
43 | * - Newer DaVinci chips have a controller called McASP, | |
44 | * incompatible with ASP and with either McBSP. | |
45 | * | |
46 | * In short: this uses ASP to implement I2S, not McBSP. | |
47 | * And it won't be the only DaVinci implemention of I2S. | |
48 | */ | |
310355c1 VB |
49 | #define DAVINCI_MCBSP_DRR_REG 0x00 |
50 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
51 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
52 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
53 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
54 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
55 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
56 | ||
57 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
58 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
59 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
60 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
61 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
62 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
63 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
64 | ||
65 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
66 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
67 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
f5cfa954 | 68 | #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) |
310355c1 VB |
69 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
70 | ||
71 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
72 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
73 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
74 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
75 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
76 | ||
77 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
78 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
79 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
80 | ||
81 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
82 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
83 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
84 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 85 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
86 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
87 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
88 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
89 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
90 | ||
310355c1 VB |
91 | enum { |
92 | DAVINCI_MCBSP_WORD_8 = 0, | |
93 | DAVINCI_MCBSP_WORD_12, | |
94 | DAVINCI_MCBSP_WORD_16, | |
95 | DAVINCI_MCBSP_WORD_20, | |
96 | DAVINCI_MCBSP_WORD_24, | |
97 | DAVINCI_MCBSP_WORD_32, | |
98 | }; | |
99 | ||
100 | static struct davinci_pcm_dma_params davinci_i2s_pcm_out = { | |
101 | .name = "I2S PCM Stereo out", | |
102 | }; | |
103 | ||
104 | static struct davinci_pcm_dma_params davinci_i2s_pcm_in = { | |
105 | .name = "I2S PCM Stereo in", | |
106 | }; | |
107 | ||
108 | struct davinci_mcbsp_dev { | |
109 | void __iomem *base; | |
f5cfa954 TK |
110 | #define MOD_DSP_A 0 |
111 | #define MOD_DSP_B 1 | |
112 | int mode; | |
c392bec7 | 113 | u32 pcr; |
310355c1 VB |
114 | struct clk *clk; |
115 | struct davinci_pcm_dma_params *dma_params[2]; | |
116 | }; | |
117 | ||
118 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
119 | int reg, u32 val) | |
120 | { | |
121 | __raw_writel(val, dev->base + reg); | |
122 | } | |
123 | ||
124 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
125 | { | |
126 | return __raw_readl(dev->base + reg); | |
127 | } | |
128 | ||
c392bec7 TK |
129 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
130 | { | |
131 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | |
132 | /* The clock needs to toggle to complete reset. | |
133 | * So, fake it by toggling the clk polarity. | |
134 | */ | |
135 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | |
136 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | |
137 | } | |
138 | ||
f9af37cc TK |
139 | static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, |
140 | struct snd_pcm_substream *substream) | |
310355c1 VB |
141 | { |
142 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
fb0ef645 | 143 | struct snd_soc_device *socdev = rtd->socdev; |
87689d56 | 144 | struct snd_soc_platform *platform = socdev->card->platform; |
c392bec7 | 145 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
35cf6358 | 146 | u32 spcr; |
c392bec7 | 147 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 148 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
c392bec7 TK |
149 | if (spcr & mask) { |
150 | /* start off disabled */ | |
151 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, | |
152 | spcr & ~mask); | |
153 | toggle_clock(dev, playback); | |
154 | } | |
1bef4499 TK |
155 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | |
156 | DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { | |
157 | /* Start the sample generator */ | |
158 | spcr |= DAVINCI_MCBSP_SPCR_GRST; | |
159 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
160 | } | |
fb0ef645 | 161 | |
1bef4499 | 162 | if (playback) { |
fb0ef645 NM |
163 | /* Stop the DMA to avoid data loss */ |
164 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
165 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 166 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
167 | SNDRV_PCM_TRIGGER_STOP); |
168 | if (ret < 0) | |
169 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
170 | } | |
171 | ||
172 | /* Enable the transmitter */ | |
35cf6358 TK |
173 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
174 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
175 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
176 | |
177 | /* wait for any unexpected frame sync error to occur */ | |
178 | udelay(100); | |
179 | ||
180 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
35cf6358 TK |
181 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
182 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; | |
183 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
c392bec7 | 184 | toggle_clock(dev, playback); |
fb0ef645 NM |
185 | |
186 | /* Restart the DMA */ | |
187 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 188 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
189 | SNDRV_PCM_TRIGGER_START); |
190 | if (ret < 0) | |
191 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
192 | } | |
fb0ef645 NM |
193 | } |
194 | ||
1bef4499 | 195 | /* Enable transmitter or receiver */ |
35cf6358 | 196 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
1bef4499 TK |
197 | spcr |= mask; |
198 | ||
199 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { | |
200 | /* Start frame sync */ | |
201 | spcr |= DAVINCI_MCBSP_SPCR_FRST; | |
202 | } | |
35cf6358 | 203 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
310355c1 VB |
204 | } |
205 | ||
f9af37cc | 206 | static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
310355c1 | 207 | { |
35cf6358 | 208 | u32 spcr; |
310355c1 VB |
209 | |
210 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
35cf6358 TK |
211 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
212 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); | |
c392bec7 | 213 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 214 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
c392bec7 | 215 | toggle_clock(dev, playback); |
310355c1 VB |
216 | } |
217 | ||
dee89c4d | 218 | static int davinci_i2s_startup(struct snd_pcm_substream *substream, |
9333b594 | 219 | struct snd_soc_dai *cpu_dai) |
310355c1 | 220 | { |
9333b594 | 221 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; |
310355c1 | 222 | cpu_dai->dma_data = dev->dma_params[substream->stream]; |
310355c1 VB |
223 | return 0; |
224 | } | |
225 | ||
21903c1c TK |
226 | #define DEFAULT_BITPERSAMPLE 16 |
227 | ||
9cb132d7 | 228 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
229 | unsigned int fmt) |
230 | { | |
231 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | |
21903c1c TK |
232 | unsigned int pcr; |
233 | unsigned int srgr; | |
21903c1c TK |
234 | srgr = DAVINCI_MCBSP_SRGR_FSGM | |
235 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | |
236 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | |
310355c1 | 237 | |
f5cfa954 | 238 | /* set master/slave audio interface */ |
310355c1 VB |
239 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
240 | case SND_SOC_DAIFMT_CBS_CFS: | |
21903c1c TK |
241 | /* cpu is master */ |
242 | pcr = DAVINCI_MCBSP_PCR_FSXM | | |
243 | DAVINCI_MCBSP_PCR_FSRM | | |
244 | DAVINCI_MCBSP_PCR_CLKXM | | |
245 | DAVINCI_MCBSP_PCR_CLKRM; | |
310355c1 | 246 | break; |
b402dff8 HV |
247 | case SND_SOC_DAIFMT_CBM_CFS: |
248 | /* McBSP CLKR pin is the input for the Sample Rate Generator. | |
249 | * McBSP FSR and FSX are driven by the Sample Rate Generator. */ | |
21903c1c TK |
250 | pcr = DAVINCI_MCBSP_PCR_SCLKME | |
251 | DAVINCI_MCBSP_PCR_FSXM | | |
252 | DAVINCI_MCBSP_PCR_FSRM; | |
b402dff8 | 253 | break; |
310355c1 | 254 | case SND_SOC_DAIFMT_CBM_CFM: |
21903c1c TK |
255 | /* codec is master */ |
256 | pcr = 0; | |
310355c1 VB |
257 | break; |
258 | default: | |
21903c1c | 259 | printk(KERN_ERR "%s:bad master\n", __func__); |
310355c1 VB |
260 | return -EINVAL; |
261 | } | |
262 | ||
f5cfa954 | 263 | /* interface format */ |
69ab820c | 264 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
69ab820c | 265 | case SND_SOC_DAIFMT_I2S: |
07d8d9dc TK |
266 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
267 | * the left and right channels contiguous. This allows | |
268 | * dsp_a mode to be used with an inverted normal frame clk. | |
269 | * If your codec is master and does not have contiguous | |
270 | * channels, then you will have sound on only one channel. | |
271 | * Try using a different mode, or codec as slave. | |
272 | * | |
273 | * The TLV320AIC33 is an example of a codec where this works. | |
274 | * It has a variable bit clock frequency allowing it to have | |
275 | * valid data on every bit clock. | |
276 | * | |
277 | * The TLV320AIC23 is an example of a codec where this does not | |
278 | * work. It has a fixed bit clock frequency with progressively | |
279 | * more empty bit clock slots between channels as the sample | |
280 | * rate is lowered. | |
281 | */ | |
282 | fmt ^= SND_SOC_DAIFMT_NB_IF; | |
283 | case SND_SOC_DAIFMT_DSP_A: | |
f5cfa954 TK |
284 | dev->mode = MOD_DSP_A; |
285 | break; | |
286 | case SND_SOC_DAIFMT_DSP_B: | |
287 | dev->mode = MOD_DSP_B; | |
69ab820c TK |
288 | break; |
289 | default: | |
290 | printk(KERN_ERR "%s:bad format\n", __func__); | |
291 | return -EINVAL; | |
292 | } | |
293 | ||
310355c1 | 294 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
9e031624 | 295 | case SND_SOC_DAIFMT_NB_NF: |
664b4af8 TK |
296 | /* CLKRP Receive clock polarity, |
297 | * 1 - sampled on rising edge of CLKR | |
298 | * valid on rising edge | |
299 | * CLKXP Transmit clock polarity, | |
300 | * 1 - clocked on falling edge of CLKX | |
301 | * valid on rising edge | |
302 | * FSRP Receive frame sync pol, 0 - active high | |
303 | * FSXP Transmit frame sync pol, 0 - active high | |
304 | */ | |
21903c1c | 305 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
310355c1 | 306 | break; |
9e031624 | 307 | case SND_SOC_DAIFMT_IB_IF: |
664b4af8 TK |
308 | /* CLKRP Receive clock polarity, |
309 | * 0 - sampled on falling edge of CLKR | |
310 | * valid on falling edge | |
311 | * CLKXP Transmit clock polarity, | |
312 | * 0 - clocked on rising edge of CLKX | |
313 | * valid on falling edge | |
314 | * FSRP Receive frame sync pol, 1 - active low | |
315 | * FSXP Transmit frame sync pol, 1 - active low | |
316 | */ | |
21903c1c | 317 | pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
310355c1 | 318 | break; |
9e031624 | 319 | case SND_SOC_DAIFMT_NB_IF: |
664b4af8 TK |
320 | /* CLKRP Receive clock polarity, |
321 | * 1 - sampled on rising edge of CLKR | |
322 | * valid on rising edge | |
323 | * CLKXP Transmit clock polarity, | |
324 | * 1 - clocked on falling edge of CLKX | |
325 | * valid on rising edge | |
326 | * FSRP Receive frame sync pol, 1 - active low | |
327 | * FSXP Transmit frame sync pol, 1 - active low | |
328 | */ | |
21903c1c TK |
329 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
330 | DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
310355c1 | 331 | break; |
9e031624 | 332 | case SND_SOC_DAIFMT_IB_NF: |
664b4af8 TK |
333 | /* CLKRP Receive clock polarity, |
334 | * 0 - sampled on falling edge of CLKR | |
335 | * valid on falling edge | |
336 | * CLKXP Transmit clock polarity, | |
337 | * 0 - clocked on rising edge of CLKX | |
338 | * valid on falling edge | |
339 | * FSRP Receive frame sync pol, 0 - active high | |
340 | * FSXP Transmit frame sync pol, 0 - active high | |
341 | */ | |
310355c1 VB |
342 | break; |
343 | default: | |
344 | return -EINVAL; | |
345 | } | |
21903c1c | 346 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
c392bec7 | 347 | dev->pcr = pcr; |
21903c1c | 348 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
310355c1 VB |
349 | return 0; |
350 | } | |
351 | ||
352 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
353 | struct snd_pcm_hw_params *params, |
354 | struct snd_soc_dai *dai) | |
310355c1 VB |
355 | { |
356 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
357 | struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data; | |
358 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
359 | struct snd_interval *i = NULL; | |
360 | int mcbsp_word_length; | |
35cf6358 TK |
361 | unsigned int rcr, xcr, srgr; |
362 | u32 spcr; | |
310355c1 VB |
363 | |
364 | /* general line settings */ | |
35cf6358 | 365 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
cb6e2063 | 366 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
367 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
368 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 369 | } else { |
35cf6358 TK |
370 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
371 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 372 | } |
310355c1 VB |
373 | |
374 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
35cf6358 TK |
375 | srgr = DAVINCI_MCBSP_SRGR_FSGM; |
376 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); | |
310355c1 VB |
377 | |
378 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
35cf6358 TK |
379 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
380 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); | |
310355c1 | 381 | |
f5cfa954 TK |
382 | rcr = DAVINCI_MCBSP_RCR_RFIG; |
383 | xcr = DAVINCI_MCBSP_XCR_XFIG; | |
384 | if (dev->mode == MOD_DSP_B) { | |
385 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); | |
386 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); | |
387 | } else { | |
388 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | |
389 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | |
390 | } | |
310355c1 VB |
391 | /* Determine xfer data type */ |
392 | switch (params_format(params)) { | |
393 | case SNDRV_PCM_FORMAT_S8: | |
394 | dma_params->data_type = 1; | |
395 | mcbsp_word_length = DAVINCI_MCBSP_WORD_8; | |
396 | break; | |
397 | case SNDRV_PCM_FORMAT_S16_LE: | |
398 | dma_params->data_type = 2; | |
399 | mcbsp_word_length = DAVINCI_MCBSP_WORD_16; | |
400 | break; | |
401 | case SNDRV_PCM_FORMAT_S32_LE: | |
402 | dma_params->data_type = 4; | |
403 | mcbsp_word_length = DAVINCI_MCBSP_WORD_32; | |
404 | break; | |
405 | default: | |
9b6e12e4 | 406 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
407 | return -EINVAL; |
408 | } | |
409 | ||
f5cfa954 TK |
410 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1); |
411 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1); | |
310355c1 | 412 | |
f5cfa954 TK |
413 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
414 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); | |
415 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
416 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); | |
310355c1 | 417 | |
f5cfa954 TK |
418 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
419 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
420 | else | |
421 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
310355c1 VB |
422 | return 0; |
423 | } | |
424 | ||
af0adf3e TK |
425 | static int davinci_i2s_prepare(struct snd_pcm_substream *substream, |
426 | struct snd_soc_dai *dai) | |
427 | { | |
428 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
429 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
430 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
431 | davinci_mcbsp_stop(dev, playback); | |
432 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) { | |
433 | /* codec is master */ | |
434 | davinci_mcbsp_start(dev, substream); | |
435 | } | |
436 | return 0; | |
437 | } | |
438 | ||
dee89c4d MB |
439 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
440 | struct snd_soc_dai *dai) | |
310355c1 | 441 | { |
f9af37cc TK |
442 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
443 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
310355c1 | 444 | int ret = 0; |
f9af37cc | 445 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
af0adf3e TK |
446 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) |
447 | return 0; /* return if codec is master */ | |
310355c1 VB |
448 | |
449 | switch (cmd) { | |
450 | case SNDRV_PCM_TRIGGER_START: | |
451 | case SNDRV_PCM_TRIGGER_RESUME: | |
452 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
f9af37cc | 453 | davinci_mcbsp_start(dev, substream); |
310355c1 VB |
454 | break; |
455 | case SNDRV_PCM_TRIGGER_STOP: | |
456 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
457 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
f9af37cc | 458 | davinci_mcbsp_stop(dev, playback); |
310355c1 VB |
459 | break; |
460 | default: | |
461 | ret = -EINVAL; | |
462 | } | |
310355c1 VB |
463 | return ret; |
464 | } | |
465 | ||
af0adf3e TK |
466 | static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
467 | struct snd_soc_dai *dai) | |
468 | { | |
469 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
470 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
471 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
472 | davinci_mcbsp_stop(dev, playback); | |
473 | } | |
474 | ||
5204d496 C |
475 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
476 | ||
477 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { | |
478 | .startup = davinci_i2s_startup, | |
3f405b46 MB |
479 | .shutdown = davinci_i2s_shutdown, |
480 | .prepare = davinci_i2s_prepare, | |
5204d496 C |
481 | .trigger = davinci_i2s_trigger, |
482 | .hw_params = davinci_i2s_hw_params, | |
483 | .set_fmt = davinci_i2s_set_dai_fmt, | |
484 | ||
485 | }; | |
486 | ||
487 | struct snd_soc_dai davinci_i2s_dai = { | |
488 | .name = "davinci-i2s", | |
489 | .id = 0, | |
490 | .playback = { | |
491 | .channels_min = 2, | |
492 | .channels_max = 2, | |
493 | .rates = DAVINCI_I2S_RATES, | |
494 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
495 | .capture = { | |
496 | .channels_min = 2, | |
497 | .channels_max = 2, | |
498 | .rates = DAVINCI_I2S_RATES, | |
499 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
500 | .ops = &davinci_i2s_dai_ops, | |
501 | ||
502 | }; | |
503 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | |
504 | ||
505 | static int davinci_i2s_probe(struct platform_device *pdev) | |
310355c1 | 506 | { |
5204d496 | 507 | struct snd_platform_data *pdata = pdev->dev.platform_data; |
310355c1 | 508 | struct davinci_mcbsp_dev *dev; |
5204d496 | 509 | struct resource *mem, *ioarea, *res; |
310355c1 VB |
510 | int ret; |
511 | ||
512 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
513 | if (!mem) { | |
514 | dev_err(&pdev->dev, "no mem resource?\n"); | |
515 | return -ENODEV; | |
516 | } | |
517 | ||
518 | ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, | |
519 | pdev->name); | |
520 | if (!ioarea) { | |
521 | dev_err(&pdev->dev, "McBSP region already claimed\n"); | |
522 | return -EBUSY; | |
523 | } | |
524 | ||
525 | dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); | |
526 | if (!dev) { | |
527 | ret = -ENOMEM; | |
528 | goto err_release_region; | |
529 | } | |
530 | ||
3e46a447 | 531 | dev->clk = clk_get(&pdev->dev, NULL); |
310355c1 VB |
532 | if (IS_ERR(dev->clk)) { |
533 | ret = -ENODEV; | |
534 | goto err_free_mem; | |
535 | } | |
536 | clk_enable(dev->clk); | |
537 | ||
538 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
310355c1 VB |
539 | |
540 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out; | |
310355c1 VB |
541 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr = |
542 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); | |
543 | ||
544 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in; | |
310355c1 VB |
545 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr = |
546 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); | |
547 | ||
5204d496 C |
548 | /* first TX, then RX */ |
549 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
550 | if (!res) { | |
551 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 552 | ret = -ENXIO; |
5204d496 C |
553 | goto err_free_mem; |
554 | } | |
555 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = res->start; | |
556 | ||
557 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
558 | if (!res) { | |
559 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 560 | ret = -ENXIO; |
5204d496 C |
561 | goto err_free_mem; |
562 | } | |
563 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = res->start; | |
564 | ||
565 | davinci_i2s_dai.private_data = dev; | |
566 | ret = snd_soc_register_dai(&davinci_i2s_dai); | |
567 | if (ret != 0) | |
568 | goto err_free_mem; | |
569 | ||
310355c1 VB |
570 | return 0; |
571 | ||
572 | err_free_mem: | |
573 | kfree(dev); | |
574 | err_release_region: | |
575 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
576 | ||
577 | return ret; | |
578 | } | |
579 | ||
5204d496 | 580 | static int davinci_i2s_remove(struct platform_device *pdev) |
310355c1 | 581 | { |
5204d496 | 582 | struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data; |
310355c1 VB |
583 | struct resource *mem; |
584 | ||
5204d496 | 585 | snd_soc_unregister_dai(&davinci_i2s_dai); |
310355c1 VB |
586 | clk_disable(dev->clk); |
587 | clk_put(dev->clk); | |
588 | dev->clk = NULL; | |
310355c1 | 589 | kfree(dev); |
310355c1 VB |
590 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
591 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
310355c1 | 592 | |
5204d496 C |
593 | return 0; |
594 | } | |
6335d055 | 595 | |
5204d496 C |
596 | static struct platform_driver davinci_mcbsp_driver = { |
597 | .probe = davinci_i2s_probe, | |
598 | .remove = davinci_i2s_remove, | |
599 | .driver = { | |
600 | .name = "davinci-asp", | |
601 | .owner = THIS_MODULE, | |
602 | }, | |
310355c1 | 603 | }; |
310355c1 | 604 | |
c9b3a40f | 605 | static int __init davinci_i2s_init(void) |
3f4b783c | 606 | { |
5204d496 | 607 | return platform_driver_register(&davinci_mcbsp_driver); |
3f4b783c MB |
608 | } |
609 | module_init(davinci_i2s_init); | |
610 | ||
611 | static void __exit davinci_i2s_exit(void) | |
612 | { | |
5204d496 | 613 | platform_driver_unregister(&davinci_mcbsp_driver); |
3f4b783c MB |
614 | } |
615 | module_exit(davinci_i2s_exit); | |
616 | ||
310355c1 VB |
617 | MODULE_AUTHOR("Vladimir Barinov"); |
618 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
619 | MODULE_LICENSE("GPL"); |