[net-next-2.6.git] / sound / soc / davinci / davinci-i2s.c

/*
 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"

#define DAVINCI_MCBSP_DRR_REG	0x00
#define DAVINCI_MCBSP_DXR_REG	0x04
#define DAVINCI_MCBSP_SPCR_REG	0x08
#define DAVINCI_MCBSP_RCR_REG	0x0c
#define DAVINCI_MCBSP_XCR_REG	0x10
#define DAVINCI_MCBSP_SRGR_REG	0x14
#define DAVINCI_MCBSP_PCR_REG	0x24

#define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
#define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
#define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
#define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
#define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
#define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
#define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)

#define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
#define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
#define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
#define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)

#define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
#define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
#define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
#define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
#define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
#define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
#define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
#define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
#define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)

#define MOD_REG_BIT(val, mask, set) do { \
	if (set) { \
		val |= mask; \
	} else { \
		val &= ~mask; \
	} \
} while (0)

enum {
	DAVINCI_MCBSP_WORD_8 = 0,
	DAVINCI_MCBSP_WORD_12,
	DAVINCI_MCBSP_WORD_16,
	DAVINCI_MCBSP_WORD_20,
	DAVINCI_MCBSP_WORD_24,
	DAVINCI_MCBSP_WORD_32,
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	.name = "I2S PCM Stereo out",
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	.name = "I2S PCM Stereo in",
};

struct davinci_mcbsp_dev {
	void __iomem			*base;
	struct clk			*clk;
	struct davinci_pcm_dma_params	*dma_params[2];
};

static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
					   int reg, u32 val)
{
	__raw_writel(val, dev->base + reg);
}

static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
{
	return __raw_readl(dev->base + reg);
}

static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_platform *platform = socdev->card->platform;
	u32 w;
	int ret;

	/* Start the sample generator and enable transmitter/receiver */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		/* Stop the DMA to avoid data loss */
		/* while the transmitter is out of reset to handle XSYNCERR */
		if (platform->pcm_ops->trigger) {
			ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_STOP);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA stop failed\n");
		}

		/* Enable the transmitter */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

		/* wait for any unexpected frame sync error to occur */
		udelay(100);

		/* Disable the transmitter to clear any outstanding XSYNCERR */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

		/* Restart the DMA */
		if (platform->pcm_ops->trigger) {
			ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_START);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA start failed\n");
		}
		/* Enable the transmitter */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	} else {

		/* Enable the reciever */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	}


	/* Start frame sync */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	u32 w;

	/* Reset transmitter/receiver and sample rate/frame sync generators */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
		       DAVINCI_MCBSP_SPCR_FRST, 0);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	else
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static int davinci_i2s_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;

	cpu_dai->dma_data = dev->dma_params[substream->stream];

	return 0;
}

static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				   unsigned int fmt)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	u32 w;

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
					DAVINCI_MCBSP_PCR_FSXM |
					DAVINCI_MCBSP_PCR_FSRM |
					DAVINCI_MCBSP_PCR_CLKXM |
					DAVINCI_MCBSP_PCR_CLKRM);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
					DAVINCI_MCBSP_SRGR_FSGM);
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP CLKR pin is the input for the Sample Rate Generator.
		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
					DAVINCI_MCBSP_PCR_SCLKME |
					DAVINCI_MCBSP_PCR_FSXM |
					DAVINCI_MCBSP_PCR_FSRM);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
					DAVINCI_MCBSP_SRGR_FSGM);
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
			       DAVINCI_MCBSP_PCR_CLKRP, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
			       DAVINCI_MCBSP_PCR_FSRP, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
			       DAVINCI_MCBSP_PCR_CLKRP |
			       DAVINCI_MCBSP_PCR_FSXP |
			       DAVINCI_MCBSP_PCR_FSRP, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
		break;
	case SND_SOC_DAIFMT_NB_NF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
					DAVINCI_MCBSP_RCR_RFRLEN1(1) |
					DAVINCI_MCBSP_RCR_RDATDLY(0));
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
					DAVINCI_MCBSP_XCR_XFRLEN1(1) |
					DAVINCI_MCBSP_XCR_XDATDLY(0) |
					DAVINCI_MCBSP_XCR_XFIG);
		break;
	case SND_SOC_DAIFMT_I2S:
	default:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
					DAVINCI_MCBSP_RCR_RFRLEN1(1) |
					DAVINCI_MCBSP_RCR_RDATDLY(1));
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
					DAVINCI_MCBSP_XCR_XFRLEN1(1) |
					DAVINCI_MCBSP_XCR_XDATDLY(1) |
					DAVINCI_MCBSP_XCR_XFIG);
		break;
	}

	return 0;
}

static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_interval *i = NULL;
	int mcbsp_word_length;
	u32 w;

	/* general line settings */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	} else {
		w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	}

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);

	/* Determine xfer data type */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
		break;
	default:
		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);

	} else {
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);

	}
	return 0;
}

static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		davinci_mcbsp_start(substream);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		davinci_mcbsp_stop(substream);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int davinci_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
	struct davinci_mcbsp_dev *dev;
	struct resource *mem, *ioarea;
	struct evm_snd_platform_data *pdata;
	int ret;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}

	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
				    pdev->name);
	if (!ioarea) {
		dev_err(&pdev->dev, "McBSP region already claimed\n");
		return -EBUSY;
	}

	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err_release_region;
	}

	cpu_dai->private_data = dev;

	dev->clk = clk_get(&pdev->dev, "McBSPCLK");
	if (IS_ERR(dev->clk)) {
		ret = -ENODEV;
		goto err_free_mem;
	}
	clk_enable(dev->clk);

	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	pdata = pdev->dev.platform_data;

	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);

	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);

	return 0;

err_free_mem:
	kfree(dev);
err_release_region:
	release_mem_region(mem->start, (mem->end - mem->start) + 1);

	return ret;
}

static void davinci_i2s_remove(struct platform_device *pdev,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	struct resource *mem;

	clk_disable(dev->clk);
	clk_put(dev->clk);
	dev->clk = NULL;

	kfree(dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem->start, (mem->end - mem->start) + 1);
}

#define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000

struct snd_soc_dai davinci_i2s_dai = {
	.name = "davinci-i2s",
	.id = 0,
	.probe = davinci_i2s_probe,
	.remove = davinci_i2s_remove,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.startup = davinci_i2s_startup,
		.trigger = davinci_i2s_trigger,
		.hw_params = davinci_i2s_hw_params,
		.set_fmt = davinci_i2s_set_dai_fmt,
	},
};
EXPORT_SYMBOL_GPL(davinci_i2s_dai);

static int __init davinci_i2s_init(void)
{
	return snd_soc_register_dai(&davinci_i2s_dai);
}
module_init(davinci_i2s_init);

static void __exit davinci_i2s_exit(void)
{
	snd_soc_unregister_dai(&davinci_i2s_dai);
}
module_exit(davinci_i2s_exit);

MODULE_AUTHOR("Vladimir Barinov");
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
310355c1 VB	1	/*
	2	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/device.h>
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/clk.h>
	18
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
	24
	25	#include "davinci-pcm.h"
	26
	27	#define DAVINCI_MCBSP_DRR_REG 0x00
	28	#define DAVINCI_MCBSP_DXR_REG 0x04
	29	#define DAVINCI_MCBSP_SPCR_REG 0x08
	30	#define DAVINCI_MCBSP_RCR_REG 0x0c
	31	#define DAVINCI_MCBSP_XCR_REG 0x10
	32	#define DAVINCI_MCBSP_SRGR_REG 0x14
	33	#define DAVINCI_MCBSP_PCR_REG 0x24
	34
	35	#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
	36	#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
	37	#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
	38	#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
	39	#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
	40	#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
	41	#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
	42
	43	#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
	44	#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
	45	#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
	46	#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
	47
	48	#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
	49	#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
	50	#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
	51	#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
	52	#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
	53
	54	#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
	55	#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
	56	#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
	57
	58	#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
	59	#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
	60	#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
	61	#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8	62	#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1 VB	63	#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
	64	#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
	65	#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
	66	#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
	67
	68	#define MOD_REG_BIT(val, mask, set) do { \
	69	if (set) { \
	70	val \|= mask; \
	71	} else { \
	72	val &= ~mask; \
	73	} \
	74	} while (0)
	75
	76	enum {
	77	DAVINCI_MCBSP_WORD_8 = 0,
	78	DAVINCI_MCBSP_WORD_12,
	79	DAVINCI_MCBSP_WORD_16,
	80	DAVINCI_MCBSP_WORD_20,
	81	DAVINCI_MCBSP_WORD_24,
	82	DAVINCI_MCBSP_WORD_32,
	83	};
	84
	85	static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	86	.name = "I2S PCM Stereo out",
	87	};
	88
	89	static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	90	.name = "I2S PCM Stereo in",
	91	};
	92
	93	struct davinci_mcbsp_dev {
	94	void __iomem *base;
	95	struct clk *clk;
	96	struct davinci_pcm_dma_params *dma_params[2];
	97	};
	98
	99	static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
	100	int reg, u32 val)
	101	{
	102	__raw_writel(val, dev->base + reg);
	103	}
	104
	105	static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
	106	{
	107	return __raw_readl(dev->base + reg);
	108	}
	109
	110	static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
	111	{
	112	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	113	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
fb0ef645	114	struct snd_soc_device *socdev = rtd->socdev;
87689d56	115	struct snd_soc_platform *platform = socdev->card->platform;
310355c1	116	u32 w;
fb0ef645	117	int ret;
310355c1 VB	118
	119	/* Start the sample generator and enable transmitter/receiver */
	120	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	121	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
fb0ef645 NM	122	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	123
	124	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	125	/* Stop the DMA to avoid data loss */
	126	/* while the transmitter is out of reset to handle XSYNCERR */
	127	if (platform->pcm_ops->trigger) {
	128	ret = platform->pcm_ops->trigger(substream,
	129	SNDRV_PCM_TRIGGER_STOP);
	130	if (ret < 0)
	131	printk(KERN_DEBUG "Playback DMA stop failed\n");
	132	}
	133
	134	/* Enable the transmitter */
	135	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
310355c1	136	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
fb0ef645 NM	137	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	138
	139	/* wait for any unexpected frame sync error to occur */
	140	udelay(100);
	141
	142	/* Disable the transmitter to clear any outstanding XSYNCERR */
	143	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	144	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	145	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	146
	147	/* Restart the DMA */
	148	if (platform->pcm_ops->trigger) {
	149	ret = platform->pcm_ops->trigger(substream,
	150	SNDRV_PCM_TRIGGER_START);
	151	if (ret < 0)
	152	printk(KERN_DEBUG "Playback DMA start failed\n");
	153	}
	154	/* Enable the transmitter */
	155	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	156	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
	157	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	158
	159	} else {
	160
	161	/* Enable the reciever */
	162	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
310355c1	163	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
fb0ef645 NM	164	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	165	}
	166
310355c1 VB	167
	168	/* Start frame sync */
	169	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	170	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	171	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	172	}
	173
	174	static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
	175	{
	176	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	177	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	178	u32 w;
	179
	180	/* Reset transmitter/receiver and sample rate/frame sync generators */
	181	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	182	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST \|
	183	DAVINCI_MCBSP_SPCR_FRST, 0);
	184	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	185	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	186	else
	187	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	188	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	189	}
	190
dee89c4d MB	191	static int davinci_i2s_startup(struct snd_pcm_substream *substream,
dee89c4d MB	192	struct snd_soc_dai *dai)
310355c1 VB	193	{
310355c1 VB	194	struct snd_soc_pcm_runtime *rtd = substream->private_data;
9cb132d7	195	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
310355c1 VB	196	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	197
	198	cpu_dai->dma_data = dev->dma_params[substream->stream];
	199
	200	return 0;
	201	}
	202
9cb132d7	203	static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1 VB	204	unsigned int fmt)
	205	{
	206	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	207	u32 w;
	208
	209	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	210	case SND_SOC_DAIFMT_CBS_CFS:
	211	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
	212	DAVINCI_MCBSP_PCR_FSXM \|
	213	DAVINCI_MCBSP_PCR_FSRM \|
	214	DAVINCI_MCBSP_PCR_CLKXM \|
	215	DAVINCI_MCBSP_PCR_CLKRM);
	216	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
	217	DAVINCI_MCBSP_SRGR_FSGM);
	218	break;
b402dff8 HV	219	case SND_SOC_DAIFMT_CBM_CFS:
	220	/* McBSP CLKR pin is the input for the Sample Rate Generator.
	221	* McBSP FSR and FSX are driven by the Sample Rate Generator. */
	222	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
	223	DAVINCI_MCBSP_PCR_SCLKME \|
	224	DAVINCI_MCBSP_PCR_FSXM \|
	225	DAVINCI_MCBSP_PCR_FSRM);
	226	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
	227	DAVINCI_MCBSP_SRGR_FSGM);
	228	break;
310355c1 VB	229	case SND_SOC_DAIFMT_CBM_CFM:
	230	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
	231	break;
	232	default:
	233	return -EINVAL;
	234	}
	235
	236	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	237	case SND_SOC_DAIFMT_IB_NF:
664b4af8 TK	238	/* CLKRP Receive clock polarity,
	239	* 1 - sampled on rising edge of CLKR
	240	* valid on rising edge
	241	* CLKXP Transmit clock polarity,
	242	* 1 - clocked on falling edge of CLKX
	243	* valid on rising edge
	244	* FSRP Receive frame sync pol, 0 - active high
	245	* FSXP Transmit frame sync pol, 0 - active high
	246	*/
310355c1 VB	247	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
	248	MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP \|
	249	DAVINCI_MCBSP_PCR_CLKRP, 1);
	250	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
	251	break;
	252	case SND_SOC_DAIFMT_NB_IF:
664b4af8 TK	253	/* CLKRP Receive clock polarity,
	254	* 0 - sampled on falling edge of CLKR
	255	* valid on falling edge
	256	* CLKXP Transmit clock polarity,
	257	* 0 - clocked on rising edge of CLKX
	258	* valid on falling edge
	259	* FSRP Receive frame sync pol, 1 - active low
	260	* FSXP Transmit frame sync pol, 1 - active low
	261	*/
310355c1 VB	262	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
	263	MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP \|
	264	DAVINCI_MCBSP_PCR_FSRP, 1);
	265	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
	266	break;
	267	case SND_SOC_DAIFMT_IB_IF:
664b4af8 TK	268	/* CLKRP Receive clock polarity,
	269	* 1 - sampled on rising edge of CLKR
	270	* valid on rising edge
	271	* CLKXP Transmit clock polarity,
	272	* 1 - clocked on falling edge of CLKX
	273	* valid on rising edge
	274	* FSRP Receive frame sync pol, 1 - active low
	275	* FSXP Transmit frame sync pol, 1 - active low
	276	*/
310355c1 VB	277	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
	278	MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP \|
	279	DAVINCI_MCBSP_PCR_CLKRP \|
	280	DAVINCI_MCBSP_PCR_FSXP \|
	281	DAVINCI_MCBSP_PCR_FSRP, 1);
	282	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
	283	break;
	284	case SND_SOC_DAIFMT_NB_NF:
664b4af8 TK	285	/* CLKRP Receive clock polarity,
	286	* 0 - sampled on falling edge of CLKR
	287	* valid on falling edge
	288	* CLKXP Transmit clock polarity,
	289	* 0 - clocked on rising edge of CLKX
	290	* valid on falling edge
	291	* FSRP Receive frame sync pol, 0 - active high
	292	* FSXP Transmit frame sync pol, 0 - active high
	293	*/
310355c1 VB	294	break;
	295	default:
	296	return -EINVAL;
	297	}
	298
b402dff8 HV	299	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	300	case SND_SOC_DAIFMT_RIGHT_J:
	301	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
	302	DAVINCI_MCBSP_RCR_RFRLEN1(1) \|
	303	DAVINCI_MCBSP_RCR_RDATDLY(0));
	304	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
	305	DAVINCI_MCBSP_XCR_XFRLEN1(1) \|
	306	DAVINCI_MCBSP_XCR_XDATDLY(0) \|
	307	DAVINCI_MCBSP_XCR_XFIG);
	308	break;
	309	case SND_SOC_DAIFMT_I2S:
	310	default:
	311	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
	312	DAVINCI_MCBSP_RCR_RFRLEN1(1) \|
	313	DAVINCI_MCBSP_RCR_RDATDLY(1));
	314	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
	315	DAVINCI_MCBSP_XCR_XFRLEN1(1) \|
	316	DAVINCI_MCBSP_XCR_XDATDLY(1) \|
	317	DAVINCI_MCBSP_XCR_XFIG);
	318	break;
	319	}
	320
310355c1 VB	321	return 0;
	322	}
	323
	324	static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	325	struct snd_pcm_hw_params *params,
dee89c4d MB	326	struct snd_soc_dai *dai)
310355c1 VB	327	{
	328	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	329	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	330	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	331	struct snd_interval *i = NULL;
	332	int mcbsp_word_length;
	333	u32 w;
	334
	335	/* general line settings */
cb6e2063 NM	336	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	337	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
	338	w \|= DAVINCI_MCBSP_SPCR_RINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
	339	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	340	} else {
	341	w \|= DAVINCI_MCBSP_SPCR_XINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
	342	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	343	}
310355c1 VB	344
	345	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	346	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	347	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
	348	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
	349
	350	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	351	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	352	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	353	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
	354
	355	/* Determine xfer data type */
	356	switch (params_format(params)) {
	357	case SNDRV_PCM_FORMAT_S8:
	358	dma_params->data_type = 1;
	359	mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
	360	break;
	361	case SNDRV_PCM_FORMAT_S16_LE:
	362	dma_params->data_type = 2;
	363	mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
	364	break;
	365	case SNDRV_PCM_FORMAT_S32_LE:
	366	dma_params->data_type = 4;
	367	mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
	368	break;
	369	default:
9b6e12e4	370	printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1 VB	371	return -EINVAL;
	372	}
	373
cb6e2063 NM	374	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
	375	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	376	MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) \|
	377	DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
	378	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
310355c1	379
cb6e2063 NM	380	} else {
	381	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	382	MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) \|
	383	DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
	384	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
310355c1	385
cb6e2063	386	}
310355c1 VB	387	return 0;
	388	}
	389
dee89c4d MB	390	static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	391	struct snd_soc_dai *dai)
310355c1 VB	392	{
	393	int ret = 0;
	394
	395	switch (cmd) {
	396	case SNDRV_PCM_TRIGGER_START:
	397	case SNDRV_PCM_TRIGGER_RESUME:
	398	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	399	davinci_mcbsp_start(substream);
	400	break;
	401	case SNDRV_PCM_TRIGGER_STOP:
	402	case SNDRV_PCM_TRIGGER_SUSPEND:
	403	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	404	davinci_mcbsp_stop(substream);
	405	break;
	406	default:
	407	ret = -EINVAL;
	408	}
	409
	410	return ret;
	411	}
	412
bdb92876	413	static int davinci_i2s_probe(struct platform_device *pdev,
9cb132d7	414	struct snd_soc_dai *dai)
310355c1 VB	415	{
310355c1 VB	416	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549 MB	417	struct snd_soc_card *card = socdev->card;
87506549 MB	418	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
310355c1 VB	419	struct davinci_mcbsp_dev *dev;
	420	struct resource mem, ioarea;
	421	struct evm_snd_platform_data *pdata;
	422	int ret;
	423
	424	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	425	if (!mem) {
	426	dev_err(&pdev->dev, "no mem resource?\n");
	427	return -ENODEV;
	428	}
	429
	430	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
	431	pdev->name);
	432	if (!ioarea) {
	433	dev_err(&pdev->dev, "McBSP region already claimed\n");
	434	return -EBUSY;
	435	}
	436
	437	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	438	if (!dev) {
	439	ret = -ENOMEM;
	440	goto err_release_region;
	441	}
	442
	443	cpu_dai->private_data = dev;
	444
	445	dev->clk = clk_get(&pdev->dev, "McBSPCLK");
	446	if (IS_ERR(dev->clk)) {
	447	ret = -ENODEV;
	448	goto err_free_mem;
	449	}
	450	clk_enable(dev->clk);
	451
	452	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	453	pdata = pdev->dev.platform_data;
	454
	455	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	456	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	457	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	458	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
	459
	460	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	461	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	462	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	463	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
	464
	465	return 0;
	466
	467	err_free_mem:
	468	kfree(dev);
	469	err_release_region:
	470	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	471
	472	return ret;
	473	}
	474
bdb92876	475	static void davinci_i2s_remove(struct platform_device *pdev,
9cb132d7	476	struct snd_soc_dai *dai)
310355c1 VB	477	{
310355c1 VB	478	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549 MB	479	struct snd_soc_card *card = socdev->card;
87506549 MB	480	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
310355c1 VB	481	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	482	struct resource *mem;
	483
	484	clk_disable(dev->clk);
	485	clk_put(dev->clk);
	486	dev->clk = NULL;
	487
	488	kfree(dev);
	489
	490	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	491	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	492	}
	493
	494	#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
	495
9cb132d7	496	struct snd_soc_dai davinci_i2s_dai = {
310355c1 VB	497	.name = "davinci-i2s",
310355c1 VB	498	.id = 0,
310355c1 VB	499	.probe = davinci_i2s_probe,
	500	.remove = davinci_i2s_remove,
	501	.playback = {
	502	.channels_min = 2,
	503	.channels_max = 2,
	504	.rates = DAVINCI_I2S_RATES,
	505	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	506	.capture = {
	507	.channels_min = 2,
	508	.channels_max = 2,
	509	.rates = DAVINCI_I2S_RATES,
	510	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	511	.ops = {
	512	.startup = davinci_i2s_startup,
	513	.trigger = davinci_i2s_trigger,
dee89c4d	514	.hw_params = davinci_i2s_hw_params,
310355c1 VB	515	.set_fmt = davinci_i2s_set_dai_fmt,
	516	},
	517	};
	518	EXPORT_SYMBOL_GPL(davinci_i2s_dai);
	519
c9b3a40f	520	static int __init davinci_i2s_init(void)
3f4b783c MB	521	{
	522	return snd_soc_register_dai(&davinci_i2s_dai);
	523	}
	524	module_init(davinci_i2s_init);
	525
	526	static void __exit davinci_i2s_exit(void)
	527	{
	528	snd_soc_unregister_dai(&davinci_i2s_dai);
	529	}
	530	module_exit(davinci_i2s_exit);
	531
310355c1 VB	532	MODULE_AUTHOR("Vladimir Barinov");
	533	MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
	534	MODULE_LICENSE("GPL");