[net-next-2.6.git] / sound / soc / davinci / davinci-i2s.c

/*
 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"

#define DAVINCI_MCBSP_DRR_REG	0x00
#define DAVINCI_MCBSP_DXR_REG	0x04
#define DAVINCI_MCBSP_SPCR_REG	0x08
#define DAVINCI_MCBSP_RCR_REG	0x0c
#define DAVINCI_MCBSP_XCR_REG	0x10
#define DAVINCI_MCBSP_SRGR_REG	0x14
#define DAVINCI_MCBSP_PCR_REG	0x24

#define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
#define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
#define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
#define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
#define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
#define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
#define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)

#define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
#define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
#define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
#define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)

#define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
#define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
#define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
#define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
#define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
#define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
#define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
#define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
#define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)

#define MOD_REG_BIT(val, mask, set) do { \
	if (set) { \
		val |= mask; \
	} else { \
		val &= ~mask; \
	} \
} while (0)

enum {
	DAVINCI_MCBSP_WORD_8 = 0,
	DAVINCI_MCBSP_WORD_12,
	DAVINCI_MCBSP_WORD_16,
	DAVINCI_MCBSP_WORD_20,
	DAVINCI_MCBSP_WORD_24,
	DAVINCI_MCBSP_WORD_32,
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	.name = "I2S PCM Stereo out",
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	.name = "I2S PCM Stereo in",
};

struct davinci_mcbsp_dev {
	void __iomem			*base;
	struct clk			*clk;
	struct davinci_pcm_dma_params	*dma_params[2];
};

static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
					   int reg, u32 val)
{
	__raw_writel(val, dev->base + reg);
}

static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
{
	return __raw_readl(dev->base + reg);
}

static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_platform *platform = socdev->card->platform;
	u32 w;
	int ret;

	/* Start the sample generator and enable transmitter/receiver */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		/* Stop the DMA to avoid data loss */
		/* while the transmitter is out of reset to handle XSYNCERR */
		if (platform->pcm_ops->trigger) {
			ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_STOP);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA stop failed\n");
		}

		/* Enable the transmitter */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

		/* wait for any unexpected frame sync error to occur */
		udelay(100);

		/* Disable the transmitter to clear any outstanding XSYNCERR */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

		/* Restart the DMA */
		if (platform->pcm_ops->trigger) {
			ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_START);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA start failed\n");
		}
		/* Enable the transmitter */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	} else {

		/* Enable the reciever */
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	}


	/* Start frame sync */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	u32 w;

	/* Reset transmitter/receiver and sample rate/frame sync generators */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
		       DAVINCI_MCBSP_SPCR_FRST, 0);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	else
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static int davinci_i2s_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;

	cpu_dai->dma_data = dev->dma_params[substream->stream];

	return 0;
}

#define DEFAULT_BITPERSAMPLE	16

static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				   unsigned int fmt)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	unsigned int pcr;
	unsigned int srgr;
	unsigned int rcr;
	unsigned int xcr;
	srgr = DAVINCI_MCBSP_SRGR_FSGM |
		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* cpu is master */
		pcr = DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM |
			DAVINCI_MCBSP_PCR_CLKXM |
			DAVINCI_MCBSP_PCR_CLKRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP CLKR pin is the input for the Sample Rate Generator.
		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
		pcr = DAVINCI_MCBSP_PCR_SCLKME |
			DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is master */
		pcr = 0;
		break;
	default:
		printk(KERN_ERR "%s:bad master\n", __func__);
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
			DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_NB_NF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		break;
	default:
		return -EINVAL;
	}

	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		break;
	case SND_SOC_DAIFMT_I2S:
	case SND_SOC_DAIFMT_DSP_B:
		rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
		xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
		break;
	default:
		printk(KERN_ERR "%s:bad format\n", __func__);
		return -EINVAL;
	}
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
	return 0;
}

static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_interval *i = NULL;
	int mcbsp_word_length;
	u32 w;

	/* general line settings */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	} else {
		w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	}

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	w = DAVINCI_MCBSP_SRGR_FSGM;
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);

	/* Determine xfer data type */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
		break;
	default:
		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);

	} else {
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);

	}
	return 0;
}

static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		davinci_mcbsp_start(substream);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		davinci_mcbsp_stop(substream);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int davinci_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
	struct davinci_mcbsp_dev *dev;
	struct resource *mem, *ioarea;
	struct evm_snd_platform_data *pdata;
	int ret;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}

	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
				    pdev->name);
	if (!ioarea) {
		dev_err(&pdev->dev, "McBSP region already claimed\n");
		return -EBUSY;
	}

	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err_release_region;
	}

	cpu_dai->private_data = dev;

	dev->clk = clk_get(&pdev->dev, "McBSPCLK");
	if (IS_ERR(dev->clk)) {
		ret = -ENODEV;
		goto err_free_mem;
	}
	clk_enable(dev->clk);

	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	pdata = pdev->dev.platform_data;

	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);

	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);

	return 0;

err_free_mem:
	kfree(dev);
err_release_region:
	release_mem_region(mem->start, (mem->end - mem->start) + 1);

	return ret;
}

static void davinci_i2s_remove(struct platform_device *pdev,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	struct resource *mem;

	clk_disable(dev->clk);
	clk_put(dev->clk);
	dev->clk = NULL;

	kfree(dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem->start, (mem->end - mem->start) + 1);
}

#define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000

struct snd_soc_dai davinci_i2s_dai = {
	.name = "davinci-i2s",
	.id = 0,
	.probe = davinci_i2s_probe,
	.remove = davinci_i2s_remove,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.startup = davinci_i2s_startup,
		.trigger = davinci_i2s_trigger,
		.hw_params = davinci_i2s_hw_params,
		.set_fmt = davinci_i2s_set_dai_fmt,
	},
};
EXPORT_SYMBOL_GPL(davinci_i2s_dai);

static int __init davinci_i2s_init(void)
{
	return snd_soc_register_dai(&davinci_i2s_dai);
}
module_init(davinci_i2s_init);

static void __exit davinci_i2s_exit(void)
{
	snd_soc_unregister_dai(&davinci_i2s_dai);
}
module_exit(davinci_i2s_exit);

MODULE_AUTHOR("Vladimir Barinov");
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
310355c1 VB	1	/*
	2	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/device.h>
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/clk.h>
	18
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
	24
	25	#include "davinci-pcm.h"
	26
	27	#define DAVINCI_MCBSP_DRR_REG 0x00
	28	#define DAVINCI_MCBSP_DXR_REG 0x04
	29	#define DAVINCI_MCBSP_SPCR_REG 0x08
	30	#define DAVINCI_MCBSP_RCR_REG 0x0c
	31	#define DAVINCI_MCBSP_XCR_REG 0x10
	32	#define DAVINCI_MCBSP_SRGR_REG 0x14
	33	#define DAVINCI_MCBSP_PCR_REG 0x24
	34
	35	#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
	36	#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
	37	#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
	38	#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
	39	#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
	40	#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
	41	#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
	42
	43	#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
	44	#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
	45	#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
	46	#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
	47
	48	#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
	49	#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
	50	#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
	51	#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
	52	#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
	53
	54	#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
	55	#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
	56	#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
	57
	58	#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
	59	#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
	60	#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
	61	#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8	62	#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1 VB	63	#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
	64	#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
	65	#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
	66	#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
	67
	68	#define MOD_REG_BIT(val, mask, set) do { \
	69	if (set) { \
	70	val \|= mask; \
	71	} else { \
	72	val &= ~mask; \
	73	} \
	74	} while (0)
	75
	76	enum {
	77	DAVINCI_MCBSP_WORD_8 = 0,
	78	DAVINCI_MCBSP_WORD_12,
	79	DAVINCI_MCBSP_WORD_16,
	80	DAVINCI_MCBSP_WORD_20,
	81	DAVINCI_MCBSP_WORD_24,
	82	DAVINCI_MCBSP_WORD_32,
	83	};
	84
	85	static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	86	.name = "I2S PCM Stereo out",
	87	};
	88
	89	static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	90	.name = "I2S PCM Stereo in",
	91	};
	92
	93	struct davinci_mcbsp_dev {
	94	void __iomem *base;
	95	struct clk *clk;
	96	struct davinci_pcm_dma_params *dma_params[2];
	97	};
	98
	99	static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
	100	int reg, u32 val)
	101	{
	102	__raw_writel(val, dev->base + reg);
	103	}
	104
	105	static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
	106	{
	107	return __raw_readl(dev->base + reg);
	108	}
	109
	110	static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
	111	{
	112	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	113	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
fb0ef645	114	struct snd_soc_device *socdev = rtd->socdev;
87689d56	115	struct snd_soc_platform *platform = socdev->card->platform;
310355c1	116	u32 w;
fb0ef645	117	int ret;
310355c1 VB	118
	119	/* Start the sample generator and enable transmitter/receiver */
	120	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	121	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
fb0ef645 NM	122	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	123
	124	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	125	/* Stop the DMA to avoid data loss */
	126	/* while the transmitter is out of reset to handle XSYNCERR */
	127	if (platform->pcm_ops->trigger) {
	128	ret = platform->pcm_ops->trigger(substream,
	129	SNDRV_PCM_TRIGGER_STOP);
	130	if (ret < 0)
	131	printk(KERN_DEBUG "Playback DMA stop failed\n");
	132	}
	133
	134	/* Enable the transmitter */
	135	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
310355c1	136	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
fb0ef645 NM	137	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	138
	139	/* wait for any unexpected frame sync error to occur */
	140	udelay(100);
	141
	142	/* Disable the transmitter to clear any outstanding XSYNCERR */
	143	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	144	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	145	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	146
	147	/* Restart the DMA */
	148	if (platform->pcm_ops->trigger) {
	149	ret = platform->pcm_ops->trigger(substream,
	150	SNDRV_PCM_TRIGGER_START);
	151	if (ret < 0)
	152	printk(KERN_DEBUG "Playback DMA start failed\n");
	153	}
	154	/* Enable the transmitter */
	155	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	156	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
	157	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	158
	159	} else {
	160
	161	/* Enable the reciever */
	162	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
310355c1	163	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
fb0ef645 NM	164	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	165	}
	166
310355c1 VB	167
	168	/* Start frame sync */
	169	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	170	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	171	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	172	}
	173
	174	static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
	175	{
	176	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	177	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	178	u32 w;
	179
	180	/* Reset transmitter/receiver and sample rate/frame sync generators */
	181	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	182	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST \|
	183	DAVINCI_MCBSP_SPCR_FRST, 0);
	184	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	185	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	186	else
	187	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	188	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	189	}
	190
dee89c4d MB	191	static int davinci_i2s_startup(struct snd_pcm_substream *substream,
dee89c4d MB	192	struct snd_soc_dai *dai)
310355c1 VB	193	{
310355c1 VB	194	struct snd_soc_pcm_runtime *rtd = substream->private_data;
9cb132d7	195	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
310355c1 VB	196	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	197
	198	cpu_dai->dma_data = dev->dma_params[substream->stream];
	199
	200	return 0;
	201	}
	202
21903c1c TK	203	#define DEFAULT_BITPERSAMPLE 16
21903c1c TK	204
9cb132d7	205	static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1 VB	206	unsigned int fmt)
	207	{
	208	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
21903c1c TK	209	unsigned int pcr;
	210	unsigned int srgr;
	211	unsigned int rcr;
	212	unsigned int xcr;
	213	srgr = DAVINCI_MCBSP_SRGR_FSGM \|
	214	DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) \|
	215	DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
310355c1 VB	216
	217	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	218	case SND_SOC_DAIFMT_CBS_CFS:
21903c1c TK	219	/* cpu is master */
	220	pcr = DAVINCI_MCBSP_PCR_FSXM \|
	221	DAVINCI_MCBSP_PCR_FSRM \|
	222	DAVINCI_MCBSP_PCR_CLKXM \|
	223	DAVINCI_MCBSP_PCR_CLKRM;
310355c1	224	break;
b402dff8 HV	225	case SND_SOC_DAIFMT_CBM_CFS:
	226	/* McBSP CLKR pin is the input for the Sample Rate Generator.
	227	* McBSP FSR and FSX are driven by the Sample Rate Generator. */
21903c1c TK	228	pcr = DAVINCI_MCBSP_PCR_SCLKME \|
	229	DAVINCI_MCBSP_PCR_FSXM \|
	230	DAVINCI_MCBSP_PCR_FSRM;
b402dff8	231	break;
310355c1	232	case SND_SOC_DAIFMT_CBM_CFM:
21903c1c TK	233	/* codec is master */
21903c1c TK	234	pcr = 0;
310355c1 VB	235	break;
310355c1 VB	236	default:
21903c1c	237	printk(KERN_ERR "%s:bad master\n", __func__);
310355c1 VB	238	return -EINVAL;
	239	}
	240
	241	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	242	case SND_SOC_DAIFMT_IB_NF:
664b4af8 TK	243	/* CLKRP Receive clock polarity,
	244	* 1 - sampled on rising edge of CLKR
	245	* valid on rising edge
	246	* CLKXP Transmit clock polarity,
	247	* 1 - clocked on falling edge of CLKX
	248	* valid on rising edge
	249	* FSRP Receive frame sync pol, 0 - active high
	250	* FSXP Transmit frame sync pol, 0 - active high
	251	*/
21903c1c	252	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP);
310355c1 VB	253	break;
310355c1 VB	254	case SND_SOC_DAIFMT_NB_IF:
664b4af8 TK	255	/* CLKRP Receive clock polarity,
	256	* 0 - sampled on falling edge of CLKR
	257	* valid on falling edge
	258	* CLKXP Transmit clock polarity,
	259	* 0 - clocked on rising edge of CLKX
	260	* valid on falling edge
	261	* FSRP Receive frame sync pol, 1 - active low
	262	* FSXP Transmit frame sync pol, 1 - active low
	263	*/
21903c1c	264	pcr \|= (DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1 VB	265	break;
310355c1 VB	266	case SND_SOC_DAIFMT_IB_IF:
664b4af8 TK	267	/* CLKRP Receive clock polarity,
	268	* 1 - sampled on rising edge of CLKR
	269	* valid on rising edge
	270	* CLKXP Transmit clock polarity,
	271	* 1 - clocked on falling edge of CLKX
	272	* valid on rising edge
	273	* FSRP Receive frame sync pol, 1 - active low
	274	* FSXP Transmit frame sync pol, 1 - active low
	275	*/
21903c1c TK	276	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP \|
21903c1c TK	277	DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1 VB	278	break;
310355c1 VB	279	case SND_SOC_DAIFMT_NB_NF:
664b4af8 TK	280	/* CLKRP Receive clock polarity,
	281	* 0 - sampled on falling edge of CLKR
	282	* valid on falling edge
	283	* CLKXP Transmit clock polarity,
	284	* 0 - clocked on rising edge of CLKX
	285	* valid on falling edge
	286	* FSRP Receive frame sync pol, 0 - active high
	287	* FSXP Transmit frame sync pol, 0 - active high
	288	*/
310355c1 VB	289	break;
	290	default:
	291	return -EINVAL;
	292	}
	293
21903c1c TK	294	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
21903c1c TK	295	xcr = DAVINCI_MCBSP_XCR_XFIG \| DAVINCI_MCBSP_XCR_XFRLEN1(1);
b402dff8 HV	296	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
b402dff8 HV	297	case SND_SOC_DAIFMT_RIGHT_J:
b402dff8 HV	298	break;
b402dff8 HV	299	case SND_SOC_DAIFMT_I2S:
21903c1c TK	300	case SND_SOC_DAIFMT_DSP_B:
	301	rcr \|= DAVINCI_MCBSP_RCR_RDATDLY(1);
	302	xcr \|= DAVINCI_MCBSP_XCR_XDATDLY(1);
b402dff8	303	break;
21903c1c TK	304	default:
	305	printk(KERN_ERR "%s:bad format\n", __func__);
	306	return -EINVAL;
b402dff8	307	}
21903c1c TK	308	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
	309	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	310	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	311	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
310355c1 VB	312	return 0;
	313	}
	314
	315	static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	316	struct snd_pcm_hw_params *params,
dee89c4d MB	317	struct snd_soc_dai *dai)
310355c1 VB	318	{
	319	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	320	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	321	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	322	struct snd_interval *i = NULL;
	323	int mcbsp_word_length;
	324	u32 w;
	325
	326	/* general line settings */
cb6e2063 NM	327	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	328	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
	329	w \|= DAVINCI_MCBSP_SPCR_RINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
	330	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	331	} else {
	332	w \|= DAVINCI_MCBSP_SPCR_XINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
	333	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	334	}
310355c1 VB	335
310355c1 VB	336	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
21903c1c	337	w = DAVINCI_MCBSP_SRGR_FSGM;
310355c1	338	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
310355c1 VB	339
310355c1 VB	340	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
310355c1 VB	341	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	342	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
	343
	344	/* Determine xfer data type */
	345	switch (params_format(params)) {
	346	case SNDRV_PCM_FORMAT_S8:
	347	dma_params->data_type = 1;
	348	mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
	349	break;
	350	case SNDRV_PCM_FORMAT_S16_LE:
	351	dma_params->data_type = 2;
	352	mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
	353	break;
	354	case SNDRV_PCM_FORMAT_S32_LE:
	355	dma_params->data_type = 4;
	356	mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
	357	break;
	358	default:
9b6e12e4	359	printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1 VB	360	return -EINVAL;
	361	}
	362
cb6e2063 NM	363	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
	364	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	365	MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) \|
	366	DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
	367	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
310355c1	368
cb6e2063 NM	369	} else {
	370	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	371	MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) \|
	372	DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
	373	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
310355c1	374
cb6e2063	375	}
310355c1 VB	376	return 0;
	377	}
	378
dee89c4d MB	379	static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	380	struct snd_soc_dai *dai)
310355c1 VB	381	{
	382	int ret = 0;
	383
	384	switch (cmd) {
	385	case SNDRV_PCM_TRIGGER_START:
	386	case SNDRV_PCM_TRIGGER_RESUME:
	387	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	388	davinci_mcbsp_start(substream);
	389	break;
	390	case SNDRV_PCM_TRIGGER_STOP:
	391	case SNDRV_PCM_TRIGGER_SUSPEND:
	392	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	393	davinci_mcbsp_stop(substream);
	394	break;
	395	default:
	396	ret = -EINVAL;
	397	}
	398
	399	return ret;
	400	}
	401
bdb92876	402	static int davinci_i2s_probe(struct platform_device *pdev,
9cb132d7	403	struct snd_soc_dai *dai)
310355c1 VB	404	{
310355c1 VB	405	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549 MB	406	struct snd_soc_card *card = socdev->card;
87506549 MB	407	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
310355c1 VB	408	struct davinci_mcbsp_dev *dev;
	409	struct resource mem, ioarea;
	410	struct evm_snd_platform_data *pdata;
	411	int ret;
	412
	413	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	414	if (!mem) {
	415	dev_err(&pdev->dev, "no mem resource?\n");
	416	return -ENODEV;
	417	}
	418
	419	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
	420	pdev->name);
	421	if (!ioarea) {
	422	dev_err(&pdev->dev, "McBSP region already claimed\n");
	423	return -EBUSY;
	424	}
	425
	426	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	427	if (!dev) {
	428	ret = -ENOMEM;
	429	goto err_release_region;
	430	}
	431
	432	cpu_dai->private_data = dev;
	433
	434	dev->clk = clk_get(&pdev->dev, "McBSPCLK");
	435	if (IS_ERR(dev->clk)) {
	436	ret = -ENODEV;
	437	goto err_free_mem;
	438	}
	439	clk_enable(dev->clk);
	440
	441	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	442	pdata = pdev->dev.platform_data;
	443
	444	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	445	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	446	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	447	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
	448
	449	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	450	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	451	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	452	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
	453
	454	return 0;
	455
	456	err_free_mem:
	457	kfree(dev);
	458	err_release_region:
	459	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	460
	461	return ret;
	462	}
	463
bdb92876	464	static void davinci_i2s_remove(struct platform_device *pdev,
9cb132d7	465	struct snd_soc_dai *dai)
310355c1 VB	466	{
310355c1 VB	467	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549 MB	468	struct snd_soc_card *card = socdev->card;
87506549 MB	469	struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai;
310355c1 VB	470	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	471	struct resource *mem;
	472
	473	clk_disable(dev->clk);
	474	clk_put(dev->clk);
	475	dev->clk = NULL;
	476
	477	kfree(dev);
	478
	479	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	480	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	481	}
	482
	483	#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
	484
9cb132d7	485	struct snd_soc_dai davinci_i2s_dai = {
310355c1 VB	486	.name = "davinci-i2s",
310355c1 VB	487	.id = 0,
310355c1 VB	488	.probe = davinci_i2s_probe,
	489	.remove = davinci_i2s_remove,
	490	.playback = {
	491	.channels_min = 2,
	492	.channels_max = 2,
	493	.rates = DAVINCI_I2S_RATES,
	494	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	495	.capture = {
	496	.channels_min = 2,
	497	.channels_max = 2,
	498	.rates = DAVINCI_I2S_RATES,
	499	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	500	.ops = {
	501	.startup = davinci_i2s_startup,
	502	.trigger = davinci_i2s_trigger,
dee89c4d	503	.hw_params = davinci_i2s_hw_params,
310355c1 VB	504	.set_fmt = davinci_i2s_set_dai_fmt,
	505	},
	506	};
	507	EXPORT_SYMBOL_GPL(davinci_i2s_dai);
	508
c9b3a40f	509	static int __init davinci_i2s_init(void)
3f4b783c MB	510	{
	511	return snd_soc_register_dai(&davinci_i2s_dai);
	512	}
	513	module_init(davinci_i2s_init);
	514
	515	static void __exit davinci_i2s_exit(void)
	516	{
	517	snd_soc_unregister_dai(&davinci_i2s_dai);
	518	}
	519	module_exit(davinci_i2s_exit);
	520
310355c1 VB	521	MODULE_AUTHOR("Vladimir Barinov");
	522	MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
	523	MODULE_LICENSE("GPL");