]> bbs.cooldavid.org Git - net-next-2.6.git/blame - sound/soc/codecs/wm8988.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Remove unneeded control_data management from Wolfson drivers
[net-next-2.6.git] / sound / soc / codecs / wm8988.c
CommitLineData
5409fb4e
MB		 1/*
2 * wm8988.c -- WM8988 ALSA SoC audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 * Copyright 2005 Openedhand Ltd.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/spi/spi.h>
21#include <linux/platform_device.h>
5a0e3ad6 22#include <linux/slab.h>
5409fb4e
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/tlv.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30
31#include "wm8988.h"
32
33/*
34 * wm8988 register cache
35 * We can't read the WM8988 register space when we
36 * are using 2 wire for device control, so we cache them instead.
37 */
38static const u16 wm8988_reg[] = {
39 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
40 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
41 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
42 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
43 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
44 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
45 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
46 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
47 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
48 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
49 0x0079, 0x0079, 0x0079, /* 40 */
50};
51
52/* codec private data */
53struct wm8988_priv {
54 unsigned int sysclk;
f0fba2ad 55 enum snd_soc_control_type control_type;
5409fb4e
MB		 56 struct snd_pcm_hw_constraint_list *sysclk_constraints;
57 u16 reg_cache[WM8988_NUM_REG];
58};
59
60
17a52fd6 61#define wm8988_reset(c) snd_soc_write(c, WM8988_RESET, 0)
5409fb4e
MB		 62
63/*
64 * WM8988 Controls
65 */
66
67static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
68static const struct soc_enum bass_boost =
69 SOC_ENUM_SINGLE(WM8988_BASS, 7, 2, bass_boost_txt);
70
71static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
72static const struct soc_enum bass_filter =
73 SOC_ENUM_SINGLE(WM8988_BASS, 6, 2, bass_filter_txt);
74
75static const char *treble_txt[] = {"8kHz", "4kHz"};
76static const struct soc_enum treble =
77 SOC_ENUM_SINGLE(WM8988_TREBLE, 6, 2, treble_txt);
78
79static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
80static const struct soc_enum stereo_3d_lc =
81 SOC_ENUM_SINGLE(WM8988_3D, 5, 2, stereo_3d_lc_txt);
82
83static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
84static const struct soc_enum stereo_3d_uc =
85 SOC_ENUM_SINGLE(WM8988_3D, 6, 2, stereo_3d_uc_txt);
86
87static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
88static const struct soc_enum stereo_3d_func =
89 SOC_ENUM_SINGLE(WM8988_3D, 7, 2, stereo_3d_func_txt);
90
91static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
92static const struct soc_enum alc_func =
93 SOC_ENUM_SINGLE(WM8988_ALC1, 7, 4, alc_func_txt);
94
95static const char *ng_type_txt[] = {"Constant PGA Gain",
96 "Mute ADC Output"};
97static const struct soc_enum ng_type =
98 SOC_ENUM_SINGLE(WM8988_NGATE, 1, 2, ng_type_txt);
99
100static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
101static const struct soc_enum deemph =
102 SOC_ENUM_SINGLE(WM8988_ADCDAC, 1, 4, deemph_txt);
103
104static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
105 "L + R Invert"};
106static const struct soc_enum adcpol =
107 SOC_ENUM_SINGLE(WM8988_ADCDAC, 5, 4, adcpol_txt);
108
109static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
110static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
111static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
112static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
113static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
114
115static const struct snd_kcontrol_new wm8988_snd_controls[] = {
116
117SOC_ENUM("Bass Boost", bass_boost),
118SOC_ENUM("Bass Filter", bass_filter),
119SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
120
121SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
122SOC_ENUM("Treble Cut-off", treble),
123
124SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
125SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
126SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
127SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
128SOC_ENUM("3D Mode", stereo_3d_func),
129
130SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
131SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
132SOC_ENUM("ALC Capture Function", alc_func),
133SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
134SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
135SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
136SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
137SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
138SOC_ENUM("ALC Capture NG Type", ng_type),
139SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
140
141SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
142
143SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
144 0, 255, 0, adc_tlv),
145SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
146 0, 63, 0, pga_tlv),
147SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
148SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
149
150SOC_ENUM("Playback De-emphasis", deemph),
151
152SOC_ENUM("Capture Polarity", adcpol),
153SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
154SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
155
156SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
157
158SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
159 bypass_tlv),
160SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
161 bypass_tlv),
162SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
163 bypass_tlv),
164SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
165 bypass_tlv),
166
167SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
168 WM8988_ROUT1V, 7, 1, 0),
169SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
170 0, 127, 0, out_tlv),
171
172SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
173 WM8988_ROUT2V, 7, 1, 0),
174SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
175 0, 127, 0, out_tlv),
176
177};
178
179/*
180 * DAPM Controls
181 */
182
183static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
184 struct snd_kcontrol *kcontrol, int event)
185{
186 struct snd_soc_codec *codec = w->codec;
17a52fd6 187 u16 adctl2 = snd_soc_read(codec, WM8988_ADCTL2);
5409fb4e
MB		 188
189 /* Use the DAC to gate LRC if active, otherwise use ADC */
17a52fd6 190 if (snd_soc_read(codec, WM8988_PWR2) & 0x180)
5409fb4e
MB		 191 adctl2 &= ~0x4;
192 else
193 adctl2 |= 0x4;
194
17a52fd6 195 return snd_soc_write(codec, WM8988_ADCTL2, adctl2);
5409fb4e
MB		 196}
197
198static const char *wm8988_line_texts[] = {
199 "Line 1", "Line 2", "PGA", "Differential"};
200
201static const unsigned int wm8988_line_values[] = {
202 0, 1, 3, 4};
203
204static const struct soc_enum wm8988_lline_enum =
205 SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
206 ARRAY_SIZE(wm8988_line_texts),
207 wm8988_line_texts,
208 wm8988_line_values);
209static const struct snd_kcontrol_new wm8988_left_line_controls =
210 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
211
212static const struct soc_enum wm8988_rline_enum =
213 SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
214 ARRAY_SIZE(wm8988_line_texts),
215 wm8988_line_texts,
216 wm8988_line_values);
217static const struct snd_kcontrol_new wm8988_right_line_controls =
218 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
219
220/* Left Mixer */
221static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
222 SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
223 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
224 SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
225 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
226};
227
228/* Right Mixer */
229static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
230 SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
231 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
232 SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
233 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
234};
235
236static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
237static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
238
239/* Left PGA Mux */
240static const struct soc_enum wm8988_lpga_enum =
241 SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
242 ARRAY_SIZE(wm8988_pga_sel),
243 wm8988_pga_sel,
244 wm8988_pga_val);
245static const struct snd_kcontrol_new wm8988_left_pga_controls =
246 SOC_DAPM_VALUE_ENUM("Route", wm8988_lpga_enum);
247
248/* Right PGA Mux */
249static const struct soc_enum wm8988_rpga_enum =
250 SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
251 ARRAY_SIZE(wm8988_pga_sel),
252 wm8988_pga_sel,
253 wm8988_pga_val);
254static const struct snd_kcontrol_new wm8988_right_pga_controls =
255 SOC_DAPM_VALUE_ENUM("Route", wm8988_rpga_enum);
256
257/* Differential Mux */
258static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
259static const struct soc_enum diffmux =
260 SOC_ENUM_SINGLE(WM8988_ADCIN, 8, 2, wm8988_diff_sel);
261static const struct snd_kcontrol_new wm8988_diffmux_controls =
262 SOC_DAPM_ENUM("Route", diffmux);
263
264/* Mono ADC Mux */
265static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
266 "Mono (Right)", "Digital Mono"};
267static const struct soc_enum monomux =
268 SOC_ENUM_SINGLE(WM8988_ADCIN, 6, 4, wm8988_mono_mux);
269static const struct snd_kcontrol_new wm8988_monomux_controls =
270 SOC_DAPM_ENUM("Route", monomux);
271
272static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
273 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8988_PWR1, 1, 0),
274
275 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
276 &wm8988_diffmux_controls),
277 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
278 &wm8988_monomux_controls),
279 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
280 &wm8988_monomux_controls),
281
282 SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
283 &wm8988_left_pga_controls),
284 SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
285 &wm8988_right_pga_controls),
286
287 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
288 &wm8988_left_line_controls),
289 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
290 &wm8988_right_line_controls),
291
292 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
293 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
294
295 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
296 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
297
298 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
299 &wm8988_left_mixer_controls[0],
300 ARRAY_SIZE(wm8988_left_mixer_controls)),
301 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
302 &wm8988_right_mixer_controls[0],
303 ARRAY_SIZE(wm8988_right_mixer_controls)),
304
305 SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
306 SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
307 SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
308 SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
309
310 SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
311
312 SND_SOC_DAPM_OUTPUT("LOUT1"),
313 SND_SOC_DAPM_OUTPUT("ROUT1"),
314 SND_SOC_DAPM_OUTPUT("LOUT2"),
315 SND_SOC_DAPM_OUTPUT("ROUT2"),
316 SND_SOC_DAPM_OUTPUT("VREF"),
317
318 SND_SOC_DAPM_INPUT("LINPUT1"),
319 SND_SOC_DAPM_INPUT("LINPUT2"),
320 SND_SOC_DAPM_INPUT("RINPUT1"),
321 SND_SOC_DAPM_INPUT("RINPUT2"),
322};
323
324static const struct snd_soc_dapm_route audio_map[] = {
325
326 { "Left Line Mux", "Line 1", "LINPUT1" },
327 { "Left Line Mux", "Line 2", "LINPUT2" },
328 { "Left Line Mux", "PGA", "Left PGA Mux" },
329 { "Left Line Mux", "Differential", "Differential Mux" },
330
331 { "Right Line Mux", "Line 1", "RINPUT1" },
332 { "Right Line Mux", "Line 2", "RINPUT2" },
333 { "Right Line Mux", "PGA", "Right PGA Mux" },
334 { "Right Line Mux", "Differential", "Differential Mux" },
335
336 { "Left PGA Mux", "Line 1", "LINPUT1" },
337 { "Left PGA Mux", "Line 2", "LINPUT2" },
338 { "Left PGA Mux", "Differential", "Differential Mux" },
339
340 { "Right PGA Mux", "Line 1", "RINPUT1" },
341 { "Right PGA Mux", "Line 2", "RINPUT2" },
342 { "Right PGA Mux", "Differential", "Differential Mux" },
343
344 { "Differential Mux", "Line 1", "LINPUT1" },
345 { "Differential Mux", "Line 1", "RINPUT1" },
346 { "Differential Mux", "Line 2", "LINPUT2" },
347 { "Differential Mux", "Line 2", "RINPUT2" },
348
349 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
350 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
351 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
352
353 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
354 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
355 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
356
357 { "Left ADC", NULL, "Left ADC Mux" },
358 { "Right ADC", NULL, "Right ADC Mux" },
359
360 { "Left Line Mux", "Line 1", "LINPUT1" },
361 { "Left Line Mux", "Line 2", "LINPUT2" },
362 { "Left Line Mux", "PGA", "Left PGA Mux" },
363 { "Left Line Mux", "Differential", "Differential Mux" },
364
365 { "Right Line Mux", "Line 1", "RINPUT1" },
366 { "Right Line Mux", "Line 2", "RINPUT2" },
367 { "Right Line Mux", "PGA", "Right PGA Mux" },
368 { "Right Line Mux", "Differential", "Differential Mux" },
369
370 { "Left Mixer", "Playback Switch", "Left DAC" },
371 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
372 { "Left Mixer", "Right Playback Switch", "Right DAC" },
373 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
374
375 { "Right Mixer", "Left Playback Switch", "Left DAC" },
376 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
377 { "Right Mixer", "Playback Switch", "Right DAC" },
378 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
379
380 { "Left Out 1", NULL, "Left Mixer" },
381 { "LOUT1", NULL, "Left Out 1" },
382 { "Right Out 1", NULL, "Right Mixer" },
383 { "ROUT1", NULL, "Right Out 1" },
384
385 { "Left Out 2", NULL, "Left Mixer" },
386 { "LOUT2", NULL, "Left Out 2" },
387 { "Right Out 2", NULL, "Right Mixer" },
388 { "ROUT2", NULL, "Right Out 2" },
389};
390
391struct _coeff_div {
392 u32 mclk;
393 u32 rate;
394 u16 fs;
395 u8 sr:5;
396 u8 usb:1;
397};
398
399/* codec hifi mclk clock divider coefficients */
400static const struct _coeff_div coeff_div[] = {
401 /* 8k */
402 {12288000, 8000, 1536, 0x6, 0x0},
403 {11289600, 8000, 1408, 0x16, 0x0},
404 {18432000, 8000, 2304, 0x7, 0x0},
405 {16934400, 8000, 2112, 0x17, 0x0},
406 {12000000, 8000, 1500, 0x6, 0x1},
407
408 /* 11.025k */
409 {11289600, 11025, 1024, 0x18, 0x0},
410 {16934400, 11025, 1536, 0x19, 0x0},
411 {12000000, 11025, 1088, 0x19, 0x1},
412
413 /* 16k */
414 {12288000, 16000, 768, 0xa, 0x0},
415 {18432000, 16000, 1152, 0xb, 0x0},
416 {12000000, 16000, 750, 0xa, 0x1},
417
418 /* 22.05k */
419 {11289600, 22050, 512, 0x1a, 0x0},
420 {16934400, 22050, 768, 0x1b, 0x0},
421 {12000000, 22050, 544, 0x1b, 0x1},
422
423 /* 32k */
424 {12288000, 32000, 384, 0xc, 0x0},
425 {18432000, 32000, 576, 0xd, 0x0},
426 {12000000, 32000, 375, 0xa, 0x1},
427
428 /* 44.1k */
429 {11289600, 44100, 256, 0x10, 0x0},
430 {16934400, 44100, 384, 0x11, 0x0},
431 {12000000, 44100, 272, 0x11, 0x1},
432
433 /* 48k */
434 {12288000, 48000, 256, 0x0, 0x0},
435 {18432000, 48000, 384, 0x1, 0x0},
436 {12000000, 48000, 250, 0x0, 0x1},
437
438 /* 88.2k */
439 {11289600, 88200, 128, 0x1e, 0x0},
440 {16934400, 88200, 192, 0x1f, 0x0},
441 {12000000, 88200, 136, 0x1f, 0x1},
442
443 /* 96k */
444 {12288000, 96000, 128, 0xe, 0x0},
445 {18432000, 96000, 192, 0xf, 0x0},
446 {12000000, 96000, 125, 0xe, 0x1},
447};
448
449static inline int get_coeff(int mclk, int rate)
450{
451 int i;
452
453 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
454 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
455 return i;
456 }
457
458 return -EINVAL;
459}
460
461/* The set of rates we can generate from the above for each SYSCLK */
462
463static unsigned int rates_12288[] = {
464 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
465};
466
467static struct snd_pcm_hw_constraint_list constraints_12288 = {
468 .count = ARRAY_SIZE(rates_12288),
469 .list = rates_12288,
470};
471
472static unsigned int rates_112896[] = {
473 8000, 11025, 22050, 44100,
474};
475
476static struct snd_pcm_hw_constraint_list constraints_112896 = {
477 .count = ARRAY_SIZE(rates_112896),
478 .list = rates_112896,
479};
480
481static unsigned int rates_12[] = {
482 8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
483 48000, 88235, 96000,
484};
485
486static struct snd_pcm_hw_constraint_list constraints_12 = {
487 .count = ARRAY_SIZE(rates_12),
488 .list = rates_12,
489};
490
491/*
492 * Note that this should be called from init rather than from hw_params.
493 */
494static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
495 int clk_id, unsigned int freq, int dir)
496{
497 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 498 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e
MB		 499
500 switch (freq) {
501 case 11289600:
502 case 18432000:
503 case 22579200:
504 case 36864000:
505 wm8988->sysclk_constraints = &constraints_112896;
506 wm8988->sysclk = freq;
507 return 0;
508
509 case 12288000:
510 case 16934400:
511 case 24576000:
512 case 33868800:
513 wm8988->sysclk_constraints = &constraints_12288;
514 wm8988->sysclk = freq;
515 return 0;
516
517 case 12000000:
518 case 24000000:
519 wm8988->sysclk_constraints = &constraints_12;
520 wm8988->sysclk = freq;
521 return 0;
522 }
523 return -EINVAL;
524}
525
526static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
527 unsigned int fmt)
528{
529 struct snd_soc_codec *codec = codec_dai->codec;
530 u16 iface = 0;
531
532 /* set master/slave audio interface */
533 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
534 case SND_SOC_DAIFMT_CBM_CFM:
535 iface = 0x0040;
536 break;
537 case SND_SOC_DAIFMT_CBS_CFS:
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 /* interface format */
544 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
545 case SND_SOC_DAIFMT_I2S:
546 iface |= 0x0002;
547 break;
548 case SND_SOC_DAIFMT_RIGHT_J:
549 break;
550 case SND_SOC_DAIFMT_LEFT_J:
551 iface |= 0x0001;
552 break;
553 case SND_SOC_DAIFMT_DSP_A:
554 iface |= 0x0003;
555 break;
556 case SND_SOC_DAIFMT_DSP_B:
557 iface |= 0x0013;
558 break;
559 default:
560 return -EINVAL;
561 }
562
563 /* clock inversion */
564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
565 case SND_SOC_DAIFMT_NB_NF:
566 break;
567 case SND_SOC_DAIFMT_IB_IF:
568 iface |= 0x0090;
569 break;
570 case SND_SOC_DAIFMT_IB_NF:
571 iface |= 0x0080;
572 break;
573 case SND_SOC_DAIFMT_NB_IF:
574 iface |= 0x0010;
575 break;
576 default:
577 return -EINVAL;
578 }
579
17a52fd6 580 snd_soc_write(codec, WM8988_IFACE, iface);
5409fb4e
MB		 581 return 0;
582}
583
584static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
585 struct snd_soc_dai *dai)
586{
587 struct snd_soc_codec *codec = dai->codec;
b2c812e2 588 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e
MB		 589
590 /* The set of sample rates that can be supported depends on the
591 * MCLK supplied to the CODEC - enforce this.
592 */
593 if (!wm8988->sysclk) {
594 dev_err(codec->dev,
595 "No MCLK configured, call set_sysclk() on init\n");
596 return -EINVAL;
597 }
598
599 snd_pcm_hw_constraint_list(substream->runtime, 0,
600 SNDRV_PCM_HW_PARAM_RATE,
601 wm8988->sysclk_constraints);
602
603 return 0;
604}
605
606static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
607 struct snd_pcm_hw_params *params,
608 struct snd_soc_dai *dai)
609{
610 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 611 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 612 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
17a52fd6
MB		 613 u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
614 u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
5409fb4e
MB		 615 int coeff;
616
617 coeff = get_coeff(wm8988->sysclk, params_rate(params));
618 if (coeff < 0) {
619 coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
620 srate |= 0x40;
621 }
622 if (coeff < 0) {
623 dev_err(codec->dev,
624 "Unable to configure sample rate %dHz with %dHz MCLK\n",
625 params_rate(params), wm8988->sysclk);
626 return coeff;
627 }
628
629 /* bit size */
630 switch (params_format(params)) {
631 case SNDRV_PCM_FORMAT_S16_LE:
632 break;
633 case SNDRV_PCM_FORMAT_S20_3LE:
634 iface |= 0x0004;
635 break;
636 case SNDRV_PCM_FORMAT_S24_LE:
637 iface |= 0x0008;
638 break;
639 case SNDRV_PCM_FORMAT_S32_LE:
640 iface |= 0x000c;
641 break;
642 }
643
644 /* set iface & srate */
17a52fd6 645 snd_soc_write(codec, WM8988_IFACE, iface);
5409fb4e 646 if (coeff >= 0)
17a52fd6 647 snd_soc_write(codec, WM8988_SRATE, srate |
5409fb4e
MB		 648 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
649
650 return 0;
651}
652
653static int wm8988_mute(struct snd_soc_dai *dai, int mute)
654{
655 struct snd_soc_codec *codec = dai->codec;
17a52fd6 656 u16 mute_reg = snd_soc_read(codec, WM8988_ADCDAC) & 0xfff7;
5409fb4e
MB		 657
658 if (mute)
17a52fd6 659 snd_soc_write(codec, WM8988_ADCDAC, mute_reg | 0x8);
5409fb4e 660 else
17a52fd6 661 snd_soc_write(codec, WM8988_ADCDAC, mute_reg);
5409fb4e
MB		 662 return 0;
663}
664
665static int wm8988_set_bias_level(struct snd_soc_codec *codec,
666 enum snd_soc_bias_level level)
667{
17a52fd6 668 u16 pwr_reg = snd_soc_read(codec, WM8988_PWR1) & ~0x1c1;
5409fb4e
MB		 669
670 switch (level) {
671 case SND_SOC_BIAS_ON:
672 break;
673
674 case SND_SOC_BIAS_PREPARE:
675 /* VREF, VMID=2x50k, digital enabled */
17a52fd6 676 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x00c0);
5409fb4e
MB		 677 break;
678
679 case SND_SOC_BIAS_STANDBY:
680 if (codec->bias_level == SND_SOC_BIAS_OFF) {
681 /* VREF, VMID=2x5k */
17a52fd6 682 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
5409fb4e
MB		 683
684 /* Charge caps */
685 msleep(100);
686 }
687
688 /* VREF, VMID=2*500k, digital stopped */
17a52fd6 689 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x0141);
5409fb4e
MB		 690 break;
691
692 case SND_SOC_BIAS_OFF:
17a52fd6 693 snd_soc_write(codec, WM8988_PWR1, 0x0000);
5409fb4e
MB		 694 break;
695 }
696 codec->bias_level = level;
697 return 0;
698}
699
700#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
701
702#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
703 SNDRV_PCM_FMTBIT_S24_LE)
704
705static struct snd_soc_dai_ops wm8988_ops = {
706 .startup = wm8988_pcm_startup,
707 .hw_params = wm8988_pcm_hw_params,
708 .set_fmt = wm8988_set_dai_fmt,
709 .set_sysclk = wm8988_set_dai_sysclk,
710 .digital_mute = wm8988_mute,
711};
712
f0fba2ad
LG		 713static struct snd_soc_dai_driver wm8988_dai = {
714 .name = "wm8988-hifi",
5409fb4e
MB		 715 .playback = {
716 .stream_name = "Playback",
717 .channels_min = 1,
718 .channels_max = 2,
719 .rates = WM8988_RATES,
720 .formats = WM8988_FORMATS,
721 },
722 .capture = {
723 .stream_name = "Capture",
724 .channels_min = 1,
725 .channels_max = 2,
726 .rates = WM8988_RATES,
727 .formats = WM8988_FORMATS,
728 },
729 .ops = &wm8988_ops,
730 .symmetric_rates = 1,
731};
5409fb4e 732
f0fba2ad 733static int wm8988_suspend(struct snd_soc_codec *codec, pm_message_t state)
5409fb4e 734{
5409fb4e
MB		 735 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
736 return 0;
737}
738
f0fba2ad 739static int wm8988_resume(struct snd_soc_codec *codec)
5409fb4e 740{
5409fb4e
MB		 741 int i;
742 u8 data[2];
743 u16 *cache = codec->reg_cache;
744
745 /* Sync reg_cache with the hardware */
746 for (i = 0; i < WM8988_NUM_REG; i++) {
747 if (i == WM8988_RESET)
748 continue;
749 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
750 data[1] = cache[i] & 0x00ff;
751 codec->hw_write(codec->control_data, data, 2);
752 }
753
754 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
755
756 return 0;
757}
758
f0fba2ad 759static int wm8988_probe(struct snd_soc_codec *codec)
5409fb4e 760{
f0fba2ad 761 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e 762 int ret = 0;
5409fb4e
MB		 763 u16 reg;
764
f0fba2ad 765 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8988->control_type);
17a52fd6
MB		 766 if (ret < 0) {
767 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 768 return ret;
17a52fd6
MB		 769 }
770
5409fb4e
MB		 771 ret = wm8988_reset(codec);
772 if (ret < 0) {
773 dev_err(codec->dev, "Failed to issue reset\n");
f0fba2ad 774 return ret;
5409fb4e
MB		 775 }
776
777 /* set the update bits (we always update left then right) */
17a52fd6
MB		 778 reg = snd_soc_read(codec, WM8988_RADC);
779 snd_soc_write(codec, WM8988_RADC, reg | 0x100);
780 reg = snd_soc_read(codec, WM8988_RDAC);
781 snd_soc_write(codec, WM8988_RDAC, reg | 0x0100);
782 reg = snd_soc_read(codec, WM8988_ROUT1V);
783 snd_soc_write(codec, WM8988_ROUT1V, reg | 0x0100);
784 reg = snd_soc_read(codec, WM8988_ROUT2V);
785 snd_soc_write(codec, WM8988_ROUT2V, reg | 0x0100);
786 reg = snd_soc_read(codec, WM8988_RINVOL);
787 snd_soc_write(codec, WM8988_RINVOL, reg | 0x0100);
5409fb4e 788
f0fba2ad 789 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
5409fb4e 790
f0fba2ad
LG		 791 snd_soc_add_controls(codec, wm8988_snd_controls,
792 ARRAY_SIZE(wm8988_snd_controls));
793 snd_soc_dapm_new_controls(codec, wm8988_dapm_widgets,
794 ARRAY_SIZE(wm8988_dapm_widgets));
795 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
5409fb4e
MB		 796
797 return 0;
5409fb4e
MB		 798}
799
f0fba2ad 800static int wm8988_remove(struct snd_soc_codec *codec)
5409fb4e 801{
f0fba2ad
LG		 802 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
803 return 0;
5409fb4e
MB		 804}
805
f0fba2ad
LG		 806static struct snd_soc_codec_driver soc_codec_dev_wm8988 = {
807 .probe = wm8988_probe,
808 .remove = wm8988_remove,
809 .suspend = wm8988_suspend,
810 .resume = wm8988_resume,
811 .set_bias_level = wm8988_set_bias_level,
812 .reg_cache_size = sizeof(wm8988_reg),
813 .reg_word_size = sizeof(u16),
814 .reg_cache_default = wm8988_reg,
815};
816
817#if defined(CONFIG_SPI_MASTER)
818static int __devinit wm8988_spi_probe(struct spi_device *spi)
5409fb4e
MB		 819{
820 struct wm8988_priv *wm8988;
f0fba2ad 821 int ret;
5409fb4e
MB		 822
823 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
824 if (wm8988 == NULL)
825 return -ENOMEM;
826
f0fba2ad
LG		 827 wm8988->control_type = SND_SOC_SPI;
828 spi_set_drvdata(spi, wm8988);
5409fb4e 829
f0fba2ad
LG		 830 ret = snd_soc_register_codec(&spi->dev,
831 &soc_codec_dev_wm8988, &wm8988_dai, 1);
832 if (ret < 0)
833 kfree(wm8988);
834 return ret;
5409fb4e
MB		 835}
836
f0fba2ad 837static int __devexit wm8988_spi_remove(struct spi_device *spi)
5409fb4e 838{
f0fba2ad
LG		 839 snd_soc_unregister_codec(&spi->dev);
840 kfree(spi_get_drvdata(spi));
5409fb4e
MB		 841 return 0;
842}
843
f0fba2ad 844static struct spi_driver wm8988_spi_driver = {
5409fb4e 845 .driver = {
f0fba2ad
LG		 846 .name = "wm8988-codec",
847 .bus = &spi_bus_type,
848 .owner = THIS_MODULE,
5409fb4e 849 },
f0fba2ad
LG		 850 .probe = wm8988_spi_probe,
851 .remove = __devexit_p(wm8988_spi_remove),
5409fb4e 852};
f0fba2ad 853#endif /* CONFIG_SPI_MASTER */
5409fb4e 854
f0fba2ad
LG		 855#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
856static __devinit int wm8988_i2c_probe(struct i2c_client *i2c,
857 const struct i2c_device_id *id)
5409fb4e
MB		 858{
859 struct wm8988_priv *wm8988;
f0fba2ad 860 int ret;
5409fb4e
MB		 861
862 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
863 if (wm8988 == NULL)
864 return -ENOMEM;
865
f0fba2ad 866 i2c_set_clientdata(i2c, wm8988);
f0fba2ad 867 wm8988->control_type = SND_SOC_I2C;
5409fb4e 868
f0fba2ad
LG		 869 ret = snd_soc_register_codec(&i2c->dev,
870 &soc_codec_dev_wm8988, &wm8988_dai, 1);
871 if (ret < 0)
872 kfree(wm8988);
873 return ret;
5409fb4e
MB		 874}
875
f0fba2ad 876static __devexit int wm8988_i2c_remove(struct i2c_client *client)
5409fb4e 877{
f0fba2ad
LG		 878 snd_soc_unregister_codec(&client->dev);
879 kfree(i2c_get_clientdata(client));
5409fb4e
MB		 880 return 0;
881}
882
f0fba2ad
LG		 883static const struct i2c_device_id wm8988_i2c_id[] = {
884 { "wm8988", 0 },
885 { }
886};
887MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
888
889static struct i2c_driver wm8988_i2c_driver = {
5409fb4e 890 .driver = {
f0fba2ad
LG		 891 .name = "wm8988-codec",
892 .owner = THIS_MODULE,
5409fb4e 893 },
f0fba2ad
LG		 894 .probe = wm8988_i2c_probe,
895 .remove = __devexit_p(wm8988_i2c_remove),
896 .id_table = wm8988_i2c_id,
5409fb4e
MB		 897};
898#endif
899
900static int __init wm8988_modinit(void)
901{
f0fba2ad 902 int ret = 0;
5409fb4e
MB		 903#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
904 ret = i2c_add_driver(&wm8988_i2c_driver);
f0fba2ad
LG		 905 if (ret != 0) {
906 printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
907 ret);
908 }
5409fb4e
MB		 909#endif
910#if defined(CONFIG_SPI_MASTER)
911 ret = spi_register_driver(&wm8988_spi_driver);
f0fba2ad
LG		 912 if (ret != 0) {
913 printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
914 ret);
915 }
5409fb4e
MB		 916#endif
917 return ret;
918}
919module_init(wm8988_modinit);
920
921static void __exit wm8988_exit(void)
922{
923#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
924 i2c_del_driver(&wm8988_i2c_driver);
925#endif
926#if defined(CONFIG_SPI_MASTER)
927 spi_unregister_driver(&wm8988_spi_driver);
928#endif
929}
930module_exit(wm8988_exit);
931
932
933MODULE_DESCRIPTION("ASoC WM8988 driver");
934MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
935MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree