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Merge branch 'fix/pcm-jiffies-check' into fix/asoc
[net-next-2.6.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
7220b9f4
PU		 125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
7393958f
PU		 128};
129
cc17557e
SS		 130/*
131 * read twl4030 register cache
132 */
133static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
134 unsigned int reg)
135{
136 u8 *cache = codec->reg_cache;
137
91432e97
IM		 138 if (reg >= TWL4030_CACHEREGNUM)
139 return -EIO;
140
cc17557e
SS		 141 return cache[reg];
142}
143
144/*
145 * write twl4030 register cache
146 */
147static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
148 u8 reg, u8 value)
149{
150 u8 *cache = codec->reg_cache;
151
152 if (reg >= TWL4030_CACHEREGNUM)
153 return;
154 cache[reg] = value;
155}
156
157/*
158 * write to the twl4030 register space
159 */
160static int twl4030_write(struct snd_soc_codec *codec,
161 unsigned int reg, unsigned int value)
162{
163 twl4030_write_reg_cache(codec, reg, value);
164 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
165}
166
db04e2c5 167static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 168{
7393958f 169 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 170 u8 mode;
171
7393958f
PU		 172 if (enable == twl4030->codec_powered)
173 return;
174
cc17557e 175 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 176 if (enable)
177 mode |= TWL4030_CODECPDZ;
178 else
179 mode &= ~TWL4030_CODECPDZ;
cc17557e 180
db04e2c5 181 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 182 twl4030->codec_powered = enable;
cc17557e
SS		 183
184 /* REVISIT: this delay is present in TI sample drivers */
185 /* but there seems to be no TRM requirement for it */
186 udelay(10);
187}
188
189static void twl4030_init_chip(struct snd_soc_codec *codec)
190{
191 int i;
192
193 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 194 twl4030_codec_enable(codec, 0);
cc17557e
SS		 195
196 /* set all audio section registers to reasonable defaults */
197 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
198 twl4030_write(codec, i, twl4030_reg[i]);
199
200}
201
7393958f
PU		 202static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
203{
204 struct twl4030_priv *twl4030 = codec->private_data;
205 u8 reg_val;
206
207 if (mute == twl4030->codec_muted)
208 return;
209
210 if (mute) {
211 /* Bypass the reg_cache and mute the volumes
212 * Headset mute is done in it's own event handler
213 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
214 */
215 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
216 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
217 reg_val & (~TWL4030_EAR_GAIN),
218 TWL4030_REG_EAR_CTL);
219
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_PREDL_GAIN),
223 TWL4030_REG_PREDL_CTL);
224 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
225 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
226 reg_val & (~TWL4030_PREDR_GAIN),
227 TWL4030_REG_PREDL_CTL);
228
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PRECKL_GAIN),
232 TWL4030_REG_PRECKL_CTL);
233 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
234 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
235 reg_val & (~TWL4030_PRECKL_GAIN),
236 TWL4030_REG_PRECKR_CTL);
237
238 /* Disable PLL */
239 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
240 reg_val &= ~TWL4030_APLL_EN;
241 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
242 } else {
243 /* Restore the volumes
244 * Headset mute is done in it's own event handler
245 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
246 */
247 twl4030_write(codec, TWL4030_REG_EAR_CTL,
248 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
249
250 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
251 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
252 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
257 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
259
260 /* Enable PLL */
261 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
262 reg_val |= TWL4030_APLL_EN;
263 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
264 }
265
266 twl4030->codec_muted = mute;
267}
268
006f367e
PU		 269static void twl4030_power_up(struct snd_soc_codec *codec)
270{
7393958f 271 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 272 u8 anamicl, regmisc1, byte;
273 int i = 0;
274
7393958f
PU		 275 if (twl4030->codec_powered)
276 return;
277
006f367e
PU		 278 /* set CODECPDZ to turn on codec */
279 twl4030_codec_enable(codec, 1);
280
281 /* initiate offset cancellation */
282 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
283 twl4030_write(codec, TWL4030_REG_ANAMICL,
284 anamicl | TWL4030_CNCL_OFFSET_START);
285
286 /* wait for offset cancellation to complete */
287 do {
288 /* this takes a little while, so don't slam i2c */
289 udelay(2000);
290 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
291 TWL4030_REG_ANAMICL);
292 } while ((i++ < 100) &&
293 ((byte & TWL4030_CNCL_OFFSET_START) ==
294 TWL4030_CNCL_OFFSET_START));
295
296 /* Make sure that the reg_cache has the same value as the HW */
297 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
298
299 /* anti-pop when changing analog gain */
300 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
301 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
302 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
303
304 /* toggle CODECPDZ as per TRM */
305 twl4030_codec_enable(codec, 0);
306 twl4030_codec_enable(codec, 1);
307}
308
7393958f
PU		 309/*
310 * Unconditional power down
311 */
006f367e
PU		 312static void twl4030_power_down(struct snd_soc_codec *codec)
313{
314 /* power down */
315 twl4030_codec_enable(codec, 0);
316}
317
5e98a464
PU		 318/* Earpiece */
319static const char *twl4030_earpiece_texts[] =
2f423577 320 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 321
2f423577
PU		 322static const unsigned int twl4030_earpiece_values[] =
323 {0x0, 0x1, 0x2, 0x4};
324
cb1ace04 325static const struct soc_enum twl4030_earpiece_enum =
2f423577 326 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 327 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 328 twl4030_earpiece_texts,
329 twl4030_earpiece_values);
5e98a464
PU		 330
331static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 332SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 333
2a6f5c58
PU		 334/* PreDrive Left */
335static const char *twl4030_predrivel_texts[] =
2f423577
PU		 336 {"Off", "DACL1", "DACL2", "DACR2"};
337
338static const unsigned int twl4030_predrivel_values[] =
339 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 340
cb1ace04 341static const struct soc_enum twl4030_predrivel_enum =
2f423577 342 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 343 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 344 twl4030_predrivel_texts,
345 twl4030_predrivel_values);
2a6f5c58
PU		 346
347static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 348SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 349
350/* PreDrive Right */
351static const char *twl4030_predriver_texts[] =
2f423577 352 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 353
2f423577
PU		 354static const unsigned int twl4030_predriver_values[] =
355 {0x0, 0x1, 0x2, 0x4};
356
cb1ace04 357static const struct soc_enum twl4030_predriver_enum =
2f423577 358 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 359 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 360 twl4030_predriver_texts,
361 twl4030_predriver_values);
2a6f5c58
PU		 362
363static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 364SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 365
dfad21a2
PU		 366/* Headset Left */
367static const char *twl4030_hsol_texts[] =
368 {"Off", "DACL1", "DACL2"};
369
370static const struct soc_enum twl4030_hsol_enum =
371 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
372 ARRAY_SIZE(twl4030_hsol_texts),
373 twl4030_hsol_texts);
374
375static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
376SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
377
378/* Headset Right */
379static const char *twl4030_hsor_texts[] =
380 {"Off", "DACR1", "DACR2"};
381
382static const struct soc_enum twl4030_hsor_enum =
383 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
384 ARRAY_SIZE(twl4030_hsor_texts),
385 twl4030_hsor_texts);
386
387static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
388SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
389
5152d8c2
PU		 390/* Carkit Left */
391static const char *twl4030_carkitl_texts[] =
392 {"Off", "DACL1", "DACL2"};
393
394static const struct soc_enum twl4030_carkitl_enum =
395 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
396 ARRAY_SIZE(twl4030_carkitl_texts),
397 twl4030_carkitl_texts);
398
399static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
400SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
401
402/* Carkit Right */
403static const char *twl4030_carkitr_texts[] =
404 {"Off", "DACR1", "DACR2"};
405
406static const struct soc_enum twl4030_carkitr_enum =
407 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
408 ARRAY_SIZE(twl4030_carkitr_texts),
409 twl4030_carkitr_texts);
410
411static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
412SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
413
df339804
PU		 414/* Handsfree Left */
415static const char *twl4030_handsfreel_texts[] =
416 {"Voice", "DACL1", "DACL2", "DACR2"};
417
418static const struct soc_enum twl4030_handsfreel_enum =
419 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
420 ARRAY_SIZE(twl4030_handsfreel_texts),
421 twl4030_handsfreel_texts);
422
423static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
424SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
425
426/* Handsfree Right */
427static const char *twl4030_handsfreer_texts[] =
428 {"Voice", "DACR1", "DACR2", "DACL2"};
429
430static const struct soc_enum twl4030_handsfreer_enum =
431 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
432 ARRAY_SIZE(twl4030_handsfreer_texts),
433 twl4030_handsfreer_texts);
434
435static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
436SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
437
276c6222
PU		 438/* Left analog microphone selection */
439static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 440 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
441
442static const unsigned int twl4030_analoglmic_values[] =
443 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 444
cb1ace04 445static const struct soc_enum twl4030_analoglmic_enum =
2f423577 446 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 447 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 448 twl4030_analoglmic_texts,
449 twl4030_analoglmic_values);
276c6222
PU		 450
451static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 452SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 453
454/* Right analog microphone selection */
455static const char *twl4030_analogrmic_texts[] =
2f423577 456 {"Off", "Sub mic", "AUXR"};
276c6222 457
2f423577
PU		 458static const unsigned int twl4030_analogrmic_values[] =
459 {0x0, 0x1, 0x4};
460
cb1ace04 461static const struct soc_enum twl4030_analogrmic_enum =
2f423577 462 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 463 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 464 twl4030_analogrmic_texts,
465 twl4030_analogrmic_values);
276c6222
PU		 466
467static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 468SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 469
470/* TX1 L/R Analog/Digital microphone selection */
471static const char *twl4030_micpathtx1_texts[] =
472 {"Analog", "Digimic0"};
473
474static const struct soc_enum twl4030_micpathtx1_enum =
475 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
476 ARRAY_SIZE(twl4030_micpathtx1_texts),
477 twl4030_micpathtx1_texts);
478
479static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
480SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
481
482/* TX2 L/R Analog/Digital microphone selection */
483static const char *twl4030_micpathtx2_texts[] =
484 {"Analog", "Digimic1"};
485
486static const struct soc_enum twl4030_micpathtx2_enum =
487 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
488 ARRAY_SIZE(twl4030_micpathtx2_texts),
489 twl4030_micpathtx2_texts);
490
491static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
492SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
493
7393958f
PU		 494/* Analog bypass for AudioR1 */
495static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
496 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
497
498/* Analog bypass for AudioL1 */
499static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
500 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
501
502/* Analog bypass for AudioR2 */
503static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
504 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
505
506/* Analog bypass for AudioL2 */
507static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
508 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
509
6bab83fd
PU		 510/* Digital bypass gain, 0 mutes the bypass */
511static const unsigned int twl4030_dapm_dbypass_tlv[] = {
512 TLV_DB_RANGE_HEAD(2),
513 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
514 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
515};
516
517/* Digital bypass left (TX1L -> RX2L) */
518static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
519 SOC_DAPM_SINGLE_TLV("Volume",
520 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
521 twl4030_dapm_dbypass_tlv);
522
523/* Digital bypass right (TX1R -> RX2R) */
524static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
525 SOC_DAPM_SINGLE_TLV("Volume",
526 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
527 twl4030_dapm_dbypass_tlv);
528
276c6222
PU		 529static int micpath_event(struct snd_soc_dapm_widget *w,
530 struct snd_kcontrol *kcontrol, int event)
531{
532 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
533 unsigned char adcmicsel, micbias_ctl;
534
535 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
536 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
537 /* Prepare the bits for the given TX path:
538 * shift_l == 0: TX1 microphone path
539 * shift_l == 2: TX2 microphone path */
540 if (e->shift_l) {
541 /* TX2 microphone path */
542 if (adcmicsel & TWL4030_TX2IN_SEL)
543 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
544 else
545 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
546 } else {
547 /* TX1 microphone path */
548 if (adcmicsel & TWL4030_TX1IN_SEL)
549 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
550 else
551 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
552 }
553
554 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
555
556 return 0;
557}
558
49d92c7d
SM		 559static int handsfree_event(struct snd_soc_dapm_widget *w,
560 struct snd_kcontrol *kcontrol, int event)
561{
562 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
563 unsigned char hs_ctl;
564
565 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
566
567 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
568 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
569 twl4030_write(w->codec, e->reg, hs_ctl);
570 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
571 twl4030_write(w->codec, e->reg, hs_ctl);
572 hs_ctl |= TWL4030_HF_CTL_HB_EN;
573 twl4030_write(w->codec, e->reg, hs_ctl);
574 } else {
575 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
576 | TWL4030_HF_CTL_HB_EN);
577 twl4030_write(w->codec, e->reg, hs_ctl);
578 }
579
580 return 0;
581}
582
aad749e5
PU		 583static int headsetl_event(struct snd_soc_dapm_widget *w,
584 struct snd_kcontrol *kcontrol, int event)
585{
586 unsigned char hs_gain, hs_pop;
587
588 /* Save the current volume */
589 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
89492be8 590 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
aad749e5
PU		 591
592 switch (event) {
593 case SND_SOC_DAPM_POST_PMU:
594 /* Do the anti-pop/bias ramp enable according to the TRM */
aad749e5
PU		 595 hs_pop |= TWL4030_VMID_EN;
596 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
597 /* Is this needed? Can we just use whatever gain here? */
598 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
599 (hs_gain & (~0x0f)) | 0x0a);
600 hs_pop |= TWL4030_RAMP_EN;
601 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
602
603 /* Restore the original volume */
604 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
605 break;
606 case SND_SOC_DAPM_POST_PMD:
607 /* Do the anti-pop/bias ramp disable according to the TRM */
aad749e5
PU		 608 hs_pop &= ~TWL4030_RAMP_EN;
609 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
610 /* Bypass the reg_cache to mute the headset */
611 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
612 hs_gain & (~0x0f),
613 TWL4030_REG_HS_GAIN_SET);
614 hs_pop &= ~TWL4030_VMID_EN;
615 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
616 break;
617 }
618 return 0;
619}
620
7393958f
PU		 621static int bypass_event(struct snd_soc_dapm_widget *w,
622 struct snd_kcontrol *kcontrol, int event)
623{
624 struct soc_mixer_control *m =
625 (struct soc_mixer_control *)w->kcontrols->private_value;
626 struct twl4030_priv *twl4030 = w->codec->private_data;
627 unsigned char reg;
628
629 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 630
631 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
632 /* Analog bypass */
633 if (reg & (1 << m->shift))
634 twl4030->bypass_state |=
635 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
636 else
637 twl4030->bypass_state &=
638 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
639 } else {
640 /* Digital bypass */
641 if (reg & (0x7 << m->shift))
642 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
643 else
644 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
645 }
7393958f
PU		 646
647 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
648 if (twl4030->bypass_state)
649 twl4030_codec_mute(w->codec, 0);
650 else
651 twl4030_codec_mute(w->codec, 1);
652 }
653 return 0;
654}
655
b0bd53a7
PU		 656/*
657 * Some of the gain controls in TWL (mostly those which are associated with
658 * the outputs) are implemented in an interesting way:
659 * 0x0 : Power down (mute)
660 * 0x1 : 6dB
661 * 0x2 : 0 dB
662 * 0x3 : -6 dB
663 * Inverting not going to help with these.
664 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
665 */
666#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
667 xinvert, tlv_array) \
668{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
669 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
670 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
671 .tlv.p = (tlv_array), \
672 .info = snd_soc_info_volsw, \
673 .get = snd_soc_get_volsw_twl4030, \
674 .put = snd_soc_put_volsw_twl4030, \
675 .private_value = (unsigned long)&(struct soc_mixer_control) \
676 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
677 .max = xmax, .invert = xinvert} }
678#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
679 xinvert, tlv_array) \
680{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
681 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
682 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
683 .tlv.p = (tlv_array), \
684 .info = snd_soc_info_volsw_2r, \
685 .get = snd_soc_get_volsw_r2_twl4030,\
686 .put = snd_soc_put_volsw_r2_twl4030, \
687 .private_value = (unsigned long)&(struct soc_mixer_control) \
688 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 689 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 690#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
691 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
692 xinvert, tlv_array)
693
694static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696{
697 struct soc_mixer_control *mc =
698 (struct soc_mixer_control *)kcontrol->private_value;
699 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
700 unsigned int reg = mc->reg;
701 unsigned int shift = mc->shift;
702 unsigned int rshift = mc->rshift;
703 int max = mc->max;
704 int mask = (1 << fls(max)) - 1;
705
706 ucontrol->value.integer.value[0] =
707 (snd_soc_read(codec, reg) >> shift) & mask;
708 if (ucontrol->value.integer.value[0])
709 ucontrol->value.integer.value[0] =
710 max + 1 - ucontrol->value.integer.value[0];
711
712 if (shift != rshift) {
713 ucontrol->value.integer.value[1] =
714 (snd_soc_read(codec, reg) >> rshift) & mask;
715 if (ucontrol->value.integer.value[1])
716 ucontrol->value.integer.value[1] =
717 max + 1 - ucontrol->value.integer.value[1];
718 }
719
720 return 0;
721}
722
723static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
724 struct snd_ctl_elem_value *ucontrol)
725{
726 struct soc_mixer_control *mc =
727 (struct soc_mixer_control *)kcontrol->private_value;
728 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
729 unsigned int reg = mc->reg;
730 unsigned int shift = mc->shift;
731 unsigned int rshift = mc->rshift;
732 int max = mc->max;
733 int mask = (1 << fls(max)) - 1;
734 unsigned short val, val2, val_mask;
735
736 val = (ucontrol->value.integer.value[0] & mask);
737
738 val_mask = mask << shift;
739 if (val)
740 val = max + 1 - val;
741 val = val << shift;
742 if (shift != rshift) {
743 val2 = (ucontrol->value.integer.value[1] & mask);
744 val_mask |= mask << rshift;
745 if (val2)
746 val2 = max + 1 - val2;
747 val |= val2 << rshift;
748 }
749 return snd_soc_update_bits(codec, reg, val_mask, val);
750}
751
752static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
753 struct snd_ctl_elem_value *ucontrol)
754{
755 struct soc_mixer_control *mc =
756 (struct soc_mixer_control *)kcontrol->private_value;
757 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
758 unsigned int reg = mc->reg;
759 unsigned int reg2 = mc->rreg;
760 unsigned int shift = mc->shift;
761 int max = mc->max;
762 int mask = (1<<fls(max))-1;
763
764 ucontrol->value.integer.value[0] =
765 (snd_soc_read(codec, reg) >> shift) & mask;
766 ucontrol->value.integer.value[1] =
767 (snd_soc_read(codec, reg2) >> shift) & mask;
768
769 if (ucontrol->value.integer.value[0])
770 ucontrol->value.integer.value[0] =
771 max + 1 - ucontrol->value.integer.value[0];
772 if (ucontrol->value.integer.value[1])
773 ucontrol->value.integer.value[1] =
774 max + 1 - ucontrol->value.integer.value[1];
775
776 return 0;
777}
778
779static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
780 struct snd_ctl_elem_value *ucontrol)
781{
782 struct soc_mixer_control *mc =
783 (struct soc_mixer_control *)kcontrol->private_value;
784 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
785 unsigned int reg = mc->reg;
786 unsigned int reg2 = mc->rreg;
787 unsigned int shift = mc->shift;
788 int max = mc->max;
789 int mask = (1 << fls(max)) - 1;
790 int err;
791 unsigned short val, val2, val_mask;
792
793 val_mask = mask << shift;
794 val = (ucontrol->value.integer.value[0] & mask);
795 val2 = (ucontrol->value.integer.value[1] & mask);
796
797 if (val)
798 val = max + 1 - val;
799 if (val2)
800 val2 = max + 1 - val2;
801
802 val = val << shift;
803 val2 = val2 << shift;
804
805 err = snd_soc_update_bits(codec, reg, val_mask, val);
806 if (err < 0)
807 return err;
808
809 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
810 return err;
811}
812
c10b82cf
PU		 813/*
814 * FGAIN volume control:
815 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
816 */
d889a72c 817static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 818
0d33ea0b
PU		 819/*
820 * CGAIN volume control:
821 * 0 dB to 12 dB in 6 dB steps
822 * value 2 and 3 means 12 dB
823 */
d889a72c
PU		 824static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
825
826/*
827 * Analog playback gain
828 * -24 dB to 12 dB in 2 dB steps
829 */
830static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 831
4290239c
PU		 832/*
833 * Gain controls tied to outputs
834 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
835 */
836static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
837
18cc8d8d
JS		 838/*
839 * Gain control for earpiece amplifier
840 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
841 */
842static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
843
381a22b5
PU		 844/*
845 * Capture gain after the ADCs
846 * from 0 dB to 31 dB in 1 dB steps
847 */
848static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
849
5920b453
GI		 850/*
851 * Gain control for input amplifiers
852 * 0 dB to 30 dB in 6 dB steps
853 */
854static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
855
89492be8
PU		 856static const char *twl4030_rampdelay_texts[] = {
857 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
858 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
859 "3495/2581/1748 ms"
860};
861
862static const struct soc_enum twl4030_rampdelay_enum =
863 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
864 ARRAY_SIZE(twl4030_rampdelay_texts),
865 twl4030_rampdelay_texts);
866
cc17557e 867static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 868 /* Common playback gain controls */
869 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
870 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
871 0, 0x3f, 0, digital_fine_tlv),
872 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
873 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
874 0, 0x3f, 0, digital_fine_tlv),
875
876 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
877 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
878 6, 0x2, 0, digital_coarse_tlv),
879 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
880 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
881 6, 0x2, 0, digital_coarse_tlv),
882
883 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
884 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
885 3, 0x12, 1, analog_tlv),
886 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
887 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
888 3, 0x12, 1, analog_tlv),
44c55870
PU		 889 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
890 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
891 1, 1, 0),
892 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
893 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
894 1, 1, 0),
381a22b5 895
4290239c
PU		 896 /* Separate output gain controls */
897 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
898 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
899 4, 3, 0, output_tvl),
900
901 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
902 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
903
904 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
905 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
906 4, 3, 0, output_tvl),
907
908 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 909 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 910
381a22b5 911 /* Common capture gain controls */
276c6222 912 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 913 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
914 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 915 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
916 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
917 0, 0x1f, 0, digital_capture_tlv),
5920b453 918
276c6222 919 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 920 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 921
922 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
cc17557e
SS		 923};
924
cc17557e 925static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 926 /* Left channel inputs */
927 SND_SOC_DAPM_INPUT("MAINMIC"),
928 SND_SOC_DAPM_INPUT("HSMIC"),
929 SND_SOC_DAPM_INPUT("AUXL"),
930 SND_SOC_DAPM_INPUT("CARKITMIC"),
931 /* Right channel inputs */
932 SND_SOC_DAPM_INPUT("SUBMIC"),
933 SND_SOC_DAPM_INPUT("AUXR"),
934 /* Digital microphones (Stereo) */
935 SND_SOC_DAPM_INPUT("DIGIMIC0"),
936 SND_SOC_DAPM_INPUT("DIGIMIC1"),
937
938 /* Outputs */
cc17557e
SS		 939 SND_SOC_DAPM_OUTPUT("OUTL"),
940 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 941 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 942 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
943 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 944 SND_SOC_DAPM_OUTPUT("HSOL"),
945 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 946 SND_SOC_DAPM_OUTPUT("CARKITL"),
947 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 948 SND_SOC_DAPM_OUTPUT("HFL"),
949 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 950
53b5047d 951 /* DACs */
1e5fa31f 952 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 953 SND_SOC_NOPM, 0, 0),
1e5fa31f 954 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 955 SND_SOC_NOPM, 0, 0),
1e5fa31f 956 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 957 SND_SOC_NOPM, 0, 0),
1e5fa31f 958 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 959 SND_SOC_NOPM, 0, 0),
cc17557e 960
44c55870
PU		 961 /* Analog PGAs */
962 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
963 0, 0, NULL, 0),
964 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
965 0, 0, NULL, 0),
966 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
967 0, 0, NULL, 0),
968 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
969 0, 0, NULL, 0),
970
7393958f
PU		 971 /* Analog bypasses */
972 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
973 &twl4030_dapm_abypassr1_control, bypass_event,
974 SND_SOC_DAPM_POST_REG),
975 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
976 &twl4030_dapm_abypassl1_control,
977 bypass_event, SND_SOC_DAPM_POST_REG),
978 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
979 &twl4030_dapm_abypassr2_control,
980 bypass_event, SND_SOC_DAPM_POST_REG),
981 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
982 &twl4030_dapm_abypassl2_control,
983 bypass_event, SND_SOC_DAPM_POST_REG),
984
6bab83fd
PU		 985 /* Digital bypasses */
986 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
987 &twl4030_dapm_dbypassl_control, bypass_event,
988 SND_SOC_DAPM_POST_REG),
989 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
990 &twl4030_dapm_dbypassr_control, bypass_event,
991 SND_SOC_DAPM_POST_REG),
992
7393958f
PU		 993 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
994 0, 0, NULL, 0),
995 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
996 1, 0, NULL, 0),
997 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
998 2, 0, NULL, 0),
999 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
1000 3, 0, NULL, 0),
1001
5e98a464
PU		 1002 /* Output MUX controls */
1003 /* Earpiece */
2f423577
PU		 1004 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
1005 &twl4030_dapm_earpiece_control),
2a6f5c58 1006 /* PreDrivL/R */
2f423577
PU		 1007 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
1008 &twl4030_dapm_predrivel_control),
1009 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
1010 &twl4030_dapm_predriver_control),
dfad21a2 1011 /* HeadsetL/R */
aad749e5
PU		 1012 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
1013 &twl4030_dapm_hsol_control, headsetl_event,
1014 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2
PU		 1015 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
1016 &twl4030_dapm_hsor_control),
5152d8c2
PU		 1017 /* CarkitL/R */
1018 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
1019 &twl4030_dapm_carkitl_control),
1020 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
1021 &twl4030_dapm_carkitr_control),
df339804 1022 /* HandsfreeL/R */
49d92c7d
SM		 1023 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1024 &twl4030_dapm_handsfreel_control, handsfree_event,
1025 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1026 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1027 &twl4030_dapm_handsfreer_control, handsfree_event,
1028 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 1029
276c6222
PU		 1030 /* Introducing four virtual ADC, since TWL4030 have four channel for
1031 capture */
1032 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1033 SND_SOC_NOPM, 0, 0),
1034 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1035 SND_SOC_NOPM, 0, 0),
1036 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1037 SND_SOC_NOPM, 0, 0),
1038 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1039 SND_SOC_NOPM, 0, 0),
1040
1041 /* Analog/Digital mic path selection.
1042 TX1 Left/Right: either analog Left/Right or Digimic0
1043 TX2 Left/Right: either analog Left/Right or Digimic1 */
1044 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1045 &twl4030_dapm_micpathtx1_control, micpath_event,
1046 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1047 SND_SOC_DAPM_POST_REG),
1048 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1049 &twl4030_dapm_micpathtx2_control, micpath_event,
1050 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1051 SND_SOC_DAPM_POST_REG),
1052
fb2a2f84 1053 /* Analog input muxes with switch for the capture amplifiers */
2f423577 1054 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 1055 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 1056 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 1057 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 1058
fb2a2f84
PU		 1059 SND_SOC_DAPM_PGA("ADC Physical Left",
1060 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1061 SND_SOC_DAPM_PGA("ADC Physical Right",
1062 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1063
1064 SND_SOC_DAPM_PGA("Digimic0 Enable",
1065 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1066 SND_SOC_DAPM_PGA("Digimic1 Enable",
1067 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1068
1069 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1070 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1071 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1072
cc17557e
SS		 1073};
1074
1075static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1076 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1077 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1078 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1079 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
1080
1081 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1082 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1083 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1084 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
44c55870 1085
5e98a464
PU		 1086 /* Internal playback routings */
1087 /* Earpiece */
1088 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
1089 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
1090 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 1091 /* PreDrivL */
1092 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
1093 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
1094 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
1095 /* PreDrivR */
1096 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
1097 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
1098 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 1099 /* HeadsetL */
1100 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
1101 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
1102 /* HeadsetR */
1103 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
1104 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 1105 /* CarkitL */
1106 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
1107 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
1108 /* CarkitR */
1109 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
1110 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 1111 /* HandsfreeL */
1112 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
1113 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
1114 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
1115 /* HandsfreeR */
1116 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
1117 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
1118 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 1119
cc17557e 1120 /* outputs */
44c55870
PU		 1121 {"OUTL", NULL, "ARXL2_APGA"},
1122 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 1123 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 1124 {"PREDRIVEL", NULL, "PredriveL Mux"},
1125 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 1126 {"HSOL", NULL, "HeadsetL Mux"},
1127 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 1128 {"CARKITL", NULL, "CarkitL Mux"},
1129 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 1130 {"HFL", NULL, "HandsfreeL Mux"},
1131 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 1132
276c6222
PU		 1133 /* Capture path */
1134 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1135 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1136 {"Analog Left Capture Route", "AUXL", "AUXL"},
1137 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1138
1139 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1140 {"Analog Right Capture Route", "AUXR", "AUXR"},
1141
fb2a2f84
PU		 1142 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1143 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1144
1145 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1146 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1147
1148 /* TX1 Left capture path */
fb2a2f84 1149 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1150 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1151 /* TX1 Right capture path */
fb2a2f84 1152 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1153 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1154 /* TX2 Left capture path */
fb2a2f84 1155 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1156 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1157 /* TX2 Right capture path */
fb2a2f84 1158 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1159 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1160
1161 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1162 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1163 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1164 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1165
7393958f
PU		 1166 /* Analog bypass routes */
1167 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1168 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1169 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1170 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1171
1172 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1173 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1174 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1175 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1176
6bab83fd
PU		 1177 /* Digital bypass routes */
1178 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1179 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1180
1181 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1182 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
1183
cc17557e
SS		 1184};
1185
1186static int twl4030_add_widgets(struct snd_soc_codec *codec)
1187{
1188 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1189 ARRAY_SIZE(twl4030_dapm_widgets));
1190
1191 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1192
1193 snd_soc_dapm_new_widgets(codec);
1194 return 0;
1195}
1196
cc17557e
SS		 1197static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1198 enum snd_soc_bias_level level)
1199{
7393958f
PU		 1200 struct twl4030_priv *twl4030 = codec->private_data;
1201
cc17557e
SS		 1202 switch (level) {
1203 case SND_SOC_BIAS_ON:
7393958f 1204 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1205 break;
1206 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1207 twl4030_power_up(codec);
1208 if (twl4030->bypass_state)
1209 twl4030_codec_mute(codec, 0);
1210 else
1211 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1212 break;
1213 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1214 twl4030_power_up(codec);
1215 if (twl4030->bypass_state)
1216 twl4030_codec_mute(codec, 0);
1217 else
1218 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1219 break;
1220 case SND_SOC_BIAS_OFF:
1221 twl4030_power_down(codec);
1222 break;
1223 }
1224 codec->bias_level = level;
1225
1226 return 0;
1227}
1228
d6648da1
PU		 1229static int twl4030_startup(struct snd_pcm_substream *substream,
1230 struct snd_soc_dai *dai)
7220b9f4
PU		 1231{
1232 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1233 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1234 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1235 struct twl4030_priv *twl4030 = codec->private_data;
1236
1237 /* If we already have a playback or capture going then constrain
1238 * this substream to match it.
1239 */
1240 if (twl4030->master_substream) {
1241 struct snd_pcm_runtime *master_runtime;
1242 master_runtime = twl4030->master_substream->runtime;
1243
1244 snd_pcm_hw_constraint_minmax(substream->runtime,
1245 SNDRV_PCM_HW_PARAM_RATE,
1246 master_runtime->rate,
1247 master_runtime->rate);
1248
1249 snd_pcm_hw_constraint_minmax(substream->runtime,
1250 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1251 master_runtime->sample_bits,
1252 master_runtime->sample_bits);
1253
1254 twl4030->slave_substream = substream;
1255 } else
1256 twl4030->master_substream = substream;
1257
1258 return 0;
1259}
1260
d6648da1
PU		 1261static void twl4030_shutdown(struct snd_pcm_substream *substream,
1262 struct snd_soc_dai *dai)
7220b9f4
PU		 1263{
1264 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1265 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1266 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1267 struct twl4030_priv *twl4030 = codec->private_data;
1268
1269 if (twl4030->master_substream == substream)
1270 twl4030->master_substream = twl4030->slave_substream;
1271
1272 twl4030->slave_substream = NULL;
1273}
1274
cc17557e 1275static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1276 struct snd_pcm_hw_params *params,
1277 struct snd_soc_dai *dai)
cc17557e
SS		 1278{
1279 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1280 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1281 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1282 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1283 u8 mode, old_mode, format, old_format;
1284
7220b9f4
PU		 1285 if (substream == twl4030->slave_substream)
1286 /* Ignoring hw_params for slave substream */
1287 return 0;
1288
cc17557e
SS		 1289 /* bit rate */
1290 old_mode = twl4030_read_reg_cache(codec,
1291 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1292 mode = old_mode & ~TWL4030_APLL_RATE;
1293
1294 switch (params_rate(params)) {
1295 case 8000:
1296 mode |= TWL4030_APLL_RATE_8000;
1297 break;
1298 case 11025:
1299 mode |= TWL4030_APLL_RATE_11025;
1300 break;
1301 case 12000:
1302 mode |= TWL4030_APLL_RATE_12000;
1303 break;
1304 case 16000:
1305 mode |= TWL4030_APLL_RATE_16000;
1306 break;
1307 case 22050:
1308 mode |= TWL4030_APLL_RATE_22050;
1309 break;
1310 case 24000:
1311 mode |= TWL4030_APLL_RATE_24000;
1312 break;
1313 case 32000:
1314 mode |= TWL4030_APLL_RATE_32000;
1315 break;
1316 case 44100:
1317 mode |= TWL4030_APLL_RATE_44100;
1318 break;
1319 case 48000:
1320 mode |= TWL4030_APLL_RATE_48000;
1321 break;
103f211d
PU		 1322 case 96000:
1323 mode |= TWL4030_APLL_RATE_96000;
1324 break;
cc17557e
SS		 1325 default:
1326 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1327 params_rate(params));
1328 return -EINVAL;
1329 }
1330
1331 if (mode != old_mode) {
1332 /* change rate and set CODECPDZ */
7393958f 1333 twl4030_codec_enable(codec, 0);
cc17557e 1334 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1335 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1336 }
1337
1338 /* sample size */
1339 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1340 format = old_format;
1341 format &= ~TWL4030_DATA_WIDTH;
1342 switch (params_format(params)) {
1343 case SNDRV_PCM_FORMAT_S16_LE:
1344 format |= TWL4030_DATA_WIDTH_16S_16W;
1345 break;
1346 case SNDRV_PCM_FORMAT_S24_LE:
1347 format |= TWL4030_DATA_WIDTH_32S_24W;
1348 break;
1349 default:
1350 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1351 params_format(params));
1352 return -EINVAL;
1353 }
1354
1355 if (format != old_format) {
1356
1357 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1358 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1359
1360 /* change format */
1361 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1362
1363 /* set CODECPDZ afterwards */
db04e2c5 1364 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1365 }
1366 return 0;
1367}
1368
1369static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1370 int clk_id, unsigned int freq, int dir)
1371{
1372 struct snd_soc_codec *codec = codec_dai->codec;
1373 u8 infreq;
1374
1375 switch (freq) {
1376 case 19200000:
1377 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1378 break;
1379 case 26000000:
1380 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1381 break;
1382 case 38400000:
1383 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1384 break;
1385 default:
1386 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1387 freq);
1388 return -EINVAL;
1389 }
1390
1391 infreq |= TWL4030_APLL_EN;
1392 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1393
1394 return 0;
1395}
1396
1397static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1398 unsigned int fmt)
1399{
1400 struct snd_soc_codec *codec = codec_dai->codec;
1401 u8 old_format, format;
1402
1403 /* get format */
1404 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1405 format = old_format;
1406
1407 /* set master/slave audio interface */
1408 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1409 case SND_SOC_DAIFMT_CBM_CFM:
1410 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1411 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1412 break;
1413 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1414 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1415 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1416 break;
1417 default:
1418 return -EINVAL;
1419 }
1420
1421 /* interface format */
1422 format &= ~TWL4030_AIF_FORMAT;
1423 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1424 case SND_SOC_DAIFMT_I2S:
1425 format |= TWL4030_AIF_FORMAT_CODEC;
1426 break;
1427 default:
1428 return -EINVAL;
1429 }
1430
1431 if (format != old_format) {
1432
1433 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1434 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1435
1436 /* change format */
1437 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1438
1439 /* set CODECPDZ afterwards */
db04e2c5 1440 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1441 }
1442
1443 return 0;
1444}
1445
bbba9444 1446#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1447#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1448
10d9e3d9 1449static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1450 .startup = twl4030_startup,
1451 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1452 .hw_params = twl4030_hw_params,
1453 .set_sysclk = twl4030_set_dai_sysclk,
1454 .set_fmt = twl4030_set_dai_fmt,
1455};
1456
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SS		 1457struct snd_soc_dai twl4030_dai = {
1458 .name = "twl4030",
1459 .playback = {
1460 .stream_name = "Playback",
1461 .channels_min = 2,
1462 .channels_max = 2,
31ad0f31 1463 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
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SS		 1464 .formats = TWL4030_FORMATS,},
1465 .capture = {
1466 .stream_name = "Capture",
1467 .channels_min = 2,
1468 .channels_max = 2,
1469 .rates = TWL4030_RATES,
1470 .formats = TWL4030_FORMATS,},
10d9e3d9 1471 .ops = &twl4030_dai_ops,
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SS		 1472};
1473EXPORT_SYMBOL_GPL(twl4030_dai);
1474
1475static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1476{
1477 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1478 struct snd_soc_codec *codec = socdev->card->codec;
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SS		 1479
1480 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1481
1482 return 0;
1483}
1484
1485static int twl4030_resume(struct platform_device *pdev)
1486{
1487 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1488 struct snd_soc_codec *codec = socdev->card->codec;
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SS		 1489
1490 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1491 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1492 return 0;
1493}
1494
1495/*
1496 * initialize the driver
1497 * register the mixer and dsp interfaces with the kernel
1498 */
1499
1500static int twl4030_init(struct snd_soc_device *socdev)
1501{
6627a653 1502 struct snd_soc_codec *codec = socdev->card->codec;
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SS		 1503 int ret = 0;
1504
1505 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1506
1507 codec->name = "twl4030";
1508 codec->owner = THIS_MODULE;
1509 codec->read = twl4030_read_reg_cache;
1510 codec->write = twl4030_write;
1511 codec->set_bias_level = twl4030_set_bias_level;
1512 codec->dai = &twl4030_dai;
1513 codec->num_dai = 1;
1514 codec->reg_cache_size = sizeof(twl4030_reg);
1515 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1516 GFP_KERNEL);
1517 if (codec->reg_cache == NULL)
1518 return -ENOMEM;
1519
1520 /* register pcms */
1521 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1522 if (ret < 0) {
1523 printk(KERN_ERR "twl4030: failed to create pcms\n");
1524 goto pcm_err;
1525 }
1526
1527 twl4030_init_chip(codec);
1528
1529 /* power on device */
1530 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1531
3e8e1952
IM		 1532 snd_soc_add_controls(codec, twl4030_snd_controls,
1533 ARRAY_SIZE(twl4030_snd_controls));
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SS		 1534 twl4030_add_widgets(codec);
1535
968a6025 1536 ret = snd_soc_init_card(socdev);
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SS		 1537 if (ret < 0) {
1538 printk(KERN_ERR "twl4030: failed to register card\n");
1539 goto card_err;
1540 }
1541
1542 return ret;
1543
1544card_err:
1545 snd_soc_free_pcms(socdev);
1546 snd_soc_dapm_free(socdev);
1547pcm_err:
1548 kfree(codec->reg_cache);
1549 return ret;
1550}
1551
1552static struct snd_soc_device *twl4030_socdev;
1553
1554static int twl4030_probe(struct platform_device *pdev)
1555{
1556 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1557 struct snd_soc_codec *codec;
7393958f 1558 struct twl4030_priv *twl4030;
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SS		 1559
1560 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1561 if (codec == NULL)
1562 return -ENOMEM;
1563
7393958f
PU		 1564 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1565 if (twl4030 == NULL) {
1566 kfree(codec);
1567 return -ENOMEM;
1568 }
1569
1570 codec->private_data = twl4030;
6627a653 1571 socdev->card->codec = codec;
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SS		 1572 mutex_init(&codec->mutex);
1573 INIT_LIST_HEAD(&codec->dapm_widgets);
1574 INIT_LIST_HEAD(&codec->dapm_paths);
1575
1576 twl4030_socdev = socdev;
1577 twl4030_init(socdev);
1578
1579 return 0;
1580}
1581
1582static int twl4030_remove(struct platform_device *pdev)
1583{
1584 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1585 struct snd_soc_codec *codec = socdev->card->codec;
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SS		 1586
1587 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1588 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1589 snd_soc_free_pcms(socdev);
1590 snd_soc_dapm_free(socdev);
7393958f 1591 kfree(codec->private_data);
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SS		 1592 kfree(codec);
1593
1594 return 0;
1595}
1596
1597struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1598 .probe = twl4030_probe,
1599 .remove = twl4030_remove,
1600 .suspend = twl4030_suspend,
1601 .resume = twl4030_resume,
1602};
1603EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1604
24e07db8 1605static int __init twl4030_modinit(void)
64089b84
MB		 1606{
1607 return snd_soc_register_dai(&twl4030_dai);
1608}
24e07db8 1609module_init(twl4030_modinit);
64089b84
MB		 1610
1611static void __exit twl4030_exit(void)
1612{
1613 snd_soc_unregister_dai(&twl4030_dai);
1614}
1615module_exit(twl4030_exit);
1616
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SS		 1617MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1618MODULE_AUTHOR("Steve Sakoman");
1619MODULE_LICENSE("GPL");
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