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ASoC: Add indirection for CODEC private data
[net-next-2.6.git] / sound / soc / codecs / tlv320aic3x.c
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44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/platform_device.h>
44d0a879
VB		 42#include <sound/core.h>
43#include <sound/pcm.h>
44#include <sound/pcm_params.h>
45#include <sound/soc.h>
46#include <sound/soc-dapm.h>
47#include <sound/initval.h>
7565fc38 48#include <sound/tlv.h>
44d0a879
VB		 49
50#include "tlv320aic3x.h"
51
4f9c16cc 52#define AIC3X_VERSION "0.2"
44d0a879
VB		 53
54/* codec private data */
55struct aic3x_priv {
cb3826f5 56 struct snd_soc_codec codec;
44d0a879
VB		 57 unsigned int sysclk;
58 int master;
59};
60
61/*
62 * AIC3X register cache
63 * We can't read the AIC3X register space when we are
64 * using 2 wire for device control, so we cache them instead.
65 * There is no point in caching the reset register
66 */
67static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
68 0x00, 0x00, 0x00, 0x10, /* 0 */
69 0x04, 0x00, 0x00, 0x00, /* 4 */
70 0x00, 0x00, 0x00, 0x01, /* 8 */
71 0x00, 0x00, 0x00, 0x80, /* 12 */
72 0x80, 0xff, 0xff, 0x78, /* 16 */
73 0x78, 0x78, 0x78, 0x78, /* 20 */
74 0x78, 0x00, 0x00, 0xfe, /* 24 */
75 0x00, 0x00, 0xfe, 0x00, /* 28 */
76 0x18, 0x18, 0x00, 0x00, /* 32 */
77 0x00, 0x00, 0x00, 0x00, /* 36 */
78 0x00, 0x00, 0x00, 0x80, /* 40 */
79 0x80, 0x00, 0x00, 0x00, /* 44 */
80 0x00, 0x00, 0x00, 0x04, /* 48 */
81 0x00, 0x00, 0x00, 0x00, /* 52 */
82 0x00, 0x00, 0x04, 0x00, /* 56 */
83 0x00, 0x00, 0x00, 0x00, /* 60 */
84 0x00, 0x04, 0x00, 0x00, /* 64 */
85 0x00, 0x00, 0x00, 0x00, /* 68 */
86 0x04, 0x00, 0x00, 0x00, /* 72 */
87 0x00, 0x00, 0x00, 0x00, /* 76 */
88 0x00, 0x00, 0x00, 0x00, /* 80 */
89 0x00, 0x00, 0x00, 0x00, /* 84 */
90 0x00, 0x00, 0x00, 0x00, /* 88 */
91 0x00, 0x00, 0x00, 0x00, /* 92 */
92 0x00, 0x00, 0x00, 0x00, /* 96 */
93 0x00, 0x00, 0x02, /* 100 */
94};
95
96/*
97 * read aic3x register cache
98 */
99static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
100 unsigned int reg)
101{
102 u8 *cache = codec->reg_cache;
103 if (reg >= AIC3X_CACHEREGNUM)
104 return -1;
105 return cache[reg];
106}
107
108/*
109 * write aic3x register cache
110 */
111static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
112 u8 reg, u8 value)
113{
114 u8 *cache = codec->reg_cache;
115 if (reg >= AIC3X_CACHEREGNUM)
116 return;
117 cache[reg] = value;
118}
119
120/*
121 * write to the aic3x register space
122 */
123static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
124 unsigned int value)
125{
126 u8 data[2];
127
128 /* data is
129 * D15..D8 aic3x register offset
130 * D7...D0 register data
131 */
132 data[0] = reg & 0xff;
133 data[1] = value & 0xff;
134
135 aic3x_write_reg_cache(codec, data[0], data[1]);
136 if (codec->hw_write(codec->control_data, data, 2) == 2)
137 return 0;
138 else
139 return -EIO;
140}
141
54e7e616
DM		 142/*
143 * read from the aic3x register space
144 */
145static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
146 u8 *value)
147{
148 *value = reg & 0xff;
5f345346
MB		 149
150 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
54e7e616
DM		 151
152 aic3x_write_reg_cache(codec, reg, *value);
153 return 0;
154}
155
44d0a879
VB		 156#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
157{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
158 .info = snd_soc_info_volsw, \
159 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
160 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
161
162/*
163 * All input lines are connected when !0xf and disconnected with 0xf bit field,
164 * so we have to use specific dapm_put call for input mixer
165 */
166static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
167 struct snd_ctl_elem_value *ucontrol)
168{
169 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 170 struct soc_mixer_control *mc =
171 (struct soc_mixer_control *)kcontrol->private_value;
172 unsigned int reg = mc->reg;
173 unsigned int shift = mc->shift;
174 int max = mc->max;
175 unsigned int mask = (1 << fls(max)) - 1;
176 unsigned int invert = mc->invert;
44d0a879
VB		 177 unsigned short val, val_mask;
178 int ret;
179 struct snd_soc_dapm_path *path;
180 int found = 0;
181
182 val = (ucontrol->value.integer.value[0] & mask);
183
184 mask = 0xf;
185 if (val)
186 val = mask;
187
188 if (invert)
189 val = mask - val;
190 val_mask = mask << shift;
191 val = val << shift;
192
193 mutex_lock(&widget->codec->mutex);
194
195 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
196 /* find dapm widget path assoc with kcontrol */
197 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
198 if (path->kcontrol != kcontrol)
199 continue;
200
201 /* found, now check type */
202 found = 1;
203 if (val)
204 /* new connection */
205 path->connect = invert ? 0 : 1;
206 else
207 /* old connection must be powered down */
208 path->connect = invert ? 1 : 0;
209 break;
210 }
211
212 if (found)
a5302181 213 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 214 }
215
216 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
217
218 mutex_unlock(&widget->codec->mutex);
219 return ret;
220}
221
222static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
223static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
224static const char *aic3x_left_hpcom_mux[] =
225 { "differential of HPLOUT", "constant VCM", "single-ended" };
226static const char *aic3x_right_hpcom_mux[] =
227 { "differential of HPROUT", "constant VCM", "single-ended",
228 "differential of HPLCOM", "external feedback" };
229static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 230static const char *aic3x_adc_hpf[] =
231 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 232
233#define LDAC_ENUM 0
234#define RDAC_ENUM 1
235#define LHPCOM_ENUM 2
236#define RHPCOM_ENUM 3
237#define LINE1L_ENUM 4
238#define LINE1R_ENUM 5
239#define LINE2L_ENUM 6
240#define LINE2R_ENUM 7
4d20f70a 241#define ADC_HPF_ENUM 8
44d0a879
VB		 242
243static const struct soc_enum aic3x_enum[] = {
244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
245 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
246 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
247 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
248 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 252 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 253};
254
7565fc38
JN		 255/*
256 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
257 */
258static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
259/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
260static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
261/*
262 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
263 * Step size is approximately 0.5 dB over most of the scale but increasing
264 * near the very low levels.
265 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
266 * but having increasing dB difference below that (and where it doesn't count
267 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
268 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
269 */
270static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
271
44d0a879
VB		 272static const struct snd_kcontrol_new aic3x_snd_controls[] = {
273 /* Output */
7565fc38
JN		 274 SOC_DOUBLE_R_TLV("PCM Playback Volume",
275 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 276
7565fc38
JN		 277 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
278 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
279 0, 118, 1, output_stage_tlv),
28a1d869
DM		 280 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
281 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
7565fc38
JN		 282 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
283 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
284 0, 118, 1, output_stage_tlv),
285 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
286 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
287 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
288 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
290 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
291 0, 118, 1, output_stage_tlv),
292 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
293 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
294 0, 118, 1, output_stage_tlv),
295
296 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
297 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
298 0, 118, 1, output_stage_tlv),
44d0a879 299 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
7565fc38
JN		 300 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
301 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
302 0, 118, 1, output_stage_tlv),
303 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
304 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
305 0, 118, 1, output_stage_tlv),
306
307 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
308 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
309 0, 118, 1, output_stage_tlv),
44d0a879
VB		 310 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
311 0x01, 0),
7565fc38
JN		 312 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
313 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
314 0, 118, 1, output_stage_tlv),
315 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
316 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
318 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
319 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
320 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
321 0, 118, 1, output_stage_tlv),
322
323 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
324 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
325 0, 118, 1, output_stage_tlv),
44d0a879
VB		 326 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
327 0x01, 0),
7565fc38
JN		 328 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
329 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
331 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
333 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
334 0, 118, 1, output_stage_tlv),
44d0a879
VB		 335
336 /*
337 * Note: enable Automatic input Gain Controller with care. It can
338 * adjust PGA to max value when ADC is on and will never go back.
339 */
340 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
341
342 /* Input */
7565fc38
JN		 343 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
344 0, 119, 0, adc_tlv),
44d0a879 345 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 346
347 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 348};
349
44d0a879
VB		 350/* Left DAC Mux */
351static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
352SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
353
354/* Right DAC Mux */
355static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
356SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
357
358/* Left HPCOM Mux */
359static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
360SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
361
362/* Right HPCOM Mux */
363static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
364SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
365
366/* Left DAC_L1 Mixer */
367static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
54f01916
DM		 368 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
369 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 370 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
371 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
372 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
373};
374
375/* Right DAC_R1 Mixer */
376static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
54f01916
DM		 377 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
378 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 379 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
380 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
381 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
382};
383
384/* Left PGA Mixer */
385static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
386 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 387 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 388 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
389 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 390 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 391};
392
393/* Right PGA Mixer */
394static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
395 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 396 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 397 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 398 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 399 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
400};
401
402/* Left Line1 Mux */
403static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
404SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
405
406/* Right Line1 Mux */
407static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
408SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
409
410/* Left Line2 Mux */
411static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
412SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
413
414/* Right Line2 Mux */
415static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
416SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
417
418/* Left PGA Bypass Mixer */
419static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
54f01916
DM		 420 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
44d0a879 422 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 423 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 427};
428
429/* Right PGA Bypass Mixer */
430static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
54f01916
DM		 431 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
44d0a879 433 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 434 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 438};
439
440/* Left Line2 Bypass Mixer */
441static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
54f01916
DM		 442 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 444 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
54f01916 446 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
44d0a879
VB		 447};
448
449/* Right Line2 Bypass Mixer */
450static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
54f01916
DM		 451 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 453 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
54f01916 455 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 456};
457
458static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
459 /* Left DAC to Left Outputs */
460 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
461 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
462 &aic3x_left_dac_mux_controls),
463 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
464 &aic3x_left_dac_mixer_controls[0],
465 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
466 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
467 &aic3x_left_hpcom_mux_controls),
468 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
469 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
470 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
471
472 /* Right DAC to Right Outputs */
473 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
474 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
475 &aic3x_right_dac_mux_controls),
476 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
477 &aic3x_right_dac_mixer_controls[0],
478 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
479 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
480 &aic3x_right_hpcom_mux_controls),
481 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
482 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
483 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
484
485 /* Mono Output */
486 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
487
54f01916 488 /* Inputs to Left ADC */
44d0a879
VB		 489 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
490 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
491 &aic3x_left_pga_mixer_controls[0],
492 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
493 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
494 &aic3x_left_line1_mux_controls),
54f01916
DM		 495 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
496 &aic3x_left_line1_mux_controls),
44d0a879
VB		 497 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
498 &aic3x_left_line2_mux_controls),
499
54f01916 500 /* Inputs to Right ADC */
44d0a879
VB		 501 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
502 LINE1R_2_RADC_CTRL, 2, 0),
503 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
504 &aic3x_right_pga_mixer_controls[0],
505 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 506 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
507 &aic3x_right_line1_mux_controls),
44d0a879
VB		 508 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
509 &aic3x_right_line1_mux_controls),
510 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
511 &aic3x_right_line2_mux_controls),
512
ee15ffdb
JN		 513 /*
514 * Not a real mic bias widget but similar function. This is for dynamic
515 * control of GPIO1 digital mic modulator clock output function when
516 * using digital mic.
517 */
518 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
519 AIC3X_GPIO1_REG, 4, 0xf,
520 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
521 AIC3X_GPIO1_FUNC_DISABLED),
522
523 /*
524 * Also similar function like mic bias. Selects digital mic with
525 * configurable oversampling rate instead of ADC converter.
526 */
527 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
528 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
529 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
530 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
531 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
532 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
533
44d0a879 534 /* Mic Bias */
0bd72a3d
JN		 535 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
536 MICBIAS_CTRL, 6, 3, 1, 0),
537 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
538 MICBIAS_CTRL, 6, 3, 2, 0),
539 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
540 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879
VB		 541
542 /* Left PGA to Left Output bypass */
543 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
544 &aic3x_left_pga_bp_mixer_controls[0],
545 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
546
547 /* Right PGA to Right Output bypass */
548 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
549 &aic3x_right_pga_bp_mixer_controls[0],
550 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
551
552 /* Left Line2 to Left Output bypass */
553 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
554 &aic3x_left_line2_bp_mixer_controls[0],
555 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
556
557 /* Right Line2 to Right Output bypass */
558 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
559 &aic3x_right_line2_bp_mixer_controls[0],
560 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
561
562 SND_SOC_DAPM_OUTPUT("LLOUT"),
563 SND_SOC_DAPM_OUTPUT("RLOUT"),
564 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
565 SND_SOC_DAPM_OUTPUT("HPLOUT"),
566 SND_SOC_DAPM_OUTPUT("HPROUT"),
567 SND_SOC_DAPM_OUTPUT("HPLCOM"),
568 SND_SOC_DAPM_OUTPUT("HPRCOM"),
569
570 SND_SOC_DAPM_INPUT("MIC3L"),
571 SND_SOC_DAPM_INPUT("MIC3R"),
572 SND_SOC_DAPM_INPUT("LINE1L"),
573 SND_SOC_DAPM_INPUT("LINE1R"),
574 SND_SOC_DAPM_INPUT("LINE2L"),
575 SND_SOC_DAPM_INPUT("LINE2R"),
576};
577
d0cc0d3a 578static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 579 /* Left Output */
580 {"Left DAC Mux", "DAC_L1", "Left DAC"},
581 {"Left DAC Mux", "DAC_L2", "Left DAC"},
582 {"Left DAC Mux", "DAC_L3", "Left DAC"},
583
54f01916
DM		 584 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
585 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
44d0a879
VB		 586 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
587 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
588 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
589 {"Left Line Out", NULL, "Left DAC Mux"},
590 {"Left HP Out", NULL, "Left DAC Mux"},
591
592 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
593 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
594 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
595
596 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
597 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
598 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
599 {"Left HP Com", NULL, "Left HPCOM Mux"},
600
601 {"LLOUT", NULL, "Left Line Out"},
602 {"LLOUT", NULL, "Left Line Out"},
603 {"HPLOUT", NULL, "Left HP Out"},
604 {"HPLCOM", NULL, "Left HP Com"},
605
606 /* Right Output */
607 {"Right DAC Mux", "DAC_R1", "Right DAC"},
608 {"Right DAC Mux", "DAC_R2", "Right DAC"},
609 {"Right DAC Mux", "DAC_R3", "Right DAC"},
610
54f01916
DM		 611 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
612 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
44d0a879
VB		 613 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
614 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
615 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
616 {"Right Line Out", NULL, "Right DAC Mux"},
617 {"Right HP Out", NULL, "Right DAC Mux"},
618
619 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
620 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
621 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
622 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
623 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
624
625 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
626 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
627 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
628 {"Right HP Com", NULL, "Right HPCOM Mux"},
629
630 {"RLOUT", NULL, "Right Line Out"},
631 {"RLOUT", NULL, "Right Line Out"},
632 {"HPROUT", NULL, "Right HP Out"},
633 {"HPRCOM", NULL, "Right HP Com"},
634
635 /* Mono Output */
5b006137
JN		 636 {"MONO_LOUT", NULL, "Mono Out"},
637 {"MONO_LOUT", NULL, "Mono Out"},
44d0a879
VB		 638
639 /* Left Input */
640 {"Left Line1L Mux", "single-ended", "LINE1L"},
641 {"Left Line1L Mux", "differential", "LINE1L"},
642
643 {"Left Line2L Mux", "single-ended", "LINE2L"},
644 {"Left Line2L Mux", "differential", "LINE2L"},
645
646 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 647 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 648 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
649 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 650 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 651
652 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 653 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 654
655 /* Right Input */
656 {"Right Line1R Mux", "single-ended", "LINE1R"},
657 {"Right Line1R Mux", "differential", "LINE1R"},
658
659 {"Right Line2R Mux", "single-ended", "LINE2R"},
660 {"Right Line2R Mux", "differential", "LINE2R"},
661
54f01916 662 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 663 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
664 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 665 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 666 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
667
668 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 669 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 670
671 /* Left PGA Bypass */
54f01916
DM		 672 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
673 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
44d0a879 674 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
54f01916
DM		 675 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
676 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
677 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
678 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
44d0a879
VB		 679
680 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
681 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
682 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
683
684 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
685 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
686 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
687
688 /* Right PGA Bypass */
54f01916
DM		 689 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
690 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
44d0a879 691 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
54f01916
DM		 692 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
693 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
694 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
695 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
44d0a879
VB		 696
697 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
698 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
699 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
700 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
701 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
702
703 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
704 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
705 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
706
707 /* Left Line2 Bypass */
54f01916
DM		 708 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
709 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
44d0a879
VB		 710 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
711 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
54f01916 712 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
44d0a879
VB		 713
714 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
715 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
716 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
717
718 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
719 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
720 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
721
722 /* Right Line2 Bypass */
54f01916
DM		 723 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
724 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
44d0a879
VB		 725 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
726 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
54f01916 727 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
44d0a879
VB		 728
729 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
730 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
731 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
732 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
733 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
734
735 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
736 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
737 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
ee15ffdb
JN		 738
739 /*
740 * Logical path between digital mic enable and GPIO1 modulator clock
741 * output function
742 */
743 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
744 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
745 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
44d0a879
VB		 746};
747
748static int aic3x_add_widgets(struct snd_soc_codec *codec)
749{
d0cc0d3a
MB		 750 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
751 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 752
753 /* set up audio path interconnects */
d0cc0d3a 754 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879 755
44d0a879
VB		 756 return 0;
757}
758
44d0a879 759static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 760 struct snd_pcm_hw_params *params,
761 struct snd_soc_dai *dai)
44d0a879
VB		 762{
763 struct snd_soc_pcm_runtime *rtd = substream->private_data;
764 struct snd_soc_device *socdev = rtd->socdev;
6627a653 765 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 766 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 767 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 768 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
769 u16 d, pll_d = 1;
06c71282 770 u8 reg;
255173b4 771 int clk;
44d0a879 772
4f9c16cc
DM		 773 /* select data word length */
774 data =
775 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
776 switch (params_format(params)) {
777 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 778 break;
4f9c16cc
DM		 779 case SNDRV_PCM_FORMAT_S20_3LE:
780 data |= (0x01 << 4);
44d0a879 781 break;
4f9c16cc
DM		 782 case SNDRV_PCM_FORMAT_S24_LE:
783 data |= (0x02 << 4);
44d0a879 784 break;
4f9c16cc
DM		 785 case SNDRV_PCM_FORMAT_S32_LE:
786 data |= (0x03 << 4);
44d0a879
VB		 787 break;
788 }
4f9c16cc
DM		 789 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
790
791 /* Fsref can be 44100 or 48000 */
792 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
793
794 /* Try to find a value for Q which allows us to bypass the PLL and
795 * generate CODEC_CLK directly. */
796 for (pll_q = 2; pll_q < 18; pll_q++)
797 if (aic3x->sysclk / (128 * pll_q) == fsref) {
798 bypass_pll = 1;
799 break;
800 }
801
802 if (bypass_pll) {
803 pll_q &= 0xf;
804 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
805 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282
C		 806 /* disable PLL if it is bypassed */
807 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
808 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
809
810 } else {
4f9c16cc 811 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282
C		 812 /* enable PLL when it is used */
813 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
814 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
815 }
4f9c16cc
DM		 816
817 /* Route Left DAC to left channel input and
818 * right DAC to right channel input */
819 data = (LDAC2LCH | RDAC2RCH);
820 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
821 if (params_rate(params) >= 64000)
822 data |= DUAL_RATE_MODE;
44d0a879
VB		 823 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
824
825 /* codec sample rate select */
4f9c16cc
DM		 826 data = (fsref * 20) / params_rate(params);
827 if (params_rate(params) < 64000)
828 data /= 2;
829 data /= 5;
830 data -= 2;
44d0a879
VB		 831 data |= (data << 4);
832 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
833
4f9c16cc
DM		 834 if (bypass_pll)
835 return 0;
836
255173b4
PM		 837 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
838 * one wins the game. Try with d==0 first, next with d!=0.
839 * Constraints for j are according to the datasheet.
4f9c16cc 840 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 841 */
255173b4 842
4f9c16cc
DM		 843 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
844
845 for (r = 1; r <= 16; r++)
846 for (p = 1; p <= 8; p++) {
255173b4
PM		 847 for (j = 4; j <= 55; j++) {
848 /* This is actually 1000*((j+(d/10000))*r)/p
849 * The term had to be converted to get
850 * rid of the division by 10000; d = 0 here
851 */
5baf8315 852 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 853
854 /* Check whether this values get closer than
855 * the best ones we had before
856 */
5baf8315 857 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 858 abs(codec_clk - last_clk)) {
859 pll_j = j; pll_d = 0;
860 pll_r = r; pll_p = p;
5baf8315 861 last_clk = tmp_clk;
255173b4
PM		 862 }
863
864 /* Early exit for exact matches */
5baf8315 865 if (tmp_clk == codec_clk)
255173b4
PM		 866 goto found;
867 }
868 }
4f9c16cc 869
255173b4
PM		 870 /* try with d != 0 */
871 for (p = 1; p <= 8; p++) {
872 j = codec_clk * p / 1000;
4f9c16cc 873
255173b4
PM		 874 if (j < 4 || j > 11)
875 continue;
4f9c16cc 876
255173b4
PM		 877 /* do not use codec_clk here since we'd loose precision */
878 d = ((2048 * p * fsref) - j * aic3x->sysclk)
879 * 100 / (aic3x->sysclk/100);
4f9c16cc 880
255173b4 881 clk = (10000 * j + d) / (10 * p);
4f9c16cc 882
255173b4
PM		 883 /* check whether this values get closer than the best
884 * ones we had before */
885 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
886 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
887 last_clk = clk;
4f9c16cc
DM		 888 }
889
255173b4
PM		 890 /* Early exit for exact matches */
891 if (clk == codec_clk)
892 goto found;
893 }
894
4f9c16cc
DM		 895 if (last_clk == 0) {
896 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
897 return -EINVAL;
898 }
44d0a879 899
255173b4 900found:
44d0a879
VB		 901 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
902 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
903 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
904 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
905 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
906 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
907 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
908
44d0a879
VB		 909 return 0;
910}
911
e550e17f 912static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 913{
914 struct snd_soc_codec *codec = dai->codec;
915 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
916 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
917
918 if (mute) {
919 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
920 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
921 } else {
922 aic3x_write(codec, LDAC_VOL, ldac_reg);
923 aic3x_write(codec, RDAC_VOL, rdac_reg);
924 }
925
926 return 0;
927}
928
e550e17f 929static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 930 int clk_id, unsigned int freq, int dir)
931{
932 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 933 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 934
4f9c16cc
DM		 935 aic3x->sysclk = freq;
936 return 0;
44d0a879
VB		 937}
938
e550e17f 939static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 940 unsigned int fmt)
941{
942 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 943 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 944 u8 iface_areg, iface_breg;
a24f4f68 945 int delay = 0;
81971a14
JN		 946
947 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
948 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 949
950 /* set master/slave audio interface */
951 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
952 case SND_SOC_DAIFMT_CBM_CFM:
953 aic3x->master = 1;
954 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
955 break;
956 case SND_SOC_DAIFMT_CBS_CFS:
957 aic3x->master = 0;
958 break;
959 default:
960 return -EINVAL;
961 }
962
4b7d2831
JN		 963 /*
964 * match both interface format and signal polarities since they
965 * are fixed
966 */
967 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
968 SND_SOC_DAIFMT_INV_MASK)) {
969 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 970 break;
a24f4f68
TK		 971 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
972 delay = 1;
4b7d2831 973 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 974 iface_breg |= (0x01 << 6);
975 break;
4b7d2831 976 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 977 iface_breg |= (0x02 << 6);
978 break;
4b7d2831 979 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 980 iface_breg |= (0x03 << 6);
981 break;
982 default:
983 return -EINVAL;
984 }
985
986 /* set iface */
987 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
988 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
a24f4f68 989 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 990
991 return 0;
992}
993
0be9898a
MB		 994static int aic3x_set_bias_level(struct snd_soc_codec *codec,
995 enum snd_soc_bias_level level)
44d0a879 996{
b2c812e2 997 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 998 u8 reg;
999
0be9898a
MB		 1000 switch (level) {
1001 case SND_SOC_BIAS_ON:
44d0a879
VB		 1002 /* all power is driven by DAPM system */
1003 if (aic3x->master) {
1004 /* enable pll */
1005 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1006 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1007 reg | PLL_ENABLE);
1008 }
1009 break;
0be9898a 1010 case SND_SOC_BIAS_PREPARE:
44d0a879 1011 break;
0be9898a 1012 case SND_SOC_BIAS_STANDBY:
44d0a879
VB		 1013 /*
1014 * all power is driven by DAPM system,
1015 * so output power is safe if bypass was set
1016 */
1017 if (aic3x->master) {
1018 /* disable pll */
1019 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1020 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1021 reg & ~PLL_ENABLE);
1022 }
1023 break;
0be9898a 1024 case SND_SOC_BIAS_OFF:
44d0a879
VB		 1025 /* force all power off */
1026 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1027 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1028 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1029 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1030
1031 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1032 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1033
1034 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1035 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1036 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1037 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1038
1039 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1040 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1041 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1042 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1043
1044 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1045 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1046
1047 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1048 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1049 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1050 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1051
1052 if (aic3x->master) {
1053 /* disable pll */
1054 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1055 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1056 reg & ~PLL_ENABLE);
1057 }
1058 break;
1059 }
0be9898a 1060 codec->bias_level = level;
44d0a879
VB		 1061
1062 return 0;
1063}
1064
54e7e616
DM		 1065void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1066{
1067 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1068 u8 bit = gpio ? 3: 0;
1069 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1070 aic3x_write(codec, reg, val | (!!state << bit));
1071}
1072EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1073
1074int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1075{
1076 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1077 u8 val, bit = gpio ? 2: 1;
1078
1079 aic3x_read(codec, reg, &val);
1080 return (val >> bit) & 1;
1081}
1082EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1083
6f2a974b
DM		 1084void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1085 int headset_debounce, int button_debounce)
1086{
1087 u8 val;
1088
1089 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1090 << AIC3X_HEADSET_DETECT_SHIFT) |
1091 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1092 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1093 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1094 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1095
1096 if (detect & AIC3X_HEADSET_DETECT_MASK)
1097 val |= AIC3X_HEADSET_DETECT_ENABLED;
1098
1099 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1100}
1101EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1102
54e7e616
DM		 1103int aic3x_headset_detected(struct snd_soc_codec *codec)
1104{
1105 u8 val;
6f2a974b
DM		 1106 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1107 return (val >> 4) & 1;
54e7e616
DM		 1108}
1109EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1110
6f2a974b
DM		 1111int aic3x_button_pressed(struct snd_soc_codec *codec)
1112{
1113 u8 val;
1114 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1115 return (val >> 5) & 1;
1116}
1117EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1118
44d0a879
VB		 1119#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1120#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1121 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1122
6335d055
EM		 1123static struct snd_soc_dai_ops aic3x_dai_ops = {
1124 .hw_params = aic3x_hw_params,
1125 .digital_mute = aic3x_mute,
1126 .set_sysclk = aic3x_set_dai_sysclk,
1127 .set_fmt = aic3x_set_dai_fmt,
1128};
1129
e550e17f 1130struct snd_soc_dai aic3x_dai = {
e78cc18d 1131 .name = "tlv320aic3x",
44d0a879
VB		 1132 .playback = {
1133 .stream_name = "Playback",
1134 .channels_min = 1,
1135 .channels_max = 2,
1136 .rates = AIC3X_RATES,
1137 .formats = AIC3X_FORMATS,},
1138 .capture = {
1139 .stream_name = "Capture",
1140 .channels_min = 1,
1141 .channels_max = 2,
1142 .rates = AIC3X_RATES,
1143 .formats = AIC3X_FORMATS,},
6335d055 1144 .ops = &aic3x_dai_ops,
44d0a879
VB		 1145};
1146EXPORT_SYMBOL_GPL(aic3x_dai);
1147
1148static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1149{
1150 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1151 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879 1152
0be9898a 1153 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1154
1155 return 0;
1156}
1157
1158static int aic3x_resume(struct platform_device *pdev)
1159{
1160 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1161 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879
VB		 1162 int i;
1163 u8 data[2];
1164 u8 *cache = codec->reg_cache;
1165
1166 /* Sync reg_cache with the hardware */
1167 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1168 data[0] = i;
1169 data[1] = cache[i];
1170 codec->hw_write(codec->control_data, data, 2);
1171 }
1172
0be9898a 1173 aic3x_set_bias_level(codec, codec->suspend_bias_level);
44d0a879
VB		 1174
1175 return 0;
1176}
1177
1178/*
1179 * initialise the AIC3X driver
1180 * register the mixer and dsp interfaces with the kernel
1181 */
cb3826f5 1182static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1183{
cb3826f5
BD		 1184 int reg;
1185
1186 mutex_init(&codec->mutex);
1187 INIT_LIST_HEAD(&codec->dapm_widgets);
1188 INIT_LIST_HEAD(&codec->dapm_paths);
44d0a879 1189
e78cc18d 1190 codec->name = "tlv320aic3x";
44d0a879
VB		 1191 codec->owner = THIS_MODULE;
1192 codec->read = aic3x_read_reg_cache;
1193 codec->write = aic3x_write;
0be9898a 1194 codec->set_bias_level = aic3x_set_bias_level;
44d0a879
VB		 1195 codec->dai = &aic3x_dai;
1196 codec->num_dai = 1;
ae2ff191 1197 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
44d0a879
VB		 1198 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1199 if (codec->reg_cache == NULL)
1200 return -ENOMEM;
1201
1202 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1203 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1204
44d0a879
VB		 1205 /* DAC default volume and mute */
1206 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1207 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1208
1209 /* DAC to HP default volume and route to Output mixer */
1210 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1211 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1212 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1213 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1214 /* DAC to Line Out default volume and route to Output mixer */
1215 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1216 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1217 /* DAC to Mono Line Out default volume and route to Output mixer */
1218 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1219 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1220
1221 /* unmute all outputs */
1222 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1223 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1224 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1225 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1226 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1227 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1228 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1229 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1230 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1231 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1232 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1233 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1234 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1235 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1236
1237 /* ADC default volume and unmute */
1238 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1239 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1240 /* By default route Line1 to ADC PGA mixer */
1241 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1242 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1243
1244 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1245 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1246 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1247 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1248 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1249 /* PGA to Line Out default volume, disconnect from Output Mixer */
1250 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1251 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1252 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1253 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1254 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1255
1256 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1257 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1258 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1259 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1260 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1261 /* Line2 Line Out default volume, disconnect from Output Mixer */
1262 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1263 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1264 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1265 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1266 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1267
1268 /* off, with power on */
0be9898a 1269 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1270
cb3826f5
BD		 1271 return 0;
1272}
54e7e616 1273
cb3826f5
BD		 1274static struct snd_soc_codec *aic3x_codec;
1275
1276static int aic3x_register(struct snd_soc_codec *codec)
1277{
1278 int ret;
1279
1280 ret = aic3x_init(codec);
44d0a879 1281 if (ret < 0) {
cb3826f5
BD		 1282 dev_err(codec->dev, "Failed to initialise device\n");
1283 return ret;
44d0a879
VB		 1284 }
1285
cb3826f5 1286 aic3x_codec = codec;
44d0a879 1287
cb3826f5
BD		 1288 ret = snd_soc_register_codec(codec);
1289 if (ret) {
1290 dev_err(codec->dev, "Failed to register codec\n");
1291 return ret;
1292 }
1293
1294 ret = snd_soc_register_dai(&aic3x_dai);
1295 if (ret) {
1296 dev_err(codec->dev, "Failed to register dai\n");
1297 snd_soc_unregister_codec(codec);
1298 return ret;
1299 }
1300
1301 return 0;
44d0a879
VB		 1302}
1303
cb3826f5
BD		 1304static int aic3x_unregister(struct aic3x_priv *aic3x)
1305{
1306 aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF);
1307
1308 snd_soc_unregister_dai(&aic3x_dai);
1309 snd_soc_unregister_codec(&aic3x->codec);
1310
1311 kfree(aic3x);
1312 aic3x_codec = NULL;
1313
1314 return 0;
1315}
44d0a879
VB		 1316
1317#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1318/*
1319 * AIC3X 2 wire address can be up to 4 devices with device addresses
1320 * 0x18, 0x19, 0x1A, 0x1B
1321 */
44d0a879
VB		 1322
1323/*
1324 * If the i2c layer weren't so broken, we could pass this kind of data
1325 * around
1326 */
ba8ed121
JD		 1327static int aic3x_i2c_probe(struct i2c_client *i2c,
1328 const struct i2c_device_id *id)
44d0a879 1329{
cb3826f5
BD		 1330 struct snd_soc_codec *codec;
1331 struct aic3x_priv *aic3x;
44d0a879 1332
cb3826f5
BD		 1333 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1334 if (aic3x == NULL) {
1335 dev_err(&i2c->dev, "failed to create private data\n");
1336 return -ENOMEM;
1337 }
1338
1339 codec = &aic3x->codec;
1340 codec->dev = &i2c->dev;
b2c812e2 1341 snd_soc_codec_set_drvdata(codec, aic3x);
44d0a879 1342 codec->control_data = i2c;
cb3826f5 1343 codec->hw_write = (hw_write_t) i2c_master_send;
44d0a879 1344
cb3826f5
BD		 1345 i2c_set_clientdata(i2c, aic3x);
1346
1347 return aic3x_register(codec);
44d0a879
VB		 1348}
1349
ba8ed121 1350static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1351{
cb3826f5
BD		 1352 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1353
1354 return aic3x_unregister(aic3x);
44d0a879
VB		 1355}
1356
ba8ed121
JD		 1357static const struct i2c_device_id aic3x_i2c_id[] = {
1358 { "tlv320aic3x", 0 },
cb3826f5 1359 { "tlv320aic33", 0 },
ba8ed121
JD		 1360 { }
1361};
1362MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
44d0a879
VB		 1363
1364/* machine i2c codec control layer */
1365static struct i2c_driver aic3x_i2c_driver = {
1366 .driver = {
1367 .name = "aic3x I2C Codec",
1368 .owner = THIS_MODULE,
1369 },
cb3826f5 1370 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1371 .remove = aic3x_i2c_remove,
1372 .id_table = aic3x_i2c_id,
44d0a879 1373};
54e7e616 1374
cb3826f5 1375static inline void aic3x_i2c_init(void)
ba8ed121 1376{
ba8ed121
JD		 1377 int ret;
1378
1379 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1380 if (ret)
1381 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1382 __func__, ret);
1383}
ba8ed121 1384
cb3826f5
BD		 1385static inline void aic3x_i2c_exit(void)
1386{
ba8ed121 1387 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1388}
cb3826f5
BD		 1389#else
1390static inline void aic3x_i2c_init(void) { }
1391static inline void aic3x_i2c_exit(void) { }
44d0a879
VB		 1392#endif
1393
1394static int aic3x_probe(struct platform_device *pdev)
1395{
1396 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1397 struct aic3x_setup_data *setup;
1398 struct snd_soc_codec *codec;
44d0a879
VB		 1399 int ret = 0;
1400
cb3826f5
BD		 1401 codec = aic3x_codec;
1402 if (!codec) {
1403 dev_err(&pdev->dev, "Codec not registered\n");
1404 return -ENODEV;
1405 }
44d0a879 1406
cb3826f5 1407 socdev->card->codec = codec;
44d0a879 1408 setup = socdev->codec_data;
44d0a879 1409
977d49e0
MB		 1410 if (setup) {
1411 /* setup GPIO functions */
1412 aic3x_write(codec, AIC3X_GPIO1_REG,
1413 (setup->gpio_func[0] & 0xf) << 4);
1414 aic3x_write(codec, AIC3X_GPIO2_REG,
1415 (setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1416 }
1417
cb3826f5
BD		 1418 /* register pcms */
1419 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1420 if (ret < 0) {
1421 printk(KERN_ERR "aic3x: failed to create pcms\n");
1422 goto pcm_err;
44d0a879 1423 }
3051e41a 1424
cb3826f5
BD		 1425 snd_soc_add_controls(codec, aic3x_snd_controls,
1426 ARRAY_SIZE(aic3x_snd_controls));
1427
1428 aic3x_add_widgets(codec);
1429
cb3826f5
BD		 1430 return ret;
1431
cb3826f5
BD		 1432pcm_err:
1433 kfree(codec->reg_cache);
44d0a879
VB		 1434 return ret;
1435}
1436
1437static int aic3x_remove(struct platform_device *pdev)
1438{
1439 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1440 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879
VB		 1441
1442 /* power down chip */
1443 if (codec->control_data)
0be9898a 1444 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1445
1446 snd_soc_free_pcms(socdev);
1447 snd_soc_dapm_free(socdev);
cb3826f5
BD		 1448
1449 kfree(codec->reg_cache);
44d0a879
VB		 1450
1451 return 0;
1452}
1453
1454struct snd_soc_codec_device soc_codec_dev_aic3x = {
1455 .probe = aic3x_probe,
1456 .remove = aic3x_remove,
1457 .suspend = aic3x_suspend,
1458 .resume = aic3x_resume,
1459};
1460EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1461
c9b3a40f 1462static int __init aic3x_modinit(void)
64089b84 1463{
cb3826f5
BD		 1464 aic3x_i2c_init();
1465
1466 return 0;
64089b84
MB		 1467}
1468module_init(aic3x_modinit);
1469
1470static void __exit aic3x_exit(void)
1471{
cb3826f5 1472 aic3x_i2c_exit();
64089b84
MB		 1473}
1474module_exit(aic3x_exit);
1475
44d0a879
VB		 1476MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1477MODULE_AUTHOR("Vladimir Barinov");
1478MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree