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ASoC: tlv320aic3x: Add basic regulator support
[net-next-2.6.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
07779fdd 41#include <linux/regulator/consumer.h>
44d0a879 42#include <linux/platform_device.h>
44d0a879
VB		 43#include <sound/core.h>
44#include <sound/pcm.h>
45#include <sound/pcm_params.h>
46#include <sound/soc.h>
47#include <sound/soc-dapm.h>
48#include <sound/initval.h>
7565fc38 49#include <sound/tlv.h>
44d0a879
VB		 50
51#include "tlv320aic3x.h"
52
07779fdd
JN		 53#define AIC3X_NUM_SUPPLIES 4
54static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
55 "IOVDD", /* I/O Voltage */
56 "DVDD", /* Digital Core Voltage */
57 "AVDD", /* Analog DAC Voltage */
58 "DRVDD", /* ADC Analog and Output Driver Voltage */
59};
60
44d0a879
VB		 61/* codec private data */
62struct aic3x_priv {
cb3826f5 63 struct snd_soc_codec codec;
07779fdd 64 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
44d0a879
VB		 65 unsigned int sysclk;
66 int master;
67};
68
69/*
70 * AIC3X register cache
71 * We can't read the AIC3X register space when we are
72 * using 2 wire for device control, so we cache them instead.
73 * There is no point in caching the reset register
74 */
75static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
76 0x00, 0x00, 0x00, 0x10, /* 0 */
77 0x04, 0x00, 0x00, 0x00, /* 4 */
78 0x00, 0x00, 0x00, 0x01, /* 8 */
79 0x00, 0x00, 0x00, 0x80, /* 12 */
80 0x80, 0xff, 0xff, 0x78, /* 16 */
81 0x78, 0x78, 0x78, 0x78, /* 20 */
82 0x78, 0x00, 0x00, 0xfe, /* 24 */
83 0x00, 0x00, 0xfe, 0x00, /* 28 */
84 0x18, 0x18, 0x00, 0x00, /* 32 */
85 0x00, 0x00, 0x00, 0x00, /* 36 */
86 0x00, 0x00, 0x00, 0x80, /* 40 */
87 0x80, 0x00, 0x00, 0x00, /* 44 */
88 0x00, 0x00, 0x00, 0x04, /* 48 */
89 0x00, 0x00, 0x00, 0x00, /* 52 */
90 0x00, 0x00, 0x04, 0x00, /* 56 */
91 0x00, 0x00, 0x00, 0x00, /* 60 */
92 0x00, 0x04, 0x00, 0x00, /* 64 */
93 0x00, 0x00, 0x00, 0x00, /* 68 */
94 0x04, 0x00, 0x00, 0x00, /* 72 */
95 0x00, 0x00, 0x00, 0x00, /* 76 */
96 0x00, 0x00, 0x00, 0x00, /* 80 */
97 0x00, 0x00, 0x00, 0x00, /* 84 */
98 0x00, 0x00, 0x00, 0x00, /* 88 */
99 0x00, 0x00, 0x00, 0x00, /* 92 */
100 0x00, 0x00, 0x00, 0x00, /* 96 */
101 0x00, 0x00, 0x02, /* 100 */
102};
103
104/*
105 * read aic3x register cache
106 */
107static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
108 unsigned int reg)
109{
110 u8 *cache = codec->reg_cache;
111 if (reg >= AIC3X_CACHEREGNUM)
112 return -1;
113 return cache[reg];
114}
115
116/*
117 * write aic3x register cache
118 */
119static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
120 u8 reg, u8 value)
121{
122 u8 *cache = codec->reg_cache;
123 if (reg >= AIC3X_CACHEREGNUM)
124 return;
125 cache[reg] = value;
126}
127
128/*
129 * write to the aic3x register space
130 */
131static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
132 unsigned int value)
133{
134 u8 data[2];
135
136 /* data is
137 * D15..D8 aic3x register offset
138 * D7...D0 register data
139 */
140 data[0] = reg & 0xff;
141 data[1] = value & 0xff;
142
143 aic3x_write_reg_cache(codec, data[0], data[1]);
144 if (codec->hw_write(codec->control_data, data, 2) == 2)
145 return 0;
146 else
147 return -EIO;
148}
149
54e7e616
DM		 150/*
151 * read from the aic3x register space
152 */
153static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
154 u8 *value)
155{
156 *value = reg & 0xff;
5f345346
MB		 157
158 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
54e7e616
DM		 159
160 aic3x_write_reg_cache(codec, reg, *value);
161 return 0;
162}
163
44d0a879
VB		 164#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
165{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
166 .info = snd_soc_info_volsw, \
167 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
168 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
169
170/*
171 * All input lines are connected when !0xf and disconnected with 0xf bit field,
172 * so we have to use specific dapm_put call for input mixer
173 */
174static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
175 struct snd_ctl_elem_value *ucontrol)
176{
177 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 178 struct soc_mixer_control *mc =
179 (struct soc_mixer_control *)kcontrol->private_value;
180 unsigned int reg = mc->reg;
181 unsigned int shift = mc->shift;
182 int max = mc->max;
183 unsigned int mask = (1 << fls(max)) - 1;
184 unsigned int invert = mc->invert;
44d0a879
VB		 185 unsigned short val, val_mask;
186 int ret;
187 struct snd_soc_dapm_path *path;
188 int found = 0;
189
190 val = (ucontrol->value.integer.value[0] & mask);
191
192 mask = 0xf;
193 if (val)
194 val = mask;
195
196 if (invert)
197 val = mask - val;
198 val_mask = mask << shift;
199 val = val << shift;
200
201 mutex_lock(&widget->codec->mutex);
202
203 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
204 /* find dapm widget path assoc with kcontrol */
205 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
206 if (path->kcontrol != kcontrol)
207 continue;
208
209 /* found, now check type */
210 found = 1;
211 if (val)
212 /* new connection */
213 path->connect = invert ? 0 : 1;
214 else
215 /* old connection must be powered down */
216 path->connect = invert ? 1 : 0;
217 break;
218 }
219
220 if (found)
a5302181 221 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 222 }
223
224 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
225
226 mutex_unlock(&widget->codec->mutex);
227 return ret;
228}
229
230static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
231static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
232static const char *aic3x_left_hpcom_mux[] =
233 { "differential of HPLOUT", "constant VCM", "single-ended" };
234static const char *aic3x_right_hpcom_mux[] =
235 { "differential of HPROUT", "constant VCM", "single-ended",
236 "differential of HPLCOM", "external feedback" };
237static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 238static const char *aic3x_adc_hpf[] =
239 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 240
241#define LDAC_ENUM 0
242#define RDAC_ENUM 1
243#define LHPCOM_ENUM 2
244#define RHPCOM_ENUM 3
245#define LINE1L_ENUM 4
246#define LINE1R_ENUM 5
247#define LINE2L_ENUM 6
248#define LINE2R_ENUM 7
4d20f70a 249#define ADC_HPF_ENUM 8
44d0a879
VB		 250
251static const struct soc_enum aic3x_enum[] = {
252 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
253 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
254 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
255 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
256 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
257 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
258 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
259 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 260 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 261};
262
7565fc38
JN		 263/*
264 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
265 */
266static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
267/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
268static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
269/*
270 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
271 * Step size is approximately 0.5 dB over most of the scale but increasing
272 * near the very low levels.
273 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
274 * but having increasing dB difference below that (and where it doesn't count
275 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
276 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
277 */
278static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
279
44d0a879
VB		 280static const struct snd_kcontrol_new aic3x_snd_controls[] = {
281 /* Output */
7565fc38
JN		 282 SOC_DOUBLE_R_TLV("PCM Playback Volume",
283 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 284
7565fc38
JN		 285 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
286 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
287 0, 118, 1, output_stage_tlv),
28a1d869
DM		 288 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
289 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
7565fc38
JN		 290 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
291 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
292 0, 118, 1, output_stage_tlv),
293 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
294 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
295 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
296 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
297 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
298 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
299 0, 118, 1, output_stage_tlv),
300 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
301 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
302 0, 118, 1, output_stage_tlv),
303
304 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
305 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
306 0, 118, 1, output_stage_tlv),
44d0a879 307 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
7565fc38
JN		 308 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
309 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
310 0, 118, 1, output_stage_tlv),
311 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
312 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
313 0, 118, 1, output_stage_tlv),
314
315 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
316 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
317 0, 118, 1, output_stage_tlv),
44d0a879
VB		 318 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
319 0x01, 0),
7565fc38
JN		 320 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
321 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
322 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
324 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
326 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
328 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
329 0, 118, 1, output_stage_tlv),
330
331 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
332 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
333 0, 118, 1, output_stage_tlv),
44d0a879
VB		 334 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
335 0x01, 0),
7565fc38
JN		 336 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
337 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
338 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
339 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
340 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
341 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
342 0, 118, 1, output_stage_tlv),
44d0a879
VB		 343
344 /*
345 * Note: enable Automatic input Gain Controller with care. It can
346 * adjust PGA to max value when ADC is on and will never go back.
347 */
348 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
349
350 /* Input */
7565fc38
JN		 351 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
352 0, 119, 0, adc_tlv),
44d0a879 353 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 354
355 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 356};
357
44d0a879
VB		 358/* Left DAC Mux */
359static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
360SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
361
362/* Right DAC Mux */
363static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
364SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
365
366/* Left HPCOM Mux */
367static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
368SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
369
370/* Right HPCOM Mux */
371static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
372SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
373
374/* Left DAC_L1 Mixer */
375static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
54f01916
DM		 376 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
377 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 378 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
379 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
380 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
381};
382
383/* Right DAC_R1 Mixer */
384static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
54f01916
DM		 385 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
386 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 387 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
388 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
389 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
390};
391
392/* Left PGA Mixer */
393static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
394 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 395 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 396 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
397 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 398 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 399};
400
401/* Right PGA Mixer */
402static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
403 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 404 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 405 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 406 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 407 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
408};
409
410/* Left Line1 Mux */
411static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
412SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
413
414/* Right Line1 Mux */
415static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
416SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
417
418/* Left Line2 Mux */
419static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
420SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
421
422/* Right Line2 Mux */
423static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
424SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
425
426/* Left PGA Bypass Mixer */
427static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
54f01916
DM		 428 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
44d0a879 430 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 431 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 435};
436
437/* Right PGA Bypass Mixer */
438static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
54f01916
DM		 439 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
44d0a879 441 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 442 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 446};
447
448/* Left Line2 Bypass Mixer */
449static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
54f01916
DM		 450 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 452 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
54f01916 454 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
44d0a879
VB		 455};
456
457/* Right Line2 Bypass Mixer */
458static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
54f01916
DM		 459 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 461 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
54f01916 463 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 464};
465
466static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
467 /* Left DAC to Left Outputs */
468 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
469 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
470 &aic3x_left_dac_mux_controls),
471 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
472 &aic3x_left_dac_mixer_controls[0],
473 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
474 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
475 &aic3x_left_hpcom_mux_controls),
476 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
477 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
478 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
479
480 /* Right DAC to Right Outputs */
481 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
482 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
483 &aic3x_right_dac_mux_controls),
484 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
485 &aic3x_right_dac_mixer_controls[0],
486 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
487 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
488 &aic3x_right_hpcom_mux_controls),
489 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
490 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
491 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
492
493 /* Mono Output */
494 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
495
54f01916 496 /* Inputs to Left ADC */
44d0a879
VB		 497 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
498 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
499 &aic3x_left_pga_mixer_controls[0],
500 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
501 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
502 &aic3x_left_line1_mux_controls),
54f01916
DM		 503 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
504 &aic3x_left_line1_mux_controls),
44d0a879
VB		 505 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
506 &aic3x_left_line2_mux_controls),
507
54f01916 508 /* Inputs to Right ADC */
44d0a879
VB		 509 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
510 LINE1R_2_RADC_CTRL, 2, 0),
511 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
512 &aic3x_right_pga_mixer_controls[0],
513 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 514 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
515 &aic3x_right_line1_mux_controls),
44d0a879
VB		 516 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
517 &aic3x_right_line1_mux_controls),
518 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
519 &aic3x_right_line2_mux_controls),
520
ee15ffdb
JN		 521 /*
522 * Not a real mic bias widget but similar function. This is for dynamic
523 * control of GPIO1 digital mic modulator clock output function when
524 * using digital mic.
525 */
526 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
527 AIC3X_GPIO1_REG, 4, 0xf,
528 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
529 AIC3X_GPIO1_FUNC_DISABLED),
530
531 /*
532 * Also similar function like mic bias. Selects digital mic with
533 * configurable oversampling rate instead of ADC converter.
534 */
535 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
536 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
537 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
538 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
539 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
540 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
541
44d0a879 542 /* Mic Bias */
0bd72a3d
JN		 543 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
544 MICBIAS_CTRL, 6, 3, 1, 0),
545 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
546 MICBIAS_CTRL, 6, 3, 2, 0),
547 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
548 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879
VB		 549
550 /* Left PGA to Left Output bypass */
551 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
552 &aic3x_left_pga_bp_mixer_controls[0],
553 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
554
555 /* Right PGA to Right Output bypass */
556 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
557 &aic3x_right_pga_bp_mixer_controls[0],
558 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
559
560 /* Left Line2 to Left Output bypass */
561 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
562 &aic3x_left_line2_bp_mixer_controls[0],
563 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
564
565 /* Right Line2 to Right Output bypass */
566 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
567 &aic3x_right_line2_bp_mixer_controls[0],
568 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
569
570 SND_SOC_DAPM_OUTPUT("LLOUT"),
571 SND_SOC_DAPM_OUTPUT("RLOUT"),
572 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
573 SND_SOC_DAPM_OUTPUT("HPLOUT"),
574 SND_SOC_DAPM_OUTPUT("HPROUT"),
575 SND_SOC_DAPM_OUTPUT("HPLCOM"),
576 SND_SOC_DAPM_OUTPUT("HPRCOM"),
577
578 SND_SOC_DAPM_INPUT("MIC3L"),
579 SND_SOC_DAPM_INPUT("MIC3R"),
580 SND_SOC_DAPM_INPUT("LINE1L"),
581 SND_SOC_DAPM_INPUT("LINE1R"),
582 SND_SOC_DAPM_INPUT("LINE2L"),
583 SND_SOC_DAPM_INPUT("LINE2R"),
584};
585
d0cc0d3a 586static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 587 /* Left Output */
588 {"Left DAC Mux", "DAC_L1", "Left DAC"},
589 {"Left DAC Mux", "DAC_L2", "Left DAC"},
590 {"Left DAC Mux", "DAC_L3", "Left DAC"},
591
54f01916
DM		 592 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
593 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
44d0a879
VB		 594 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
595 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
596 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
597 {"Left Line Out", NULL, "Left DAC Mux"},
598 {"Left HP Out", NULL, "Left DAC Mux"},
599
600 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
601 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
602 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
603
604 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
605 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
606 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
607 {"Left HP Com", NULL, "Left HPCOM Mux"},
608
609 {"LLOUT", NULL, "Left Line Out"},
610 {"LLOUT", NULL, "Left Line Out"},
611 {"HPLOUT", NULL, "Left HP Out"},
612 {"HPLCOM", NULL, "Left HP Com"},
613
614 /* Right Output */
615 {"Right DAC Mux", "DAC_R1", "Right DAC"},
616 {"Right DAC Mux", "DAC_R2", "Right DAC"},
617 {"Right DAC Mux", "DAC_R3", "Right DAC"},
618
54f01916
DM		 619 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
620 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
44d0a879
VB		 621 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
622 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
623 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
624 {"Right Line Out", NULL, "Right DAC Mux"},
625 {"Right HP Out", NULL, "Right DAC Mux"},
626
627 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
628 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
629 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
630 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
631 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
632
633 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
634 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
635 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
636 {"Right HP Com", NULL, "Right HPCOM Mux"},
637
638 {"RLOUT", NULL, "Right Line Out"},
639 {"RLOUT", NULL, "Right Line Out"},
640 {"HPROUT", NULL, "Right HP Out"},
641 {"HPRCOM", NULL, "Right HP Com"},
642
643 /* Mono Output */
5b006137
JN		 644 {"MONO_LOUT", NULL, "Mono Out"},
645 {"MONO_LOUT", NULL, "Mono Out"},
44d0a879
VB		 646
647 /* Left Input */
648 {"Left Line1L Mux", "single-ended", "LINE1L"},
649 {"Left Line1L Mux", "differential", "LINE1L"},
650
651 {"Left Line2L Mux", "single-ended", "LINE2L"},
652 {"Left Line2L Mux", "differential", "LINE2L"},
653
654 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 655 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 656 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
657 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 658 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 659
660 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 661 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 662
663 /* Right Input */
664 {"Right Line1R Mux", "single-ended", "LINE1R"},
665 {"Right Line1R Mux", "differential", "LINE1R"},
666
667 {"Right Line2R Mux", "single-ended", "LINE2R"},
668 {"Right Line2R Mux", "differential", "LINE2R"},
669
54f01916 670 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 671 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
672 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 673 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 674 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
675
676 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 677 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 678
679 /* Left PGA Bypass */
54f01916
DM		 680 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
681 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
44d0a879 682 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
54f01916
DM		 683 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
684 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
685 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
686 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
44d0a879
VB		 687
688 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
689 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
690 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
691
692 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
693 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
694 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
695
696 /* Right PGA Bypass */
54f01916
DM		 697 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
698 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
44d0a879 699 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
54f01916
DM		 700 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
701 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
702 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
703 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
44d0a879
VB		 704
705 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
706 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
707 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
708 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
709 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
710
711 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
712 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
713 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
714
715 /* Left Line2 Bypass */
54f01916
DM		 716 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
717 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
44d0a879
VB		 718 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
719 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
54f01916 720 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
44d0a879
VB		 721
722 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
723 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
724 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
725
726 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
727 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
728 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
729
730 /* Right Line2 Bypass */
54f01916
DM		 731 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
732 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
44d0a879
VB		 733 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
734 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
54f01916 735 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
44d0a879
VB		 736
737 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
738 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
739 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
740 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
741 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
742
743 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
744 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
745 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
ee15ffdb
JN		 746
747 /*
748 * Logical path between digital mic enable and GPIO1 modulator clock
749 * output function
750 */
751 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
752 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
753 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
44d0a879
VB		 754};
755
756static int aic3x_add_widgets(struct snd_soc_codec *codec)
757{
d0cc0d3a
MB		 758 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
759 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 760
761 /* set up audio path interconnects */
d0cc0d3a 762 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879 763
44d0a879
VB		 764 return 0;
765}
766
44d0a879 767static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 768 struct snd_pcm_hw_params *params,
769 struct snd_soc_dai *dai)
44d0a879
VB		 770{
771 struct snd_soc_pcm_runtime *rtd = substream->private_data;
772 struct snd_soc_device *socdev = rtd->socdev;
6627a653 773 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 774 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 775 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 776 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
777 u16 d, pll_d = 1;
06c71282 778 u8 reg;
255173b4 779 int clk;
44d0a879 780
4f9c16cc
DM		 781 /* select data word length */
782 data =
783 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
784 switch (params_format(params)) {
785 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 786 break;
4f9c16cc
DM		 787 case SNDRV_PCM_FORMAT_S20_3LE:
788 data |= (0x01 << 4);
44d0a879 789 break;
4f9c16cc
DM		 790 case SNDRV_PCM_FORMAT_S24_LE:
791 data |= (0x02 << 4);
44d0a879 792 break;
4f9c16cc
DM		 793 case SNDRV_PCM_FORMAT_S32_LE:
794 data |= (0x03 << 4);
44d0a879
VB		 795 break;
796 }
4f9c16cc
DM		 797 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
798
799 /* Fsref can be 44100 or 48000 */
800 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
801
802 /* Try to find a value for Q which allows us to bypass the PLL and
803 * generate CODEC_CLK directly. */
804 for (pll_q = 2; pll_q < 18; pll_q++)
805 if (aic3x->sysclk / (128 * pll_q) == fsref) {
806 bypass_pll = 1;
807 break;
808 }
809
810 if (bypass_pll) {
811 pll_q &= 0xf;
812 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
813 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282
C		 814 /* disable PLL if it is bypassed */
815 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
816 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
817
818 } else {
4f9c16cc 819 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282
C		 820 /* enable PLL when it is used */
821 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
822 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
823 }
4f9c16cc
DM		 824
825 /* Route Left DAC to left channel input and
826 * right DAC to right channel input */
827 data = (LDAC2LCH | RDAC2RCH);
828 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
829 if (params_rate(params) >= 64000)
830 data |= DUAL_RATE_MODE;
44d0a879
VB		 831 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
832
833 /* codec sample rate select */
4f9c16cc
DM		 834 data = (fsref * 20) / params_rate(params);
835 if (params_rate(params) < 64000)
836 data /= 2;
837 data /= 5;
838 data -= 2;
44d0a879
VB		 839 data |= (data << 4);
840 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
841
4f9c16cc
DM		 842 if (bypass_pll)
843 return 0;
844
255173b4
PM		 845 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
846 * one wins the game. Try with d==0 first, next with d!=0.
847 * Constraints for j are according to the datasheet.
4f9c16cc 848 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 849 */
255173b4 850
4f9c16cc
DM		 851 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
852
853 for (r = 1; r <= 16; r++)
854 for (p = 1; p <= 8; p++) {
255173b4
PM		 855 for (j = 4; j <= 55; j++) {
856 /* This is actually 1000*((j+(d/10000))*r)/p
857 * The term had to be converted to get
858 * rid of the division by 10000; d = 0 here
859 */
5baf8315 860 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 861
862 /* Check whether this values get closer than
863 * the best ones we had before
864 */
5baf8315 865 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 866 abs(codec_clk - last_clk)) {
867 pll_j = j; pll_d = 0;
868 pll_r = r; pll_p = p;
5baf8315 869 last_clk = tmp_clk;
255173b4
PM		 870 }
871
872 /* Early exit for exact matches */
5baf8315 873 if (tmp_clk == codec_clk)
255173b4
PM		 874 goto found;
875 }
876 }
4f9c16cc 877
255173b4
PM		 878 /* try with d != 0 */
879 for (p = 1; p <= 8; p++) {
880 j = codec_clk * p / 1000;
4f9c16cc 881
255173b4
PM		 882 if (j < 4 || j > 11)
883 continue;
4f9c16cc 884
255173b4
PM		 885 /* do not use codec_clk here since we'd loose precision */
886 d = ((2048 * p * fsref) - j * aic3x->sysclk)
887 * 100 / (aic3x->sysclk/100);
4f9c16cc 888
255173b4 889 clk = (10000 * j + d) / (10 * p);
4f9c16cc 890
255173b4
PM		 891 /* check whether this values get closer than the best
892 * ones we had before */
893 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
894 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
895 last_clk = clk;
4f9c16cc
DM		 896 }
897
255173b4
PM		 898 /* Early exit for exact matches */
899 if (clk == codec_clk)
900 goto found;
901 }
902
4f9c16cc
DM		 903 if (last_clk == 0) {
904 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
905 return -EINVAL;
906 }
44d0a879 907
255173b4 908found:
44d0a879
VB		 909 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
910 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
911 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
912 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
913 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
914 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
915 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
916
44d0a879
VB		 917 return 0;
918}
919
e550e17f 920static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 921{
922 struct snd_soc_codec *codec = dai->codec;
923 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
924 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
925
926 if (mute) {
927 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
928 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
929 } else {
930 aic3x_write(codec, LDAC_VOL, ldac_reg);
931 aic3x_write(codec, RDAC_VOL, rdac_reg);
932 }
933
934 return 0;
935}
936
e550e17f 937static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 938 int clk_id, unsigned int freq, int dir)
939{
940 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 941 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 942
4f9c16cc
DM		 943 aic3x->sysclk = freq;
944 return 0;
44d0a879
VB		 945}
946
e550e17f 947static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 948 unsigned int fmt)
949{
950 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 951 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 952 u8 iface_areg, iface_breg;
a24f4f68 953 int delay = 0;
81971a14
JN		 954
955 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
956 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 957
958 /* set master/slave audio interface */
959 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
960 case SND_SOC_DAIFMT_CBM_CFM:
961 aic3x->master = 1;
962 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
963 break;
964 case SND_SOC_DAIFMT_CBS_CFS:
965 aic3x->master = 0;
966 break;
967 default:
968 return -EINVAL;
969 }
970
4b7d2831
JN		 971 /*
972 * match both interface format and signal polarities since they
973 * are fixed
974 */
975 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
976 SND_SOC_DAIFMT_INV_MASK)) {
977 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 978 break;
a24f4f68
TK		 979 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
980 delay = 1;
4b7d2831 981 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 982 iface_breg |= (0x01 << 6);
983 break;
4b7d2831 984 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 985 iface_breg |= (0x02 << 6);
986 break;
4b7d2831 987 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 988 iface_breg |= (0x03 << 6);
989 break;
990 default:
991 return -EINVAL;
992 }
993
994 /* set iface */
995 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
996 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
a24f4f68 997 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 998
999 return 0;
1000}
1001
0be9898a
MB		 1002static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1003 enum snd_soc_bias_level level)
44d0a879 1004{
b2c812e2 1005 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1006 u8 reg;
1007
0be9898a
MB		 1008 switch (level) {
1009 case SND_SOC_BIAS_ON:
db13802e
JN		 1010 break;
1011 case SND_SOC_BIAS_PREPARE:
44d0a879
VB		 1012 if (aic3x->master) {
1013 /* enable pll */
1014 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1015 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1016 reg | PLL_ENABLE);
1017 }
1018 break;
0be9898a 1019 case SND_SOC_BIAS_STANDBY:
db13802e 1020 /* fall through and disable pll */
0be9898a 1021 case SND_SOC_BIAS_OFF:
44d0a879
VB		 1022 if (aic3x->master) {
1023 /* disable pll */
1024 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1025 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1026 reg & ~PLL_ENABLE);
1027 }
1028 break;
1029 }
0be9898a 1030 codec->bias_level = level;
44d0a879
VB		 1031
1032 return 0;
1033}
1034
54e7e616
DM		 1035void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1036{
1037 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1038 u8 bit = gpio ? 3: 0;
1039 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1040 aic3x_write(codec, reg, val | (!!state << bit));
1041}
1042EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1043
1044int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1045{
1046 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1047 u8 val, bit = gpio ? 2: 1;
1048
1049 aic3x_read(codec, reg, &val);
1050 return (val >> bit) & 1;
1051}
1052EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1053
6f2a974b
DM		 1054void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1055 int headset_debounce, int button_debounce)
1056{
1057 u8 val;
1058
1059 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1060 << AIC3X_HEADSET_DETECT_SHIFT) |
1061 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1062 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1063 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1064 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1065
1066 if (detect & AIC3X_HEADSET_DETECT_MASK)
1067 val |= AIC3X_HEADSET_DETECT_ENABLED;
1068
1069 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1070}
1071EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1072
54e7e616
DM		 1073int aic3x_headset_detected(struct snd_soc_codec *codec)
1074{
1075 u8 val;
6f2a974b
DM		 1076 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1077 return (val >> 4) & 1;
54e7e616
DM		 1078}
1079EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1080
6f2a974b
DM		 1081int aic3x_button_pressed(struct snd_soc_codec *codec)
1082{
1083 u8 val;
1084 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1085 return (val >> 5) & 1;
1086}
1087EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1088
44d0a879
VB		 1089#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1090#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1091 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1092
6335d055
EM		 1093static struct snd_soc_dai_ops aic3x_dai_ops = {
1094 .hw_params = aic3x_hw_params,
1095 .digital_mute = aic3x_mute,
1096 .set_sysclk = aic3x_set_dai_sysclk,
1097 .set_fmt = aic3x_set_dai_fmt,
1098};
1099
e550e17f 1100struct snd_soc_dai aic3x_dai = {
e78cc18d 1101 .name = "tlv320aic3x",
44d0a879
VB		 1102 .playback = {
1103 .stream_name = "Playback",
1104 .channels_min = 1,
1105 .channels_max = 2,
1106 .rates = AIC3X_RATES,
1107 .formats = AIC3X_FORMATS,},
1108 .capture = {
1109 .stream_name = "Capture",
1110 .channels_min = 1,
1111 .channels_max = 2,
1112 .rates = AIC3X_RATES,
1113 .formats = AIC3X_FORMATS,},
6335d055 1114 .ops = &aic3x_dai_ops,
44d0a879
VB		 1115};
1116EXPORT_SYMBOL_GPL(aic3x_dai);
1117
1118static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1119{
1120 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1121 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879 1122
0be9898a 1123 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1124
1125 return 0;
1126}
1127
1128static int aic3x_resume(struct platform_device *pdev)
1129{
1130 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1131 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879
VB		 1132 int i;
1133 u8 data[2];
1134 u8 *cache = codec->reg_cache;
1135
1136 /* Sync reg_cache with the hardware */
1137 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1138 data[0] = i;
1139 data[1] = cache[i];
1140 codec->hw_write(codec->control_data, data, 2);
1141 }
1142
0be9898a 1143 aic3x_set_bias_level(codec, codec->suspend_bias_level);
44d0a879
VB		 1144
1145 return 0;
1146}
1147
1148/*
1149 * initialise the AIC3X driver
1150 * register the mixer and dsp interfaces with the kernel
1151 */
cb3826f5 1152static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1153{
cb3826f5
BD		 1154 int reg;
1155
1156 mutex_init(&codec->mutex);
1157 INIT_LIST_HEAD(&codec->dapm_widgets);
1158 INIT_LIST_HEAD(&codec->dapm_paths);
44d0a879 1159
e78cc18d 1160 codec->name = "tlv320aic3x";
44d0a879
VB		 1161 codec->owner = THIS_MODULE;
1162 codec->read = aic3x_read_reg_cache;
1163 codec->write = aic3x_write;
0be9898a 1164 codec->set_bias_level = aic3x_set_bias_level;
44d0a879
VB		 1165 codec->dai = &aic3x_dai;
1166 codec->num_dai = 1;
ae2ff191 1167 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
44d0a879
VB		 1168 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1169 if (codec->reg_cache == NULL)
1170 return -ENOMEM;
1171
1172 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1173 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1174
44d0a879
VB		 1175 /* DAC default volume and mute */
1176 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1177 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1178
1179 /* DAC to HP default volume and route to Output mixer */
1180 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1181 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1182 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1183 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1184 /* DAC to Line Out default volume and route to Output mixer */
1185 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1186 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1187 /* DAC to Mono Line Out default volume and route to Output mixer */
1188 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1189 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1190
1191 /* unmute all outputs */
1192 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1193 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1194 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1195 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1196 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1197 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1198 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1199 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1200 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1201 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1202 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1203 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1204 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1205 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1206
1207 /* ADC default volume and unmute */
1208 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1209 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1210 /* By default route Line1 to ADC PGA mixer */
1211 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1212 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1213
1214 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1215 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1216 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1217 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1218 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1219 /* PGA to Line Out default volume, disconnect from Output Mixer */
1220 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1221 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1222 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1223 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1224 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1225
1226 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1227 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1228 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1229 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1230 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1231 /* Line2 Line Out default volume, disconnect from Output Mixer */
1232 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1233 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1234 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1235 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1236 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1237
1238 /* off, with power on */
0be9898a 1239 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1240
cb3826f5
BD		 1241 return 0;
1242}
54e7e616 1243
cb3826f5
BD		 1244static struct snd_soc_codec *aic3x_codec;
1245
1246static int aic3x_register(struct snd_soc_codec *codec)
1247{
1248 int ret;
1249
1250 ret = aic3x_init(codec);
44d0a879 1251 if (ret < 0) {
cb3826f5
BD		 1252 dev_err(codec->dev, "Failed to initialise device\n");
1253 return ret;
44d0a879
VB		 1254 }
1255
cb3826f5 1256 aic3x_codec = codec;
44d0a879 1257
cb3826f5
BD		 1258 ret = snd_soc_register_codec(codec);
1259 if (ret) {
1260 dev_err(codec->dev, "Failed to register codec\n");
1261 return ret;
1262 }
1263
1264 ret = snd_soc_register_dai(&aic3x_dai);
1265 if (ret) {
1266 dev_err(codec->dev, "Failed to register dai\n");
1267 snd_soc_unregister_codec(codec);
1268 return ret;
1269 }
1270
1271 return 0;
44d0a879
VB		 1272}
1273
cb3826f5
BD		 1274static int aic3x_unregister(struct aic3x_priv *aic3x)
1275{
1276 aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF);
1277
1278 snd_soc_unregister_dai(&aic3x_dai);
1279 snd_soc_unregister_codec(&aic3x->codec);
1280
07779fdd
JN		 1281 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1282 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1283
cb3826f5
BD		 1284 kfree(aic3x);
1285 aic3x_codec = NULL;
1286
1287 return 0;
1288}
44d0a879
VB		 1289
1290#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1291/*
1292 * AIC3X 2 wire address can be up to 4 devices with device addresses
1293 * 0x18, 0x19, 0x1A, 0x1B
1294 */
44d0a879
VB		 1295
1296/*
1297 * If the i2c layer weren't so broken, we could pass this kind of data
1298 * around
1299 */
ba8ed121
JD		 1300static int aic3x_i2c_probe(struct i2c_client *i2c,
1301 const struct i2c_device_id *id)
44d0a879 1302{
cb3826f5
BD		 1303 struct snd_soc_codec *codec;
1304 struct aic3x_priv *aic3x;
07779fdd 1305 int ret, i;
44d0a879 1306
cb3826f5
BD		 1307 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1308 if (aic3x == NULL) {
1309 dev_err(&i2c->dev, "failed to create private data\n");
1310 return -ENOMEM;
1311 }
1312
1313 codec = &aic3x->codec;
1314 codec->dev = &i2c->dev;
b2c812e2 1315 snd_soc_codec_set_drvdata(codec, aic3x);
44d0a879 1316 codec->control_data = i2c;
cb3826f5 1317 codec->hw_write = (hw_write_t) i2c_master_send;
44d0a879 1318
cb3826f5
BD		 1319 i2c_set_clientdata(i2c, aic3x);
1320
07779fdd
JN		 1321 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1322 aic3x->supplies[i].supply = aic3x_supply_names[i];
1323
1324 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1325 aic3x->supplies);
1326 if (ret != 0) {
1327 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1328 goto err_get;
1329 }
1330
1331 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1332 aic3x->supplies);
1333 if (ret != 0) {
1334 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1335 goto err_enable;
1336 }
1337
cb3826f5 1338 return aic3x_register(codec);
07779fdd
JN		 1339
1340err_enable:
1341 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1342err_get:
1343 kfree(aic3x);
1344 return ret;
44d0a879
VB		 1345}
1346
ba8ed121 1347static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1348{
cb3826f5
BD		 1349 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1350
1351 return aic3x_unregister(aic3x);
44d0a879
VB		 1352}
1353
ba8ed121
JD		 1354static const struct i2c_device_id aic3x_i2c_id[] = {
1355 { "tlv320aic3x", 0 },
cb3826f5 1356 { "tlv320aic33", 0 },
ba8ed121
JD		 1357 { }
1358};
1359MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
44d0a879
VB		 1360
1361/* machine i2c codec control layer */
1362static struct i2c_driver aic3x_i2c_driver = {
1363 .driver = {
1364 .name = "aic3x I2C Codec",
1365 .owner = THIS_MODULE,
1366 },
cb3826f5 1367 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1368 .remove = aic3x_i2c_remove,
1369 .id_table = aic3x_i2c_id,
44d0a879 1370};
54e7e616 1371
cb3826f5 1372static inline void aic3x_i2c_init(void)
ba8ed121 1373{
ba8ed121
JD		 1374 int ret;
1375
1376 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1377 if (ret)
1378 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1379 __func__, ret);
1380}
ba8ed121 1381
cb3826f5
BD		 1382static inline void aic3x_i2c_exit(void)
1383{
ba8ed121 1384 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1385}
cb3826f5
BD		 1386#else
1387static inline void aic3x_i2c_init(void) { }
1388static inline void aic3x_i2c_exit(void) { }
44d0a879
VB		 1389#endif
1390
1391static int aic3x_probe(struct platform_device *pdev)
1392{
1393 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1394 struct aic3x_setup_data *setup;
1395 struct snd_soc_codec *codec;
44d0a879
VB		 1396 int ret = 0;
1397
cb3826f5
BD		 1398 codec = aic3x_codec;
1399 if (!codec) {
1400 dev_err(&pdev->dev, "Codec not registered\n");
1401 return -ENODEV;
1402 }
44d0a879 1403
cb3826f5 1404 socdev->card->codec = codec;
44d0a879 1405 setup = socdev->codec_data;
44d0a879 1406
977d49e0
MB		 1407 if (setup) {
1408 /* setup GPIO functions */
1409 aic3x_write(codec, AIC3X_GPIO1_REG,
1410 (setup->gpio_func[0] & 0xf) << 4);
1411 aic3x_write(codec, AIC3X_GPIO2_REG,
1412 (setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1413 }
1414
cb3826f5
BD		 1415 /* register pcms */
1416 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1417 if (ret < 0) {
1418 printk(KERN_ERR "aic3x: failed to create pcms\n");
1419 goto pcm_err;
44d0a879 1420 }
3051e41a 1421
cb3826f5
BD		 1422 snd_soc_add_controls(codec, aic3x_snd_controls,
1423 ARRAY_SIZE(aic3x_snd_controls));
1424
1425 aic3x_add_widgets(codec);
1426
cb3826f5
BD		 1427 return ret;
1428
cb3826f5
BD		 1429pcm_err:
1430 kfree(codec->reg_cache);
44d0a879
VB		 1431 return ret;
1432}
1433
1434static int aic3x_remove(struct platform_device *pdev)
1435{
1436 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1437 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879
VB		 1438
1439 /* power down chip */
1440 if (codec->control_data)
0be9898a 1441 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1442
1443 snd_soc_free_pcms(socdev);
1444 snd_soc_dapm_free(socdev);
cb3826f5
BD		 1445
1446 kfree(codec->reg_cache);
44d0a879
VB		 1447
1448 return 0;
1449}
1450
1451struct snd_soc_codec_device soc_codec_dev_aic3x = {
1452 .probe = aic3x_probe,
1453 .remove = aic3x_remove,
1454 .suspend = aic3x_suspend,
1455 .resume = aic3x_resume,
1456};
1457EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1458
c9b3a40f 1459static int __init aic3x_modinit(void)
64089b84 1460{
cb3826f5
BD		 1461 aic3x_i2c_init();
1462
1463 return 0;
64089b84
MB		 1464}
1465module_init(aic3x_modinit);
1466
1467static void __exit aic3x_exit(void)
1468{
cb3826f5 1469 aic3x_i2c_exit();
64089b84
MB		 1470}
1471module_exit(aic3x_exit);
1472
44d0a879
VB		 1473MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1474MODULE_AUTHOR("Vladimir Barinov");
1475MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree