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1da177e4 LT |
1 | /* |
2 | * ALSA driver for RME Hammerfall DSP audio interface(s) | |
3 | * | |
4 | * Copyright (c) 2002 Paul Davis | |
5 | * Marcus Andersson | |
6 | * Thomas Charbonnel | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <sound/driver.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/firmware.h> | |
31 | #include <linux/moduleparam.h> | |
32 | ||
33 | #include <sound/core.h> | |
34 | #include <sound/control.h> | |
35 | #include <sound/pcm.h> | |
36 | #include <sound/info.h> | |
37 | #include <sound/asoundef.h> | |
38 | #include <sound/rawmidi.h> | |
39 | #include <sound/hwdep.h> | |
40 | #include <sound/initval.h> | |
41 | #include <sound/hdsp.h> | |
42 | ||
43 | #include <asm/byteorder.h> | |
44 | #include <asm/current.h> | |
45 | #include <asm/io.h> | |
46 | ||
47 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
48 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
49 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ | |
50 | ||
51 | module_param_array(index, int, NULL, 0444); | |
52 | MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); | |
53 | module_param_array(id, charp, NULL, 0444); | |
54 | MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); | |
55 | module_param_array(enable, bool, NULL, 0444); | |
56 | MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); | |
57 | MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); | |
58 | MODULE_DESCRIPTION("RME Hammerfall DSP"); | |
59 | MODULE_LICENSE("GPL"); | |
60 | MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP}," | |
61 | "{RME HDSP-9652}," | |
62 | "{RME HDSP-9632}}"); | |
7e0af29d CL |
63 | #ifdef HDSP_FW_LOADER |
64 | MODULE_FIRMWARE("multiface_firmware.bin"); | |
65 | MODULE_FIRMWARE("multiface_firmware_rev11.bin"); | |
66 | MODULE_FIRMWARE("digiface_firmware.bin"); | |
67 | MODULE_FIRMWARE("digiface_firmware_rev11.bin"); | |
68 | #endif | |
1da177e4 LT |
69 | |
70 | #define HDSP_MAX_CHANNELS 26 | |
71 | #define HDSP_MAX_DS_CHANNELS 14 | |
72 | #define HDSP_MAX_QS_CHANNELS 8 | |
73 | #define DIGIFACE_SS_CHANNELS 26 | |
74 | #define DIGIFACE_DS_CHANNELS 14 | |
75 | #define MULTIFACE_SS_CHANNELS 18 | |
76 | #define MULTIFACE_DS_CHANNELS 14 | |
77 | #define H9652_SS_CHANNELS 26 | |
78 | #define H9652_DS_CHANNELS 14 | |
79 | /* This does not include possible Analog Extension Boards | |
80 | AEBs are detected at card initialization | |
81 | */ | |
82 | #define H9632_SS_CHANNELS 12 | |
83 | #define H9632_DS_CHANNELS 8 | |
84 | #define H9632_QS_CHANNELS 4 | |
85 | ||
86 | /* Write registers. These are defined as byte-offsets from the iobase value. | |
87 | */ | |
88 | #define HDSP_resetPointer 0 | |
d7923b2a | 89 | #define HDSP_freqReg 0 |
1da177e4 LT |
90 | #define HDSP_outputBufferAddress 32 |
91 | #define HDSP_inputBufferAddress 36 | |
92 | #define HDSP_controlRegister 64 | |
93 | #define HDSP_interruptConfirmation 96 | |
94 | #define HDSP_outputEnable 128 | |
95 | #define HDSP_control2Reg 256 | |
96 | #define HDSP_midiDataOut0 352 | |
97 | #define HDSP_midiDataOut1 356 | |
98 | #define HDSP_fifoData 368 | |
99 | #define HDSP_inputEnable 384 | |
100 | ||
101 | /* Read registers. These are defined as byte-offsets from the iobase value | |
102 | */ | |
103 | ||
104 | #define HDSP_statusRegister 0 | |
105 | #define HDSP_timecode 128 | |
106 | #define HDSP_status2Register 192 | |
1da177e4 LT |
107 | #define HDSP_midiDataIn0 360 |
108 | #define HDSP_midiDataIn1 364 | |
109 | #define HDSP_midiStatusOut0 384 | |
110 | #define HDSP_midiStatusOut1 388 | |
111 | #define HDSP_midiStatusIn0 392 | |
112 | #define HDSP_midiStatusIn1 396 | |
113 | #define HDSP_fifoStatus 400 | |
114 | ||
115 | /* the meters are regular i/o-mapped registers, but offset | |
116 | considerably from the rest. the peak registers are reset | |
117 | when read; the least-significant 4 bits are full-scale counters; | |
118 | the actual peak value is in the most-significant 24 bits. | |
119 | */ | |
120 | ||
121 | #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ | |
122 | #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ | |
123 | #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ | |
124 | #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ | |
125 | #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ | |
126 | ||
127 | ||
128 | /* This is for H9652 cards | |
129 | Peak values are read downward from the base | |
130 | Rms values are read upward | |
131 | There are rms values for the outputs too | |
132 | 26*3 values are read in ss mode | |
133 | 14*3 in ds mode, with no gap between values | |
134 | */ | |
135 | #define HDSP_9652_peakBase 7164 | |
136 | #define HDSP_9652_rmsBase 4096 | |
137 | ||
138 | /* c.f. the hdsp_9632_meters_t struct */ | |
139 | #define HDSP_9632_metersBase 4096 | |
140 | ||
141 | #define HDSP_IO_EXTENT 7168 | |
142 | ||
143 | /* control2 register bits */ | |
144 | ||
145 | #define HDSP_TMS 0x01 | |
146 | #define HDSP_TCK 0x02 | |
147 | #define HDSP_TDI 0x04 | |
148 | #define HDSP_JTAG 0x08 | |
149 | #define HDSP_PWDN 0x10 | |
150 | #define HDSP_PROGRAM 0x020 | |
151 | #define HDSP_CONFIG_MODE_0 0x040 | |
152 | #define HDSP_CONFIG_MODE_1 0x080 | |
153 | #define HDSP_VERSION_BIT 0x100 | |
154 | #define HDSP_BIGENDIAN_MODE 0x200 | |
155 | #define HDSP_RD_MULTIPLE 0x400 | |
156 | #define HDSP_9652_ENABLE_MIXER 0x800 | |
157 | #define HDSP_TDO 0x10000000 | |
158 | ||
159 | #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) | |
160 | #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1) | |
161 | ||
162 | /* Control Register bits */ | |
163 | ||
164 | #define HDSP_Start (1<<0) /* start engine */ | |
165 | #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ | |
166 | #define HDSP_Latency1 (1<<2) /* [ see above ] */ | |
167 | #define HDSP_Latency2 (1<<3) /* [ see above ] */ | |
168 | #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ | |
169 | #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ | |
170 | #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ | |
171 | #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ | |
172 | #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ | |
173 | #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ | |
174 | #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ | |
175 | #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ | |
176 | #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ | |
177 | #define HDSP_SyncRef2 (1<<13) | |
178 | #define HDSP_SPDIFInputSelect0 (1<<14) | |
179 | #define HDSP_SPDIFInputSelect1 (1<<15) | |
180 | #define HDSP_SyncRef0 (1<<16) | |
181 | #define HDSP_SyncRef1 (1<<17) | |
182 | #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ | |
183 | #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ | |
184 | #define HDSP_Midi0InterruptEnable (1<<22) | |
185 | #define HDSP_Midi1InterruptEnable (1<<23) | |
186 | #define HDSP_LineOut (1<<24) | |
187 | #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ | |
188 | #define HDSP_ADGain1 (1<<26) | |
189 | #define HDSP_DAGain0 (1<<27) | |
190 | #define HDSP_DAGain1 (1<<28) | |
191 | #define HDSP_PhoneGain0 (1<<29) | |
192 | #define HDSP_PhoneGain1 (1<<30) | |
193 | #define HDSP_QuadSpeed (1<<31) | |
194 | ||
195 | #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) | |
196 | #define HDSP_ADGainMinus10dBV HDSP_ADGainMask | |
197 | #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) | |
198 | #define HDSP_ADGainLowGain 0 | |
199 | ||
200 | #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) | |
201 | #define HDSP_DAGainHighGain HDSP_DAGainMask | |
202 | #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) | |
203 | #define HDSP_DAGainMinus10dBV 0 | |
204 | ||
205 | #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) | |
206 | #define HDSP_PhoneGain0dB HDSP_PhoneGainMask | |
207 | #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) | |
208 | #define HDSP_PhoneGainMinus12dB 0 | |
209 | ||
210 | #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) | |
211 | #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) | |
212 | ||
213 | #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) | |
214 | #define HDSP_SPDIFInputADAT1 0 | |
215 | #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) | |
216 | #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) | |
217 | #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) | |
218 | ||
219 | #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) | |
220 | #define HDSP_SyncRef_ADAT1 0 | |
221 | #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) | |
222 | #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) | |
223 | #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) | |
224 | #define HDSP_SyncRef_WORD (HDSP_SyncRef2) | |
225 | #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) | |
226 | ||
227 | /* Sample Clock Sources */ | |
228 | ||
229 | #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 | |
230 | #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 | |
231 | #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 | |
232 | #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 | |
233 | #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 | |
234 | #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 | |
235 | #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 | |
236 | #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 | |
237 | #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 | |
238 | #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 | |
239 | ||
240 | /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ | |
241 | ||
242 | #define HDSP_SYNC_FROM_WORD 0 | |
243 | #define HDSP_SYNC_FROM_SPDIF 1 | |
244 | #define HDSP_SYNC_FROM_ADAT1 2 | |
245 | #define HDSP_SYNC_FROM_ADAT_SYNC 3 | |
246 | #define HDSP_SYNC_FROM_ADAT2 4 | |
247 | #define HDSP_SYNC_FROM_ADAT3 5 | |
248 | ||
249 | /* SyncCheck status */ | |
250 | ||
251 | #define HDSP_SYNC_CHECK_NO_LOCK 0 | |
252 | #define HDSP_SYNC_CHECK_LOCK 1 | |
253 | #define HDSP_SYNC_CHECK_SYNC 2 | |
254 | ||
255 | /* AutoSync references - used by "autosync_ref" control switch */ | |
256 | ||
257 | #define HDSP_AUTOSYNC_FROM_WORD 0 | |
258 | #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 | |
259 | #define HDSP_AUTOSYNC_FROM_SPDIF 2 | |
260 | #define HDSP_AUTOSYNC_FROM_NONE 3 | |
261 | #define HDSP_AUTOSYNC_FROM_ADAT1 4 | |
262 | #define HDSP_AUTOSYNC_FROM_ADAT2 5 | |
263 | #define HDSP_AUTOSYNC_FROM_ADAT3 6 | |
264 | ||
265 | /* Possible sources of S/PDIF input */ | |
266 | ||
267 | #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ | |
268 | #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ | |
269 | #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ | |
270 | #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ | |
271 | ||
272 | #define HDSP_Frequency32KHz HDSP_Frequency0 | |
273 | #define HDSP_Frequency44_1KHz HDSP_Frequency1 | |
274 | #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) | |
275 | #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) | |
276 | #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) | |
277 | #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) | |
278 | /* For H9632 cards */ | |
279 | #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) | |
280 | #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) | |
281 | #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) | |
e4b6088c JC |
282 | /* RME says n = 104857600000000, but in the windows MADI driver, I see: |
283 | return 104857600000000 / rate; // 100 MHz | |
284 | return 110100480000000 / rate; // 105 MHz | |
285 | */ | |
286 | #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */ | |
1da177e4 LT |
287 | |
288 | #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) | |
289 | #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) | |
290 | ||
291 | #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) | |
292 | #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) | |
293 | ||
294 | /* Status Register bits */ | |
295 | ||
296 | #define HDSP_audioIRQPending (1<<0) | |
297 | #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ | |
298 | #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ | |
299 | #define HDSP_Lock1 (1<<2) | |
300 | #define HDSP_Lock0 (1<<3) | |
301 | #define HDSP_SPDIFSync (1<<4) | |
302 | #define HDSP_TimecodeLock (1<<5) | |
303 | #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ | |
304 | #define HDSP_Sync2 (1<<16) | |
305 | #define HDSP_Sync1 (1<<17) | |
306 | #define HDSP_Sync0 (1<<18) | |
307 | #define HDSP_DoubleSpeedStatus (1<<19) | |
308 | #define HDSP_ConfigError (1<<20) | |
309 | #define HDSP_DllError (1<<21) | |
310 | #define HDSP_spdifFrequency0 (1<<22) | |
311 | #define HDSP_spdifFrequency1 (1<<23) | |
312 | #define HDSP_spdifFrequency2 (1<<24) | |
313 | #define HDSP_SPDIFErrorFlag (1<<25) | |
314 | #define HDSP_BufferID (1<<26) | |
315 | #define HDSP_TimecodeSync (1<<27) | |
316 | #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ | |
317 | #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ | |
318 | #define HDSP_midi0IRQPending (1<<30) | |
319 | #define HDSP_midi1IRQPending (1<<31) | |
320 | ||
321 | #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) | |
322 | ||
323 | #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) | |
324 | #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) | |
325 | #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) | |
326 | ||
327 | #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) | |
328 | #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) | |
329 | #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) | |
330 | ||
331 | /* This is for H9632 cards */ | |
332 | #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask | |
333 | #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 | |
334 | #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) | |
335 | ||
336 | /* Status2 Register bits */ | |
337 | ||
338 | #define HDSP_version0 (1<<0) | |
339 | #define HDSP_version1 (1<<1) | |
340 | #define HDSP_version2 (1<<2) | |
341 | #define HDSP_wc_lock (1<<3) | |
342 | #define HDSP_wc_sync (1<<4) | |
343 | #define HDSP_inp_freq0 (1<<5) | |
344 | #define HDSP_inp_freq1 (1<<6) | |
345 | #define HDSP_inp_freq2 (1<<7) | |
346 | #define HDSP_SelSyncRef0 (1<<8) | |
347 | #define HDSP_SelSyncRef1 (1<<9) | |
348 | #define HDSP_SelSyncRef2 (1<<10) | |
349 | ||
350 | #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) | |
351 | ||
352 | #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) | |
353 | #define HDSP_systemFrequency32 (HDSP_inp_freq0) | |
354 | #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) | |
355 | #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) | |
356 | #define HDSP_systemFrequency64 (HDSP_inp_freq2) | |
357 | #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) | |
358 | #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) | |
359 | /* FIXME : more values for 9632 cards ? */ | |
360 | ||
361 | #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) | |
362 | #define HDSP_SelSyncRef_ADAT1 0 | |
363 | #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) | |
364 | #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) | |
365 | #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) | |
366 | #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) | |
367 | #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) | |
368 | ||
369 | /* Card state flags */ | |
370 | ||
371 | #define HDSP_InitializationComplete (1<<0) | |
372 | #define HDSP_FirmwareLoaded (1<<1) | |
373 | #define HDSP_FirmwareCached (1<<2) | |
374 | ||
375 | /* FIFO wait times, defined in terms of 1/10ths of msecs */ | |
376 | ||
377 | #define HDSP_LONG_WAIT 5000 | |
378 | #define HDSP_SHORT_WAIT 30 | |
379 | ||
380 | #define UNITY_GAIN 32768 | |
381 | #define MINUS_INFINITY_GAIN 0 | |
382 | ||
1da177e4 LT |
383 | /* the size of a substream (1 mono data stream) */ |
384 | ||
385 | #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) | |
386 | #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) | |
387 | ||
388 | /* the size of the area we need to allocate for DMA transfers. the | |
389 | size is the same regardless of the number of channels - the | |
390 | Multiface still uses the same memory area. | |
391 | ||
392 | Note that we allocate 1 more channel than is apparently needed | |
393 | because the h/w seems to write 1 byte beyond the end of the last | |
394 | page. Sigh. | |
395 | */ | |
396 | ||
397 | #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) | |
398 | #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) | |
399 | ||
400 | /* use hotplug firmeare loader? */ | |
401 | #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) | |
140432fd | 402 | #if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP) |
1da177e4 LT |
403 | #define HDSP_FW_LOADER |
404 | #endif | |
405 | #endif | |
406 | ||
55e957d8 | 407 | struct hdsp_9632_meters { |
1da177e4 LT |
408 | u32 input_peak[16]; |
409 | u32 playback_peak[16]; | |
410 | u32 output_peak[16]; | |
411 | u32 xxx_peak[16]; | |
412 | u32 padding[64]; | |
413 | u32 input_rms_low[16]; | |
414 | u32 playback_rms_low[16]; | |
415 | u32 output_rms_low[16]; | |
416 | u32 xxx_rms_low[16]; | |
417 | u32 input_rms_high[16]; | |
418 | u32 playback_rms_high[16]; | |
419 | u32 output_rms_high[16]; | |
420 | u32 xxx_rms_high[16]; | |
421 | }; | |
422 | ||
55e957d8 TI |
423 | struct hdsp_midi { |
424 | struct hdsp *hdsp; | |
1da177e4 | 425 | int id; |
55e957d8 TI |
426 | struct snd_rawmidi *rmidi; |
427 | struct snd_rawmidi_substream *input; | |
428 | struct snd_rawmidi_substream *output; | |
1da177e4 LT |
429 | char istimer; /* timer in use */ |
430 | struct timer_list timer; | |
431 | spinlock_t lock; | |
432 | int pending; | |
433 | }; | |
434 | ||
55e957d8 | 435 | struct hdsp { |
1da177e4 | 436 | spinlock_t lock; |
55e957d8 TI |
437 | struct snd_pcm_substream *capture_substream; |
438 | struct snd_pcm_substream *playback_substream; | |
439 | struct hdsp_midi midi[2]; | |
1da177e4 LT |
440 | struct tasklet_struct midi_tasklet; |
441 | int use_midi_tasklet; | |
442 | int precise_ptr; | |
443 | u32 control_register; /* cached value */ | |
444 | u32 control2_register; /* cached value */ | |
445 | u32 creg_spdif; | |
446 | u32 creg_spdif_stream; | |
e3ea4d89 | 447 | int clock_source_locked; |
1da177e4 | 448 | char *card_name; /* digiface/multiface */ |
55e957d8 | 449 | enum HDSP_IO_Type io_type; /* ditto, but for code use */ |
1da177e4 LT |
450 | unsigned short firmware_rev; |
451 | unsigned short state; /* stores state bits */ | |
452 | u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ | |
453 | size_t period_bytes; /* guess what this is */ | |
454 | unsigned char max_channels; | |
455 | unsigned char qs_in_channels; /* quad speed mode for H9632 */ | |
456 | unsigned char ds_in_channels; | |
457 | unsigned char ss_in_channels; /* different for multiface/digiface */ | |
458 | unsigned char qs_out_channels; | |
459 | unsigned char ds_out_channels; | |
460 | unsigned char ss_out_channels; | |
461 | ||
462 | struct snd_dma_buffer capture_dma_buf; | |
463 | struct snd_dma_buffer playback_dma_buf; | |
464 | unsigned char *capture_buffer; /* suitably aligned address */ | |
465 | unsigned char *playback_buffer; /* suitably aligned address */ | |
466 | ||
467 | pid_t capture_pid; | |
468 | pid_t playback_pid; | |
469 | int running; | |
470 | int system_sample_rate; | |
471 | char *channel_map; | |
472 | int dev; | |
473 | int irq; | |
474 | unsigned long port; | |
475 | void __iomem *iobase; | |
55e957d8 TI |
476 | struct snd_card *card; |
477 | struct snd_pcm *pcm; | |
478 | struct snd_hwdep *hwdep; | |
1da177e4 | 479 | struct pci_dev *pci; |
55e957d8 | 480 | struct snd_kcontrol *spdif_ctl; |
1da177e4 | 481 | unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; |
d7923b2a | 482 | unsigned int dds_value; /* last value written to freq register */ |
1da177e4 LT |
483 | }; |
484 | ||
485 | /* These tables map the ALSA channels 1..N to the channels that we | |
486 | need to use in order to find the relevant channel buffer. RME | |
487 | refer to this kind of mapping as between "the ADAT channel and | |
488 | the DMA channel." We index it using the logical audio channel, | |
489 | and the value is the DMA channel (i.e. channel buffer number) | |
490 | where the data for that channel can be read/written from/to. | |
491 | */ | |
492 | ||
493 | static char channel_map_df_ss[HDSP_MAX_CHANNELS] = { | |
494 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
495 | 18, 19, 20, 21, 22, 23, 24, 25 | |
496 | }; | |
497 | ||
498 | static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ | |
499 | /* Analog */ | |
500 | 0, 1, 2, 3, 4, 5, 6, 7, | |
501 | /* ADAT 2 */ | |
502 | 16, 17, 18, 19, 20, 21, 22, 23, | |
503 | /* SPDIF */ | |
504 | 24, 25, | |
505 | -1, -1, -1, -1, -1, -1, -1, -1 | |
506 | }; | |
507 | ||
508 | static char channel_map_ds[HDSP_MAX_CHANNELS] = { | |
509 | /* ADAT channels are remapped */ | |
510 | 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, | |
511 | /* channels 12 and 13 are S/PDIF */ | |
512 | 24, 25, | |
513 | /* others don't exist */ | |
514 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 | |
515 | }; | |
516 | ||
517 | static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { | |
518 | /* ADAT channels */ | |
519 | 0, 1, 2, 3, 4, 5, 6, 7, | |
520 | /* SPDIF */ | |
521 | 8, 9, | |
522 | /* Analog */ | |
523 | 10, 11, | |
524 | /* AO4S-192 and AI4S-192 extension boards */ | |
525 | 12, 13, 14, 15, | |
526 | /* others don't exist */ | |
527 | -1, -1, -1, -1, -1, -1, -1, -1, | |
528 | -1, -1 | |
529 | }; | |
530 | ||
531 | static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { | |
532 | /* ADAT */ | |
533 | 1, 3, 5, 7, | |
534 | /* SPDIF */ | |
535 | 8, 9, | |
536 | /* Analog */ | |
537 | 10, 11, | |
538 | /* AO4S-192 and AI4S-192 extension boards */ | |
539 | 12, 13, 14, 15, | |
540 | /* others don't exist */ | |
541 | -1, -1, -1, -1, -1, -1, -1, -1, | |
542 | -1, -1, -1, -1, -1, -1 | |
543 | }; | |
544 | ||
545 | static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { | |
546 | /* ADAT is disabled in this mode */ | |
547 | /* SPDIF */ | |
548 | 8, 9, | |
549 | /* Analog */ | |
550 | 10, 11, | |
551 | /* AO4S-192 and AI4S-192 extension boards */ | |
552 | 12, 13, 14, 15, | |
553 | /* others don't exist */ | |
554 | -1, -1, -1, -1, -1, -1, -1, -1, | |
555 | -1, -1, -1, -1, -1, -1, -1, -1, | |
556 | -1, -1 | |
557 | }; | |
558 | ||
559 | static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) | |
560 | { | |
561 | dmab->dev.type = SNDRV_DMA_TYPE_DEV; | |
562 | dmab->dev.dev = snd_dma_pci_data(pci); | |
b6a96915 TI |
563 | if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) { |
564 | if (dmab->bytes >= size) | |
565 | return 0; | |
1da177e4 | 566 | } |
b6a96915 TI |
567 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), |
568 | size, dmab) < 0) | |
569 | return -ENOMEM; | |
1da177e4 LT |
570 | return 0; |
571 | } | |
572 | ||
573 | static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) | |
574 | { | |
b6a96915 TI |
575 | if (dmab->area) { |
576 | dmab->dev.dev = NULL; /* make it anonymous */ | |
1da177e4 | 577 | snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci)); |
b6a96915 | 578 | } |
1da177e4 LT |
579 | } |
580 | ||
581 | ||
f40b6890 | 582 | static struct pci_device_id snd_hdsp_ids[] = { |
1da177e4 LT |
583 | { |
584 | .vendor = PCI_VENDOR_ID_XILINX, | |
585 | .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, | |
586 | .subvendor = PCI_ANY_ID, | |
587 | .subdevice = PCI_ANY_ID, | |
588 | }, /* RME Hammerfall-DSP */ | |
589 | { 0, }, | |
590 | }; | |
591 | ||
592 | MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); | |
593 | ||
594 | /* prototypes */ | |
55e957d8 TI |
595 | static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); |
596 | static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); | |
597 | static int snd_hdsp_enable_io (struct hdsp *hdsp); | |
598 | static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); | |
599 | static void snd_hdsp_initialize_channels (struct hdsp *hdsp); | |
600 | static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); | |
601 | static int hdsp_autosync_ref(struct hdsp *hdsp); | |
602 | static int snd_hdsp_set_defaults(struct hdsp *hdsp); | |
603 | static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); | |
604 | ||
605 | static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) | |
1da177e4 | 606 | { |
a3a68c85 RB |
607 | switch (hdsp->io_type) { |
608 | case Multiface: | |
609 | case Digiface: | |
610 | default: | |
1da177e4 | 611 | return (64 * out) + (32 + (in)); |
a3a68c85 | 612 | case H9632: |
1da177e4 | 613 | return (32 * out) + (16 + (in)); |
a3a68c85 | 614 | case H9652: |
1da177e4 LT |
615 | return (52 * out) + (26 + (in)); |
616 | } | |
617 | } | |
618 | ||
55e957d8 | 619 | static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) |
1da177e4 | 620 | { |
a3a68c85 RB |
621 | switch (hdsp->io_type) { |
622 | case Multiface: | |
623 | case Digiface: | |
624 | default: | |
1da177e4 | 625 | return (64 * out) + in; |
a3a68c85 | 626 | case H9632: |
1da177e4 | 627 | return (32 * out) + in; |
a3a68c85 | 628 | case H9652: |
1da177e4 LT |
629 | return (52 * out) + in; |
630 | } | |
631 | } | |
632 | ||
55e957d8 | 633 | static void hdsp_write(struct hdsp *hdsp, int reg, int val) |
1da177e4 LT |
634 | { |
635 | writel(val, hdsp->iobase + reg); | |
636 | } | |
637 | ||
55e957d8 | 638 | static unsigned int hdsp_read(struct hdsp *hdsp, int reg) |
1da177e4 LT |
639 | { |
640 | return readl (hdsp->iobase + reg); | |
641 | } | |
642 | ||
55e957d8 | 643 | static int hdsp_check_for_iobox (struct hdsp *hdsp) |
1da177e4 LT |
644 | { |
645 | ||
646 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; | |
647 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { | |
648 | snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); | |
649 | hdsp->state &= ~HDSP_FirmwareLoaded; | |
650 | return -EIO; | |
651 | } | |
652 | return 0; | |
653 | ||
654 | } | |
655 | ||
55e957d8 | 656 | static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { |
1da177e4 LT |
657 | |
658 | int i; | |
659 | unsigned long flags; | |
660 | ||
661 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
662 | ||
663 | snd_printk ("Hammerfall-DSP: loading firmware\n"); | |
664 | ||
665 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); | |
666 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
667 | ||
668 | if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { | |
669 | snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n"); | |
670 | return -EIO; | |
671 | } | |
672 | ||
673 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
674 | ||
675 | for (i = 0; i < 24413; ++i) { | |
676 | hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]); | |
677 | if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { | |
678 | snd_printk ("Hammerfall-DSP: timeout during firmware loading\n"); | |
679 | return -EIO; | |
680 | } | |
681 | } | |
682 | ||
b0b98119 | 683 | ssleep(3); |
1da177e4 LT |
684 | |
685 | if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { | |
686 | snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n"); | |
687 | return -EIO; | |
688 | } | |
689 | ||
690 | #ifdef SNDRV_BIG_ENDIAN | |
691 | hdsp->control2_register = HDSP_BIGENDIAN_MODE; | |
692 | #else | |
693 | hdsp->control2_register = 0; | |
694 | #endif | |
695 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
696 | snd_printk ("Hammerfall-DSP: finished firmware loading\n"); | |
697 | ||
698 | } | |
699 | if (hdsp->state & HDSP_InitializationComplete) { | |
b0b98119 | 700 | snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n"); |
1da177e4 LT |
701 | spin_lock_irqsave(&hdsp->lock, flags); |
702 | snd_hdsp_set_defaults(hdsp); | |
703 | spin_unlock_irqrestore(&hdsp->lock, flags); | |
704 | } | |
705 | ||
706 | hdsp->state |= HDSP_FirmwareLoaded; | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
55e957d8 | 711 | static int hdsp_get_iobox_version (struct hdsp *hdsp) |
1da177e4 LT |
712 | { |
713 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
714 | ||
715 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM); | |
716 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
b0b98119 | 717 | if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) |
1da177e4 | 718 | return -EIO; |
1da177e4 LT |
719 | |
720 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
721 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
722 | ||
723 | if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { | |
724 | hdsp->io_type = Multiface; | |
725 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT); | |
726 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
727 | hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); | |
728 | } else { | |
729 | hdsp->io_type = Digiface; | |
730 | } | |
731 | } else { | |
732 | /* firmware was already loaded, get iobox type */ | |
b0b98119 | 733 | if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) |
1da177e4 | 734 | hdsp->io_type = Multiface; |
b0b98119 | 735 | else |
1da177e4 | 736 | hdsp->io_type = Digiface; |
1da177e4 LT |
737 | } |
738 | return 0; | |
739 | } | |
740 | ||
741 | ||
311e70a4 TI |
742 | #ifdef HDSP_FW_LOADER |
743 | static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp); | |
744 | #endif | |
745 | ||
746 | static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) | |
1da177e4 | 747 | { |
311e70a4 TI |
748 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) |
749 | return 0; | |
1da177e4 | 750 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { |
1da177e4 | 751 | hdsp->state &= ~HDSP_FirmwareLoaded; |
311e70a4 | 752 | if (! load_on_demand) |
b0b98119 | 753 | return -EIO; |
311e70a4 | 754 | snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n"); |
b0b98119 | 755 | /* try to load firmware */ |
311e70a4 TI |
756 | if (! (hdsp->state & HDSP_FirmwareCached)) { |
757 | #ifdef HDSP_FW_LOADER | |
758 | if (! hdsp_request_fw_loader(hdsp)) | |
759 | return 0; | |
760 | #endif | |
761 | snd_printk(KERN_ERR | |
762 | "Hammerfall-DSP: No firmware loaded nor " | |
763 | "cached, please upload firmware.\n"); | |
764 | return -EIO; | |
765 | } | |
766 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
767 | snd_printk(KERN_ERR | |
768 | "Hammerfall-DSP: Firmware loading from " | |
769 | "cache failed, please upload manually.\n"); | |
770 | return -EIO; | |
b0b98119 | 771 | } |
1da177e4 LT |
772 | } |
773 | return 0; | |
774 | } | |
775 | ||
776 | ||
55e957d8 | 777 | static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) |
1da177e4 LT |
778 | { |
779 | int i; | |
780 | ||
781 | /* the fifoStatus registers reports on how many words | |
782 | are available in the command FIFO. | |
783 | */ | |
784 | ||
785 | for (i = 0; i < timeout; i++) { | |
786 | ||
787 | if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) | |
788 | return 0; | |
789 | ||
790 | /* not very friendly, but we only do this during a firmware | |
791 | load and changing the mixer, so we just put up with it. | |
792 | */ | |
793 | ||
794 | udelay (100); | |
795 | } | |
796 | ||
797 | snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n", | |
798 | count, timeout); | |
799 | return -1; | |
800 | } | |
801 | ||
55e957d8 | 802 | static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) |
1da177e4 | 803 | { |
b0b98119 | 804 | if (addr >= HDSP_MATRIX_MIXER_SIZE) |
1da177e4 | 805 | return 0; |
b0b98119 | 806 | |
1da177e4 LT |
807 | return hdsp->mixer_matrix[addr]; |
808 | } | |
809 | ||
55e957d8 | 810 | static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) |
1da177e4 LT |
811 | { |
812 | unsigned int ad; | |
813 | ||
814 | if (addr >= HDSP_MATRIX_MIXER_SIZE) | |
815 | return -1; | |
816 | ||
817 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { | |
818 | ||
819 | /* from martin bjornsen: | |
820 | ||
821 | "You can only write dwords to the | |
822 | mixer memory which contain two | |
823 | mixer values in the low and high | |
824 | word. So if you want to change | |
825 | value 0 you have to read value 1 | |
826 | from the cache and write both to | |
827 | the first dword in the mixer | |
828 | memory." | |
829 | */ | |
830 | ||
b0b98119 | 831 | if (hdsp->io_type == H9632 && addr >= 512) |
1da177e4 | 832 | return 0; |
1da177e4 | 833 | |
b0b98119 | 834 | if (hdsp->io_type == H9652 && addr >= 1352) |
1da177e4 | 835 | return 0; |
1da177e4 LT |
836 | |
837 | hdsp->mixer_matrix[addr] = data; | |
838 | ||
839 | ||
840 | /* `addr' addresses a 16-bit wide address, but | |
841 | the address space accessed via hdsp_write | |
842 | uses byte offsets. put another way, addr | |
843 | varies from 0 to 1351, but to access the | |
844 | corresponding memory location, we need | |
845 | to access 0 to 2703 ... | |
846 | */ | |
847 | ad = addr/2; | |
848 | ||
849 | hdsp_write (hdsp, 4096 + (ad*4), | |
850 | (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + | |
851 | hdsp->mixer_matrix[addr&0x7fe]); | |
852 | ||
853 | return 0; | |
854 | ||
855 | } else { | |
856 | ||
857 | ad = (addr << 16) + data; | |
858 | ||
b0b98119 | 859 | if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) |
1da177e4 | 860 | return -1; |
1da177e4 LT |
861 | |
862 | hdsp_write (hdsp, HDSP_fifoData, ad); | |
863 | hdsp->mixer_matrix[addr] = data; | |
864 | ||
865 | } | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
55e957d8 | 870 | static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) |
1da177e4 LT |
871 | { |
872 | unsigned long flags; | |
873 | int ret = 1; | |
874 | ||
875 | spin_lock_irqsave(&hdsp->lock, flags); | |
876 | if ((hdsp->playback_pid != hdsp->capture_pid) && | |
b0b98119 | 877 | (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) |
1da177e4 | 878 | ret = 0; |
1da177e4 LT |
879 | spin_unlock_irqrestore(&hdsp->lock, flags); |
880 | return ret; | |
881 | } | |
882 | ||
55e957d8 | 883 | static int hdsp_external_sample_rate (struct hdsp *hdsp) |
1da177e4 LT |
884 | { |
885 | unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
886 | unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; | |
887 | ||
888 | switch (rate_bits) { | |
889 | case HDSP_systemFrequency32: return 32000; | |
890 | case HDSP_systemFrequency44_1: return 44100; | |
891 | case HDSP_systemFrequency48: return 48000; | |
892 | case HDSP_systemFrequency64: return 64000; | |
893 | case HDSP_systemFrequency88_2: return 88200; | |
894 | case HDSP_systemFrequency96: return 96000; | |
895 | default: | |
896 | return 0; | |
897 | } | |
898 | } | |
899 | ||
55e957d8 | 900 | static int hdsp_spdif_sample_rate(struct hdsp *hdsp) |
1da177e4 LT |
901 | { |
902 | unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); | |
903 | unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); | |
904 | ||
b0b98119 | 905 | if (status & HDSP_SPDIFErrorFlag) |
1da177e4 | 906 | return 0; |
1da177e4 LT |
907 | |
908 | switch (rate_bits) { | |
909 | case HDSP_spdifFrequency32KHz: return 32000; | |
910 | case HDSP_spdifFrequency44_1KHz: return 44100; | |
911 | case HDSP_spdifFrequency48KHz: return 48000; | |
912 | case HDSP_spdifFrequency64KHz: return 64000; | |
913 | case HDSP_spdifFrequency88_2KHz: return 88200; | |
914 | case HDSP_spdifFrequency96KHz: return 96000; | |
915 | case HDSP_spdifFrequency128KHz: | |
916 | if (hdsp->io_type == H9632) return 128000; | |
917 | break; | |
918 | case HDSP_spdifFrequency176_4KHz: | |
919 | if (hdsp->io_type == H9632) return 176400; | |
920 | break; | |
921 | case HDSP_spdifFrequency192KHz: | |
922 | if (hdsp->io_type == H9632) return 192000; | |
923 | break; | |
924 | default: | |
925 | break; | |
926 | } | |
927 | snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); | |
928 | return 0; | |
929 | } | |
930 | ||
55e957d8 | 931 | static void hdsp_compute_period_size(struct hdsp *hdsp) |
1da177e4 LT |
932 | { |
933 | hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); | |
934 | } | |
935 | ||
55e957d8 | 936 | static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) |
1da177e4 LT |
937 | { |
938 | int position; | |
939 | ||
940 | position = hdsp_read(hdsp, HDSP_statusRegister); | |
941 | ||
b0b98119 | 942 | if (!hdsp->precise_ptr) |
1da177e4 | 943 | return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; |
1da177e4 LT |
944 | |
945 | position &= HDSP_BufferPositionMask; | |
946 | position /= 4; | |
947 | position &= (hdsp->period_bytes/2) - 1; | |
948 | return position; | |
949 | } | |
950 | ||
55e957d8 | 951 | static void hdsp_reset_hw_pointer(struct hdsp *hdsp) |
1da177e4 LT |
952 | { |
953 | hdsp_write (hdsp, HDSP_resetPointer, 0); | |
d7923b2a RB |
954 | if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) |
955 | /* HDSP_resetPointer = HDSP_freqReg, which is strange and | |
956 | * requires (?) to write again DDS value after a reset pointer | |
957 | * (at least, it works like this) */ | |
958 | hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); | |
1da177e4 LT |
959 | } |
960 | ||
55e957d8 | 961 | static void hdsp_start_audio(struct hdsp *s) |
1da177e4 LT |
962 | { |
963 | s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); | |
964 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
965 | } | |
966 | ||
55e957d8 | 967 | static void hdsp_stop_audio(struct hdsp *s) |
1da177e4 LT |
968 | { |
969 | s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); | |
970 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
971 | } | |
972 | ||
55e957d8 | 973 | static void hdsp_silence_playback(struct hdsp *hdsp) |
1da177e4 LT |
974 | { |
975 | memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); | |
976 | } | |
977 | ||
55e957d8 | 978 | static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) |
1da177e4 LT |
979 | { |
980 | int n; | |
981 | ||
982 | spin_lock_irq(&s->lock); | |
983 | ||
984 | frames >>= 7; | |
985 | n = 0; | |
986 | while (frames) { | |
987 | n++; | |
988 | frames >>= 1; | |
989 | } | |
990 | ||
991 | s->control_register &= ~HDSP_LatencyMask; | |
992 | s->control_register |= hdsp_encode_latency(n); | |
993 | ||
994 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
995 | ||
996 | hdsp_compute_period_size(s); | |
997 | ||
998 | spin_unlock_irq(&s->lock); | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
d7923b2a RB |
1003 | static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) |
1004 | { | |
1005 | u64 n; | |
1006 | u32 r; | |
1007 | ||
1008 | if (rate >= 112000) | |
1009 | rate /= 4; | |
1010 | else if (rate >= 56000) | |
1011 | rate /= 2; | |
1012 | ||
e4b6088c | 1013 | n = DDS_NUMERATOR; |
d7923b2a RB |
1014 | div64_32(&n, rate, &r); |
1015 | /* n should be less than 2^32 for being written to FREQ register */ | |
1016 | snd_assert((n >> 32) == 0); | |
1017 | /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS | |
1018 | value to write it after a reset */ | |
1019 | hdsp->dds_value = n; | |
1020 | hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); | |
1021 | } | |
1022 | ||
55e957d8 | 1023 | static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) |
1da177e4 LT |
1024 | { |
1025 | int reject_if_open = 0; | |
1026 | int current_rate; | |
1027 | int rate_bits; | |
1028 | ||
1029 | /* ASSUMPTION: hdsp->lock is either held, or | |
1030 | there is no need for it (e.g. during module | |
1031 | initialization). | |
1032 | */ | |
1033 | ||
1034 | if (!(hdsp->control_register & HDSP_ClockModeMaster)) { | |
1035 | if (called_internally) { | |
1036 | /* request from ctl or card initialization */ | |
b0b98119 | 1037 | snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n"); |
1da177e4 LT |
1038 | return -1; |
1039 | } else { | |
1040 | /* hw_param request while in AutoSync mode */ | |
1041 | int external_freq = hdsp_external_sample_rate(hdsp); | |
1042 | int spdif_freq = hdsp_spdif_sample_rate(hdsp); | |
1043 | ||
b0b98119 TI |
1044 | if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) |
1045 | snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n"); | |
1046 | else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) | |
1047 | snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n"); | |
1048 | else if (rate != external_freq) { | |
1049 | snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n"); | |
1da177e4 LT |
1050 | return -1; |
1051 | } | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | current_rate = hdsp->system_sample_rate; | |
1056 | ||
1057 | /* Changing from a "single speed" to a "double speed" rate is | |
1058 | not allowed if any substreams are open. This is because | |
1059 | such a change causes a shift in the location of | |
1060 | the DMA buffers and a reduction in the number of available | |
1061 | buffers. | |
1062 | ||
1063 | Note that a similar but essentially insoluble problem | |
1064 | exists for externally-driven rate changes. All we can do | |
1065 | is to flag rate changes in the read/write routines. */ | |
1066 | ||
b0b98119 | 1067 | if (rate > 96000 && hdsp->io_type != H9632) |
1da177e4 | 1068 | return -EINVAL; |
1da177e4 LT |
1069 | |
1070 | switch (rate) { | |
1071 | case 32000: | |
b0b98119 | 1072 | if (current_rate > 48000) |
1da177e4 | 1073 | reject_if_open = 1; |
1da177e4 LT |
1074 | rate_bits = HDSP_Frequency32KHz; |
1075 | break; | |
1076 | case 44100: | |
b0b98119 | 1077 | if (current_rate > 48000) |
1da177e4 | 1078 | reject_if_open = 1; |
1da177e4 LT |
1079 | rate_bits = HDSP_Frequency44_1KHz; |
1080 | break; | |
1081 | case 48000: | |
b0b98119 | 1082 | if (current_rate > 48000) |
1da177e4 | 1083 | reject_if_open = 1; |
1da177e4 LT |
1084 | rate_bits = HDSP_Frequency48KHz; |
1085 | break; | |
1086 | case 64000: | |
b0b98119 | 1087 | if (current_rate <= 48000 || current_rate > 96000) |
1da177e4 | 1088 | reject_if_open = 1; |
1da177e4 LT |
1089 | rate_bits = HDSP_Frequency64KHz; |
1090 | break; | |
1091 | case 88200: | |
b0b98119 | 1092 | if (current_rate <= 48000 || current_rate > 96000) |
1da177e4 | 1093 | reject_if_open = 1; |
1da177e4 LT |
1094 | rate_bits = HDSP_Frequency88_2KHz; |
1095 | break; | |
1096 | case 96000: | |
b0b98119 | 1097 | if (current_rate <= 48000 || current_rate > 96000) |
1da177e4 | 1098 | reject_if_open = 1; |
1da177e4 LT |
1099 | rate_bits = HDSP_Frequency96KHz; |
1100 | break; | |
1101 | case 128000: | |
b0b98119 | 1102 | if (current_rate < 128000) |
1da177e4 | 1103 | reject_if_open = 1; |
1da177e4 LT |
1104 | rate_bits = HDSP_Frequency128KHz; |
1105 | break; | |
1106 | case 176400: | |
b0b98119 | 1107 | if (current_rate < 128000) |
1da177e4 | 1108 | reject_if_open = 1; |
1da177e4 LT |
1109 | rate_bits = HDSP_Frequency176_4KHz; |
1110 | break; | |
1111 | case 192000: | |
b0b98119 | 1112 | if (current_rate < 128000) |
1da177e4 | 1113 | reject_if_open = 1; |
1da177e4 LT |
1114 | rate_bits = HDSP_Frequency192KHz; |
1115 | break; | |
1116 | default: | |
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
1120 | if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { | |
1121 | snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n", | |
1122 | hdsp->capture_pid, | |
1123 | hdsp->playback_pid); | |
1124 | return -EBUSY; | |
1125 | } | |
1126 | ||
1127 | hdsp->control_register &= ~HDSP_FrequencyMask; | |
1128 | hdsp->control_register |= rate_bits; | |
1129 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1130 | ||
d7923b2a RB |
1131 | /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ |
1132 | if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) | |
1133 | hdsp_set_dds_value(hdsp, rate); | |
1134 | ||
1da177e4 LT |
1135 | if (rate >= 128000) { |
1136 | hdsp->channel_map = channel_map_H9632_qs; | |
1137 | } else if (rate > 48000) { | |
b0b98119 | 1138 | if (hdsp->io_type == H9632) |
1da177e4 | 1139 | hdsp->channel_map = channel_map_H9632_ds; |
b0b98119 | 1140 | else |
1da177e4 | 1141 | hdsp->channel_map = channel_map_ds; |
1da177e4 LT |
1142 | } else { |
1143 | switch (hdsp->io_type) { | |
1144 | case Multiface: | |
1145 | hdsp->channel_map = channel_map_mf_ss; | |
1146 | break; | |
1147 | case Digiface: | |
1148 | case H9652: | |
1149 | hdsp->channel_map = channel_map_df_ss; | |
1150 | break; | |
1151 | case H9632: | |
1152 | hdsp->channel_map = channel_map_H9632_ss; | |
1153 | break; | |
1154 | default: | |
1155 | /* should never happen */ | |
1156 | break; | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | hdsp->system_sample_rate = rate; | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | /*---------------------------------------------------------------------------- | |
1166 | MIDI | |
1167 | ----------------------------------------------------------------------------*/ | |
1168 | ||
55e957d8 | 1169 | static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) |
1da177e4 LT |
1170 | { |
1171 | /* the hardware already does the relevant bit-mask with 0xff */ | |
b0b98119 | 1172 | if (id) |
1da177e4 | 1173 | return hdsp_read(hdsp, HDSP_midiDataIn1); |
b0b98119 | 1174 | else |
1da177e4 | 1175 | return hdsp_read(hdsp, HDSP_midiDataIn0); |
1da177e4 LT |
1176 | } |
1177 | ||
55e957d8 | 1178 | static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) |
1da177e4 LT |
1179 | { |
1180 | /* the hardware already does the relevant bit-mask with 0xff */ | |
b0b98119 | 1181 | if (id) |
1da177e4 | 1182 | hdsp_write(hdsp, HDSP_midiDataOut1, val); |
b0b98119 | 1183 | else |
1da177e4 | 1184 | hdsp_write(hdsp, HDSP_midiDataOut0, val); |
1da177e4 LT |
1185 | } |
1186 | ||
55e957d8 | 1187 | static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) |
1da177e4 | 1188 | { |
b0b98119 | 1189 | if (id) |
1da177e4 | 1190 | return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); |
b0b98119 | 1191 | else |
1da177e4 | 1192 | return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); |
1da177e4 LT |
1193 | } |
1194 | ||
55e957d8 | 1195 | static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) |
1da177e4 LT |
1196 | { |
1197 | int fifo_bytes_used; | |
1198 | ||
b0b98119 | 1199 | if (id) |
1da177e4 | 1200 | fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; |
b0b98119 | 1201 | else |
1da177e4 | 1202 | fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; |
1da177e4 | 1203 | |
b0b98119 | 1204 | if (fifo_bytes_used < 128) |
1da177e4 | 1205 | return 128 - fifo_bytes_used; |
b0b98119 | 1206 | else |
1da177e4 | 1207 | return 0; |
1da177e4 LT |
1208 | } |
1209 | ||
55e957d8 | 1210 | static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) |
1da177e4 | 1211 | { |
b0b98119 | 1212 | while (snd_hdsp_midi_input_available (hdsp, id)) |
1da177e4 | 1213 | snd_hdsp_midi_read_byte (hdsp, id); |
1da177e4 LT |
1214 | } |
1215 | ||
55e957d8 | 1216 | static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) |
1da177e4 LT |
1217 | { |
1218 | unsigned long flags; | |
1219 | int n_pending; | |
1220 | int to_write; | |
1221 | int i; | |
1222 | unsigned char buf[128]; | |
1223 | ||
1224 | /* Output is not interrupt driven */ | |
1225 | ||
1226 | spin_lock_irqsave (&hmidi->lock, flags); | |
1227 | if (hmidi->output) { | |
1228 | if (!snd_rawmidi_transmit_empty (hmidi->output)) { | |
1229 | if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) { | |
1230 | if (n_pending > (int)sizeof (buf)) | |
1231 | n_pending = sizeof (buf); | |
1232 | ||
1233 | if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) { | |
1234 | for (i = 0; i < to_write; ++i) | |
1235 | snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); | |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | } | |
1240 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1241 | return 0; | |
1242 | } | |
1243 | ||
55e957d8 | 1244 | static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) |
1da177e4 LT |
1245 | { |
1246 | unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ | |
1247 | unsigned long flags; | |
1248 | int n_pending; | |
1249 | int i; | |
1250 | ||
1251 | spin_lock_irqsave (&hmidi->lock, flags); | |
1252 | if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { | |
1253 | if (hmidi->input) { | |
b0b98119 | 1254 | if (n_pending > (int)sizeof (buf)) |
1da177e4 | 1255 | n_pending = sizeof (buf); |
b0b98119 | 1256 | for (i = 0; i < n_pending; ++i) |
1da177e4 | 1257 | buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); |
b0b98119 | 1258 | if (n_pending) |
1da177e4 | 1259 | snd_rawmidi_receive (hmidi->input, buf, n_pending); |
1da177e4 LT |
1260 | } else { |
1261 | /* flush the MIDI input FIFO */ | |
b0b98119 | 1262 | while (--n_pending) |
1da177e4 | 1263 | snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); |
1da177e4 LT |
1264 | } |
1265 | } | |
1266 | hmidi->pending = 0; | |
b0b98119 | 1267 | if (hmidi->id) |
1da177e4 | 1268 | hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; |
b0b98119 | 1269 | else |
1da177e4 | 1270 | hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; |
1da177e4 LT |
1271 | hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); |
1272 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1273 | return snd_hdsp_midi_output_write (hmidi); | |
1274 | } | |
1275 | ||
55e957d8 | 1276 | static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 | 1277 | { |
55e957d8 TI |
1278 | struct hdsp *hdsp; |
1279 | struct hdsp_midi *hmidi; | |
1da177e4 LT |
1280 | unsigned long flags; |
1281 | u32 ie; | |
1282 | ||
55e957d8 | 1283 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1284 | hdsp = hmidi->hdsp; |
1285 | ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; | |
1286 | spin_lock_irqsave (&hdsp->lock, flags); | |
1287 | if (up) { | |
1288 | if (!(hdsp->control_register & ie)) { | |
1289 | snd_hdsp_flush_midi_input (hdsp, hmidi->id); | |
1290 | hdsp->control_register |= ie; | |
1291 | } | |
1292 | } else { | |
1293 | hdsp->control_register &= ~ie; | |
1294 | tasklet_kill(&hdsp->midi_tasklet); | |
1295 | } | |
1296 | ||
1297 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1298 | spin_unlock_irqrestore (&hdsp->lock, flags); | |
1299 | } | |
1300 | ||
1301 | static void snd_hdsp_midi_output_timer(unsigned long data) | |
1302 | { | |
55e957d8 | 1303 | struct hdsp_midi *hmidi = (struct hdsp_midi *) data; |
1da177e4 LT |
1304 | unsigned long flags; |
1305 | ||
1306 | snd_hdsp_midi_output_write(hmidi); | |
1307 | spin_lock_irqsave (&hmidi->lock, flags); | |
1308 | ||
1309 | /* this does not bump hmidi->istimer, because the | |
1310 | kernel automatically removed the timer when it | |
1311 | expired, and we are now adding it back, thus | |
1312 | leaving istimer wherever it was set before. | |
1313 | */ | |
1314 | ||
1315 | if (hmidi->istimer) { | |
1316 | hmidi->timer.expires = 1 + jiffies; | |
1317 | add_timer(&hmidi->timer); | |
1318 | } | |
1319 | ||
1320 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1321 | } | |
1322 | ||
55e957d8 | 1323 | static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) |
1da177e4 | 1324 | { |
55e957d8 | 1325 | struct hdsp_midi *hmidi; |
1da177e4 LT |
1326 | unsigned long flags; |
1327 | ||
55e957d8 | 1328 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1329 | spin_lock_irqsave (&hmidi->lock, flags); |
1330 | if (up) { | |
1331 | if (!hmidi->istimer) { | |
1332 | init_timer(&hmidi->timer); | |
1333 | hmidi->timer.function = snd_hdsp_midi_output_timer; | |
1334 | hmidi->timer.data = (unsigned long) hmidi; | |
1335 | hmidi->timer.expires = 1 + jiffies; | |
1336 | add_timer(&hmidi->timer); | |
1337 | hmidi->istimer++; | |
1338 | } | |
1339 | } else { | |
b0b98119 | 1340 | if (hmidi->istimer && --hmidi->istimer <= 0) |
1da177e4 | 1341 | del_timer (&hmidi->timer); |
1da177e4 LT |
1342 | } |
1343 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1344 | if (up) | |
1345 | snd_hdsp_midi_output_write(hmidi); | |
1346 | } | |
1347 | ||
55e957d8 | 1348 | static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 1349 | { |
55e957d8 | 1350 | struct hdsp_midi *hmidi; |
1da177e4 | 1351 | |
55e957d8 | 1352 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1353 | spin_lock_irq (&hmidi->lock); |
1354 | snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); | |
1355 | hmidi->input = substream; | |
1356 | spin_unlock_irq (&hmidi->lock); | |
1357 | ||
1358 | return 0; | |
1359 | } | |
1360 | ||
55e957d8 | 1361 | static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) |
1da177e4 | 1362 | { |
55e957d8 | 1363 | struct hdsp_midi *hmidi; |
1da177e4 | 1364 | |
55e957d8 | 1365 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1366 | spin_lock_irq (&hmidi->lock); |
1367 | hmidi->output = substream; | |
1368 | spin_unlock_irq (&hmidi->lock); | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
55e957d8 | 1373 | static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 1374 | { |
55e957d8 | 1375 | struct hdsp_midi *hmidi; |
1da177e4 LT |
1376 | |
1377 | snd_hdsp_midi_input_trigger (substream, 0); | |
1378 | ||
55e957d8 | 1379 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1380 | spin_lock_irq (&hmidi->lock); |
1381 | hmidi->input = NULL; | |
1382 | spin_unlock_irq (&hmidi->lock); | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
55e957d8 | 1387 | static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) |
1da177e4 | 1388 | { |
55e957d8 | 1389 | struct hdsp_midi *hmidi; |
1da177e4 LT |
1390 | |
1391 | snd_hdsp_midi_output_trigger (substream, 0); | |
1392 | ||
55e957d8 | 1393 | hmidi = (struct hdsp_midi *) substream->rmidi->private_data; |
1da177e4 LT |
1394 | spin_lock_irq (&hmidi->lock); |
1395 | hmidi->output = NULL; | |
1396 | spin_unlock_irq (&hmidi->lock); | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
55e957d8 | 1401 | static struct snd_rawmidi_ops snd_hdsp_midi_output = |
1da177e4 LT |
1402 | { |
1403 | .open = snd_hdsp_midi_output_open, | |
1404 | .close = snd_hdsp_midi_output_close, | |
1405 | .trigger = snd_hdsp_midi_output_trigger, | |
1406 | }; | |
1407 | ||
55e957d8 | 1408 | static struct snd_rawmidi_ops snd_hdsp_midi_input = |
1da177e4 LT |
1409 | { |
1410 | .open = snd_hdsp_midi_input_open, | |
1411 | .close = snd_hdsp_midi_input_close, | |
1412 | .trigger = snd_hdsp_midi_input_trigger, | |
1413 | }; | |
1414 | ||
f40b6890 | 1415 | static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) |
1da177e4 LT |
1416 | { |
1417 | char buf[32]; | |
1418 | ||
1419 | hdsp->midi[id].id = id; | |
1420 | hdsp->midi[id].rmidi = NULL; | |
1421 | hdsp->midi[id].input = NULL; | |
1422 | hdsp->midi[id].output = NULL; | |
1423 | hdsp->midi[id].hdsp = hdsp; | |
1424 | hdsp->midi[id].istimer = 0; | |
1425 | hdsp->midi[id].pending = 0; | |
1426 | spin_lock_init (&hdsp->midi[id].lock); | |
1427 | ||
1428 | sprintf (buf, "%s MIDI %d", card->shortname, id+1); | |
b0b98119 | 1429 | if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) |
1da177e4 | 1430 | return -1; |
1da177e4 LT |
1431 | |
1432 | sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1); | |
1433 | hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; | |
1434 | ||
1435 | snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); | |
1436 | snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); | |
1437 | ||
1438 | hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | | |
1439 | SNDRV_RAWMIDI_INFO_INPUT | | |
1440 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1441 | ||
1442 | return 0; | |
1443 | } | |
1444 | ||
1445 | /*----------------------------------------------------------------------------- | |
1446 | Control Interface | |
1447 | ----------------------------------------------------------------------------*/ | |
1448 | ||
55e957d8 | 1449 | static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) |
1da177e4 LT |
1450 | { |
1451 | u32 val = 0; | |
1452 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; | |
1453 | val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; | |
1454 | if (val & HDSP_SPDIFProfessional) | |
1455 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; | |
1456 | else | |
1457 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; | |
1458 | return val; | |
1459 | } | |
1460 | ||
55e957d8 | 1461 | static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) |
1da177e4 LT |
1462 | { |
1463 | aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | | |
1464 | ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); | |
1465 | if (val & HDSP_SPDIFProfessional) | |
1466 | aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; | |
1467 | else | |
1468 | aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; | |
1469 | } | |
1470 | ||
55e957d8 | 1471 | static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1472 | { |
1473 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1474 | uinfo->count = 1; | |
1475 | return 0; | |
1476 | } | |
1477 | ||
55e957d8 | 1478 | static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1479 | { |
55e957d8 | 1480 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1481 | |
1482 | snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); | |
1483 | return 0; | |
1484 | } | |
1485 | ||
55e957d8 | 1486 | static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1487 | { |
55e957d8 | 1488 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1489 | int change; |
1490 | u32 val; | |
1491 | ||
1492 | val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); | |
1493 | spin_lock_irq(&hdsp->lock); | |
1494 | change = val != hdsp->creg_spdif; | |
1495 | hdsp->creg_spdif = val; | |
1496 | spin_unlock_irq(&hdsp->lock); | |
1497 | return change; | |
1498 | } | |
1499 | ||
55e957d8 | 1500 | static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1501 | { |
1502 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1503 | uinfo->count = 1; | |
1504 | return 0; | |
1505 | } | |
1506 | ||
55e957d8 | 1507 | static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1508 | { |
55e957d8 | 1509 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1510 | |
1511 | snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); | |
1512 | return 0; | |
1513 | } | |
1514 | ||
55e957d8 | 1515 | static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1516 | { |
55e957d8 | 1517 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1518 | int change; |
1519 | u32 val; | |
1520 | ||
1521 | val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); | |
1522 | spin_lock_irq(&hdsp->lock); | |
1523 | change = val != hdsp->creg_spdif_stream; | |
1524 | hdsp->creg_spdif_stream = val; | |
1525 | hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); | |
1526 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); | |
1527 | spin_unlock_irq(&hdsp->lock); | |
1528 | return change; | |
1529 | } | |
1530 | ||
55e957d8 | 1531 | static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1532 | { |
1533 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1534 | uinfo->count = 1; | |
1535 | return 0; | |
1536 | } | |
1537 | ||
55e957d8 | 1538 | static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 LT |
1539 | { |
1540 | ucontrol->value.iec958.status[0] = kcontrol->private_value; | |
1541 | return 0; | |
1542 | } | |
1543 | ||
1544 | #define HDSP_SPDIF_IN(xname, xindex) \ | |
67ed4161 | 1545 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1546 | .name = xname, \ |
1547 | .index = xindex, \ | |
1548 | .info = snd_hdsp_info_spdif_in, \ | |
1549 | .get = snd_hdsp_get_spdif_in, \ | |
1550 | .put = snd_hdsp_put_spdif_in } | |
1551 | ||
55e957d8 | 1552 | static unsigned int hdsp_spdif_in(struct hdsp *hdsp) |
1da177e4 LT |
1553 | { |
1554 | return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); | |
1555 | } | |
1556 | ||
55e957d8 | 1557 | static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) |
1da177e4 LT |
1558 | { |
1559 | hdsp->control_register &= ~HDSP_SPDIFInputMask; | |
1560 | hdsp->control_register |= hdsp_encode_spdif_in(in); | |
1561 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1562 | return 0; | |
1563 | } | |
1564 | ||
55e957d8 | 1565 | static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1566 | { |
1567 | static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; | |
55e957d8 | 1568 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1569 | |
1570 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1571 | uinfo->count = 1; | |
1572 | uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); | |
1573 | if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) | |
1574 | uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); | |
1575 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1576 | return 0; | |
1577 | } | |
1578 | ||
55e957d8 | 1579 | static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1580 | { |
55e957d8 | 1581 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1582 | |
1583 | ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); | |
1584 | return 0; | |
1585 | } | |
1586 | ||
55e957d8 | 1587 | static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1588 | { |
55e957d8 | 1589 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1590 | int change; |
1591 | unsigned int val; | |
1592 | ||
1593 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1594 | return -EBUSY; | |
1595 | val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); | |
1596 | spin_lock_irq(&hdsp->lock); | |
1597 | change = val != hdsp_spdif_in(hdsp); | |
1598 | if (change) | |
1599 | hdsp_set_spdif_input(hdsp, val); | |
1600 | spin_unlock_irq(&hdsp->lock); | |
1601 | return change; | |
1602 | } | |
1603 | ||
1604 | #define HDSP_SPDIF_OUT(xname, xindex) \ | |
67ed4161 | 1605 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1606 | .info = snd_hdsp_info_spdif_bits, \ |
1607 | .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } | |
1608 | ||
55e957d8 | 1609 | static int hdsp_spdif_out(struct hdsp *hdsp) |
1da177e4 LT |
1610 | { |
1611 | return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0; | |
1612 | } | |
1613 | ||
55e957d8 | 1614 | static int hdsp_set_spdif_output(struct hdsp *hdsp, int out) |
1da177e4 | 1615 | { |
b0b98119 | 1616 | if (out) |
1da177e4 | 1617 | hdsp->control_register |= HDSP_SPDIFOpticalOut; |
b0b98119 | 1618 | else |
1da177e4 | 1619 | hdsp->control_register &= ~HDSP_SPDIFOpticalOut; |
1da177e4 LT |
1620 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1621 | return 0; | |
1622 | } | |
1623 | ||
a5ce8890 | 1624 | #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info |
1da177e4 | 1625 | |
55e957d8 | 1626 | static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1627 | { |
55e957d8 | 1628 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1629 | |
1630 | ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); | |
1631 | return 0; | |
1632 | } | |
1633 | ||
55e957d8 | 1634 | static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1635 | { |
55e957d8 | 1636 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1637 | int change; |
1638 | unsigned int val; | |
1639 | ||
1640 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1641 | return -EBUSY; | |
1642 | val = ucontrol->value.integer.value[0] & 1; | |
1643 | spin_lock_irq(&hdsp->lock); | |
1644 | change = (int)val != hdsp_spdif_out(hdsp); | |
1645 | hdsp_set_spdif_output(hdsp, val); | |
1646 | spin_unlock_irq(&hdsp->lock); | |
1647 | return change; | |
1648 | } | |
1649 | ||
1650 | #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ | |
67ed4161 | 1651 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1652 | .info = snd_hdsp_info_spdif_bits, \ |
1653 | .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } | |
1654 | ||
55e957d8 | 1655 | static int hdsp_spdif_professional(struct hdsp *hdsp) |
1da177e4 LT |
1656 | { |
1657 | return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; | |
1658 | } | |
1659 | ||
55e957d8 | 1660 | static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val) |
1da177e4 | 1661 | { |
b0b98119 | 1662 | if (val) |
1da177e4 | 1663 | hdsp->control_register |= HDSP_SPDIFProfessional; |
b0b98119 | 1664 | else |
1da177e4 | 1665 | hdsp->control_register &= ~HDSP_SPDIFProfessional; |
1da177e4 LT |
1666 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1667 | return 0; | |
1668 | } | |
1669 | ||
55e957d8 | 1670 | static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1671 | { |
55e957d8 | 1672 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1673 | |
1674 | ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); | |
1675 | return 0; | |
1676 | } | |
1677 | ||
55e957d8 | 1678 | static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1679 | { |
55e957d8 | 1680 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1681 | int change; |
1682 | unsigned int val; | |
1683 | ||
1684 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1685 | return -EBUSY; | |
1686 | val = ucontrol->value.integer.value[0] & 1; | |
1687 | spin_lock_irq(&hdsp->lock); | |
1688 | change = (int)val != hdsp_spdif_professional(hdsp); | |
1689 | hdsp_set_spdif_professional(hdsp, val); | |
1690 | spin_unlock_irq(&hdsp->lock); | |
1691 | return change; | |
1692 | } | |
1693 | ||
1694 | #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ | |
67ed4161 | 1695 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1696 | .info = snd_hdsp_info_spdif_bits, \ |
1697 | .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } | |
1698 | ||
55e957d8 | 1699 | static int hdsp_spdif_emphasis(struct hdsp *hdsp) |
1da177e4 LT |
1700 | { |
1701 | return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; | |
1702 | } | |
1703 | ||
55e957d8 | 1704 | static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val) |
1da177e4 | 1705 | { |
b0b98119 | 1706 | if (val) |
1da177e4 | 1707 | hdsp->control_register |= HDSP_SPDIFEmphasis; |
b0b98119 | 1708 | else |
1da177e4 | 1709 | hdsp->control_register &= ~HDSP_SPDIFEmphasis; |
1da177e4 LT |
1710 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1711 | return 0; | |
1712 | } | |
1713 | ||
55e957d8 | 1714 | static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1715 | { |
55e957d8 | 1716 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1717 | |
1718 | ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); | |
1719 | return 0; | |
1720 | } | |
1721 | ||
55e957d8 | 1722 | static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1723 | { |
55e957d8 | 1724 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1725 | int change; |
1726 | unsigned int val; | |
1727 | ||
1728 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1729 | return -EBUSY; | |
1730 | val = ucontrol->value.integer.value[0] & 1; | |
1731 | spin_lock_irq(&hdsp->lock); | |
1732 | change = (int)val != hdsp_spdif_emphasis(hdsp); | |
1733 | hdsp_set_spdif_emphasis(hdsp, val); | |
1734 | spin_unlock_irq(&hdsp->lock); | |
1735 | return change; | |
1736 | } | |
1737 | ||
1738 | #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ | |
67ed4161 | 1739 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ |
1da177e4 LT |
1740 | .info = snd_hdsp_info_spdif_bits, \ |
1741 | .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } | |
1742 | ||
55e957d8 | 1743 | static int hdsp_spdif_nonaudio(struct hdsp *hdsp) |
1da177e4 LT |
1744 | { |
1745 | return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; | |
1746 | } | |
1747 | ||
55e957d8 | 1748 | static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val) |
1da177e4 | 1749 | { |
b0b98119 | 1750 | if (val) |
1da177e4 | 1751 | hdsp->control_register |= HDSP_SPDIFNonAudio; |
b0b98119 | 1752 | else |
1da177e4 | 1753 | hdsp->control_register &= ~HDSP_SPDIFNonAudio; |
1da177e4 LT |
1754 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
1755 | return 0; | |
1756 | } | |
1757 | ||
55e957d8 | 1758 | static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1759 | { |
55e957d8 | 1760 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1761 | |
1762 | ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); | |
1763 | return 0; | |
1764 | } | |
1765 | ||
55e957d8 | 1766 | static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1767 | { |
55e957d8 | 1768 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1769 | int change; |
1770 | unsigned int val; | |
1771 | ||
1772 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1773 | return -EBUSY; | |
1774 | val = ucontrol->value.integer.value[0] & 1; | |
1775 | spin_lock_irq(&hdsp->lock); | |
1776 | change = (int)val != hdsp_spdif_nonaudio(hdsp); | |
1777 | hdsp_set_spdif_nonaudio(hdsp, val); | |
1778 | spin_unlock_irq(&hdsp->lock); | |
1779 | return change; | |
1780 | } | |
1781 | ||
1782 | #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 1783 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1784 | .name = xname, \ |
1785 | .index = xindex, \ | |
1786 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1787 | .info = snd_hdsp_info_spdif_sample_rate, \ | |
1788 | .get = snd_hdsp_get_spdif_sample_rate \ | |
1789 | } | |
1790 | ||
55e957d8 | 1791 | static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1792 | { |
1793 | static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; | |
55e957d8 | 1794 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1795 | |
1796 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1797 | uinfo->count = 1; | |
1798 | uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; | |
1799 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1800 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1801 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1802 | return 0; | |
1803 | } | |
1804 | ||
55e957d8 | 1805 | static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1806 | { |
55e957d8 | 1807 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1808 | |
1809 | switch (hdsp_spdif_sample_rate(hdsp)) { | |
1810 | case 32000: | |
1811 | ucontrol->value.enumerated.item[0] = 0; | |
1812 | break; | |
1813 | case 44100: | |
1814 | ucontrol->value.enumerated.item[0] = 1; | |
1815 | break; | |
1816 | case 48000: | |
1817 | ucontrol->value.enumerated.item[0] = 2; | |
1818 | break; | |
1819 | case 64000: | |
1820 | ucontrol->value.enumerated.item[0] = 3; | |
1821 | break; | |
1822 | case 88200: | |
1823 | ucontrol->value.enumerated.item[0] = 4; | |
1824 | break; | |
1825 | case 96000: | |
1826 | ucontrol->value.enumerated.item[0] = 5; | |
1827 | break; | |
1828 | case 128000: | |
1829 | ucontrol->value.enumerated.item[0] = 7; | |
1830 | break; | |
1831 | case 176400: | |
1832 | ucontrol->value.enumerated.item[0] = 8; | |
1833 | break; | |
1834 | case 192000: | |
1835 | ucontrol->value.enumerated.item[0] = 9; | |
1836 | break; | |
1837 | default: | |
1838 | ucontrol->value.enumerated.item[0] = 6; | |
1839 | } | |
1840 | return 0; | |
1841 | } | |
1842 | ||
1843 | #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 1844 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1845 | .name = xname, \ |
1846 | .index = xindex, \ | |
1847 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1848 | .info = snd_hdsp_info_system_sample_rate, \ | |
1849 | .get = snd_hdsp_get_system_sample_rate \ | |
1850 | } | |
1851 | ||
55e957d8 | 1852 | static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1853 | { |
1854 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1855 | uinfo->count = 1; | |
1856 | return 0; | |
1857 | } | |
1858 | ||
55e957d8 | 1859 | static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1860 | { |
55e957d8 | 1861 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1862 | |
1863 | ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; | |
1864 | return 0; | |
1865 | } | |
1866 | ||
1867 | #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 1868 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1869 | .name = xname, \ |
1870 | .index = xindex, \ | |
1871 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1872 | .info = snd_hdsp_info_autosync_sample_rate, \ | |
1873 | .get = snd_hdsp_get_autosync_sample_rate \ | |
1874 | } | |
1875 | ||
55e957d8 | 1876 | static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 1877 | { |
55e957d8 | 1878 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1879 | static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; |
1880 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1881 | uinfo->count = 1; | |
1882 | uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; | |
1883 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1884 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1885 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1886 | return 0; | |
1887 | } | |
1888 | ||
55e957d8 | 1889 | static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1890 | { |
55e957d8 | 1891 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1892 | |
1893 | switch (hdsp_external_sample_rate(hdsp)) { | |
1894 | case 32000: | |
1895 | ucontrol->value.enumerated.item[0] = 0; | |
1896 | break; | |
1897 | case 44100: | |
1898 | ucontrol->value.enumerated.item[0] = 1; | |
1899 | break; | |
1900 | case 48000: | |
1901 | ucontrol->value.enumerated.item[0] = 2; | |
1902 | break; | |
1903 | case 64000: | |
1904 | ucontrol->value.enumerated.item[0] = 3; | |
1905 | break; | |
1906 | case 88200: | |
1907 | ucontrol->value.enumerated.item[0] = 4; | |
1908 | break; | |
1909 | case 96000: | |
1910 | ucontrol->value.enumerated.item[0] = 5; | |
1911 | break; | |
1912 | case 128000: | |
1913 | ucontrol->value.enumerated.item[0] = 7; | |
1914 | break; | |
1915 | case 176400: | |
1916 | ucontrol->value.enumerated.item[0] = 8; | |
1917 | break; | |
1918 | case 192000: | |
1919 | ucontrol->value.enumerated.item[0] = 9; | |
1920 | break; | |
1921 | default: | |
1922 | ucontrol->value.enumerated.item[0] = 6; | |
1923 | } | |
1924 | return 0; | |
1925 | } | |
1926 | ||
1927 | #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ | |
67ed4161 | 1928 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1929 | .name = xname, \ |
1930 | .index = xindex, \ | |
1931 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1932 | .info = snd_hdsp_info_system_clock_mode, \ | |
1933 | .get = snd_hdsp_get_system_clock_mode \ | |
1934 | } | |
1935 | ||
55e957d8 | 1936 | static int hdsp_system_clock_mode(struct hdsp *hdsp) |
1da177e4 | 1937 | { |
b0b98119 | 1938 | if (hdsp->control_register & HDSP_ClockModeMaster) |
1da177e4 | 1939 | return 0; |
b0b98119 | 1940 | else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) |
1da177e4 | 1941 | return 0; |
1da177e4 LT |
1942 | return 1; |
1943 | } | |
1944 | ||
55e957d8 | 1945 | static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
1946 | { |
1947 | static char *texts[] = {"Master", "Slave" }; | |
1948 | ||
1949 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1950 | uinfo->count = 1; | |
1951 | uinfo->value.enumerated.items = 2; | |
1952 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1953 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1954 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1955 | return 0; | |
1956 | } | |
1957 | ||
55e957d8 | 1958 | static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1959 | { |
55e957d8 | 1960 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1961 | |
1962 | ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); | |
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | #define HDSP_CLOCK_SOURCE(xname, xindex) \ | |
67ed4161 | 1967 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
1968 | .name = xname, \ |
1969 | .index = xindex, \ | |
1970 | .info = snd_hdsp_info_clock_source, \ | |
1971 | .get = snd_hdsp_get_clock_source, \ | |
1972 | .put = snd_hdsp_put_clock_source \ | |
1973 | } | |
1974 | ||
55e957d8 | 1975 | static int hdsp_clock_source(struct hdsp *hdsp) |
1da177e4 LT |
1976 | { |
1977 | if (hdsp->control_register & HDSP_ClockModeMaster) { | |
1978 | switch (hdsp->system_sample_rate) { | |
1979 | case 32000: | |
1980 | return 1; | |
1981 | case 44100: | |
1982 | return 2; | |
1983 | case 48000: | |
1984 | return 3; | |
1985 | case 64000: | |
1986 | return 4; | |
1987 | case 88200: | |
1988 | return 5; | |
1989 | case 96000: | |
1990 | return 6; | |
1991 | case 128000: | |
1992 | return 7; | |
1993 | case 176400: | |
1994 | return 8; | |
1995 | case 192000: | |
1996 | return 9; | |
1997 | default: | |
1998 | return 3; | |
1999 | } | |
2000 | } else { | |
2001 | return 0; | |
2002 | } | |
2003 | } | |
2004 | ||
55e957d8 | 2005 | static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2006 | { |
2007 | int rate; | |
2008 | switch (mode) { | |
2009 | case HDSP_CLOCK_SOURCE_AUTOSYNC: | |
2010 | if (hdsp_external_sample_rate(hdsp) != 0) { | |
2011 | if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { | |
2012 | hdsp->control_register &= ~HDSP_ClockModeMaster; | |
2013 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2014 | return 0; | |
2015 | } | |
2016 | } | |
2017 | return -1; | |
2018 | case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: | |
2019 | rate = 32000; | |
2020 | break; | |
2021 | case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
2022 | rate = 44100; | |
2023 | break; | |
2024 | case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: | |
2025 | rate = 48000; | |
2026 | break; | |
2027 | case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: | |
2028 | rate = 64000; | |
2029 | break; | |
2030 | case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
2031 | rate = 88200; | |
2032 | break; | |
2033 | case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: | |
2034 | rate = 96000; | |
2035 | break; | |
2036 | case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: | |
2037 | rate = 128000; | |
2038 | break; | |
2039 | case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
2040 | rate = 176400; | |
2041 | break; | |
2042 | case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: | |
2043 | rate = 192000; | |
2044 | break; | |
2045 | default: | |
2046 | rate = 48000; | |
2047 | } | |
2048 | hdsp->control_register |= HDSP_ClockModeMaster; | |
2049 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2050 | hdsp_set_rate(hdsp, rate, 1); | |
2051 | return 0; | |
2052 | } | |
2053 | ||
55e957d8 | 2054 | static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2055 | { |
2056 | static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; | |
55e957d8 | 2057 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2058 | |
2059 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2060 | uinfo->count = 1; | |
2061 | if (hdsp->io_type == H9632) | |
2062 | uinfo->value.enumerated.items = 10; | |
2063 | else | |
2064 | uinfo->value.enumerated.items = 7; | |
2065 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2066 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2067 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2068 | return 0; | |
2069 | } | |
2070 | ||
55e957d8 | 2071 | static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2072 | { |
55e957d8 | 2073 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2074 | |
2075 | ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); | |
2076 | return 0; | |
2077 | } | |
2078 | ||
55e957d8 | 2079 | static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2080 | { |
55e957d8 | 2081 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2082 | int change; |
2083 | int val; | |
2084 | ||
2085 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2086 | return -EBUSY; | |
2087 | val = ucontrol->value.enumerated.item[0]; | |
2088 | if (val < 0) val = 0; | |
2089 | if (hdsp->io_type == H9632) { | |
b0b98119 TI |
2090 | if (val > 9) |
2091 | val = 9; | |
1da177e4 | 2092 | } else { |
b0b98119 TI |
2093 | if (val > 6) |
2094 | val = 6; | |
1da177e4 LT |
2095 | } |
2096 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2097 | if (val != hdsp_clock_source(hdsp)) |
1da177e4 | 2098 | change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2099 | else |
1da177e4 | 2100 | change = 0; |
1da177e4 LT |
2101 | spin_unlock_irq(&hdsp->lock); |
2102 | return change; | |
2103 | } | |
2104 | ||
a5ce8890 | 2105 | #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info |
e3ea4d89 | 2106 | |
55e957d8 | 2107 | static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
e3ea4d89 | 2108 | { |
55e957d8 | 2109 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
e3ea4d89 TI |
2110 | |
2111 | ucontrol->value.integer.value[0] = hdsp->clock_source_locked; | |
2112 | return 0; | |
2113 | } | |
2114 | ||
55e957d8 | 2115 | static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
e3ea4d89 | 2116 | { |
55e957d8 | 2117 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
e3ea4d89 TI |
2118 | int change; |
2119 | ||
2120 | change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; | |
2121 | if (change) | |
2122 | hdsp->clock_source_locked = ucontrol->value.integer.value[0]; | |
2123 | return change; | |
2124 | } | |
2125 | ||
1da177e4 | 2126 | #define HDSP_DA_GAIN(xname, xindex) \ |
67ed4161 | 2127 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2128 | .name = xname, \ |
2129 | .index = xindex, \ | |
2130 | .info = snd_hdsp_info_da_gain, \ | |
2131 | .get = snd_hdsp_get_da_gain, \ | |
2132 | .put = snd_hdsp_put_da_gain \ | |
2133 | } | |
2134 | ||
55e957d8 | 2135 | static int hdsp_da_gain(struct hdsp *hdsp) |
1da177e4 LT |
2136 | { |
2137 | switch (hdsp->control_register & HDSP_DAGainMask) { | |
2138 | case HDSP_DAGainHighGain: | |
2139 | return 0; | |
2140 | case HDSP_DAGainPlus4dBu: | |
2141 | return 1; | |
2142 | case HDSP_DAGainMinus10dBV: | |
2143 | return 2; | |
2144 | default: | |
2145 | return 1; | |
2146 | } | |
2147 | } | |
2148 | ||
55e957d8 | 2149 | static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2150 | { |
2151 | hdsp->control_register &= ~HDSP_DAGainMask; | |
2152 | switch (mode) { | |
2153 | case 0: | |
2154 | hdsp->control_register |= HDSP_DAGainHighGain; | |
2155 | break; | |
2156 | case 1: | |
2157 | hdsp->control_register |= HDSP_DAGainPlus4dBu; | |
2158 | break; | |
2159 | case 2: | |
2160 | hdsp->control_register |= HDSP_DAGainMinus10dBV; | |
2161 | break; | |
2162 | default: | |
2163 | return -1; | |
2164 | ||
2165 | } | |
2166 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2167 | return 0; | |
2168 | } | |
2169 | ||
55e957d8 | 2170 | static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2171 | { |
2172 | static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; | |
2173 | ||
2174 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2175 | uinfo->count = 1; | |
2176 | uinfo->value.enumerated.items = 3; | |
2177 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2178 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2179 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2180 | return 0; | |
2181 | } | |
2182 | ||
55e957d8 | 2183 | static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2184 | { |
55e957d8 | 2185 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2186 | |
2187 | ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); | |
2188 | return 0; | |
2189 | } | |
2190 | ||
55e957d8 | 2191 | static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2192 | { |
55e957d8 | 2193 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2194 | int change; |
2195 | int val; | |
2196 | ||
2197 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2198 | return -EBUSY; | |
2199 | val = ucontrol->value.enumerated.item[0]; | |
2200 | if (val < 0) val = 0; | |
2201 | if (val > 2) val = 2; | |
2202 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2203 | if (val != hdsp_da_gain(hdsp)) |
1da177e4 | 2204 | change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2205 | else |
1da177e4 | 2206 | change = 0; |
1da177e4 LT |
2207 | spin_unlock_irq(&hdsp->lock); |
2208 | return change; | |
2209 | } | |
2210 | ||
2211 | #define HDSP_AD_GAIN(xname, xindex) \ | |
67ed4161 | 2212 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2213 | .name = xname, \ |
2214 | .index = xindex, \ | |
2215 | .info = snd_hdsp_info_ad_gain, \ | |
2216 | .get = snd_hdsp_get_ad_gain, \ | |
2217 | .put = snd_hdsp_put_ad_gain \ | |
2218 | } | |
2219 | ||
55e957d8 | 2220 | static int hdsp_ad_gain(struct hdsp *hdsp) |
1da177e4 LT |
2221 | { |
2222 | switch (hdsp->control_register & HDSP_ADGainMask) { | |
2223 | case HDSP_ADGainMinus10dBV: | |
2224 | return 0; | |
2225 | case HDSP_ADGainPlus4dBu: | |
2226 | return 1; | |
2227 | case HDSP_ADGainLowGain: | |
2228 | return 2; | |
2229 | default: | |
2230 | return 1; | |
2231 | } | |
2232 | } | |
2233 | ||
55e957d8 | 2234 | static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2235 | { |
2236 | hdsp->control_register &= ~HDSP_ADGainMask; | |
2237 | switch (mode) { | |
2238 | case 0: | |
2239 | hdsp->control_register |= HDSP_ADGainMinus10dBV; | |
2240 | break; | |
2241 | case 1: | |
2242 | hdsp->control_register |= HDSP_ADGainPlus4dBu; | |
2243 | break; | |
2244 | case 2: | |
2245 | hdsp->control_register |= HDSP_ADGainLowGain; | |
2246 | break; | |
2247 | default: | |
2248 | return -1; | |
2249 | ||
2250 | } | |
2251 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2252 | return 0; | |
2253 | } | |
2254 | ||
55e957d8 | 2255 | static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2256 | { |
2257 | static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; | |
2258 | ||
2259 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2260 | uinfo->count = 1; | |
2261 | uinfo->value.enumerated.items = 3; | |
2262 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2263 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2264 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2265 | return 0; | |
2266 | } | |
2267 | ||
55e957d8 | 2268 | static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2269 | { |
55e957d8 | 2270 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2271 | |
2272 | ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); | |
2273 | return 0; | |
2274 | } | |
2275 | ||
55e957d8 | 2276 | static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2277 | { |
55e957d8 | 2278 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2279 | int change; |
2280 | int val; | |
2281 | ||
2282 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2283 | return -EBUSY; | |
2284 | val = ucontrol->value.enumerated.item[0]; | |
2285 | if (val < 0) val = 0; | |
2286 | if (val > 2) val = 2; | |
2287 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2288 | if (val != hdsp_ad_gain(hdsp)) |
1da177e4 | 2289 | change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2290 | else |
1da177e4 | 2291 | change = 0; |
1da177e4 LT |
2292 | spin_unlock_irq(&hdsp->lock); |
2293 | return change; | |
2294 | } | |
2295 | ||
2296 | #define HDSP_PHONE_GAIN(xname, xindex) \ | |
67ed4161 | 2297 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2298 | .name = xname, \ |
2299 | .index = xindex, \ | |
2300 | .info = snd_hdsp_info_phone_gain, \ | |
2301 | .get = snd_hdsp_get_phone_gain, \ | |
2302 | .put = snd_hdsp_put_phone_gain \ | |
2303 | } | |
2304 | ||
55e957d8 | 2305 | static int hdsp_phone_gain(struct hdsp *hdsp) |
1da177e4 LT |
2306 | { |
2307 | switch (hdsp->control_register & HDSP_PhoneGainMask) { | |
2308 | case HDSP_PhoneGain0dB: | |
2309 | return 0; | |
2310 | case HDSP_PhoneGainMinus6dB: | |
2311 | return 1; | |
2312 | case HDSP_PhoneGainMinus12dB: | |
2313 | return 2; | |
2314 | default: | |
2315 | return 0; | |
2316 | } | |
2317 | } | |
2318 | ||
55e957d8 | 2319 | static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) |
1da177e4 LT |
2320 | { |
2321 | hdsp->control_register &= ~HDSP_PhoneGainMask; | |
2322 | switch (mode) { | |
2323 | case 0: | |
2324 | hdsp->control_register |= HDSP_PhoneGain0dB; | |
2325 | break; | |
2326 | case 1: | |
2327 | hdsp->control_register |= HDSP_PhoneGainMinus6dB; | |
2328 | break; | |
2329 | case 2: | |
2330 | hdsp->control_register |= HDSP_PhoneGainMinus12dB; | |
2331 | break; | |
2332 | default: | |
2333 | return -1; | |
2334 | ||
2335 | } | |
2336 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2337 | return 0; | |
2338 | } | |
2339 | ||
55e957d8 | 2340 | static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2341 | { |
2342 | static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; | |
2343 | ||
2344 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2345 | uinfo->count = 1; | |
2346 | uinfo->value.enumerated.items = 3; | |
2347 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2348 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2349 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2350 | return 0; | |
2351 | } | |
2352 | ||
55e957d8 | 2353 | static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2354 | { |
55e957d8 | 2355 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2356 | |
2357 | ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); | |
2358 | return 0; | |
2359 | } | |
2360 | ||
55e957d8 | 2361 | static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2362 | { |
55e957d8 | 2363 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2364 | int change; |
2365 | int val; | |
2366 | ||
2367 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2368 | return -EBUSY; | |
2369 | val = ucontrol->value.enumerated.item[0]; | |
2370 | if (val < 0) val = 0; | |
2371 | if (val > 2) val = 2; | |
2372 | spin_lock_irq(&hdsp->lock); | |
b0b98119 | 2373 | if (val != hdsp_phone_gain(hdsp)) |
1da177e4 | 2374 | change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; |
b0b98119 | 2375 | else |
1da177e4 | 2376 | change = 0; |
1da177e4 LT |
2377 | spin_unlock_irq(&hdsp->lock); |
2378 | return change; | |
2379 | } | |
2380 | ||
2381 | #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ | |
67ed4161 | 2382 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2383 | .name = xname, \ |
2384 | .index = xindex, \ | |
2385 | .info = snd_hdsp_info_xlr_breakout_cable, \ | |
2386 | .get = snd_hdsp_get_xlr_breakout_cable, \ | |
2387 | .put = snd_hdsp_put_xlr_breakout_cable \ | |
2388 | } | |
2389 | ||
55e957d8 | 2390 | static int hdsp_xlr_breakout_cable(struct hdsp *hdsp) |
1da177e4 | 2391 | { |
b0b98119 | 2392 | if (hdsp->control_register & HDSP_XLRBreakoutCable) |
1da177e4 | 2393 | return 1; |
1da177e4 LT |
2394 | return 0; |
2395 | } | |
2396 | ||
55e957d8 | 2397 | static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode) |
1da177e4 | 2398 | { |
b0b98119 | 2399 | if (mode) |
1da177e4 | 2400 | hdsp->control_register |= HDSP_XLRBreakoutCable; |
b0b98119 | 2401 | else |
1da177e4 | 2402 | hdsp->control_register &= ~HDSP_XLRBreakoutCable; |
1da177e4 LT |
2403 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2404 | return 0; | |
2405 | } | |
2406 | ||
a5ce8890 | 2407 | #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info |
1da177e4 | 2408 | |
55e957d8 | 2409 | static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2410 | { |
55e957d8 | 2411 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2412 | |
2413 | ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); | |
2414 | return 0; | |
2415 | } | |
2416 | ||
55e957d8 | 2417 | static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2418 | { |
55e957d8 | 2419 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2420 | int change; |
2421 | int val; | |
2422 | ||
2423 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2424 | return -EBUSY; | |
2425 | val = ucontrol->value.integer.value[0] & 1; | |
2426 | spin_lock_irq(&hdsp->lock); | |
2427 | change = (int)val != hdsp_xlr_breakout_cable(hdsp); | |
2428 | hdsp_set_xlr_breakout_cable(hdsp, val); | |
2429 | spin_unlock_irq(&hdsp->lock); | |
2430 | return change; | |
2431 | } | |
2432 | ||
2433 | /* (De)activates old RME Analog Extension Board | |
2434 | These are connected to the internal ADAT connector | |
2435 | Switching this on desactivates external ADAT | |
2436 | */ | |
2437 | #define HDSP_AEB(xname, xindex) \ | |
67ed4161 | 2438 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2439 | .name = xname, \ |
2440 | .index = xindex, \ | |
2441 | .info = snd_hdsp_info_aeb, \ | |
2442 | .get = snd_hdsp_get_aeb, \ | |
2443 | .put = snd_hdsp_put_aeb \ | |
2444 | } | |
2445 | ||
55e957d8 | 2446 | static int hdsp_aeb(struct hdsp *hdsp) |
1da177e4 | 2447 | { |
b0b98119 | 2448 | if (hdsp->control_register & HDSP_AnalogExtensionBoard) |
1da177e4 | 2449 | return 1; |
1da177e4 LT |
2450 | return 0; |
2451 | } | |
2452 | ||
55e957d8 | 2453 | static int hdsp_set_aeb(struct hdsp *hdsp, int mode) |
1da177e4 | 2454 | { |
b0b98119 | 2455 | if (mode) |
1da177e4 | 2456 | hdsp->control_register |= HDSP_AnalogExtensionBoard; |
b0b98119 | 2457 | else |
1da177e4 | 2458 | hdsp->control_register &= ~HDSP_AnalogExtensionBoard; |
1da177e4 LT |
2459 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2460 | return 0; | |
2461 | } | |
2462 | ||
a5ce8890 | 2463 | #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info |
1da177e4 | 2464 | |
55e957d8 | 2465 | static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2466 | { |
55e957d8 | 2467 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2468 | |
2469 | ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); | |
2470 | return 0; | |
2471 | } | |
2472 | ||
55e957d8 | 2473 | static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2474 | { |
55e957d8 | 2475 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2476 | int change; |
2477 | int val; | |
2478 | ||
2479 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2480 | return -EBUSY; | |
2481 | val = ucontrol->value.integer.value[0] & 1; | |
2482 | spin_lock_irq(&hdsp->lock); | |
2483 | change = (int)val != hdsp_aeb(hdsp); | |
2484 | hdsp_set_aeb(hdsp, val); | |
2485 | spin_unlock_irq(&hdsp->lock); | |
2486 | return change; | |
2487 | } | |
2488 | ||
2489 | #define HDSP_PREF_SYNC_REF(xname, xindex) \ | |
67ed4161 | 2490 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2491 | .name = xname, \ |
2492 | .index = xindex, \ | |
2493 | .info = snd_hdsp_info_pref_sync_ref, \ | |
2494 | .get = snd_hdsp_get_pref_sync_ref, \ | |
2495 | .put = snd_hdsp_put_pref_sync_ref \ | |
2496 | } | |
2497 | ||
55e957d8 | 2498 | static int hdsp_pref_sync_ref(struct hdsp *hdsp) |
1da177e4 LT |
2499 | { |
2500 | /* Notice that this looks at the requested sync source, | |
2501 | not the one actually in use. | |
2502 | */ | |
2503 | ||
2504 | switch (hdsp->control_register & HDSP_SyncRefMask) { | |
2505 | case HDSP_SyncRef_ADAT1: | |
2506 | return HDSP_SYNC_FROM_ADAT1; | |
2507 | case HDSP_SyncRef_ADAT2: | |
2508 | return HDSP_SYNC_FROM_ADAT2; | |
2509 | case HDSP_SyncRef_ADAT3: | |
2510 | return HDSP_SYNC_FROM_ADAT3; | |
2511 | case HDSP_SyncRef_SPDIF: | |
2512 | return HDSP_SYNC_FROM_SPDIF; | |
2513 | case HDSP_SyncRef_WORD: | |
2514 | return HDSP_SYNC_FROM_WORD; | |
2515 | case HDSP_SyncRef_ADAT_SYNC: | |
2516 | return HDSP_SYNC_FROM_ADAT_SYNC; | |
2517 | default: | |
2518 | return HDSP_SYNC_FROM_WORD; | |
2519 | } | |
2520 | return 0; | |
2521 | } | |
2522 | ||
55e957d8 | 2523 | static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) |
1da177e4 LT |
2524 | { |
2525 | hdsp->control_register &= ~HDSP_SyncRefMask; | |
2526 | switch (pref) { | |
2527 | case HDSP_SYNC_FROM_ADAT1: | |
2528 | hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ | |
2529 | break; | |
2530 | case HDSP_SYNC_FROM_ADAT2: | |
2531 | hdsp->control_register |= HDSP_SyncRef_ADAT2; | |
2532 | break; | |
2533 | case HDSP_SYNC_FROM_ADAT3: | |
2534 | hdsp->control_register |= HDSP_SyncRef_ADAT3; | |
2535 | break; | |
2536 | case HDSP_SYNC_FROM_SPDIF: | |
2537 | hdsp->control_register |= HDSP_SyncRef_SPDIF; | |
2538 | break; | |
2539 | case HDSP_SYNC_FROM_WORD: | |
2540 | hdsp->control_register |= HDSP_SyncRef_WORD; | |
2541 | break; | |
2542 | case HDSP_SYNC_FROM_ADAT_SYNC: | |
2543 | hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; | |
2544 | break; | |
2545 | default: | |
2546 | return -1; | |
2547 | } | |
2548 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2549 | return 0; | |
2550 | } | |
2551 | ||
55e957d8 | 2552 | static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2553 | { |
2554 | static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; | |
55e957d8 | 2555 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2556 | |
2557 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2558 | uinfo->count = 1; | |
2559 | ||
2560 | switch (hdsp->io_type) { | |
2561 | case Digiface: | |
2562 | case H9652: | |
2563 | uinfo->value.enumerated.items = 6; | |
2564 | break; | |
2565 | case Multiface: | |
2566 | uinfo->value.enumerated.items = 4; | |
2567 | break; | |
2568 | case H9632: | |
2569 | uinfo->value.enumerated.items = 3; | |
2570 | break; | |
2571 | default: | |
2572 | uinfo->value.enumerated.items = 0; | |
2573 | break; | |
2574 | } | |
2575 | ||
2576 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2577 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2578 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2579 | return 0; | |
2580 | } | |
2581 | ||
55e957d8 | 2582 | static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2583 | { |
55e957d8 | 2584 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2585 | |
2586 | ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); | |
2587 | return 0; | |
2588 | } | |
2589 | ||
55e957d8 | 2590 | static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2591 | { |
55e957d8 | 2592 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2593 | int change, max; |
2594 | unsigned int val; | |
2595 | ||
2596 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2597 | return -EBUSY; | |
2598 | ||
2599 | switch (hdsp->io_type) { | |
2600 | case Digiface: | |
2601 | case H9652: | |
2602 | max = 6; | |
2603 | break; | |
2604 | case Multiface: | |
2605 | max = 4; | |
2606 | break; | |
2607 | case H9632: | |
2608 | max = 3; | |
2609 | break; | |
2610 | default: | |
2611 | return -EIO; | |
2612 | } | |
2613 | ||
2614 | val = ucontrol->value.enumerated.item[0] % max; | |
2615 | spin_lock_irq(&hdsp->lock); | |
2616 | change = (int)val != hdsp_pref_sync_ref(hdsp); | |
2617 | hdsp_set_pref_sync_ref(hdsp, val); | |
2618 | spin_unlock_irq(&hdsp->lock); | |
2619 | return change; | |
2620 | } | |
2621 | ||
2622 | #define HDSP_AUTOSYNC_REF(xname, xindex) \ | |
67ed4161 | 2623 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2624 | .name = xname, \ |
2625 | .index = xindex, \ | |
2626 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2627 | .info = snd_hdsp_info_autosync_ref, \ | |
2628 | .get = snd_hdsp_get_autosync_ref, \ | |
2629 | } | |
2630 | ||
55e957d8 | 2631 | static int hdsp_autosync_ref(struct hdsp *hdsp) |
1da177e4 LT |
2632 | { |
2633 | /* This looks at the autosync selected sync reference */ | |
2634 | unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
2635 | ||
2636 | switch (status2 & HDSP_SelSyncRefMask) { | |
2637 | case HDSP_SelSyncRef_WORD: | |
2638 | return HDSP_AUTOSYNC_FROM_WORD; | |
2639 | case HDSP_SelSyncRef_ADAT_SYNC: | |
2640 | return HDSP_AUTOSYNC_FROM_ADAT_SYNC; | |
2641 | case HDSP_SelSyncRef_SPDIF: | |
2642 | return HDSP_AUTOSYNC_FROM_SPDIF; | |
2643 | case HDSP_SelSyncRefMask: | |
2644 | return HDSP_AUTOSYNC_FROM_NONE; | |
2645 | case HDSP_SelSyncRef_ADAT1: | |
2646 | return HDSP_AUTOSYNC_FROM_ADAT1; | |
2647 | case HDSP_SelSyncRef_ADAT2: | |
2648 | return HDSP_AUTOSYNC_FROM_ADAT2; | |
2649 | case HDSP_SelSyncRef_ADAT3: | |
2650 | return HDSP_AUTOSYNC_FROM_ADAT3; | |
2651 | default: | |
2652 | return HDSP_AUTOSYNC_FROM_WORD; | |
2653 | } | |
2654 | return 0; | |
2655 | } | |
2656 | ||
55e957d8 | 2657 | static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2658 | { |
2659 | static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; | |
2660 | ||
2661 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2662 | uinfo->count = 1; | |
2663 | uinfo->value.enumerated.items = 7; | |
2664 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2665 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2666 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2667 | return 0; | |
2668 | } | |
2669 | ||
55e957d8 | 2670 | static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2671 | { |
55e957d8 | 2672 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2673 | |
2674 | ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); | |
2675 | return 0; | |
2676 | } | |
2677 | ||
2678 | #define HDSP_LINE_OUT(xname, xindex) \ | |
67ed4161 | 2679 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2680 | .name = xname, \ |
2681 | .index = xindex, \ | |
2682 | .info = snd_hdsp_info_line_out, \ | |
2683 | .get = snd_hdsp_get_line_out, \ | |
2684 | .put = snd_hdsp_put_line_out \ | |
2685 | } | |
2686 | ||
55e957d8 | 2687 | static int hdsp_line_out(struct hdsp *hdsp) |
1da177e4 LT |
2688 | { |
2689 | return (hdsp->control_register & HDSP_LineOut) ? 1 : 0; | |
2690 | } | |
2691 | ||
55e957d8 | 2692 | static int hdsp_set_line_output(struct hdsp *hdsp, int out) |
1da177e4 | 2693 | { |
b0b98119 | 2694 | if (out) |
1da177e4 | 2695 | hdsp->control_register |= HDSP_LineOut; |
b0b98119 | 2696 | else |
1da177e4 | 2697 | hdsp->control_register &= ~HDSP_LineOut; |
1da177e4 LT |
2698 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); |
2699 | return 0; | |
2700 | } | |
2701 | ||
a5ce8890 | 2702 | #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info |
1da177e4 | 2703 | |
55e957d8 | 2704 | static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2705 | { |
55e957d8 | 2706 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2707 | |
2708 | spin_lock_irq(&hdsp->lock); | |
2709 | ucontrol->value.integer.value[0] = hdsp_line_out(hdsp); | |
2710 | spin_unlock_irq(&hdsp->lock); | |
2711 | return 0; | |
2712 | } | |
2713 | ||
55e957d8 | 2714 | static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2715 | { |
55e957d8 | 2716 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2717 | int change; |
2718 | unsigned int val; | |
2719 | ||
2720 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2721 | return -EBUSY; | |
2722 | val = ucontrol->value.integer.value[0] & 1; | |
2723 | spin_lock_irq(&hdsp->lock); | |
2724 | change = (int)val != hdsp_line_out(hdsp); | |
2725 | hdsp_set_line_output(hdsp, val); | |
2726 | spin_unlock_irq(&hdsp->lock); | |
2727 | return change; | |
2728 | } | |
2729 | ||
2730 | #define HDSP_PRECISE_POINTER(xname, xindex) \ | |
67ed4161 | 2731 | { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ |
1da177e4 LT |
2732 | .name = xname, \ |
2733 | .index = xindex, \ | |
2734 | .info = snd_hdsp_info_precise_pointer, \ | |
2735 | .get = snd_hdsp_get_precise_pointer, \ | |
2736 | .put = snd_hdsp_put_precise_pointer \ | |
2737 | } | |
2738 | ||
55e957d8 | 2739 | static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) |
1da177e4 | 2740 | { |
b0b98119 | 2741 | if (precise) |
1da177e4 | 2742 | hdsp->precise_ptr = 1; |
b0b98119 | 2743 | else |
1da177e4 | 2744 | hdsp->precise_ptr = 0; |
1da177e4 LT |
2745 | return 0; |
2746 | } | |
2747 | ||
a5ce8890 | 2748 | #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info |
1da177e4 | 2749 | |
55e957d8 | 2750 | static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2751 | { |
55e957d8 | 2752 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2753 | |
2754 | spin_lock_irq(&hdsp->lock); | |
2755 | ucontrol->value.integer.value[0] = hdsp->precise_ptr; | |
2756 | spin_unlock_irq(&hdsp->lock); | |
2757 | return 0; | |
2758 | } | |
2759 | ||
55e957d8 | 2760 | static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2761 | { |
55e957d8 | 2762 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2763 | int change; |
2764 | unsigned int val; | |
2765 | ||
2766 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2767 | return -EBUSY; | |
2768 | val = ucontrol->value.integer.value[0] & 1; | |
2769 | spin_lock_irq(&hdsp->lock); | |
2770 | change = (int)val != hdsp->precise_ptr; | |
2771 | hdsp_set_precise_pointer(hdsp, val); | |
2772 | spin_unlock_irq(&hdsp->lock); | |
2773 | return change; | |
2774 | } | |
2775 | ||
2776 | #define HDSP_USE_MIDI_TASKLET(xname, xindex) \ | |
67ed4161 | 2777 | { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ |
1da177e4 LT |
2778 | .name = xname, \ |
2779 | .index = xindex, \ | |
2780 | .info = snd_hdsp_info_use_midi_tasklet, \ | |
2781 | .get = snd_hdsp_get_use_midi_tasklet, \ | |
2782 | .put = snd_hdsp_put_use_midi_tasklet \ | |
2783 | } | |
2784 | ||
55e957d8 | 2785 | static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet) |
1da177e4 | 2786 | { |
b0b98119 | 2787 | if (use_tasklet) |
1da177e4 | 2788 | hdsp->use_midi_tasklet = 1; |
b0b98119 | 2789 | else |
1da177e4 | 2790 | hdsp->use_midi_tasklet = 0; |
1da177e4 LT |
2791 | return 0; |
2792 | } | |
2793 | ||
a5ce8890 | 2794 | #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info |
1da177e4 | 2795 | |
55e957d8 | 2796 | static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2797 | { |
55e957d8 | 2798 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2799 | |
2800 | spin_lock_irq(&hdsp->lock); | |
2801 | ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet; | |
2802 | spin_unlock_irq(&hdsp->lock); | |
2803 | return 0; | |
2804 | } | |
2805 | ||
55e957d8 | 2806 | static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2807 | { |
55e957d8 | 2808 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2809 | int change; |
2810 | unsigned int val; | |
2811 | ||
2812 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2813 | return -EBUSY; | |
2814 | val = ucontrol->value.integer.value[0] & 1; | |
2815 | spin_lock_irq(&hdsp->lock); | |
2816 | change = (int)val != hdsp->use_midi_tasklet; | |
2817 | hdsp_set_use_midi_tasklet(hdsp, val); | |
2818 | spin_unlock_irq(&hdsp->lock); | |
2819 | return change; | |
2820 | } | |
2821 | ||
2822 | #define HDSP_MIXER(xname, xindex) \ | |
2823 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2824 | .name = xname, \ | |
2825 | .index = xindex, \ | |
67ed4161 | 2826 | .device = 0, \ |
1da177e4 LT |
2827 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ |
2828 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2829 | .info = snd_hdsp_info_mixer, \ | |
2830 | .get = snd_hdsp_get_mixer, \ | |
2831 | .put = snd_hdsp_put_mixer \ | |
2832 | } | |
2833 | ||
55e957d8 | 2834 | static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2835 | { |
2836 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2837 | uinfo->count = 3; | |
2838 | uinfo->value.integer.min = 0; | |
2839 | uinfo->value.integer.max = 65536; | |
2840 | uinfo->value.integer.step = 1; | |
2841 | return 0; | |
2842 | } | |
2843 | ||
55e957d8 | 2844 | static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2845 | { |
55e957d8 | 2846 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2847 | int source; |
2848 | int destination; | |
2849 | int addr; | |
2850 | ||
2851 | source = ucontrol->value.integer.value[0]; | |
2852 | destination = ucontrol->value.integer.value[1]; | |
2853 | ||
b0b98119 | 2854 | if (source >= hdsp->max_channels) |
1da177e4 | 2855 | addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); |
b0b98119 | 2856 | else |
1da177e4 | 2857 | addr = hdsp_input_to_output_key(hdsp,source, destination); |
1da177e4 LT |
2858 | |
2859 | spin_lock_irq(&hdsp->lock); | |
2860 | ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); | |
2861 | spin_unlock_irq(&hdsp->lock); | |
2862 | return 0; | |
2863 | } | |
2864 | ||
55e957d8 | 2865 | static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2866 | { |
55e957d8 | 2867 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2868 | int change; |
2869 | int source; | |
2870 | int destination; | |
2871 | int gain; | |
2872 | int addr; | |
2873 | ||
2874 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2875 | return -EBUSY; | |
2876 | ||
2877 | source = ucontrol->value.integer.value[0]; | |
2878 | destination = ucontrol->value.integer.value[1]; | |
2879 | ||
b0b98119 | 2880 | if (source >= hdsp->max_channels) |
1da177e4 | 2881 | addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); |
b0b98119 | 2882 | else |
1da177e4 | 2883 | addr = hdsp_input_to_output_key(hdsp,source, destination); |
1da177e4 LT |
2884 | |
2885 | gain = ucontrol->value.integer.value[2]; | |
2886 | ||
2887 | spin_lock_irq(&hdsp->lock); | |
2888 | change = gain != hdsp_read_gain(hdsp, addr); | |
2889 | if (change) | |
2890 | hdsp_write_gain(hdsp, addr, gain); | |
2891 | spin_unlock_irq(&hdsp->lock); | |
2892 | return change; | |
2893 | } | |
2894 | ||
2895 | #define HDSP_WC_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 2896 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2897 | .name = xname, \ |
2898 | .index = xindex, \ | |
2899 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2900 | .info = snd_hdsp_info_sync_check, \ | |
2901 | .get = snd_hdsp_get_wc_sync_check \ | |
2902 | } | |
2903 | ||
55e957d8 | 2904 | static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2905 | { |
2906 | static char *texts[] = {"No Lock", "Lock", "Sync" }; | |
2907 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2908 | uinfo->count = 1; | |
2909 | uinfo->value.enumerated.items = 3; | |
2910 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2911 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2912 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2913 | return 0; | |
2914 | } | |
2915 | ||
55e957d8 | 2916 | static int hdsp_wc_sync_check(struct hdsp *hdsp) |
1da177e4 LT |
2917 | { |
2918 | int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
2919 | if (status2 & HDSP_wc_lock) { | |
b0b98119 | 2920 | if (status2 & HDSP_wc_sync) |
1da177e4 | 2921 | return 2; |
b0b98119 | 2922 | else |
1da177e4 | 2923 | return 1; |
b0b98119 | 2924 | } else |
1da177e4 | 2925 | return 0; |
1da177e4 LT |
2926 | return 0; |
2927 | } | |
2928 | ||
55e957d8 | 2929 | static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2930 | { |
55e957d8 | 2931 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2932 | |
2933 | ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); | |
2934 | return 0; | |
2935 | } | |
2936 | ||
2937 | #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 2938 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2939 | .name = xname, \ |
2940 | .index = xindex, \ | |
2941 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2942 | .info = snd_hdsp_info_sync_check, \ | |
2943 | .get = snd_hdsp_get_spdif_sync_check \ | |
2944 | } | |
2945 | ||
55e957d8 | 2946 | static int hdsp_spdif_sync_check(struct hdsp *hdsp) |
1da177e4 LT |
2947 | { |
2948 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
b0b98119 | 2949 | if (status & HDSP_SPDIFErrorFlag) |
1da177e4 | 2950 | return 0; |
b0b98119 TI |
2951 | else { |
2952 | if (status & HDSP_SPDIFSync) | |
1da177e4 | 2953 | return 2; |
b0b98119 | 2954 | else |
1da177e4 | 2955 | return 1; |
1da177e4 LT |
2956 | } |
2957 | return 0; | |
2958 | } | |
2959 | ||
55e957d8 | 2960 | static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2961 | { |
55e957d8 | 2962 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2963 | |
2964 | ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); | |
2965 | return 0; | |
2966 | } | |
2967 | ||
2968 | #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 2969 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2970 | .name = xname, \ |
2971 | .index = xindex, \ | |
2972 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2973 | .info = snd_hdsp_info_sync_check, \ | |
2974 | .get = snd_hdsp_get_adatsync_sync_check \ | |
2975 | } | |
2976 | ||
55e957d8 | 2977 | static int hdsp_adatsync_sync_check(struct hdsp *hdsp) |
1da177e4 LT |
2978 | { |
2979 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
2980 | if (status & HDSP_TimecodeLock) { | |
b0b98119 | 2981 | if (status & HDSP_TimecodeSync) |
1da177e4 | 2982 | return 2; |
b0b98119 | 2983 | else |
1da177e4 | 2984 | return 1; |
b0b98119 | 2985 | } else |
1da177e4 | 2986 | return 0; |
1da177e4 LT |
2987 | } |
2988 | ||
55e957d8 | 2989 | static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2990 | { |
55e957d8 | 2991 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2992 | |
2993 | ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); | |
2994 | return 0; | |
2995 | } | |
2996 | ||
2997 | #define HDSP_ADAT_SYNC_CHECK \ | |
67ed4161 | 2998 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
1da177e4 LT |
2999 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ |
3000 | .info = snd_hdsp_info_sync_check, \ | |
3001 | .get = snd_hdsp_get_adat_sync_check \ | |
3002 | } | |
3003 | ||
55e957d8 | 3004 | static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) |
1da177e4 LT |
3005 | { |
3006 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
3007 | ||
3008 | if (status & (HDSP_Lock0>>idx)) { | |
b0b98119 | 3009 | if (status & (HDSP_Sync0>>idx)) |
1da177e4 | 3010 | return 2; |
b0b98119 | 3011 | else |
1da177e4 | 3012 | return 1; |
b0b98119 | 3013 | } else |
1da177e4 | 3014 | return 0; |
1da177e4 LT |
3015 | } |
3016 | ||
55e957d8 | 3017 | static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 LT |
3018 | { |
3019 | int offset; | |
55e957d8 | 3020 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
3021 | |
3022 | offset = ucontrol->id.index - 1; | |
3023 | snd_assert(offset >= 0); | |
3024 | ||
3025 | switch (hdsp->io_type) { | |
3026 | case Digiface: | |
3027 | case H9652: | |
3028 | if (offset >= 3) | |
3029 | return -EINVAL; | |
3030 | break; | |
3031 | case Multiface: | |
3032 | case H9632: | |
3033 | if (offset >= 1) | |
3034 | return -EINVAL; | |
3035 | break; | |
3036 | default: | |
3037 | return -EIO; | |
3038 | } | |
3039 | ||
3040 | ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); | |
3041 | return 0; | |
3042 | } | |
3043 | ||
e4b6088c JC |
3044 | #define HDSP_DDS_OFFSET(xname, xindex) \ |
3045 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3046 | .name = xname, \ | |
3047 | .index = xindex, \ | |
3048 | .info = snd_hdsp_info_dds_offset, \ | |
3049 | .get = snd_hdsp_get_dds_offset, \ | |
3050 | .put = snd_hdsp_put_dds_offset \ | |
3051 | } | |
3052 | ||
3053 | static int hdsp_dds_offset(struct hdsp *hdsp) | |
3054 | { | |
3055 | u64 n; | |
3056 | u32 r; | |
3057 | unsigned int dds_value = hdsp->dds_value; | |
3058 | int system_sample_rate = hdsp->system_sample_rate; | |
3059 | ||
2a3988f6 TI |
3060 | if (!dds_value) |
3061 | return 0; | |
3062 | ||
e4b6088c JC |
3063 | n = DDS_NUMERATOR; |
3064 | /* | |
3065 | * dds_value = n / rate | |
3066 | * rate = n / dds_value | |
3067 | */ | |
3068 | div64_32(&n, dds_value, &r); | |
3069 | if (system_sample_rate >= 112000) | |
3070 | n *= 4; | |
3071 | else if (system_sample_rate >= 56000) | |
3072 | n *= 2; | |
3073 | return ((int)n) - system_sample_rate; | |
3074 | } | |
3075 | ||
3076 | static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) | |
3077 | { | |
3078 | int rate = hdsp->system_sample_rate + offset_hz; | |
3079 | hdsp_set_dds_value(hdsp, rate); | |
3080 | return 0; | |
3081 | } | |
3082 | ||
3083 | static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) | |
3084 | { | |
3085 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3086 | uinfo->count = 1; | |
3087 | uinfo->value.integer.min = -5000; | |
3088 | uinfo->value.integer.max = 5000; | |
3089 | return 0; | |
3090 | } | |
3091 | ||
3092 | static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3093 | { | |
3094 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3095 | ||
3096 | ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp); | |
3097 | return 0; | |
3098 | } | |
3099 | ||
3100 | static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) | |
3101 | { | |
3102 | struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); | |
3103 | int change; | |
3104 | int val; | |
3105 | ||
3106 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
3107 | return -EBUSY; | |
3108 | val = ucontrol->value.enumerated.item[0]; | |
3109 | spin_lock_irq(&hdsp->lock); | |
3110 | if (val != hdsp_dds_offset(hdsp)) | |
3111 | change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; | |
3112 | else | |
3113 | change = 0; | |
3114 | spin_unlock_irq(&hdsp->lock); | |
3115 | return change; | |
3116 | } | |
3117 | ||
55e957d8 | 3118 | static struct snd_kcontrol_new snd_hdsp_9632_controls[] = { |
1da177e4 LT |
3119 | HDSP_DA_GAIN("DA Gain", 0), |
3120 | HDSP_AD_GAIN("AD Gain", 0), | |
3121 | HDSP_PHONE_GAIN("Phones Gain", 0), | |
e4b6088c JC |
3122 | HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0), |
3123 | HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) | |
1da177e4 LT |
3124 | }; |
3125 | ||
55e957d8 | 3126 | static struct snd_kcontrol_new snd_hdsp_controls[] = { |
1da177e4 | 3127 | { |
5549d549 | 3128 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3129 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), |
3130 | .info = snd_hdsp_control_spdif_info, | |
3131 | .get = snd_hdsp_control_spdif_get, | |
3132 | .put = snd_hdsp_control_spdif_put, | |
3133 | }, | |
3134 | { | |
3135 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
5549d549 | 3136 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3137 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), |
3138 | .info = snd_hdsp_control_spdif_stream_info, | |
3139 | .get = snd_hdsp_control_spdif_stream_get, | |
3140 | .put = snd_hdsp_control_spdif_stream_put, | |
3141 | }, | |
3142 | { | |
3143 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
5549d549 | 3144 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3145 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), |
3146 | .info = snd_hdsp_control_spdif_mask_info, | |
3147 | .get = snd_hdsp_control_spdif_mask_get, | |
3148 | .private_value = IEC958_AES0_NONAUDIO | | |
3149 | IEC958_AES0_PROFESSIONAL | | |
3150 | IEC958_AES0_CON_EMPHASIS, | |
3151 | }, | |
3152 | { | |
3153 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
5549d549 | 3154 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
3155 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), |
3156 | .info = snd_hdsp_control_spdif_mask_info, | |
3157 | .get = snd_hdsp_control_spdif_mask_get, | |
3158 | .private_value = IEC958_AES0_NONAUDIO | | |
3159 | IEC958_AES0_PROFESSIONAL | | |
3160 | IEC958_AES0_PRO_EMPHASIS, | |
3161 | }, | |
3162 | HDSP_MIXER("Mixer", 0), | |
3163 | HDSP_SPDIF_IN("IEC958 Input Connector", 0), | |
3164 | HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), | |
3165 | HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), | |
3166 | HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), | |
3167 | HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), | |
3168 | /* 'Sample Clock Source' complies with the alsa control naming scheme */ | |
3169 | HDSP_CLOCK_SOURCE("Sample Clock Source", 0), | |
e3ea4d89 | 3170 | { |
e3ea4d89 TI |
3171 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
3172 | .name = "Sample Clock Source Locking", | |
3173 | .info = snd_hdsp_info_clock_source_lock, | |
3174 | .get = snd_hdsp_get_clock_source_lock, | |
3175 | .put = snd_hdsp_put_clock_source_lock, | |
3176 | }, | |
1da177e4 LT |
3177 | HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), |
3178 | HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
3179 | HDSP_AUTOSYNC_REF("AutoSync Reference", 0), | |
3180 | HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), | |
3181 | HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
3182 | /* 'External Rate' complies with the alsa control naming scheme */ | |
3183 | HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
3184 | HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), | |
3185 | HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), | |
3186 | HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), | |
3187 | HDSP_LINE_OUT("Line Out", 0), | |
3188 | HDSP_PRECISE_POINTER("Precise Pointer", 0), | |
3189 | HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0), | |
3190 | }; | |
3191 | ||
55e957d8 TI |
3192 | static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); |
3193 | static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; | |
1da177e4 | 3194 | |
55e957d8 | 3195 | static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 LT |
3196 | { |
3197 | unsigned int idx; | |
3198 | int err; | |
55e957d8 | 3199 | struct snd_kcontrol *kctl; |
1da177e4 LT |
3200 | |
3201 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { | |
b0b98119 | 3202 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) |
1da177e4 | 3203 | return err; |
1da177e4 LT |
3204 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ |
3205 | hdsp->spdif_ctl = kctl; | |
3206 | } | |
3207 | ||
3208 | /* ADAT SyncCheck status */ | |
3209 | snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; | |
3210 | snd_hdsp_adat_sync_check.index = 1; | |
b0b98119 | 3211 | if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) |
1da177e4 | 3212 | return err; |
1da177e4 LT |
3213 | if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { |
3214 | for (idx = 1; idx < 3; ++idx) { | |
3215 | snd_hdsp_adat_sync_check.index = idx+1; | |
b0b98119 | 3216 | if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) |
1da177e4 | 3217 | return err; |
1da177e4 LT |
3218 | } |
3219 | } | |
3220 | ||
3221 | /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ | |
3222 | if (hdsp->io_type == H9632) { | |
3223 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { | |
b0b98119 | 3224 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) |
1da177e4 | 3225 | return err; |
1da177e4 LT |
3226 | } |
3227 | } | |
3228 | ||
3229 | /* AEB control for H96xx card */ | |
3230 | if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { | |
b0b98119 | 3231 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) |
1da177e4 | 3232 | return err; |
1da177e4 LT |
3233 | } |
3234 | ||
3235 | return 0; | |
3236 | } | |
3237 | ||
3238 | /*------------------------------------------------------------ | |
3239 | /proc interface | |
3240 | ------------------------------------------------------------*/ | |
3241 | ||
3242 | static void | |
55e957d8 | 3243 | snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) |
1da177e4 | 3244 | { |
55e957d8 | 3245 | struct hdsp *hdsp = (struct hdsp *) entry->private_data; |
1da177e4 LT |
3246 | unsigned int status; |
3247 | unsigned int status2; | |
3248 | char *pref_sync_ref; | |
3249 | char *autosync_ref; | |
3250 | char *system_clock_mode; | |
3251 | char *clock_source; | |
3252 | int x; | |
3253 | ||
ecb594e6 | 3254 | if (hdsp_check_for_iobox (hdsp)) { |
1da177e4 LT |
3255 | snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n"); |
3256 | return; | |
ecb594e6 | 3257 | } |
1da177e4 | 3258 | |
b0b98119 | 3259 | if (hdsp_check_for_firmware(hdsp, 0)) { |
1da177e4 LT |
3260 | if (hdsp->state & HDSP_FirmwareCached) { |
3261 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
3262 | snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n"); | |
3263 | return; | |
3264 | } | |
3265 | } else { | |
311e70a4 TI |
3266 | int err = -EINVAL; |
3267 | #ifdef HDSP_FW_LOADER | |
3268 | err = hdsp_request_fw_loader(hdsp); | |
3269 | #endif | |
3270 | if (err < 0) { | |
3271 | snd_iprintf(buffer, | |
3272 | "No firmware loaded nor cached, " | |
3273 | "please upload firmware.\n"); | |
3274 | return; | |
3275 | } | |
1da177e4 LT |
3276 | } |
3277 | } | |
3278 | ||
3279 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
3280 | status2 = hdsp_read(hdsp, HDSP_status2Register); | |
3281 | ||
3282 | snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1); | |
3283 | snd_iprintf(buffer, "Buffers: capture %p playback %p\n", | |
3284 | hdsp->capture_buffer, hdsp->playback_buffer); | |
3285 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
3286 | hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); | |
3287 | snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); | |
3288 | snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register); | |
3289 | snd_iprintf(buffer, "Status register: 0x%x\n", status); | |
3290 | snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); | |
3291 | snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); | |
3292 | snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); | |
3293 | snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); | |
3294 | snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); | |
3295 | snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); | |
3296 | snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off"); | |
3297 | ||
3298 | snd_iprintf(buffer, "\n"); | |
3299 | ||
3300 | x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); | |
3301 | ||
3302 | snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); | |
3303 | snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); | |
3304 | snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); | |
3305 | snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); | |
3306 | ||
3307 | snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); | |
3308 | ||
3309 | snd_iprintf(buffer, "\n"); | |
3310 | ||
3311 | ||
3312 | switch (hdsp_clock_source(hdsp)) { | |
3313 | case HDSP_CLOCK_SOURCE_AUTOSYNC: | |
3314 | clock_source = "AutoSync"; | |
3315 | break; | |
3316 | case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: | |
3317 | clock_source = "Internal 32 kHz"; | |
3318 | break; | |
3319 | case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
3320 | clock_source = "Internal 44.1 kHz"; | |
3321 | break; | |
3322 | case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: | |
3323 | clock_source = "Internal 48 kHz"; | |
3324 | break; | |
3325 | case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: | |
3326 | clock_source = "Internal 64 kHz"; | |
3327 | break; | |
3328 | case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
3329 | clock_source = "Internal 88.2 kHz"; | |
3330 | break; | |
3331 | case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: | |
3332 | clock_source = "Internal 96 kHz"; | |
3333 | break; | |
3334 | case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: | |
3335 | clock_source = "Internal 128 kHz"; | |
3336 | break; | |
3337 | case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
3338 | clock_source = "Internal 176.4 kHz"; | |
3339 | break; | |
3340 | case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: | |
3341 | clock_source = "Internal 192 kHz"; | |
3342 | break; | |
3343 | default: | |
3344 | clock_source = "Error"; | |
3345 | } | |
3346 | snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); | |
3347 | ||
b0b98119 | 3348 | if (hdsp_system_clock_mode(hdsp)) |
1da177e4 | 3349 | system_clock_mode = "Slave"; |
b0b98119 | 3350 | else |
1da177e4 | 3351 | system_clock_mode = "Master"; |
1da177e4 LT |
3352 | |
3353 | switch (hdsp_pref_sync_ref (hdsp)) { | |
3354 | case HDSP_SYNC_FROM_WORD: | |
3355 | pref_sync_ref = "Word Clock"; | |
3356 | break; | |
3357 | case HDSP_SYNC_FROM_ADAT_SYNC: | |
3358 | pref_sync_ref = "ADAT Sync"; | |
3359 | break; | |
3360 | case HDSP_SYNC_FROM_SPDIF: | |
3361 | pref_sync_ref = "SPDIF"; | |
3362 | break; | |
3363 | case HDSP_SYNC_FROM_ADAT1: | |
3364 | pref_sync_ref = "ADAT1"; | |
3365 | break; | |
3366 | case HDSP_SYNC_FROM_ADAT2: | |
3367 | pref_sync_ref = "ADAT2"; | |
3368 | break; | |
3369 | case HDSP_SYNC_FROM_ADAT3: | |
3370 | pref_sync_ref = "ADAT3"; | |
3371 | break; | |
3372 | default: | |
3373 | pref_sync_ref = "Word Clock"; | |
3374 | break; | |
3375 | } | |
3376 | snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); | |
3377 | ||
3378 | switch (hdsp_autosync_ref (hdsp)) { | |
3379 | case HDSP_AUTOSYNC_FROM_WORD: | |
3380 | autosync_ref = "Word Clock"; | |
3381 | break; | |
3382 | case HDSP_AUTOSYNC_FROM_ADAT_SYNC: | |
3383 | autosync_ref = "ADAT Sync"; | |
3384 | break; | |
3385 | case HDSP_AUTOSYNC_FROM_SPDIF: | |
3386 | autosync_ref = "SPDIF"; | |
3387 | break; | |
3388 | case HDSP_AUTOSYNC_FROM_NONE: | |
3389 | autosync_ref = "None"; | |
3390 | break; | |
3391 | case HDSP_AUTOSYNC_FROM_ADAT1: | |
3392 | autosync_ref = "ADAT1"; | |
3393 | break; | |
3394 | case HDSP_AUTOSYNC_FROM_ADAT2: | |
3395 | autosync_ref = "ADAT2"; | |
3396 | break; | |
3397 | case HDSP_AUTOSYNC_FROM_ADAT3: | |
3398 | autosync_ref = "ADAT3"; | |
3399 | break; | |
3400 | default: | |
3401 | autosync_ref = "---"; | |
3402 | break; | |
3403 | } | |
3404 | snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); | |
3405 | ||
3406 | snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); | |
3407 | ||
3408 | snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); | |
3409 | ||
3410 | snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); | |
e3ea4d89 | 3411 | snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); |
1da177e4 LT |
3412 | |
3413 | snd_iprintf(buffer, "\n"); | |
3414 | ||
3415 | switch (hdsp_spdif_in(hdsp)) { | |
3416 | case HDSP_SPDIFIN_OPTICAL: | |
3417 | snd_iprintf(buffer, "IEC958 input: Optical\n"); | |
3418 | break; | |
3419 | case HDSP_SPDIFIN_COAXIAL: | |
3420 | snd_iprintf(buffer, "IEC958 input: Coaxial\n"); | |
3421 | break; | |
3422 | case HDSP_SPDIFIN_INTERNAL: | |
3423 | snd_iprintf(buffer, "IEC958 input: Internal\n"); | |
3424 | break; | |
3425 | case HDSP_SPDIFIN_AES: | |
3426 | snd_iprintf(buffer, "IEC958 input: AES\n"); | |
3427 | break; | |
3428 | default: | |
3429 | snd_iprintf(buffer, "IEC958 input: ???\n"); | |
3430 | break; | |
3431 | } | |
3432 | ||
b0b98119 | 3433 | if (hdsp->control_register & HDSP_SPDIFOpticalOut) |
1da177e4 | 3434 | snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); |
b0b98119 | 3435 | else |
1da177e4 | 3436 | snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); |
1da177e4 | 3437 | |
b0b98119 | 3438 | if (hdsp->control_register & HDSP_SPDIFProfessional) |
1da177e4 | 3439 | snd_iprintf(buffer, "IEC958 quality: Professional\n"); |
b0b98119 | 3440 | else |
1da177e4 | 3441 | snd_iprintf(buffer, "IEC958 quality: Consumer\n"); |
1da177e4 | 3442 | |
b0b98119 | 3443 | if (hdsp->control_register & HDSP_SPDIFEmphasis) |
1da177e4 | 3444 | snd_iprintf(buffer, "IEC958 emphasis: on\n"); |
b0b98119 | 3445 | else |
1da177e4 | 3446 | snd_iprintf(buffer, "IEC958 emphasis: off\n"); |
1da177e4 | 3447 | |
b0b98119 | 3448 | if (hdsp->control_register & HDSP_SPDIFNonAudio) |
1da177e4 | 3449 | snd_iprintf(buffer, "IEC958 NonAudio: on\n"); |
b0b98119 | 3450 | else |
1da177e4 | 3451 | snd_iprintf(buffer, "IEC958 NonAudio: off\n"); |
b0b98119 | 3452 | if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) |
1da177e4 | 3453 | snd_iprintf (buffer, "IEC958 sample rate: %d\n", x); |
b0b98119 | 3454 | else |
1da177e4 | 3455 | snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n"); |
1da177e4 LT |
3456 | |
3457 | snd_iprintf(buffer, "\n"); | |
3458 | ||
3459 | /* Sync Check */ | |
3460 | x = status & HDSP_Sync0; | |
b0b98119 | 3461 | if (status & HDSP_Lock0) |
1da177e4 | 3462 | snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 3463 | else |
1da177e4 | 3464 | snd_iprintf(buffer, "ADAT1: No Lock\n"); |
1da177e4 LT |
3465 | |
3466 | switch (hdsp->io_type) { | |
3467 | case Digiface: | |
3468 | case H9652: | |
3469 | x = status & HDSP_Sync1; | |
b0b98119 | 3470 | if (status & HDSP_Lock1) |
1da177e4 | 3471 | snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 3472 | else |
1da177e4 | 3473 | snd_iprintf(buffer, "ADAT2: No Lock\n"); |
1da177e4 | 3474 | x = status & HDSP_Sync2; |
b0b98119 | 3475 | if (status & HDSP_Lock2) |
1da177e4 | 3476 | snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 3477 | else |
1da177e4 | 3478 | snd_iprintf(buffer, "ADAT3: No Lock\n"); |
b0b98119 | 3479 | break; |
1da177e4 LT |
3480 | default: |
3481 | /* relax */ | |
3482 | break; | |
3483 | } | |
3484 | ||
3485 | x = status & HDSP_SPDIFSync; | |
b0b98119 | 3486 | if (status & HDSP_SPDIFErrorFlag) |
1da177e4 | 3487 | snd_iprintf (buffer, "SPDIF: No Lock\n"); |
b0b98119 | 3488 | else |
1da177e4 | 3489 | snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); |
1da177e4 LT |
3490 | |
3491 | x = status2 & HDSP_wc_sync; | |
b0b98119 | 3492 | if (status2 & HDSP_wc_lock) |
1da177e4 | 3493 | snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 3494 | else |
1da177e4 | 3495 | snd_iprintf (buffer, "Word Clock: No Lock\n"); |
1da177e4 LT |
3496 | |
3497 | x = status & HDSP_TimecodeSync; | |
b0b98119 | 3498 | if (status & HDSP_TimecodeLock) |
1da177e4 | 3499 | snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); |
b0b98119 | 3500 | else |
1da177e4 | 3501 | snd_iprintf(buffer, "ADAT Sync: No Lock\n"); |
1da177e4 LT |
3502 | |
3503 | snd_iprintf(buffer, "\n"); | |
3504 | ||
3505 | /* Informations about H9632 specific controls */ | |
3506 | if (hdsp->io_type == H9632) { | |
3507 | char *tmp; | |
3508 | ||
3509 | switch (hdsp_ad_gain(hdsp)) { | |
3510 | case 0: | |
3511 | tmp = "-10 dBV"; | |
3512 | break; | |
3513 | case 1: | |
3514 | tmp = "+4 dBu"; | |
3515 | break; | |
3516 | default: | |
3517 | tmp = "Lo Gain"; | |
3518 | break; | |
3519 | } | |
3520 | snd_iprintf(buffer, "AD Gain : %s\n", tmp); | |
3521 | ||
3522 | switch (hdsp_da_gain(hdsp)) { | |
3523 | case 0: | |
3524 | tmp = "Hi Gain"; | |
3525 | break; | |
3526 | case 1: | |
3527 | tmp = "+4 dBu"; | |
3528 | break; | |
3529 | default: | |
3530 | tmp = "-10 dBV"; | |
3531 | break; | |
3532 | } | |
3533 | snd_iprintf(buffer, "DA Gain : %s\n", tmp); | |
3534 | ||
3535 | switch (hdsp_phone_gain(hdsp)) { | |
3536 | case 0: | |
3537 | tmp = "0 dB"; | |
3538 | break; | |
3539 | case 1: | |
3540 | tmp = "-6 dB"; | |
3541 | break; | |
3542 | default: | |
3543 | tmp = "-12 dB"; | |
3544 | break; | |
3545 | } | |
3546 | snd_iprintf(buffer, "Phones Gain : %s\n", tmp); | |
3547 | ||
3548 | snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); | |
3549 | ||
b0b98119 | 3550 | if (hdsp->control_register & HDSP_AnalogExtensionBoard) |
1da177e4 | 3551 | snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); |
b0b98119 | 3552 | else |
1da177e4 | 3553 | snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); |
1da177e4 LT |
3554 | snd_iprintf(buffer, "\n"); |
3555 | } | |
3556 | ||
3557 | } | |
3558 | ||
55e957d8 | 3559 | static void __devinit snd_hdsp_proc_init(struct hdsp *hdsp) |
1da177e4 | 3560 | { |
55e957d8 | 3561 | struct snd_info_entry *entry; |
1da177e4 LT |
3562 | |
3563 | if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) | |
bf850204 | 3564 | snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read); |
1da177e4 LT |
3565 | } |
3566 | ||
55e957d8 | 3567 | static void snd_hdsp_free_buffers(struct hdsp *hdsp) |
1da177e4 LT |
3568 | { |
3569 | snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); | |
3570 | snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); | |
3571 | } | |
3572 | ||
55e957d8 | 3573 | static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp) |
1da177e4 LT |
3574 | { |
3575 | unsigned long pb_bus, cb_bus; | |
3576 | ||
3577 | if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || | |
3578 | snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { | |
3579 | if (hdsp->capture_dma_buf.area) | |
3580 | snd_dma_free_pages(&hdsp->capture_dma_buf); | |
3581 | printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name); | |
3582 | return -ENOMEM; | |
3583 | } | |
3584 | ||
3585 | /* Align to bus-space 64K boundary */ | |
3586 | ||
7ab39926 CL |
3587 | cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul); |
3588 | pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul); | |
1da177e4 LT |
3589 | |
3590 | /* Tell the card where it is */ | |
3591 | ||
3592 | hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); | |
3593 | hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); | |
3594 | ||
3595 | hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); | |
3596 | hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); | |
3597 | ||
3598 | return 0; | |
3599 | } | |
3600 | ||
55e957d8 | 3601 | static int snd_hdsp_set_defaults(struct hdsp *hdsp) |
1da177e4 LT |
3602 | { |
3603 | unsigned int i; | |
3604 | ||
3605 | /* ASSUMPTION: hdsp->lock is either held, or | |
3606 | there is no need to hold it (e.g. during module | |
3607 | initalization). | |
3608 | */ | |
3609 | ||
3610 | /* set defaults: | |
3611 | ||
3612 | SPDIF Input via Coax | |
3613 | Master clock mode | |
3614 | maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, | |
3615 | which implies 2 4096 sample, 32Kbyte periods). | |
3616 | Enable line out. | |
3617 | */ | |
3618 | ||
3619 | hdsp->control_register = HDSP_ClockModeMaster | | |
3620 | HDSP_SPDIFInputCoaxial | | |
3621 | hdsp_encode_latency(7) | | |
3622 | HDSP_LineOut; | |
3623 | ||
3624 | ||
3625 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3626 | ||
3627 | #ifdef SNDRV_BIG_ENDIAN | |
3628 | hdsp->control2_register = HDSP_BIGENDIAN_MODE; | |
3629 | #else | |
3630 | hdsp->control2_register = 0; | |
3631 | #endif | |
b0b98119 | 3632 | if (hdsp->io_type == H9652) |
1da177e4 | 3633 | snd_hdsp_9652_enable_mixer (hdsp); |
b0b98119 TI |
3634 | else |
3635 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
1da177e4 LT |
3636 | |
3637 | hdsp_reset_hw_pointer(hdsp); | |
3638 | hdsp_compute_period_size(hdsp); | |
3639 | ||
3640 | /* silence everything */ | |
3641 | ||
b0b98119 | 3642 | for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) |
1da177e4 | 3643 | hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; |
1da177e4 LT |
3644 | |
3645 | for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { | |
b0b98119 | 3646 | if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) |
1da177e4 | 3647 | return -EIO; |
1da177e4 LT |
3648 | } |
3649 | ||
3650 | /* H9632 specific defaults */ | |
3651 | if (hdsp->io_type == H9632) { | |
3652 | hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); | |
3653 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3654 | } | |
3655 | ||
3656 | /* set a default rate so that the channel map is set up. | |
3657 | */ | |
3658 | ||
3659 | hdsp_set_rate(hdsp, 48000, 1); | |
3660 | ||
3661 | return 0; | |
3662 | } | |
3663 | ||
3664 | static void hdsp_midi_tasklet(unsigned long arg) | |
3665 | { | |
55e957d8 | 3666 | struct hdsp *hdsp = (struct hdsp *)arg; |
1da177e4 | 3667 | |
b0b98119 | 3668 | if (hdsp->midi[0].pending) |
1da177e4 | 3669 | snd_hdsp_midi_input_read (&hdsp->midi[0]); |
b0b98119 | 3670 | if (hdsp->midi[1].pending) |
1da177e4 | 3671 | snd_hdsp_midi_input_read (&hdsp->midi[1]); |
1da177e4 LT |
3672 | } |
3673 | ||
7d12e780 | 3674 | static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) |
1da177e4 | 3675 | { |
55e957d8 | 3676 | struct hdsp *hdsp = (struct hdsp *) dev_id; |
1da177e4 LT |
3677 | unsigned int status; |
3678 | int audio; | |
3679 | int midi0; | |
3680 | int midi1; | |
3681 | unsigned int midi0status; | |
3682 | unsigned int midi1status; | |
3683 | int schedule = 0; | |
3684 | ||
3685 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
3686 | ||
3687 | audio = status & HDSP_audioIRQPending; | |
3688 | midi0 = status & HDSP_midi0IRQPending; | |
3689 | midi1 = status & HDSP_midi1IRQPending; | |
3690 | ||
b0b98119 | 3691 | if (!audio && !midi0 && !midi1) |
1da177e4 | 3692 | return IRQ_NONE; |
1da177e4 LT |
3693 | |
3694 | hdsp_write(hdsp, HDSP_interruptConfirmation, 0); | |
3695 | ||
3696 | midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; | |
3697 | midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; | |
3698 | ||
3699 | if (audio) { | |
b0b98119 | 3700 | if (hdsp->capture_substream) |
1da177e4 | 3701 | snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); |
1da177e4 | 3702 | |
b0b98119 | 3703 | if (hdsp->playback_substream) |
1da177e4 | 3704 | snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); |
1da177e4 LT |
3705 | } |
3706 | ||
3707 | if (midi0 && midi0status) { | |
3708 | if (hdsp->use_midi_tasklet) { | |
3709 | /* we disable interrupts for this input until processing is done */ | |
3710 | hdsp->control_register &= ~HDSP_Midi0InterruptEnable; | |
3711 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3712 | hdsp->midi[0].pending = 1; | |
3713 | schedule = 1; | |
3714 | } else { | |
3715 | snd_hdsp_midi_input_read (&hdsp->midi[0]); | |
3716 | } | |
3717 | } | |
3718 | if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) { | |
3719 | if (hdsp->use_midi_tasklet) { | |
3720 | /* we disable interrupts for this input until processing is done */ | |
3721 | hdsp->control_register &= ~HDSP_Midi1InterruptEnable; | |
3722 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3723 | hdsp->midi[1].pending = 1; | |
3724 | schedule = 1; | |
3725 | } else { | |
3726 | snd_hdsp_midi_input_read (&hdsp->midi[1]); | |
3727 | } | |
3728 | } | |
3729 | if (hdsp->use_midi_tasklet && schedule) | |
3730 | tasklet_hi_schedule(&hdsp->midi_tasklet); | |
3731 | return IRQ_HANDLED; | |
3732 | } | |
3733 | ||
55e957d8 | 3734 | static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 3735 | { |
55e957d8 | 3736 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
3737 | return hdsp_hw_pointer(hdsp); |
3738 | } | |
3739 | ||
55e957d8 | 3740 | static char *hdsp_channel_buffer_location(struct hdsp *hdsp, |
1da177e4 LT |
3741 | int stream, |
3742 | int channel) | |
3743 | ||
3744 | { | |
3745 | int mapped_channel; | |
3746 | ||
3747 | snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL); | |
3748 | ||
b0b98119 | 3749 | if ((mapped_channel = hdsp->channel_map[channel]) < 0) |
1da177e4 | 3750 | return NULL; |
1da177e4 | 3751 | |
b0b98119 | 3752 | if (stream == SNDRV_PCM_STREAM_CAPTURE) |
1da177e4 | 3753 | return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); |
b0b98119 | 3754 | else |
1da177e4 | 3755 | return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); |
1da177e4 LT |
3756 | } |
3757 | ||
55e957d8 | 3758 | static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel, |
1da177e4 LT |
3759 | snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) |
3760 | { | |
55e957d8 | 3761 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
3762 | char *channel_buf; |
3763 | ||
3764 | snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); | |
3765 | ||
3766 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
3767 | snd_assert(channel_buf != NULL, return -EIO); | |
3768 | if (copy_from_user(channel_buf + pos * 4, src, count * 4)) | |
3769 | return -EFAULT; | |
3770 | return count; | |
3771 | } | |
3772 | ||
55e957d8 | 3773 | static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel, |
1da177e4 LT |
3774 | snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) |
3775 | { | |
55e957d8 | 3776 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
3777 | char *channel_buf; |
3778 | ||
3779 | snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); | |
3780 | ||
3781 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
3782 | snd_assert(channel_buf != NULL, return -EIO); | |
3783 | if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) | |
3784 | return -EFAULT; | |
3785 | return count; | |
3786 | } | |
3787 | ||
55e957d8 | 3788 | static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel, |
1da177e4 LT |
3789 | snd_pcm_uframes_t pos, snd_pcm_uframes_t count) |
3790 | { | |
55e957d8 | 3791 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
3792 | char *channel_buf; |
3793 | ||
3794 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
3795 | snd_assert(channel_buf != NULL, return -EIO); | |
3796 | memset(channel_buf + pos * 4, 0, count * 4); | |
3797 | return count; | |
3798 | } | |
3799 | ||
55e957d8 | 3800 | static int snd_hdsp_reset(struct snd_pcm_substream *substream) |
1da177e4 | 3801 | { |
55e957d8 TI |
3802 | struct snd_pcm_runtime *runtime = substream->runtime; |
3803 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); | |
3804 | struct snd_pcm_substream *other; | |
1da177e4 LT |
3805 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
3806 | other = hdsp->capture_substream; | |
3807 | else | |
3808 | other = hdsp->playback_substream; | |
3809 | if (hdsp->running) | |
3810 | runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); | |
3811 | else | |
3812 | runtime->status->hw_ptr = 0; | |
3813 | if (other) { | |
55e957d8 TI |
3814 | struct snd_pcm_substream *s; |
3815 | struct snd_pcm_runtime *oruntime = other->runtime; | |
ef991b95 | 3816 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
3817 | if (s == other) { |
3818 | oruntime->status->hw_ptr = runtime->status->hw_ptr; | |
3819 | break; | |
3820 | } | |
3821 | } | |
3822 | } | |
3823 | return 0; | |
3824 | } | |
3825 | ||
55e957d8 TI |
3826 | static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, |
3827 | struct snd_pcm_hw_params *params) | |
1da177e4 | 3828 | { |
55e957d8 | 3829 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
3830 | int err; |
3831 | pid_t this_pid; | |
3832 | pid_t other_pid; | |
3833 | ||
b0b98119 | 3834 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 3835 | return -EIO; |
1da177e4 | 3836 | |
b0b98119 | 3837 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 3838 | return -EIO; |
1da177e4 LT |
3839 | |
3840 | spin_lock_irq(&hdsp->lock); | |
3841 | ||
3842 | if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
3843 | hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); | |
3844 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); | |
3845 | this_pid = hdsp->playback_pid; | |
3846 | other_pid = hdsp->capture_pid; | |
3847 | } else { | |
3848 | this_pid = hdsp->capture_pid; | |
3849 | other_pid = hdsp->playback_pid; | |
3850 | } | |
3851 | ||
3852 | if ((other_pid > 0) && (this_pid != other_pid)) { | |
3853 | ||
3854 | /* The other stream is open, and not by the same | |
3855 | task as this one. Make sure that the parameters | |
3856 | that matter are the same. | |
3857 | */ | |
3858 | ||
3859 | if (params_rate(params) != hdsp->system_sample_rate) { | |
3860 | spin_unlock_irq(&hdsp->lock); | |
3861 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); | |
3862 | return -EBUSY; | |
3863 | } | |
3864 | ||
3865 | if (params_period_size(params) != hdsp->period_bytes / 4) { | |
3866 | spin_unlock_irq(&hdsp->lock); | |
3867 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
3868 | return -EBUSY; | |
3869 | } | |
3870 | ||
3871 | /* We're fine. */ | |
3872 | ||
3873 | spin_unlock_irq(&hdsp->lock); | |
3874 | return 0; | |
3875 | ||
3876 | } else { | |
3877 | spin_unlock_irq(&hdsp->lock); | |
3878 | } | |
3879 | ||
3880 | /* how to make sure that the rate matches an externally-set one ? | |
3881 | */ | |
3882 | ||
3883 | spin_lock_irq(&hdsp->lock); | |
e3ea4d89 TI |
3884 | if (! hdsp->clock_source_locked) { |
3885 | if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { | |
3886 | spin_unlock_irq(&hdsp->lock); | |
3887 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); | |
3888 | return err; | |
3889 | } | |
1da177e4 | 3890 | } |
e3ea4d89 | 3891 | spin_unlock_irq(&hdsp->lock); |
1da177e4 LT |
3892 | |
3893 | if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { | |
3894 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
3895 | return err; | |
3896 | } | |
3897 | ||
3898 | return 0; | |
3899 | } | |
3900 | ||
55e957d8 TI |
3901 | static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, |
3902 | struct snd_pcm_channel_info *info) | |
1da177e4 | 3903 | { |
55e957d8 | 3904 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
3905 | int mapped_channel; |
3906 | ||
3907 | snd_assert(info->channel < hdsp->max_channels, return -EINVAL); | |
3908 | ||
b0b98119 | 3909 | if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) |
1da177e4 | 3910 | return -EINVAL; |
1da177e4 LT |
3911 | |
3912 | info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; | |
3913 | info->first = 0; | |
3914 | info->step = 32; | |
3915 | return 0; | |
3916 | } | |
3917 | ||
55e957d8 | 3918 | static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, |
1da177e4 LT |
3919 | unsigned int cmd, void *arg) |
3920 | { | |
3921 | switch (cmd) { | |
3922 | case SNDRV_PCM_IOCTL1_RESET: | |
1da177e4 | 3923 | return snd_hdsp_reset(substream); |
1da177e4 | 3924 | case SNDRV_PCM_IOCTL1_CHANNEL_INFO: |
b0b98119 | 3925 | return snd_hdsp_channel_info(substream, arg); |
1da177e4 LT |
3926 | default: |
3927 | break; | |
3928 | } | |
3929 | ||
3930 | return snd_pcm_lib_ioctl(substream, cmd, arg); | |
3931 | } | |
3932 | ||
55e957d8 | 3933 | static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 3934 | { |
55e957d8 TI |
3935 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
3936 | struct snd_pcm_substream *other; | |
1da177e4 LT |
3937 | int running; |
3938 | ||
b0b98119 | 3939 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 3940 | return -EIO; |
1da177e4 | 3941 | |
311e70a4 | 3942 | if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ |
1da177e4 | 3943 | return -EIO; |
1da177e4 LT |
3944 | |
3945 | spin_lock(&hdsp->lock); | |
3946 | running = hdsp->running; | |
3947 | switch (cmd) { | |
3948 | case SNDRV_PCM_TRIGGER_START: | |
3949 | running |= 1 << substream->stream; | |
3950 | break; | |
3951 | case SNDRV_PCM_TRIGGER_STOP: | |
3952 | running &= ~(1 << substream->stream); | |
3953 | break; | |
3954 | default: | |
3955 | snd_BUG(); | |
3956 | spin_unlock(&hdsp->lock); | |
3957 | return -EINVAL; | |
3958 | } | |
3959 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3960 | other = hdsp->capture_substream; | |
3961 | else | |
3962 | other = hdsp->playback_substream; | |
3963 | ||
3964 | if (other) { | |
55e957d8 | 3965 | struct snd_pcm_substream *s; |
ef991b95 | 3966 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
3967 | if (s == other) { |
3968 | snd_pcm_trigger_done(s, substream); | |
3969 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
3970 | running |= 1 << s->stream; | |
3971 | else | |
3972 | running &= ~(1 << s->stream); | |
3973 | goto _ok; | |
3974 | } | |
3975 | } | |
3976 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
3977 | if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && | |
3978 | substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
3979 | hdsp_silence_playback(hdsp); | |
3980 | } else { | |
3981 | if (running && | |
3982 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3983 | hdsp_silence_playback(hdsp); | |
3984 | } | |
3985 | } else { | |
3986 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
3987 | hdsp_silence_playback(hdsp); | |
3988 | } | |
3989 | _ok: | |
3990 | snd_pcm_trigger_done(substream, substream); | |
3991 | if (!hdsp->running && running) | |
3992 | hdsp_start_audio(hdsp); | |
3993 | else if (hdsp->running && !running) | |
3994 | hdsp_stop_audio(hdsp); | |
3995 | hdsp->running = running; | |
3996 | spin_unlock(&hdsp->lock); | |
3997 | ||
3998 | return 0; | |
3999 | } | |
4000 | ||
55e957d8 | 4001 | static int snd_hdsp_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 4002 | { |
55e957d8 | 4003 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4004 | int result = 0; |
4005 | ||
b0b98119 | 4006 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4007 | return -EIO; |
1da177e4 | 4008 | |
b0b98119 | 4009 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4010 | return -EIO; |
1da177e4 LT |
4011 | |
4012 | spin_lock_irq(&hdsp->lock); | |
4013 | if (!hdsp->running) | |
4014 | hdsp_reset_hw_pointer(hdsp); | |
4015 | spin_unlock_irq(&hdsp->lock); | |
4016 | return result; | |
4017 | } | |
4018 | ||
55e957d8 | 4019 | static struct snd_pcm_hardware snd_hdsp_playback_subinfo = |
1da177e4 LT |
4020 | { |
4021 | .info = (SNDRV_PCM_INFO_MMAP | | |
4022 | SNDRV_PCM_INFO_MMAP_VALID | | |
4023 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
4024 | SNDRV_PCM_INFO_SYNC_START | | |
4025 | SNDRV_PCM_INFO_DOUBLE), | |
4026 | #ifdef SNDRV_BIG_ENDIAN | |
4027 | .formats = SNDRV_PCM_FMTBIT_S32_BE, | |
4028 | #else | |
4029 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
4030 | #endif | |
4031 | .rates = (SNDRV_PCM_RATE_32000 | | |
4032 | SNDRV_PCM_RATE_44100 | | |
4033 | SNDRV_PCM_RATE_48000 | | |
4034 | SNDRV_PCM_RATE_64000 | | |
4035 | SNDRV_PCM_RATE_88200 | | |
4036 | SNDRV_PCM_RATE_96000), | |
4037 | .rate_min = 32000, | |
4038 | .rate_max = 96000, | |
4039 | .channels_min = 14, | |
4040 | .channels_max = HDSP_MAX_CHANNELS, | |
4041 | .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, | |
4042 | .period_bytes_min = (64 * 4) * 10, | |
4043 | .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, | |
4044 | .periods_min = 2, | |
4045 | .periods_max = 2, | |
4046 | .fifo_size = 0 | |
4047 | }; | |
4048 | ||
55e957d8 | 4049 | static struct snd_pcm_hardware snd_hdsp_capture_subinfo = |
1da177e4 LT |
4050 | { |
4051 | .info = (SNDRV_PCM_INFO_MMAP | | |
4052 | SNDRV_PCM_INFO_MMAP_VALID | | |
4053 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
4054 | SNDRV_PCM_INFO_SYNC_START), | |
4055 | #ifdef SNDRV_BIG_ENDIAN | |
4056 | .formats = SNDRV_PCM_FMTBIT_S32_BE, | |
4057 | #else | |
4058 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
4059 | #endif | |
4060 | .rates = (SNDRV_PCM_RATE_32000 | | |
4061 | SNDRV_PCM_RATE_44100 | | |
4062 | SNDRV_PCM_RATE_48000 | | |
4063 | SNDRV_PCM_RATE_64000 | | |
4064 | SNDRV_PCM_RATE_88200 | | |
4065 | SNDRV_PCM_RATE_96000), | |
4066 | .rate_min = 32000, | |
4067 | .rate_max = 96000, | |
4068 | .channels_min = 14, | |
4069 | .channels_max = HDSP_MAX_CHANNELS, | |
4070 | .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, | |
4071 | .period_bytes_min = (64 * 4) * 10, | |
4072 | .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, | |
4073 | .periods_min = 2, | |
4074 | .periods_max = 2, | |
4075 | .fifo_size = 0 | |
4076 | }; | |
4077 | ||
4078 | static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; | |
4079 | ||
55e957d8 | 4080 | static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { |
1da177e4 LT |
4081 | .count = ARRAY_SIZE(hdsp_period_sizes), |
4082 | .list = hdsp_period_sizes, | |
4083 | .mask = 0 | |
4084 | }; | |
4085 | ||
4086 | static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; | |
4087 | ||
55e957d8 | 4088 | static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = { |
1da177e4 LT |
4089 | .count = ARRAY_SIZE(hdsp_9632_sample_rates), |
4090 | .list = hdsp_9632_sample_rates, | |
4091 | .mask = 0 | |
4092 | }; | |
4093 | ||
55e957d8 TI |
4094 | static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, |
4095 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4096 | { |
55e957d8 TI |
4097 | struct hdsp *hdsp = rule->private; |
4098 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
1da177e4 LT |
4099 | if (hdsp->io_type == H9632) { |
4100 | unsigned int list[3]; | |
4101 | list[0] = hdsp->qs_in_channels; | |
4102 | list[1] = hdsp->ds_in_channels; | |
4103 | list[2] = hdsp->ss_in_channels; | |
4104 | return snd_interval_list(c, 3, list, 0); | |
4105 | } else { | |
4106 | unsigned int list[2]; | |
4107 | list[0] = hdsp->ds_in_channels; | |
4108 | list[1] = hdsp->ss_in_channels; | |
4109 | return snd_interval_list(c, 2, list, 0); | |
4110 | } | |
4111 | } | |
4112 | ||
55e957d8 TI |
4113 | static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, |
4114 | struct snd_pcm_hw_rule *rule) | |
1da177e4 LT |
4115 | { |
4116 | unsigned int list[3]; | |
55e957d8 TI |
4117 | struct hdsp *hdsp = rule->private; |
4118 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
1da177e4 LT |
4119 | if (hdsp->io_type == H9632) { |
4120 | list[0] = hdsp->qs_out_channels; | |
4121 | list[1] = hdsp->ds_out_channels; | |
4122 | list[2] = hdsp->ss_out_channels; | |
4123 | return snd_interval_list(c, 3, list, 0); | |
4124 | } else { | |
4125 | list[0] = hdsp->ds_out_channels; | |
4126 | list[1] = hdsp->ss_out_channels; | |
4127 | } | |
4128 | return snd_interval_list(c, 2, list, 0); | |
4129 | } | |
4130 | ||
55e957d8 TI |
4131 | static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, |
4132 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4133 | { |
55e957d8 TI |
4134 | struct hdsp *hdsp = rule->private; |
4135 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4136 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4137 | if (r->min > 96000 && hdsp->io_type == H9632) { |
55e957d8 | 4138 | struct snd_interval t = { |
1da177e4 LT |
4139 | .min = hdsp->qs_in_channels, |
4140 | .max = hdsp->qs_in_channels, | |
4141 | .integer = 1, | |
4142 | }; | |
4143 | return snd_interval_refine(c, &t); | |
4144 | } else if (r->min > 48000 && r->max <= 96000) { | |
55e957d8 | 4145 | struct snd_interval t = { |
1da177e4 LT |
4146 | .min = hdsp->ds_in_channels, |
4147 | .max = hdsp->ds_in_channels, | |
4148 | .integer = 1, | |
4149 | }; | |
4150 | return snd_interval_refine(c, &t); | |
4151 | } else if (r->max < 64000) { | |
55e957d8 | 4152 | struct snd_interval t = { |
1da177e4 LT |
4153 | .min = hdsp->ss_in_channels, |
4154 | .max = hdsp->ss_in_channels, | |
4155 | .integer = 1, | |
4156 | }; | |
4157 | return snd_interval_refine(c, &t); | |
4158 | } | |
4159 | return 0; | |
4160 | } | |
4161 | ||
55e957d8 TI |
4162 | static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, |
4163 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4164 | { |
55e957d8 TI |
4165 | struct hdsp *hdsp = rule->private; |
4166 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4167 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4168 | if (r->min > 96000 && hdsp->io_type == H9632) { |
55e957d8 | 4169 | struct snd_interval t = { |
1da177e4 LT |
4170 | .min = hdsp->qs_out_channels, |
4171 | .max = hdsp->qs_out_channels, | |
4172 | .integer = 1, | |
4173 | }; | |
4174 | return snd_interval_refine(c, &t); | |
4175 | } else if (r->min > 48000 && r->max <= 96000) { | |
55e957d8 | 4176 | struct snd_interval t = { |
1da177e4 LT |
4177 | .min = hdsp->ds_out_channels, |
4178 | .max = hdsp->ds_out_channels, | |
4179 | .integer = 1, | |
4180 | }; | |
4181 | return snd_interval_refine(c, &t); | |
4182 | } else if (r->max < 64000) { | |
55e957d8 | 4183 | struct snd_interval t = { |
1da177e4 LT |
4184 | .min = hdsp->ss_out_channels, |
4185 | .max = hdsp->ss_out_channels, | |
4186 | .integer = 1, | |
4187 | }; | |
4188 | return snd_interval_refine(c, &t); | |
4189 | } | |
4190 | return 0; | |
4191 | } | |
4192 | ||
55e957d8 TI |
4193 | static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, |
4194 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4195 | { |
55e957d8 TI |
4196 | struct hdsp *hdsp = rule->private; |
4197 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4198 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4199 | if (c->min >= hdsp->ss_out_channels) { |
55e957d8 | 4200 | struct snd_interval t = { |
1da177e4 LT |
4201 | .min = 32000, |
4202 | .max = 48000, | |
4203 | .integer = 1, | |
4204 | }; | |
4205 | return snd_interval_refine(r, &t); | |
4206 | } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { | |
55e957d8 | 4207 | struct snd_interval t = { |
1da177e4 LT |
4208 | .min = 128000, |
4209 | .max = 192000, | |
4210 | .integer = 1, | |
4211 | }; | |
4212 | return snd_interval_refine(r, &t); | |
4213 | } else if (c->max <= hdsp->ds_out_channels) { | |
55e957d8 | 4214 | struct snd_interval t = { |
1da177e4 LT |
4215 | .min = 64000, |
4216 | .max = 96000, | |
4217 | .integer = 1, | |
4218 | }; | |
4219 | return snd_interval_refine(r, &t); | |
4220 | } | |
4221 | return 0; | |
4222 | } | |
4223 | ||
55e957d8 TI |
4224 | static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, |
4225 | struct snd_pcm_hw_rule *rule) | |
1da177e4 | 4226 | { |
55e957d8 TI |
4227 | struct hdsp *hdsp = rule->private; |
4228 | struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4229 | struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1da177e4 | 4230 | if (c->min >= hdsp->ss_in_channels) { |
55e957d8 | 4231 | struct snd_interval t = { |
1da177e4 LT |
4232 | .min = 32000, |
4233 | .max = 48000, | |
4234 | .integer = 1, | |
4235 | }; | |
4236 | return snd_interval_refine(r, &t); | |
4237 | } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { | |
55e957d8 | 4238 | struct snd_interval t = { |
1da177e4 LT |
4239 | .min = 128000, |
4240 | .max = 192000, | |
4241 | .integer = 1, | |
4242 | }; | |
4243 | return snd_interval_refine(r, &t); | |
4244 | } else if (c->max <= hdsp->ds_in_channels) { | |
55e957d8 | 4245 | struct snd_interval t = { |
1da177e4 LT |
4246 | .min = 64000, |
4247 | .max = 96000, | |
4248 | .integer = 1, | |
4249 | }; | |
4250 | return snd_interval_refine(r, &t); | |
4251 | } | |
4252 | return 0; | |
4253 | } | |
4254 | ||
55e957d8 | 4255 | static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 4256 | { |
55e957d8 TI |
4257 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
4258 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 4259 | |
b0b98119 | 4260 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4261 | return -EIO; |
1da177e4 | 4262 | |
b0b98119 | 4263 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4264 | return -EIO; |
1da177e4 LT |
4265 | |
4266 | spin_lock_irq(&hdsp->lock); | |
4267 | ||
4268 | snd_pcm_set_sync(substream); | |
4269 | ||
4270 | runtime->hw = snd_hdsp_playback_subinfo; | |
4271 | runtime->dma_area = hdsp->playback_buffer; | |
4272 | runtime->dma_bytes = HDSP_DMA_AREA_BYTES; | |
4273 | ||
4274 | hdsp->playback_pid = current->pid; | |
4275 | hdsp->playback_substream = substream; | |
4276 | ||
4277 | spin_unlock_irq(&hdsp->lock); | |
4278 | ||
4279 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4280 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); | |
e3ea4d89 TI |
4281 | if (hdsp->clock_source_locked) { |
4282 | runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; | |
4283 | } else if (hdsp->io_type == H9632) { | |
1da177e4 LT |
4284 | runtime->hw.rate_max = 192000; |
4285 | runtime->hw.rates = SNDRV_PCM_RATE_KNOT; | |
4286 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); | |
4287 | } | |
e3ea4d89 TI |
4288 | if (hdsp->io_type == H9632) { |
4289 | runtime->hw.channels_min = hdsp->qs_out_channels; | |
4290 | runtime->hw.channels_max = hdsp->ss_out_channels; | |
4291 | } | |
1da177e4 LT |
4292 | |
4293 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4294 | snd_hdsp_hw_rule_out_channels, hdsp, | |
4295 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4296 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4297 | snd_hdsp_hw_rule_out_channels_rate, hdsp, | |
4298 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4299 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4300 | snd_hdsp_hw_rule_rate_out_channels, hdsp, | |
4301 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4302 | ||
4303 | hdsp->creg_spdif_stream = hdsp->creg_spdif; | |
4304 | hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
4305 | snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
4306 | SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); | |
4307 | return 0; | |
4308 | } | |
4309 | ||
55e957d8 | 4310 | static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) |
1da177e4 | 4311 | { |
55e957d8 | 4312 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4313 | |
4314 | spin_lock_irq(&hdsp->lock); | |
4315 | ||
4316 | hdsp->playback_pid = -1; | |
4317 | hdsp->playback_substream = NULL; | |
4318 | ||
4319 | spin_unlock_irq(&hdsp->lock); | |
4320 | ||
4321 | hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
4322 | snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
4323 | SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); | |
4324 | return 0; | |
4325 | } | |
4326 | ||
4327 | ||
55e957d8 | 4328 | static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 4329 | { |
55e957d8 TI |
4330 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
4331 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 4332 | |
b0b98119 | 4333 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4334 | return -EIO; |
1da177e4 | 4335 | |
b0b98119 | 4336 | if (hdsp_check_for_firmware(hdsp, 1)) |
1da177e4 | 4337 | return -EIO; |
1da177e4 LT |
4338 | |
4339 | spin_lock_irq(&hdsp->lock); | |
4340 | ||
4341 | snd_pcm_set_sync(substream); | |
4342 | ||
4343 | runtime->hw = snd_hdsp_capture_subinfo; | |
4344 | runtime->dma_area = hdsp->capture_buffer; | |
4345 | runtime->dma_bytes = HDSP_DMA_AREA_BYTES; | |
4346 | ||
4347 | hdsp->capture_pid = current->pid; | |
4348 | hdsp->capture_substream = substream; | |
4349 | ||
4350 | spin_unlock_irq(&hdsp->lock); | |
4351 | ||
4352 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4353 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); | |
4354 | if (hdsp->io_type == H9632) { | |
4355 | runtime->hw.channels_min = hdsp->qs_in_channels; | |
4356 | runtime->hw.channels_max = hdsp->ss_in_channels; | |
4357 | runtime->hw.rate_max = 192000; | |
4358 | runtime->hw.rates = SNDRV_PCM_RATE_KNOT; | |
4359 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); | |
4360 | } | |
4361 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4362 | snd_hdsp_hw_rule_in_channels, hdsp, | |
4363 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4364 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4365 | snd_hdsp_hw_rule_in_channels_rate, hdsp, | |
4366 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4367 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4368 | snd_hdsp_hw_rule_rate_in_channels, hdsp, | |
4369 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4370 | return 0; | |
4371 | } | |
4372 | ||
55e957d8 | 4373 | static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) |
1da177e4 | 4374 | { |
55e957d8 | 4375 | struct hdsp *hdsp = snd_pcm_substream_chip(substream); |
1da177e4 LT |
4376 | |
4377 | spin_lock_irq(&hdsp->lock); | |
4378 | ||
4379 | hdsp->capture_pid = -1; | |
4380 | hdsp->capture_substream = NULL; | |
4381 | ||
4382 | spin_unlock_irq(&hdsp->lock); | |
4383 | return 0; | |
4384 | } | |
4385 | ||
55e957d8 | 4386 | static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) |
1da177e4 LT |
4387 | { |
4388 | /* we have nothing to initialize but the call is required */ | |
4389 | return 0; | |
4390 | } | |
4391 | ||
4392 | ||
4393 | /* helper functions for copying meter values */ | |
4394 | static inline int copy_u32_le(void __user *dest, void __iomem *src) | |
4395 | { | |
4396 | u32 val = readl(src); | |
4397 | return copy_to_user(dest, &val, 4); | |
4398 | } | |
4399 | ||
4400 | static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) | |
4401 | { | |
4402 | u32 rms_low, rms_high; | |
4403 | u64 rms; | |
4404 | rms_low = readl(src_low); | |
4405 | rms_high = readl(src_high); | |
4406 | rms = ((u64)rms_high << 32) | rms_low; | |
4407 | return copy_to_user(dest, &rms, 8); | |
4408 | } | |
4409 | ||
4410 | static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) | |
4411 | { | |
4412 | u32 rms_low, rms_high; | |
4413 | u64 rms; | |
4414 | rms_low = readl(src_low) & 0xffffff00; | |
4415 | rms_high = readl(src_high) & 0xffffff00; | |
4416 | rms = ((u64)rms_high << 32) | rms_low; | |
4417 | return copy_to_user(dest, &rms, 8); | |
4418 | } | |
4419 | ||
55e957d8 | 4420 | static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) |
1da177e4 LT |
4421 | { |
4422 | int doublespeed = 0; | |
4423 | int i, j, channels, ofs; | |
4424 | ||
4425 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) | |
4426 | doublespeed = 1; | |
4427 | channels = doublespeed ? 14 : 26; | |
4428 | for (i = 0, j = 0; i < 26; ++i) { | |
4429 | if (doublespeed && (i & 4)) | |
4430 | continue; | |
4431 | ofs = HDSP_9652_peakBase - j * 4; | |
4432 | if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) | |
4433 | return -EFAULT; | |
4434 | ofs -= channels * 4; | |
4435 | if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) | |
4436 | return -EFAULT; | |
4437 | ofs -= channels * 4; | |
4438 | if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) | |
4439 | return -EFAULT; | |
4440 | ofs = HDSP_9652_rmsBase + j * 8; | |
4441 | if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, | |
4442 | hdsp->iobase + ofs + 4)) | |
4443 | return -EFAULT; | |
4444 | ofs += channels * 8; | |
4445 | if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, | |
4446 | hdsp->iobase + ofs + 4)) | |
4447 | return -EFAULT; | |
4448 | ofs += channels * 8; | |
4449 | if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, | |
4450 | hdsp->iobase + ofs + 4)) | |
4451 | return -EFAULT; | |
4452 | j++; | |
4453 | } | |
4454 | return 0; | |
4455 | } | |
4456 | ||
55e957d8 | 4457 | static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) |
1da177e4 LT |
4458 | { |
4459 | int i, j; | |
55e957d8 | 4460 | struct hdsp_9632_meters __iomem *m; |
1da177e4 LT |
4461 | int doublespeed = 0; |
4462 | ||
4463 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) | |
4464 | doublespeed = 1; | |
55e957d8 | 4465 | m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); |
1da177e4 LT |
4466 | for (i = 0, j = 0; i < 16; ++i, ++j) { |
4467 | if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) | |
4468 | return -EFAULT; | |
4469 | if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) | |
4470 | return -EFAULT; | |
4471 | if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) | |
4472 | return -EFAULT; | |
4473 | if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], | |
4474 | &m->input_rms_high[j])) | |
4475 | return -EFAULT; | |
4476 | if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], | |
4477 | &m->playback_rms_high[j])) | |
4478 | return -EFAULT; | |
4479 | if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], | |
4480 | &m->output_rms_high[j])) | |
4481 | return -EFAULT; | |
4482 | if (doublespeed && i == 3) i += 4; | |
4483 | } | |
4484 | return 0; | |
4485 | } | |
4486 | ||
55e957d8 | 4487 | static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) |
1da177e4 LT |
4488 | { |
4489 | int i; | |
4490 | ||
4491 | for (i = 0; i < 26; i++) { | |
4492 | if (copy_u32_le(&peak_rms->playback_peaks[i], | |
4493 | hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) | |
4494 | return -EFAULT; | |
4495 | if (copy_u32_le(&peak_rms->input_peaks[i], | |
4496 | hdsp->iobase + HDSP_inputPeakLevel + i * 4)) | |
4497 | return -EFAULT; | |
4498 | } | |
4499 | for (i = 0; i < 28; i++) { | |
4500 | if (copy_u32_le(&peak_rms->output_peaks[i], | |
4501 | hdsp->iobase + HDSP_outputPeakLevel + i * 4)) | |
4502 | return -EFAULT; | |
4503 | } | |
4504 | for (i = 0; i < 26; ++i) { | |
4505 | if (copy_u64_le(&peak_rms->playback_rms[i], | |
4506 | hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, | |
4507 | hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) | |
4508 | return -EFAULT; | |
4509 | if (copy_u64_le(&peak_rms->input_rms[i], | |
4510 | hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, | |
4511 | hdsp->iobase + HDSP_inputRmsLevel + i * 8)) | |
4512 | return -EFAULT; | |
4513 | } | |
4514 | return 0; | |
4515 | } | |
4516 | ||
55e957d8 | 4517 | static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) |
1da177e4 | 4518 | { |
55e957d8 | 4519 | struct hdsp *hdsp = (struct hdsp *)hw->private_data; |
1da177e4 LT |
4520 | void __user *argp = (void __user *)arg; |
4521 | ||
4522 | switch (cmd) { | |
4523 | case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { | |
55e957d8 | 4524 | struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; |
1da177e4 LT |
4525 | |
4526 | if (!(hdsp->state & HDSP_FirmwareLoaded)) { | |
4527 | snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); | |
4528 | return -EINVAL; | |
4529 | } | |
4530 | ||
4531 | switch (hdsp->io_type) { | |
4532 | case H9652: | |
4533 | return hdsp_9652_get_peak(hdsp, peak_rms); | |
4534 | case H9632: | |
4535 | return hdsp_9632_get_peak(hdsp, peak_rms); | |
4536 | default: | |
4537 | return hdsp_get_peak(hdsp, peak_rms); | |
4538 | } | |
4539 | } | |
4540 | case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { | |
55e957d8 | 4541 | struct hdsp_config_info info; |
1da177e4 LT |
4542 | unsigned long flags; |
4543 | int i; | |
4544 | ||
4545 | if (!(hdsp->state & HDSP_FirmwareLoaded)) { | |
b0b98119 | 4546 | snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n"); |
1da177e4 LT |
4547 | return -EINVAL; |
4548 | } | |
4549 | spin_lock_irqsave(&hdsp->lock, flags); | |
4550 | info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); | |
4551 | info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); | |
b0b98119 | 4552 | if (hdsp->io_type != H9632) |
1da177e4 | 4553 | info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); |
1da177e4 | 4554 | info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); |
b0b98119 | 4555 | for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) |
1da177e4 | 4556 | info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); |
1da177e4 LT |
4557 | info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); |
4558 | info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); | |
4559 | info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); | |
4560 | info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); | |
4561 | info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); | |
4562 | info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); | |
4563 | info.system_sample_rate = hdsp->system_sample_rate; | |
4564 | info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); | |
4565 | info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); | |
4566 | info.clock_source = (unsigned char)hdsp_clock_source(hdsp); | |
4567 | info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); | |
4568 | info.line_out = (unsigned char)hdsp_line_out(hdsp); | |
4569 | if (hdsp->io_type == H9632) { | |
4570 | info.da_gain = (unsigned char)hdsp_da_gain(hdsp); | |
4571 | info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); | |
4572 | info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); | |
4573 | info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); | |
4574 | ||
4575 | } | |
b0b98119 | 4576 | if (hdsp->io_type == H9632 || hdsp->io_type == H9652) |
1da177e4 | 4577 | info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); |
1da177e4 LT |
4578 | spin_unlock_irqrestore(&hdsp->lock, flags); |
4579 | if (copy_to_user(argp, &info, sizeof(info))) | |
4580 | return -EFAULT; | |
4581 | break; | |
4582 | } | |
4583 | case SNDRV_HDSP_IOCTL_GET_9632_AEB: { | |
55e957d8 | 4584 | struct hdsp_9632_aeb h9632_aeb; |
1da177e4 LT |
4585 | |
4586 | if (hdsp->io_type != H9632) return -EINVAL; | |
4587 | h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; | |
4588 | h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; | |
4589 | if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) | |
4590 | return -EFAULT; | |
4591 | break; | |
4592 | } | |
4593 | case SNDRV_HDSP_IOCTL_GET_VERSION: { | |
55e957d8 | 4594 | struct hdsp_version hdsp_version; |
1da177e4 LT |
4595 | int err; |
4596 | ||
4597 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; | |
4598 | if (hdsp->io_type == Undefined) { | |
b0b98119 | 4599 | if ((err = hdsp_get_iobox_version(hdsp)) < 0) |
1da177e4 | 4600 | return err; |
1da177e4 LT |
4601 | } |
4602 | hdsp_version.io_type = hdsp->io_type; | |
4603 | hdsp_version.firmware_rev = hdsp->firmware_rev; | |
b0b98119 | 4604 | if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) |
1da177e4 | 4605 | return -EFAULT; |
1da177e4 LT |
4606 | break; |
4607 | } | |
4608 | case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { | |
55e957d8 | 4609 | struct hdsp_firmware __user *firmware; |
1da177e4 LT |
4610 | u32 __user *firmware_data; |
4611 | int err; | |
4612 | ||
4613 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; | |
4614 | /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ | |
4615 | if (hdsp->io_type == Undefined) return -EINVAL; | |
4616 | ||
4617 | if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) | |
4618 | return -EBUSY; | |
4619 | ||
b0b98119 | 4620 | snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n"); |
55e957d8 | 4621 | firmware = (struct hdsp_firmware __user *)argp; |
1da177e4 | 4622 | |
b0b98119 | 4623 | if (get_user(firmware_data, &firmware->firmware_data)) |
1da177e4 | 4624 | return -EFAULT; |
1da177e4 | 4625 | |
b0b98119 | 4626 | if (hdsp_check_for_iobox (hdsp)) |
1da177e4 | 4627 | return -EIO; |
1da177e4 | 4628 | |
b0b98119 | 4629 | if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) |
1da177e4 | 4630 | return -EFAULT; |
1da177e4 LT |
4631 | |
4632 | hdsp->state |= HDSP_FirmwareCached; | |
4633 | ||
b0b98119 | 4634 | if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) |
1da177e4 | 4635 | return err; |
1da177e4 LT |
4636 | |
4637 | if (!(hdsp->state & HDSP_InitializationComplete)) { | |
b0b98119 | 4638 | if ((err = snd_hdsp_enable_io(hdsp)) < 0) |
1da177e4 | 4639 | return err; |
1da177e4 LT |
4640 | |
4641 | snd_hdsp_initialize_channels(hdsp); | |
4642 | snd_hdsp_initialize_midi_flush(hdsp); | |
4643 | ||
4644 | if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { | |
b0b98119 TI |
4645 | snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); |
4646 | return err; | |
1da177e4 LT |
4647 | } |
4648 | } | |
4649 | break; | |
4650 | } | |
4651 | case SNDRV_HDSP_IOCTL_GET_MIXER: { | |
55e957d8 | 4652 | struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; |
1da177e4 LT |
4653 | if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) |
4654 | return -EFAULT; | |
4655 | break; | |
4656 | } | |
4657 | default: | |
4658 | return -EINVAL; | |
4659 | } | |
4660 | return 0; | |
4661 | } | |
4662 | ||
55e957d8 | 4663 | static struct snd_pcm_ops snd_hdsp_playback_ops = { |
1da177e4 LT |
4664 | .open = snd_hdsp_playback_open, |
4665 | .close = snd_hdsp_playback_release, | |
4666 | .ioctl = snd_hdsp_ioctl, | |
4667 | .hw_params = snd_hdsp_hw_params, | |
4668 | .prepare = snd_hdsp_prepare, | |
4669 | .trigger = snd_hdsp_trigger, | |
4670 | .pointer = snd_hdsp_hw_pointer, | |
4671 | .copy = snd_hdsp_playback_copy, | |
4672 | .silence = snd_hdsp_hw_silence, | |
4673 | }; | |
4674 | ||
55e957d8 | 4675 | static struct snd_pcm_ops snd_hdsp_capture_ops = { |
1da177e4 LT |
4676 | .open = snd_hdsp_capture_open, |
4677 | .close = snd_hdsp_capture_release, | |
4678 | .ioctl = snd_hdsp_ioctl, | |
4679 | .hw_params = snd_hdsp_hw_params, | |
4680 | .prepare = snd_hdsp_prepare, | |
4681 | .trigger = snd_hdsp_trigger, | |
4682 | .pointer = snd_hdsp_hw_pointer, | |
4683 | .copy = snd_hdsp_capture_copy, | |
4684 | }; | |
4685 | ||
55e957d8 TI |
4686 | static int __devinit snd_hdsp_create_hwdep(struct snd_card *card, |
4687 | struct hdsp *hdsp) | |
1da177e4 | 4688 | { |
55e957d8 | 4689 | struct snd_hwdep *hw; |
1da177e4 LT |
4690 | int err; |
4691 | ||
4692 | if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) | |
4693 | return err; | |
4694 | ||
4695 | hdsp->hwdep = hw; | |
4696 | hw->private_data = hdsp; | |
4697 | strcpy(hw->name, "HDSP hwdep interface"); | |
4698 | ||
4699 | hw->ops.open = snd_hdsp_hwdep_dummy_op; | |
4700 | hw->ops.ioctl = snd_hdsp_hwdep_ioctl; | |
4701 | hw->ops.release = snd_hdsp_hwdep_dummy_op; | |
4702 | ||
4703 | return 0; | |
4704 | } | |
4705 | ||
55e957d8 | 4706 | static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 | 4707 | { |
55e957d8 | 4708 | struct snd_pcm *pcm; |
1da177e4 LT |
4709 | int err; |
4710 | ||
4711 | if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0) | |
4712 | return err; | |
4713 | ||
4714 | hdsp->pcm = pcm; | |
4715 | pcm->private_data = hdsp; | |
4716 | strcpy(pcm->name, hdsp->card_name); | |
4717 | ||
4718 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); | |
4719 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); | |
4720 | ||
4721 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
4722 | ||
4723 | return 0; | |
4724 | } | |
4725 | ||
55e957d8 | 4726 | static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) |
1da177e4 LT |
4727 | { |
4728 | hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; | |
4729 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
4730 | } | |
4731 | ||
55e957d8 | 4732 | static int snd_hdsp_enable_io (struct hdsp *hdsp) |
1da177e4 LT |
4733 | { |
4734 | int i; | |
4735 | ||
4736 | if (hdsp_fifo_wait (hdsp, 0, 100)) { | |
b0b98119 | 4737 | snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n"); |
1da177e4 LT |
4738 | return -EIO; |
4739 | } | |
4740 | ||
4741 | for (i = 0; i < hdsp->max_channels; ++i) { | |
4742 | hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); | |
4743 | hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); | |
4744 | } | |
4745 | ||
4746 | return 0; | |
4747 | } | |
4748 | ||
55e957d8 | 4749 | static void snd_hdsp_initialize_channels(struct hdsp *hdsp) |
1da177e4 LT |
4750 | { |
4751 | int status, aebi_channels, aebo_channels; | |
4752 | ||
4753 | switch (hdsp->io_type) { | |
4754 | case Digiface: | |
4755 | hdsp->card_name = "RME Hammerfall DSP + Digiface"; | |
4756 | hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; | |
4757 | hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; | |
4758 | break; | |
4759 | ||
4760 | case H9652: | |
4761 | hdsp->card_name = "RME Hammerfall HDSP 9652"; | |
4762 | hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; | |
4763 | hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; | |
4764 | break; | |
4765 | ||
4766 | case H9632: | |
4767 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
4768 | /* HDSP_AEBx bits are low when AEB are connected */ | |
4769 | aebi_channels = (status & HDSP_AEBI) ? 0 : 4; | |
4770 | aebo_channels = (status & HDSP_AEBO) ? 0 : 4; | |
4771 | hdsp->card_name = "RME Hammerfall HDSP 9632"; | |
4772 | hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; | |
4773 | hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; | |
4774 | hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; | |
4775 | hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; | |
4776 | hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; | |
4777 | hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; | |
4778 | break; | |
4779 | ||
4780 | case Multiface: | |
4781 | hdsp->card_name = "RME Hammerfall DSP + Multiface"; | |
4782 | hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; | |
4783 | hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; | |
4784 | break; | |
4785 | ||
4786 | default: | |
4787 | /* should never get here */ | |
4788 | break; | |
4789 | } | |
4790 | } | |
4791 | ||
55e957d8 | 4792 | static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) |
1da177e4 LT |
4793 | { |
4794 | snd_hdsp_flush_midi_input (hdsp, 0); | |
4795 | snd_hdsp_flush_midi_input (hdsp, 1); | |
4796 | } | |
4797 | ||
55e957d8 | 4798 | static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) |
1da177e4 LT |
4799 | { |
4800 | int err; | |
4801 | ||
4802 | if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { | |
b0b98119 | 4803 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n"); |
1da177e4 LT |
4804 | return err; |
4805 | } | |
4806 | ||
4807 | ||
4808 | if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { | |
b0b98119 | 4809 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n"); |
1da177e4 LT |
4810 | return err; |
4811 | } | |
4812 | ||
4813 | if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { | |
4814 | if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { | |
b0b98119 | 4815 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n"); |
1da177e4 LT |
4816 | return err; |
4817 | } | |
4818 | } | |
4819 | ||
4820 | if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { | |
b0b98119 | 4821 | snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n"); |
1da177e4 LT |
4822 | return err; |
4823 | } | |
4824 | ||
4825 | snd_hdsp_proc_init(hdsp); | |
4826 | ||
4827 | hdsp->system_sample_rate = -1; | |
4828 | hdsp->playback_pid = -1; | |
4829 | hdsp->capture_pid = -1; | |
4830 | hdsp->capture_substream = NULL; | |
4831 | hdsp->playback_substream = NULL; | |
4832 | ||
4833 | if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { | |
b0b98119 | 4834 | snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n"); |
1da177e4 LT |
4835 | return err; |
4836 | } | |
4837 | ||
4838 | if (!(hdsp->state & HDSP_InitializationComplete)) { | |
b73c1c12 | 4839 | strcpy(card->shortname, "Hammerfall DSP"); |
1da177e4 LT |
4840 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, |
4841 | hdsp->port, hdsp->irq); | |
4842 | ||
4843 | if ((err = snd_card_register(card)) < 0) { | |
b0b98119 | 4844 | snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n"); |
1da177e4 LT |
4845 | return err; |
4846 | } | |
4847 | hdsp->state |= HDSP_InitializationComplete; | |
4848 | } | |
4849 | ||
4850 | return 0; | |
4851 | } | |
4852 | ||
4853 | #ifdef HDSP_FW_LOADER | |
4854 | /* load firmware via hotplug fw loader */ | |
55e957d8 | 4855 | static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp) |
1da177e4 LT |
4856 | { |
4857 | const char *fwfile; | |
4858 | const struct firmware *fw; | |
4859 | int err; | |
4860 | ||
4861 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) | |
4862 | return 0; | |
4863 | if (hdsp->io_type == Undefined) { | |
4864 | if ((err = hdsp_get_iobox_version(hdsp)) < 0) | |
4865 | return err; | |
4866 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) | |
4867 | return 0; | |
4868 | } | |
4869 | ||
4870 | /* caution: max length of firmware filename is 30! */ | |
4871 | switch (hdsp->io_type) { | |
4872 | case Multiface: | |
4873 | if (hdsp->firmware_rev == 0xa) | |
4874 | fwfile = "multiface_firmware.bin"; | |
4875 | else | |
4876 | fwfile = "multiface_firmware_rev11.bin"; | |
4877 | break; | |
4878 | case Digiface: | |
4879 | if (hdsp->firmware_rev == 0xa) | |
4880 | fwfile = "digiface_firmware.bin"; | |
4881 | else | |
4882 | fwfile = "digiface_firmware_rev11.bin"; | |
4883 | break; | |
4884 | default: | |
4885 | snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type); | |
4886 | return -EINVAL; | |
4887 | } | |
4888 | ||
4889 | if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { | |
4890 | snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile); | |
4891 | return -ENOENT; | |
4892 | } | |
4893 | if (fw->size < sizeof(hdsp->firmware_cache)) { | |
4894 | snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", | |
4895 | (int)fw->size, (int)sizeof(hdsp->firmware_cache)); | |
4896 | release_firmware(fw); | |
4897 | return -EINVAL; | |
4898 | } | |
7679a030 | 4899 | |
1da177e4 | 4900 | memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache)); |
7679a030 | 4901 | |
1da177e4 LT |
4902 | release_firmware(fw); |
4903 | ||
4904 | hdsp->state |= HDSP_FirmwareCached; | |
4905 | ||
4906 | if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) | |
4907 | return err; | |
4908 | ||
4909 | if (!(hdsp->state & HDSP_InitializationComplete)) { | |
b0b98119 | 4910 | if ((err = snd_hdsp_enable_io(hdsp)) < 0) |
1da177e4 | 4911 | return err; |
1da177e4 LT |
4912 | |
4913 | if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) { | |
b0b98119 | 4914 | snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n"); |
1da177e4 LT |
4915 | return err; |
4916 | } | |
4917 | snd_hdsp_initialize_channels(hdsp); | |
4918 | snd_hdsp_initialize_midi_flush(hdsp); | |
4919 | if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { | |
b0b98119 | 4920 | snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); |
1da177e4 LT |
4921 | return err; |
4922 | } | |
4923 | } | |
4924 | return 0; | |
4925 | } | |
4926 | #endif | |
4927 | ||
55e957d8 TI |
4928 | static int __devinit snd_hdsp_create(struct snd_card *card, |
4929 | struct hdsp *hdsp) | |
1da177e4 LT |
4930 | { |
4931 | struct pci_dev *pci = hdsp->pci; | |
4932 | int err; | |
4933 | int is_9652 = 0; | |
4934 | int is_9632 = 0; | |
4935 | ||
4936 | hdsp->irq = -1; | |
4937 | hdsp->state = 0; | |
4938 | hdsp->midi[0].rmidi = NULL; | |
4939 | hdsp->midi[1].rmidi = NULL; | |
4940 | hdsp->midi[0].input = NULL; | |
4941 | hdsp->midi[1].input = NULL; | |
4942 | hdsp->midi[0].output = NULL; | |
4943 | hdsp->midi[1].output = NULL; | |
4944 | hdsp->midi[0].pending = 0; | |
4945 | hdsp->midi[1].pending = 0; | |
4946 | spin_lock_init(&hdsp->midi[0].lock); | |
4947 | spin_lock_init(&hdsp->midi[1].lock); | |
4948 | hdsp->iobase = NULL; | |
4949 | hdsp->control_register = 0; | |
4950 | hdsp->control2_register = 0; | |
4951 | hdsp->io_type = Undefined; | |
4952 | hdsp->max_channels = 26; | |
4953 | ||
4954 | hdsp->card = card; | |
4955 | ||
4956 | spin_lock_init(&hdsp->lock); | |
4957 | ||
4958 | tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); | |
4959 | ||
4960 | pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); | |
4961 | hdsp->firmware_rev &= 0xff; | |
4962 | ||
4963 | /* From Martin Bjoernsen : | |
4964 | "It is important that the card's latency timer register in | |
4965 | the PCI configuration space is set to a value much larger | |
4966 | than 0 by the computer's BIOS or the driver. | |
4967 | The windows driver always sets this 8 bit register [...] | |
4968 | to its maximum 255 to avoid problems with some computers." | |
4969 | */ | |
4970 | pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); | |
4971 | ||
4972 | strcpy(card->driver, "H-DSP"); | |
4973 | strcpy(card->mixername, "Xilinx FPGA"); | |
4974 | ||
b0b98119 | 4975 | if (hdsp->firmware_rev < 0xa) |
1da177e4 | 4976 | return -ENODEV; |
b0b98119 | 4977 | else if (hdsp->firmware_rev < 0x64) |
1da177e4 | 4978 | hdsp->card_name = "RME Hammerfall DSP"; |
b0b98119 | 4979 | else if (hdsp->firmware_rev < 0x96) { |
1da177e4 LT |
4980 | hdsp->card_name = "RME HDSP 9652"; |
4981 | is_9652 = 1; | |
4982 | } else { | |
4983 | hdsp->card_name = "RME HDSP 9632"; | |
4984 | hdsp->max_channels = 16; | |
4985 | is_9632 = 1; | |
4986 | } | |
4987 | ||
b0b98119 | 4988 | if ((err = pci_enable_device(pci)) < 0) |
1da177e4 | 4989 | return err; |
1da177e4 LT |
4990 | |
4991 | pci_set_master(hdsp->pci); | |
4992 | ||
4993 | if ((err = pci_request_regions(pci, "hdsp")) < 0) | |
4994 | return err; | |
4995 | hdsp->port = pci_resource_start(pci, 0); | |
4996 | if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) { | |
b0b98119 | 4997 | snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); |
1da177e4 LT |
4998 | return -EBUSY; |
4999 | } | |
5000 | ||
437a5a46 TI |
5001 | if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED, |
5002 | "hdsp", hdsp)) { | |
b0b98119 | 5003 | snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq); |
1da177e4 LT |
5004 | return -EBUSY; |
5005 | } | |
5006 | ||
5007 | hdsp->irq = pci->irq; | |
176546ab | 5008 | hdsp->precise_ptr = 0; |
1da177e4 | 5009 | hdsp->use_midi_tasklet = 1; |
d7923b2a | 5010 | hdsp->dds_value = 0; |
1da177e4 | 5011 | |
b0b98119 | 5012 | if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) |
1da177e4 | 5013 | return err; |
1da177e4 LT |
5014 | |
5015 | if (!is_9652 && !is_9632) { | |
5016 | /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */ | |
b0b98119 | 5017 | ssleep(2); |
1da177e4 LT |
5018 | |
5019 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
5020 | #ifdef HDSP_FW_LOADER | |
b0b98119 | 5021 | if ((err = hdsp_request_fw_loader(hdsp)) < 0) |
1da177e4 LT |
5022 | /* we don't fail as this can happen |
5023 | if userspace is not ready for | |
5024 | firmware upload | |
5025 | */ | |
b0b98119 TI |
5026 | snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n"); |
5027 | else | |
1da177e4 LT |
5028 | /* init is complete, we return */ |
5029 | return 0; | |
1da177e4 LT |
5030 | #endif |
5031 | /* no iobox connected, we defer initialization */ | |
b0b98119 TI |
5032 | snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n"); |
5033 | if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) | |
1da177e4 | 5034 | return err; |
1da177e4 LT |
5035 | return 0; |
5036 | } else { | |
b0b98119 TI |
5037 | snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n"); |
5038 | if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) | |
1da177e4 | 5039 | hdsp->io_type = Multiface; |
b0b98119 | 5040 | else |
1da177e4 | 5041 | hdsp->io_type = Digiface; |
1da177e4 LT |
5042 | } |
5043 | } | |
5044 | ||
b0b98119 | 5045 | if ((err = snd_hdsp_enable_io(hdsp)) != 0) |
1da177e4 | 5046 | return err; |
1da177e4 | 5047 | |
b0b98119 | 5048 | if (is_9652) |
1da177e4 | 5049 | hdsp->io_type = H9652; |
1da177e4 | 5050 | |
b0b98119 | 5051 | if (is_9632) |
1da177e4 | 5052 | hdsp->io_type = H9632; |
1da177e4 | 5053 | |
b0b98119 | 5054 | if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) |
1da177e4 | 5055 | return err; |
1da177e4 LT |
5056 | |
5057 | snd_hdsp_initialize_channels(hdsp); | |
5058 | snd_hdsp_initialize_midi_flush(hdsp); | |
5059 | ||
5060 | hdsp->state |= HDSP_FirmwareLoaded; | |
5061 | ||
b0b98119 | 5062 | if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) |
1da177e4 | 5063 | return err; |
1da177e4 LT |
5064 | |
5065 | return 0; | |
5066 | } | |
5067 | ||
55e957d8 | 5068 | static int snd_hdsp_free(struct hdsp *hdsp) |
1da177e4 LT |
5069 | { |
5070 | if (hdsp->port) { | |
5071 | /* stop the audio, and cancel all interrupts */ | |
5072 | tasklet_kill(&hdsp->midi_tasklet); | |
5073 | hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); | |
5074 | hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); | |
5075 | } | |
5076 | ||
5077 | if (hdsp->irq >= 0) | |
5078 | free_irq(hdsp->irq, (void *)hdsp); | |
5079 | ||
5080 | snd_hdsp_free_buffers(hdsp); | |
5081 | ||
5082 | if (hdsp->iobase) | |
5083 | iounmap(hdsp->iobase); | |
5084 | ||
5085 | if (hdsp->port) | |
5086 | pci_release_regions(hdsp->pci); | |
5087 | ||
5088 | pci_disable_device(hdsp->pci); | |
5089 | return 0; | |
5090 | } | |
5091 | ||
55e957d8 | 5092 | static void snd_hdsp_card_free(struct snd_card *card) |
1da177e4 | 5093 | { |
55e957d8 | 5094 | struct hdsp *hdsp = (struct hdsp *) card->private_data; |
1da177e4 LT |
5095 | |
5096 | if (hdsp) | |
5097 | snd_hdsp_free(hdsp); | |
5098 | } | |
5099 | ||
5100 | static int __devinit snd_hdsp_probe(struct pci_dev *pci, | |
5101 | const struct pci_device_id *pci_id) | |
5102 | { | |
5103 | static int dev; | |
55e957d8 TI |
5104 | struct hdsp *hdsp; |
5105 | struct snd_card *card; | |
1da177e4 LT |
5106 | int err; |
5107 | ||
5108 | if (dev >= SNDRV_CARDS) | |
5109 | return -ENODEV; | |
5110 | if (!enable[dev]) { | |
5111 | dev++; | |
5112 | return -ENOENT; | |
5113 | } | |
5114 | ||
55e957d8 | 5115 | if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp)))) |
1da177e4 LT |
5116 | return -ENOMEM; |
5117 | ||
55e957d8 | 5118 | hdsp = (struct hdsp *) card->private_data; |
1da177e4 LT |
5119 | card->private_free = snd_hdsp_card_free; |
5120 | hdsp->dev = dev; | |
5121 | hdsp->pci = pci; | |
5122 | snd_card_set_dev(card, &pci->dev); | |
5123 | ||
5124 | if ((err = snd_hdsp_create(card, hdsp)) < 0) { | |
5125 | snd_card_free(card); | |
5126 | return err; | |
5127 | } | |
5128 | ||
5129 | strcpy(card->shortname, "Hammerfall DSP"); | |
5130 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, | |
5131 | hdsp->port, hdsp->irq); | |
5132 | ||
5133 | if ((err = snd_card_register(card)) < 0) { | |
5134 | snd_card_free(card); | |
5135 | return err; | |
5136 | } | |
5137 | pci_set_drvdata(pci, card); | |
5138 | dev++; | |
5139 | return 0; | |
5140 | } | |
5141 | ||
5142 | static void __devexit snd_hdsp_remove(struct pci_dev *pci) | |
5143 | { | |
5144 | snd_card_free(pci_get_drvdata(pci)); | |
5145 | pci_set_drvdata(pci, NULL); | |
5146 | } | |
5147 | ||
5148 | static struct pci_driver driver = { | |
5149 | .name = "RME Hammerfall DSP", | |
5150 | .id_table = snd_hdsp_ids, | |
5151 | .probe = snd_hdsp_probe, | |
5152 | .remove = __devexit_p(snd_hdsp_remove), | |
5153 | }; | |
5154 | ||
5155 | static int __init alsa_card_hdsp_init(void) | |
5156 | { | |
01d25d46 | 5157 | return pci_register_driver(&driver); |
1da177e4 LT |
5158 | } |
5159 | ||
5160 | static void __exit alsa_card_hdsp_exit(void) | |
5161 | { | |
5162 | pci_unregister_driver(&driver); | |
5163 | } | |
5164 | ||
5165 | module_init(alsa_card_hdsp_init) | |
5166 | module_exit(alsa_card_hdsp_exit) |