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1da177e4 LT |
1 | /* |
2 | * ALSA driver for RME Hammerfall DSP audio interface(s) | |
3 | * | |
4 | * Copyright (c) 2002 Paul Davis | |
5 | * Marcus Andersson | |
6 | * Thomas Charbonnel | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <sound/driver.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/firmware.h> | |
31 | #include <linux/moduleparam.h> | |
32 | ||
33 | #include <sound/core.h> | |
34 | #include <sound/control.h> | |
35 | #include <sound/pcm.h> | |
36 | #include <sound/info.h> | |
37 | #include <sound/asoundef.h> | |
38 | #include <sound/rawmidi.h> | |
39 | #include <sound/hwdep.h> | |
40 | #include <sound/initval.h> | |
41 | #include <sound/hdsp.h> | |
42 | ||
43 | #include <asm/byteorder.h> | |
44 | #include <asm/current.h> | |
45 | #include <asm/io.h> | |
46 | ||
47 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
48 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
49 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ | |
50 | ||
51 | module_param_array(index, int, NULL, 0444); | |
52 | MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); | |
53 | module_param_array(id, charp, NULL, 0444); | |
54 | MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); | |
55 | module_param_array(enable, bool, NULL, 0444); | |
56 | MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); | |
57 | MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); | |
58 | MODULE_DESCRIPTION("RME Hammerfall DSP"); | |
59 | MODULE_LICENSE("GPL"); | |
60 | MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP}," | |
61 | "{RME HDSP-9652}," | |
62 | "{RME HDSP-9632}}"); | |
63 | ||
64 | #define HDSP_MAX_CHANNELS 26 | |
65 | #define HDSP_MAX_DS_CHANNELS 14 | |
66 | #define HDSP_MAX_QS_CHANNELS 8 | |
67 | #define DIGIFACE_SS_CHANNELS 26 | |
68 | #define DIGIFACE_DS_CHANNELS 14 | |
69 | #define MULTIFACE_SS_CHANNELS 18 | |
70 | #define MULTIFACE_DS_CHANNELS 14 | |
71 | #define H9652_SS_CHANNELS 26 | |
72 | #define H9652_DS_CHANNELS 14 | |
73 | /* This does not include possible Analog Extension Boards | |
74 | AEBs are detected at card initialization | |
75 | */ | |
76 | #define H9632_SS_CHANNELS 12 | |
77 | #define H9632_DS_CHANNELS 8 | |
78 | #define H9632_QS_CHANNELS 4 | |
79 | ||
80 | /* Write registers. These are defined as byte-offsets from the iobase value. | |
81 | */ | |
82 | #define HDSP_resetPointer 0 | |
83 | #define HDSP_outputBufferAddress 32 | |
84 | #define HDSP_inputBufferAddress 36 | |
85 | #define HDSP_controlRegister 64 | |
86 | #define HDSP_interruptConfirmation 96 | |
87 | #define HDSP_outputEnable 128 | |
88 | #define HDSP_control2Reg 256 | |
89 | #define HDSP_midiDataOut0 352 | |
90 | #define HDSP_midiDataOut1 356 | |
91 | #define HDSP_fifoData 368 | |
92 | #define HDSP_inputEnable 384 | |
93 | ||
94 | /* Read registers. These are defined as byte-offsets from the iobase value | |
95 | */ | |
96 | ||
97 | #define HDSP_statusRegister 0 | |
98 | #define HDSP_timecode 128 | |
99 | #define HDSP_status2Register 192 | |
100 | #define HDSP_midiDataOut0 352 | |
101 | #define HDSP_midiDataOut1 356 | |
102 | #define HDSP_midiDataIn0 360 | |
103 | #define HDSP_midiDataIn1 364 | |
104 | #define HDSP_midiStatusOut0 384 | |
105 | #define HDSP_midiStatusOut1 388 | |
106 | #define HDSP_midiStatusIn0 392 | |
107 | #define HDSP_midiStatusIn1 396 | |
108 | #define HDSP_fifoStatus 400 | |
109 | ||
110 | /* the meters are regular i/o-mapped registers, but offset | |
111 | considerably from the rest. the peak registers are reset | |
112 | when read; the least-significant 4 bits are full-scale counters; | |
113 | the actual peak value is in the most-significant 24 bits. | |
114 | */ | |
115 | ||
116 | #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ | |
117 | #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ | |
118 | #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ | |
119 | #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ | |
120 | #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ | |
121 | ||
122 | ||
123 | /* This is for H9652 cards | |
124 | Peak values are read downward from the base | |
125 | Rms values are read upward | |
126 | There are rms values for the outputs too | |
127 | 26*3 values are read in ss mode | |
128 | 14*3 in ds mode, with no gap between values | |
129 | */ | |
130 | #define HDSP_9652_peakBase 7164 | |
131 | #define HDSP_9652_rmsBase 4096 | |
132 | ||
133 | /* c.f. the hdsp_9632_meters_t struct */ | |
134 | #define HDSP_9632_metersBase 4096 | |
135 | ||
136 | #define HDSP_IO_EXTENT 7168 | |
137 | ||
138 | /* control2 register bits */ | |
139 | ||
140 | #define HDSP_TMS 0x01 | |
141 | #define HDSP_TCK 0x02 | |
142 | #define HDSP_TDI 0x04 | |
143 | #define HDSP_JTAG 0x08 | |
144 | #define HDSP_PWDN 0x10 | |
145 | #define HDSP_PROGRAM 0x020 | |
146 | #define HDSP_CONFIG_MODE_0 0x040 | |
147 | #define HDSP_CONFIG_MODE_1 0x080 | |
148 | #define HDSP_VERSION_BIT 0x100 | |
149 | #define HDSP_BIGENDIAN_MODE 0x200 | |
150 | #define HDSP_RD_MULTIPLE 0x400 | |
151 | #define HDSP_9652_ENABLE_MIXER 0x800 | |
152 | #define HDSP_TDO 0x10000000 | |
153 | ||
154 | #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) | |
155 | #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1) | |
156 | ||
157 | /* Control Register bits */ | |
158 | ||
159 | #define HDSP_Start (1<<0) /* start engine */ | |
160 | #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ | |
161 | #define HDSP_Latency1 (1<<2) /* [ see above ] */ | |
162 | #define HDSP_Latency2 (1<<3) /* [ see above ] */ | |
163 | #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ | |
164 | #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ | |
165 | #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ | |
166 | #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ | |
167 | #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ | |
168 | #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ | |
169 | #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ | |
170 | #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ | |
171 | #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ | |
172 | #define HDSP_SyncRef2 (1<<13) | |
173 | #define HDSP_SPDIFInputSelect0 (1<<14) | |
174 | #define HDSP_SPDIFInputSelect1 (1<<15) | |
175 | #define HDSP_SyncRef0 (1<<16) | |
176 | #define HDSP_SyncRef1 (1<<17) | |
177 | #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ | |
178 | #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ | |
179 | #define HDSP_Midi0InterruptEnable (1<<22) | |
180 | #define HDSP_Midi1InterruptEnable (1<<23) | |
181 | #define HDSP_LineOut (1<<24) | |
182 | #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ | |
183 | #define HDSP_ADGain1 (1<<26) | |
184 | #define HDSP_DAGain0 (1<<27) | |
185 | #define HDSP_DAGain1 (1<<28) | |
186 | #define HDSP_PhoneGain0 (1<<29) | |
187 | #define HDSP_PhoneGain1 (1<<30) | |
188 | #define HDSP_QuadSpeed (1<<31) | |
189 | ||
190 | #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) | |
191 | #define HDSP_ADGainMinus10dBV HDSP_ADGainMask | |
192 | #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) | |
193 | #define HDSP_ADGainLowGain 0 | |
194 | ||
195 | #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) | |
196 | #define HDSP_DAGainHighGain HDSP_DAGainMask | |
197 | #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) | |
198 | #define HDSP_DAGainMinus10dBV 0 | |
199 | ||
200 | #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) | |
201 | #define HDSP_PhoneGain0dB HDSP_PhoneGainMask | |
202 | #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) | |
203 | #define HDSP_PhoneGainMinus12dB 0 | |
204 | ||
205 | #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) | |
206 | #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) | |
207 | ||
208 | #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) | |
209 | #define HDSP_SPDIFInputADAT1 0 | |
210 | #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) | |
211 | #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) | |
212 | #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) | |
213 | ||
214 | #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) | |
215 | #define HDSP_SyncRef_ADAT1 0 | |
216 | #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) | |
217 | #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) | |
218 | #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) | |
219 | #define HDSP_SyncRef_WORD (HDSP_SyncRef2) | |
220 | #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) | |
221 | ||
222 | /* Sample Clock Sources */ | |
223 | ||
224 | #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 | |
225 | #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 | |
226 | #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 | |
227 | #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 | |
228 | #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 | |
229 | #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 | |
230 | #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 | |
231 | #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 | |
232 | #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 | |
233 | #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 | |
234 | ||
235 | /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ | |
236 | ||
237 | #define HDSP_SYNC_FROM_WORD 0 | |
238 | #define HDSP_SYNC_FROM_SPDIF 1 | |
239 | #define HDSP_SYNC_FROM_ADAT1 2 | |
240 | #define HDSP_SYNC_FROM_ADAT_SYNC 3 | |
241 | #define HDSP_SYNC_FROM_ADAT2 4 | |
242 | #define HDSP_SYNC_FROM_ADAT3 5 | |
243 | ||
244 | /* SyncCheck status */ | |
245 | ||
246 | #define HDSP_SYNC_CHECK_NO_LOCK 0 | |
247 | #define HDSP_SYNC_CHECK_LOCK 1 | |
248 | #define HDSP_SYNC_CHECK_SYNC 2 | |
249 | ||
250 | /* AutoSync references - used by "autosync_ref" control switch */ | |
251 | ||
252 | #define HDSP_AUTOSYNC_FROM_WORD 0 | |
253 | #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 | |
254 | #define HDSP_AUTOSYNC_FROM_SPDIF 2 | |
255 | #define HDSP_AUTOSYNC_FROM_NONE 3 | |
256 | #define HDSP_AUTOSYNC_FROM_ADAT1 4 | |
257 | #define HDSP_AUTOSYNC_FROM_ADAT2 5 | |
258 | #define HDSP_AUTOSYNC_FROM_ADAT3 6 | |
259 | ||
260 | /* Possible sources of S/PDIF input */ | |
261 | ||
262 | #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ | |
263 | #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ | |
264 | #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ | |
265 | #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ | |
266 | ||
267 | #define HDSP_Frequency32KHz HDSP_Frequency0 | |
268 | #define HDSP_Frequency44_1KHz HDSP_Frequency1 | |
269 | #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) | |
270 | #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) | |
271 | #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) | |
272 | #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) | |
273 | /* For H9632 cards */ | |
274 | #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) | |
275 | #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) | |
276 | #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) | |
277 | ||
278 | #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) | |
279 | #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) | |
280 | ||
281 | #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) | |
282 | #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) | |
283 | ||
284 | /* Status Register bits */ | |
285 | ||
286 | #define HDSP_audioIRQPending (1<<0) | |
287 | #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ | |
288 | #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ | |
289 | #define HDSP_Lock1 (1<<2) | |
290 | #define HDSP_Lock0 (1<<3) | |
291 | #define HDSP_SPDIFSync (1<<4) | |
292 | #define HDSP_TimecodeLock (1<<5) | |
293 | #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ | |
294 | #define HDSP_Sync2 (1<<16) | |
295 | #define HDSP_Sync1 (1<<17) | |
296 | #define HDSP_Sync0 (1<<18) | |
297 | #define HDSP_DoubleSpeedStatus (1<<19) | |
298 | #define HDSP_ConfigError (1<<20) | |
299 | #define HDSP_DllError (1<<21) | |
300 | #define HDSP_spdifFrequency0 (1<<22) | |
301 | #define HDSP_spdifFrequency1 (1<<23) | |
302 | #define HDSP_spdifFrequency2 (1<<24) | |
303 | #define HDSP_SPDIFErrorFlag (1<<25) | |
304 | #define HDSP_BufferID (1<<26) | |
305 | #define HDSP_TimecodeSync (1<<27) | |
306 | #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ | |
307 | #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ | |
308 | #define HDSP_midi0IRQPending (1<<30) | |
309 | #define HDSP_midi1IRQPending (1<<31) | |
310 | ||
311 | #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) | |
312 | ||
313 | #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) | |
314 | #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) | |
315 | #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) | |
316 | ||
317 | #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) | |
318 | #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) | |
319 | #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) | |
320 | ||
321 | /* This is for H9632 cards */ | |
322 | #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask | |
323 | #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 | |
324 | #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) | |
325 | ||
326 | /* Status2 Register bits */ | |
327 | ||
328 | #define HDSP_version0 (1<<0) | |
329 | #define HDSP_version1 (1<<1) | |
330 | #define HDSP_version2 (1<<2) | |
331 | #define HDSP_wc_lock (1<<3) | |
332 | #define HDSP_wc_sync (1<<4) | |
333 | #define HDSP_inp_freq0 (1<<5) | |
334 | #define HDSP_inp_freq1 (1<<6) | |
335 | #define HDSP_inp_freq2 (1<<7) | |
336 | #define HDSP_SelSyncRef0 (1<<8) | |
337 | #define HDSP_SelSyncRef1 (1<<9) | |
338 | #define HDSP_SelSyncRef2 (1<<10) | |
339 | ||
340 | #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) | |
341 | ||
342 | #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) | |
343 | #define HDSP_systemFrequency32 (HDSP_inp_freq0) | |
344 | #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) | |
345 | #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) | |
346 | #define HDSP_systemFrequency64 (HDSP_inp_freq2) | |
347 | #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) | |
348 | #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) | |
349 | /* FIXME : more values for 9632 cards ? */ | |
350 | ||
351 | #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) | |
352 | #define HDSP_SelSyncRef_ADAT1 0 | |
353 | #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) | |
354 | #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) | |
355 | #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) | |
356 | #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) | |
357 | #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) | |
358 | ||
359 | /* Card state flags */ | |
360 | ||
361 | #define HDSP_InitializationComplete (1<<0) | |
362 | #define HDSP_FirmwareLoaded (1<<1) | |
363 | #define HDSP_FirmwareCached (1<<2) | |
364 | ||
365 | /* FIFO wait times, defined in terms of 1/10ths of msecs */ | |
366 | ||
367 | #define HDSP_LONG_WAIT 5000 | |
368 | #define HDSP_SHORT_WAIT 30 | |
369 | ||
370 | #define UNITY_GAIN 32768 | |
371 | #define MINUS_INFINITY_GAIN 0 | |
372 | ||
373 | #ifndef PCI_VENDOR_ID_XILINX | |
374 | #define PCI_VENDOR_ID_XILINX 0x10ee | |
375 | #endif | |
376 | #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP | |
377 | #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 | |
378 | #endif | |
379 | ||
380 | /* the size of a substream (1 mono data stream) */ | |
381 | ||
382 | #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) | |
383 | #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) | |
384 | ||
385 | /* the size of the area we need to allocate for DMA transfers. the | |
386 | size is the same regardless of the number of channels - the | |
387 | Multiface still uses the same memory area. | |
388 | ||
389 | Note that we allocate 1 more channel than is apparently needed | |
390 | because the h/w seems to write 1 byte beyond the end of the last | |
391 | page. Sigh. | |
392 | */ | |
393 | ||
394 | #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) | |
395 | #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) | |
396 | ||
397 | /* use hotplug firmeare loader? */ | |
398 | #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) | |
399 | #ifndef HDSP_USE_HWDEP_LOADER | |
400 | #define HDSP_FW_LOADER | |
401 | #endif | |
402 | #endif | |
403 | ||
404 | typedef struct _hdsp hdsp_t; | |
405 | typedef struct _hdsp_midi hdsp_midi_t; | |
406 | typedef struct _hdsp_9632_meters hdsp_9632_meters_t; | |
407 | ||
408 | struct _hdsp_9632_meters { | |
409 | u32 input_peak[16]; | |
410 | u32 playback_peak[16]; | |
411 | u32 output_peak[16]; | |
412 | u32 xxx_peak[16]; | |
413 | u32 padding[64]; | |
414 | u32 input_rms_low[16]; | |
415 | u32 playback_rms_low[16]; | |
416 | u32 output_rms_low[16]; | |
417 | u32 xxx_rms_low[16]; | |
418 | u32 input_rms_high[16]; | |
419 | u32 playback_rms_high[16]; | |
420 | u32 output_rms_high[16]; | |
421 | u32 xxx_rms_high[16]; | |
422 | }; | |
423 | ||
424 | struct _hdsp_midi { | |
425 | hdsp_t *hdsp; | |
426 | int id; | |
427 | snd_rawmidi_t *rmidi; | |
428 | snd_rawmidi_substream_t *input; | |
429 | snd_rawmidi_substream_t *output; | |
430 | char istimer; /* timer in use */ | |
431 | struct timer_list timer; | |
432 | spinlock_t lock; | |
433 | int pending; | |
434 | }; | |
435 | ||
436 | struct _hdsp { | |
437 | spinlock_t lock; | |
438 | snd_pcm_substream_t *capture_substream; | |
439 | snd_pcm_substream_t *playback_substream; | |
440 | hdsp_midi_t midi[2]; | |
441 | struct tasklet_struct midi_tasklet; | |
442 | int use_midi_tasklet; | |
443 | int precise_ptr; | |
444 | u32 control_register; /* cached value */ | |
445 | u32 control2_register; /* cached value */ | |
446 | u32 creg_spdif; | |
447 | u32 creg_spdif_stream; | |
448 | char *card_name; /* digiface/multiface */ | |
449 | HDSP_IO_Type io_type; /* ditto, but for code use */ | |
450 | unsigned short firmware_rev; | |
451 | unsigned short state; /* stores state bits */ | |
452 | u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ | |
453 | size_t period_bytes; /* guess what this is */ | |
454 | unsigned char max_channels; | |
455 | unsigned char qs_in_channels; /* quad speed mode for H9632 */ | |
456 | unsigned char ds_in_channels; | |
457 | unsigned char ss_in_channels; /* different for multiface/digiface */ | |
458 | unsigned char qs_out_channels; | |
459 | unsigned char ds_out_channels; | |
460 | unsigned char ss_out_channels; | |
461 | ||
462 | struct snd_dma_buffer capture_dma_buf; | |
463 | struct snd_dma_buffer playback_dma_buf; | |
464 | unsigned char *capture_buffer; /* suitably aligned address */ | |
465 | unsigned char *playback_buffer; /* suitably aligned address */ | |
466 | ||
467 | pid_t capture_pid; | |
468 | pid_t playback_pid; | |
469 | int running; | |
470 | int system_sample_rate; | |
471 | char *channel_map; | |
472 | int dev; | |
473 | int irq; | |
474 | unsigned long port; | |
475 | void __iomem *iobase; | |
476 | snd_card_t *card; | |
477 | snd_pcm_t *pcm; | |
478 | snd_hwdep_t *hwdep; | |
479 | struct pci_dev *pci; | |
480 | snd_kcontrol_t *spdif_ctl; | |
481 | unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; | |
482 | }; | |
483 | ||
484 | /* These tables map the ALSA channels 1..N to the channels that we | |
485 | need to use in order to find the relevant channel buffer. RME | |
486 | refer to this kind of mapping as between "the ADAT channel and | |
487 | the DMA channel." We index it using the logical audio channel, | |
488 | and the value is the DMA channel (i.e. channel buffer number) | |
489 | where the data for that channel can be read/written from/to. | |
490 | */ | |
491 | ||
492 | static char channel_map_df_ss[HDSP_MAX_CHANNELS] = { | |
493 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
494 | 18, 19, 20, 21, 22, 23, 24, 25 | |
495 | }; | |
496 | ||
497 | static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ | |
498 | /* Analog */ | |
499 | 0, 1, 2, 3, 4, 5, 6, 7, | |
500 | /* ADAT 2 */ | |
501 | 16, 17, 18, 19, 20, 21, 22, 23, | |
502 | /* SPDIF */ | |
503 | 24, 25, | |
504 | -1, -1, -1, -1, -1, -1, -1, -1 | |
505 | }; | |
506 | ||
507 | static char channel_map_ds[HDSP_MAX_CHANNELS] = { | |
508 | /* ADAT channels are remapped */ | |
509 | 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, | |
510 | /* channels 12 and 13 are S/PDIF */ | |
511 | 24, 25, | |
512 | /* others don't exist */ | |
513 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 | |
514 | }; | |
515 | ||
516 | static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { | |
517 | /* ADAT channels */ | |
518 | 0, 1, 2, 3, 4, 5, 6, 7, | |
519 | /* SPDIF */ | |
520 | 8, 9, | |
521 | /* Analog */ | |
522 | 10, 11, | |
523 | /* AO4S-192 and AI4S-192 extension boards */ | |
524 | 12, 13, 14, 15, | |
525 | /* others don't exist */ | |
526 | -1, -1, -1, -1, -1, -1, -1, -1, | |
527 | -1, -1 | |
528 | }; | |
529 | ||
530 | static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { | |
531 | /* ADAT */ | |
532 | 1, 3, 5, 7, | |
533 | /* SPDIF */ | |
534 | 8, 9, | |
535 | /* Analog */ | |
536 | 10, 11, | |
537 | /* AO4S-192 and AI4S-192 extension boards */ | |
538 | 12, 13, 14, 15, | |
539 | /* others don't exist */ | |
540 | -1, -1, -1, -1, -1, -1, -1, -1, | |
541 | -1, -1, -1, -1, -1, -1 | |
542 | }; | |
543 | ||
544 | static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { | |
545 | /* ADAT is disabled in this mode */ | |
546 | /* SPDIF */ | |
547 | 8, 9, | |
548 | /* Analog */ | |
549 | 10, 11, | |
550 | /* AO4S-192 and AI4S-192 extension boards */ | |
551 | 12, 13, 14, 15, | |
552 | /* others don't exist */ | |
553 | -1, -1, -1, -1, -1, -1, -1, -1, | |
554 | -1, -1, -1, -1, -1, -1, -1, -1, | |
555 | -1, -1 | |
556 | }; | |
557 | ||
558 | static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) | |
559 | { | |
560 | dmab->dev.type = SNDRV_DMA_TYPE_DEV; | |
561 | dmab->dev.dev = snd_dma_pci_data(pci); | |
b6a96915 TI |
562 | if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) { |
563 | if (dmab->bytes >= size) | |
564 | return 0; | |
1da177e4 | 565 | } |
b6a96915 TI |
566 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), |
567 | size, dmab) < 0) | |
568 | return -ENOMEM; | |
1da177e4 LT |
569 | return 0; |
570 | } | |
571 | ||
572 | static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) | |
573 | { | |
b6a96915 TI |
574 | if (dmab->area) { |
575 | dmab->dev.dev = NULL; /* make it anonymous */ | |
1da177e4 | 576 | snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci)); |
b6a96915 | 577 | } |
1da177e4 LT |
578 | } |
579 | ||
580 | ||
581 | static struct pci_device_id snd_hdsp_ids[] = { | |
582 | { | |
583 | .vendor = PCI_VENDOR_ID_XILINX, | |
584 | .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, | |
585 | .subvendor = PCI_ANY_ID, | |
586 | .subdevice = PCI_ANY_ID, | |
587 | }, /* RME Hammerfall-DSP */ | |
588 | { 0, }, | |
589 | }; | |
590 | ||
591 | MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); | |
592 | ||
593 | /* prototypes */ | |
594 | static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp); | |
595 | static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp); | |
596 | static int snd_hdsp_enable_io (hdsp_t *hdsp); | |
597 | static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp); | |
598 | static void snd_hdsp_initialize_channels (hdsp_t *hdsp); | |
599 | static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout); | |
600 | static int hdsp_autosync_ref(hdsp_t *hdsp); | |
601 | static int snd_hdsp_set_defaults(hdsp_t *hdsp); | |
602 | static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp); | |
603 | ||
604 | static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out) | |
605 | { | |
606 | switch (hdsp->firmware_rev) { | |
607 | case 0xa: | |
608 | return (64 * out) + (32 + (in)); | |
609 | case 0x96: | |
610 | case 0x97: | |
611 | return (32 * out) + (16 + (in)); | |
612 | default: | |
613 | return (52 * out) + (26 + (in)); | |
614 | } | |
615 | } | |
616 | ||
617 | static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out) | |
618 | { | |
619 | switch (hdsp->firmware_rev) { | |
620 | case 0xa: | |
621 | return (64 * out) + in; | |
622 | case 0x96: | |
623 | case 0x97: | |
624 | return (32 * out) + in; | |
625 | default: | |
626 | return (52 * out) + in; | |
627 | } | |
628 | } | |
629 | ||
630 | static void hdsp_write(hdsp_t *hdsp, int reg, int val) | |
631 | { | |
632 | writel(val, hdsp->iobase + reg); | |
633 | } | |
634 | ||
635 | static unsigned int hdsp_read(hdsp_t *hdsp, int reg) | |
636 | { | |
637 | return readl (hdsp->iobase + reg); | |
638 | } | |
639 | ||
640 | static int hdsp_check_for_iobox (hdsp_t *hdsp) | |
641 | { | |
642 | ||
643 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; | |
644 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { | |
645 | snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); | |
646 | hdsp->state &= ~HDSP_FirmwareLoaded; | |
647 | return -EIO; | |
648 | } | |
649 | return 0; | |
650 | ||
651 | } | |
652 | ||
653 | static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) { | |
654 | ||
655 | int i; | |
656 | unsigned long flags; | |
657 | ||
658 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
659 | ||
660 | snd_printk ("Hammerfall-DSP: loading firmware\n"); | |
661 | ||
662 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); | |
663 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
664 | ||
665 | if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { | |
666 | snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n"); | |
667 | return -EIO; | |
668 | } | |
669 | ||
670 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
671 | ||
672 | for (i = 0; i < 24413; ++i) { | |
673 | hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]); | |
674 | if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { | |
675 | snd_printk ("Hammerfall-DSP: timeout during firmware loading\n"); | |
676 | return -EIO; | |
677 | } | |
678 | } | |
679 | ||
680 | if ((1000 / HZ) < 3000) { | |
681 | set_current_state(TASK_UNINTERRUPTIBLE); | |
682 | schedule_timeout((3000 * HZ + 999) / 1000); | |
683 | } else { | |
684 | mdelay(3000); | |
685 | } | |
686 | ||
687 | if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { | |
688 | snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n"); | |
689 | return -EIO; | |
690 | } | |
691 | ||
692 | #ifdef SNDRV_BIG_ENDIAN | |
693 | hdsp->control2_register = HDSP_BIGENDIAN_MODE; | |
694 | #else | |
695 | hdsp->control2_register = 0; | |
696 | #endif | |
697 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
698 | snd_printk ("Hammerfall-DSP: finished firmware loading\n"); | |
699 | ||
700 | } | |
701 | if (hdsp->state & HDSP_InitializationComplete) { | |
702 | snd_printk("Hammerfall-DSP: firmware loaded from cache, restoring defaults\n"); | |
703 | spin_lock_irqsave(&hdsp->lock, flags); | |
704 | snd_hdsp_set_defaults(hdsp); | |
705 | spin_unlock_irqrestore(&hdsp->lock, flags); | |
706 | } | |
707 | ||
708 | hdsp->state |= HDSP_FirmwareLoaded; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static int hdsp_get_iobox_version (hdsp_t *hdsp) | |
714 | { | |
715 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
716 | ||
717 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM); | |
718 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
719 | if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) { | |
720 | return -EIO; | |
721 | } | |
722 | ||
723 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
724 | hdsp_write (hdsp, HDSP_fifoData, 0); | |
725 | ||
726 | if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { | |
727 | hdsp->io_type = Multiface; | |
728 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT); | |
729 | hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); | |
730 | hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); | |
731 | } else { | |
732 | hdsp->io_type = Digiface; | |
733 | } | |
734 | } else { | |
735 | /* firmware was already loaded, get iobox type */ | |
736 | if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) { | |
737 | hdsp->io_type = Multiface; | |
738 | } else { | |
739 | hdsp->io_type = Digiface; | |
740 | } | |
741 | } | |
742 | return 0; | |
743 | } | |
744 | ||
745 | ||
746 | static int hdsp_check_for_firmware (hdsp_t *hdsp) | |
747 | { | |
748 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; | |
749 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
750 | snd_printk("Hammerfall-DSP: firmware not present.\n"); | |
751 | hdsp->state &= ~HDSP_FirmwareLoaded; | |
752 | return -EIO; | |
753 | } | |
754 | return 0; | |
755 | } | |
756 | ||
757 | ||
758 | static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout) | |
759 | { | |
760 | int i; | |
761 | ||
762 | /* the fifoStatus registers reports on how many words | |
763 | are available in the command FIFO. | |
764 | */ | |
765 | ||
766 | for (i = 0; i < timeout; i++) { | |
767 | ||
768 | if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) | |
769 | return 0; | |
770 | ||
771 | /* not very friendly, but we only do this during a firmware | |
772 | load and changing the mixer, so we just put up with it. | |
773 | */ | |
774 | ||
775 | udelay (100); | |
776 | } | |
777 | ||
778 | snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n", | |
779 | count, timeout); | |
780 | return -1; | |
781 | } | |
782 | ||
783 | static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr) | |
784 | { | |
785 | if (addr >= HDSP_MATRIX_MIXER_SIZE) { | |
786 | return 0; | |
787 | } | |
788 | return hdsp->mixer_matrix[addr]; | |
789 | } | |
790 | ||
791 | static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data) | |
792 | { | |
793 | unsigned int ad; | |
794 | ||
795 | if (addr >= HDSP_MATRIX_MIXER_SIZE) | |
796 | return -1; | |
797 | ||
798 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { | |
799 | ||
800 | /* from martin bjornsen: | |
801 | ||
802 | "You can only write dwords to the | |
803 | mixer memory which contain two | |
804 | mixer values in the low and high | |
805 | word. So if you want to change | |
806 | value 0 you have to read value 1 | |
807 | from the cache and write both to | |
808 | the first dword in the mixer | |
809 | memory." | |
810 | */ | |
811 | ||
812 | if (hdsp->io_type == H9632 && addr >= 512) { | |
813 | return 0; | |
814 | } | |
815 | ||
816 | if (hdsp->io_type == H9652 && addr >= 1352) { | |
817 | return 0; | |
818 | } | |
819 | ||
820 | hdsp->mixer_matrix[addr] = data; | |
821 | ||
822 | ||
823 | /* `addr' addresses a 16-bit wide address, but | |
824 | the address space accessed via hdsp_write | |
825 | uses byte offsets. put another way, addr | |
826 | varies from 0 to 1351, but to access the | |
827 | corresponding memory location, we need | |
828 | to access 0 to 2703 ... | |
829 | */ | |
830 | ad = addr/2; | |
831 | ||
832 | hdsp_write (hdsp, 4096 + (ad*4), | |
833 | (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + | |
834 | hdsp->mixer_matrix[addr&0x7fe]); | |
835 | ||
836 | return 0; | |
837 | ||
838 | } else { | |
839 | ||
840 | ad = (addr << 16) + data; | |
841 | ||
842 | if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) { | |
843 | return -1; | |
844 | } | |
845 | ||
846 | hdsp_write (hdsp, HDSP_fifoData, ad); | |
847 | hdsp->mixer_matrix[addr] = data; | |
848 | ||
849 | } | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
854 | static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp) | |
855 | { | |
856 | unsigned long flags; | |
857 | int ret = 1; | |
858 | ||
859 | spin_lock_irqsave(&hdsp->lock, flags); | |
860 | if ((hdsp->playback_pid != hdsp->capture_pid) && | |
861 | (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) { | |
862 | ret = 0; | |
863 | } | |
864 | spin_unlock_irqrestore(&hdsp->lock, flags); | |
865 | return ret; | |
866 | } | |
867 | ||
868 | static int hdsp_external_sample_rate (hdsp_t *hdsp) | |
869 | { | |
870 | unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
871 | unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; | |
872 | ||
873 | switch (rate_bits) { | |
874 | case HDSP_systemFrequency32: return 32000; | |
875 | case HDSP_systemFrequency44_1: return 44100; | |
876 | case HDSP_systemFrequency48: return 48000; | |
877 | case HDSP_systemFrequency64: return 64000; | |
878 | case HDSP_systemFrequency88_2: return 88200; | |
879 | case HDSP_systemFrequency96: return 96000; | |
880 | default: | |
881 | return 0; | |
882 | } | |
883 | } | |
884 | ||
885 | static int hdsp_spdif_sample_rate(hdsp_t *hdsp) | |
886 | { | |
887 | unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); | |
888 | unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); | |
889 | ||
890 | if (status & HDSP_SPDIFErrorFlag) { | |
891 | return 0; | |
892 | } | |
893 | ||
894 | switch (rate_bits) { | |
895 | case HDSP_spdifFrequency32KHz: return 32000; | |
896 | case HDSP_spdifFrequency44_1KHz: return 44100; | |
897 | case HDSP_spdifFrequency48KHz: return 48000; | |
898 | case HDSP_spdifFrequency64KHz: return 64000; | |
899 | case HDSP_spdifFrequency88_2KHz: return 88200; | |
900 | case HDSP_spdifFrequency96KHz: return 96000; | |
901 | case HDSP_spdifFrequency128KHz: | |
902 | if (hdsp->io_type == H9632) return 128000; | |
903 | break; | |
904 | case HDSP_spdifFrequency176_4KHz: | |
905 | if (hdsp->io_type == H9632) return 176400; | |
906 | break; | |
907 | case HDSP_spdifFrequency192KHz: | |
908 | if (hdsp->io_type == H9632) return 192000; | |
909 | break; | |
910 | default: | |
911 | break; | |
912 | } | |
913 | snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); | |
914 | return 0; | |
915 | } | |
916 | ||
917 | static void hdsp_compute_period_size(hdsp_t *hdsp) | |
918 | { | |
919 | hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); | |
920 | } | |
921 | ||
922 | static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp) | |
923 | { | |
924 | int position; | |
925 | ||
926 | position = hdsp_read(hdsp, HDSP_statusRegister); | |
927 | ||
928 | if (!hdsp->precise_ptr) { | |
929 | return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; | |
930 | } | |
931 | ||
932 | position &= HDSP_BufferPositionMask; | |
933 | position /= 4; | |
934 | position &= (hdsp->period_bytes/2) - 1; | |
935 | return position; | |
936 | } | |
937 | ||
938 | static void hdsp_reset_hw_pointer(hdsp_t *hdsp) | |
939 | { | |
940 | hdsp_write (hdsp, HDSP_resetPointer, 0); | |
941 | } | |
942 | ||
943 | static void hdsp_start_audio(hdsp_t *s) | |
944 | { | |
945 | s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); | |
946 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
947 | } | |
948 | ||
949 | static void hdsp_stop_audio(hdsp_t *s) | |
950 | { | |
951 | s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); | |
952 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
953 | } | |
954 | ||
955 | static void hdsp_silence_playback(hdsp_t *hdsp) | |
956 | { | |
957 | memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); | |
958 | } | |
959 | ||
960 | static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames) | |
961 | { | |
962 | int n; | |
963 | ||
964 | spin_lock_irq(&s->lock); | |
965 | ||
966 | frames >>= 7; | |
967 | n = 0; | |
968 | while (frames) { | |
969 | n++; | |
970 | frames >>= 1; | |
971 | } | |
972 | ||
973 | s->control_register &= ~HDSP_LatencyMask; | |
974 | s->control_register |= hdsp_encode_latency(n); | |
975 | ||
976 | hdsp_write(s, HDSP_controlRegister, s->control_register); | |
977 | ||
978 | hdsp_compute_period_size(s); | |
979 | ||
980 | spin_unlock_irq(&s->lock); | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally) | |
986 | { | |
987 | int reject_if_open = 0; | |
988 | int current_rate; | |
989 | int rate_bits; | |
990 | ||
991 | /* ASSUMPTION: hdsp->lock is either held, or | |
992 | there is no need for it (e.g. during module | |
993 | initialization). | |
994 | */ | |
995 | ||
996 | if (!(hdsp->control_register & HDSP_ClockModeMaster)) { | |
997 | if (called_internally) { | |
998 | /* request from ctl or card initialization */ | |
999 | snd_printk("Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n"); | |
1000 | return -1; | |
1001 | } else { | |
1002 | /* hw_param request while in AutoSync mode */ | |
1003 | int external_freq = hdsp_external_sample_rate(hdsp); | |
1004 | int spdif_freq = hdsp_spdif_sample_rate(hdsp); | |
1005 | ||
1006 | if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) { | |
1007 | snd_printk("Hammerfall-DSP: Detected ADAT in double speed mode\n"); | |
1008 | } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) { | |
1009 | snd_printk("Hammerfall-DSP: Detected ADAT in quad speed mode\n"); | |
1010 | } else if (rate != external_freq) { | |
1011 | snd_printk("Hammerfall-DSP: No AutoSync source for requested rate\n"); | |
1012 | return -1; | |
1013 | } | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | current_rate = hdsp->system_sample_rate; | |
1018 | ||
1019 | /* Changing from a "single speed" to a "double speed" rate is | |
1020 | not allowed if any substreams are open. This is because | |
1021 | such a change causes a shift in the location of | |
1022 | the DMA buffers and a reduction in the number of available | |
1023 | buffers. | |
1024 | ||
1025 | Note that a similar but essentially insoluble problem | |
1026 | exists for externally-driven rate changes. All we can do | |
1027 | is to flag rate changes in the read/write routines. */ | |
1028 | ||
1029 | if (rate > 96000 && hdsp->io_type != H9632) { | |
1030 | return -EINVAL; | |
1031 | } | |
1032 | ||
1033 | switch (rate) { | |
1034 | case 32000: | |
1035 | if (current_rate > 48000) { | |
1036 | reject_if_open = 1; | |
1037 | } | |
1038 | rate_bits = HDSP_Frequency32KHz; | |
1039 | break; | |
1040 | case 44100: | |
1041 | if (current_rate > 48000) { | |
1042 | reject_if_open = 1; | |
1043 | } | |
1044 | rate_bits = HDSP_Frequency44_1KHz; | |
1045 | break; | |
1046 | case 48000: | |
1047 | if (current_rate > 48000) { | |
1048 | reject_if_open = 1; | |
1049 | } | |
1050 | rate_bits = HDSP_Frequency48KHz; | |
1051 | break; | |
1052 | case 64000: | |
1053 | if (current_rate <= 48000 || current_rate > 96000) { | |
1054 | reject_if_open = 1; | |
1055 | } | |
1056 | rate_bits = HDSP_Frequency64KHz; | |
1057 | break; | |
1058 | case 88200: | |
1059 | if (current_rate <= 48000 || current_rate > 96000) { | |
1060 | reject_if_open = 1; | |
1061 | } | |
1062 | rate_bits = HDSP_Frequency88_2KHz; | |
1063 | break; | |
1064 | case 96000: | |
1065 | if (current_rate <= 48000 || current_rate > 96000) { | |
1066 | reject_if_open = 1; | |
1067 | } | |
1068 | rate_bits = HDSP_Frequency96KHz; | |
1069 | break; | |
1070 | case 128000: | |
1071 | if (current_rate < 128000) { | |
1072 | reject_if_open = 1; | |
1073 | } | |
1074 | rate_bits = HDSP_Frequency128KHz; | |
1075 | break; | |
1076 | case 176400: | |
1077 | if (current_rate < 128000) { | |
1078 | reject_if_open = 1; | |
1079 | } | |
1080 | rate_bits = HDSP_Frequency176_4KHz; | |
1081 | break; | |
1082 | case 192000: | |
1083 | if (current_rate < 128000) { | |
1084 | reject_if_open = 1; | |
1085 | } | |
1086 | rate_bits = HDSP_Frequency192KHz; | |
1087 | break; | |
1088 | default: | |
1089 | return -EINVAL; | |
1090 | } | |
1091 | ||
1092 | if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { | |
1093 | snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n", | |
1094 | hdsp->capture_pid, | |
1095 | hdsp->playback_pid); | |
1096 | return -EBUSY; | |
1097 | } | |
1098 | ||
1099 | hdsp->control_register &= ~HDSP_FrequencyMask; | |
1100 | hdsp->control_register |= rate_bits; | |
1101 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1102 | ||
1103 | if (rate >= 128000) { | |
1104 | hdsp->channel_map = channel_map_H9632_qs; | |
1105 | } else if (rate > 48000) { | |
1106 | if (hdsp->io_type == H9632) { | |
1107 | hdsp->channel_map = channel_map_H9632_ds; | |
1108 | } else { | |
1109 | hdsp->channel_map = channel_map_ds; | |
1110 | } | |
1111 | } else { | |
1112 | switch (hdsp->io_type) { | |
1113 | case Multiface: | |
1114 | hdsp->channel_map = channel_map_mf_ss; | |
1115 | break; | |
1116 | case Digiface: | |
1117 | case H9652: | |
1118 | hdsp->channel_map = channel_map_df_ss; | |
1119 | break; | |
1120 | case H9632: | |
1121 | hdsp->channel_map = channel_map_H9632_ss; | |
1122 | break; | |
1123 | default: | |
1124 | /* should never happen */ | |
1125 | break; | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | hdsp->system_sample_rate = rate; | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | /*---------------------------------------------------------------------------- | |
1135 | MIDI | |
1136 | ----------------------------------------------------------------------------*/ | |
1137 | ||
1138 | static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id) | |
1139 | { | |
1140 | /* the hardware already does the relevant bit-mask with 0xff */ | |
1141 | if (id) { | |
1142 | return hdsp_read(hdsp, HDSP_midiDataIn1); | |
1143 | } else { | |
1144 | return hdsp_read(hdsp, HDSP_midiDataIn0); | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val) | |
1149 | { | |
1150 | /* the hardware already does the relevant bit-mask with 0xff */ | |
1151 | if (id) { | |
1152 | hdsp_write(hdsp, HDSP_midiDataOut1, val); | |
1153 | } else { | |
1154 | hdsp_write(hdsp, HDSP_midiDataOut0, val); | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id) | |
1159 | { | |
1160 | if (id) { | |
1161 | return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); | |
1162 | } else { | |
1163 | return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id) | |
1168 | { | |
1169 | int fifo_bytes_used; | |
1170 | ||
1171 | if (id) { | |
1172 | fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; | |
1173 | } else { | |
1174 | fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; | |
1175 | } | |
1176 | ||
1177 | if (fifo_bytes_used < 128) { | |
1178 | return 128 - fifo_bytes_used; | |
1179 | } else { | |
1180 | return 0; | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id) | |
1185 | { | |
1186 | while (snd_hdsp_midi_input_available (hdsp, id)) { | |
1187 | snd_hdsp_midi_read_byte (hdsp, id); | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi) | |
1192 | { | |
1193 | unsigned long flags; | |
1194 | int n_pending; | |
1195 | int to_write; | |
1196 | int i; | |
1197 | unsigned char buf[128]; | |
1198 | ||
1199 | /* Output is not interrupt driven */ | |
1200 | ||
1201 | spin_lock_irqsave (&hmidi->lock, flags); | |
1202 | if (hmidi->output) { | |
1203 | if (!snd_rawmidi_transmit_empty (hmidi->output)) { | |
1204 | if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) { | |
1205 | if (n_pending > (int)sizeof (buf)) | |
1206 | n_pending = sizeof (buf); | |
1207 | ||
1208 | if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) { | |
1209 | for (i = 0; i < to_write; ++i) | |
1210 | snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); | |
1211 | } | |
1212 | } | |
1213 | } | |
1214 | } | |
1215 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi) | |
1220 | { | |
1221 | unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ | |
1222 | unsigned long flags; | |
1223 | int n_pending; | |
1224 | int i; | |
1225 | ||
1226 | spin_lock_irqsave (&hmidi->lock, flags); | |
1227 | if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { | |
1228 | if (hmidi->input) { | |
1229 | if (n_pending > (int)sizeof (buf)) { | |
1230 | n_pending = sizeof (buf); | |
1231 | } | |
1232 | for (i = 0; i < n_pending; ++i) { | |
1233 | buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); | |
1234 | } | |
1235 | if (n_pending) { | |
1236 | snd_rawmidi_receive (hmidi->input, buf, n_pending); | |
1237 | } | |
1238 | } else { | |
1239 | /* flush the MIDI input FIFO */ | |
1240 | while (--n_pending) { | |
1241 | snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); | |
1242 | } | |
1243 | } | |
1244 | } | |
1245 | hmidi->pending = 0; | |
1246 | if (hmidi->id) { | |
1247 | hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; | |
1248 | } else { | |
1249 | hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; | |
1250 | } | |
1251 | hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); | |
1252 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1253 | return snd_hdsp_midi_output_write (hmidi); | |
1254 | } | |
1255 | ||
1256 | static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up) | |
1257 | { | |
1258 | hdsp_t *hdsp; | |
1259 | hdsp_midi_t *hmidi; | |
1260 | unsigned long flags; | |
1261 | u32 ie; | |
1262 | ||
1263 | hmidi = (hdsp_midi_t *) substream->rmidi->private_data; | |
1264 | hdsp = hmidi->hdsp; | |
1265 | ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; | |
1266 | spin_lock_irqsave (&hdsp->lock, flags); | |
1267 | if (up) { | |
1268 | if (!(hdsp->control_register & ie)) { | |
1269 | snd_hdsp_flush_midi_input (hdsp, hmidi->id); | |
1270 | hdsp->control_register |= ie; | |
1271 | } | |
1272 | } else { | |
1273 | hdsp->control_register &= ~ie; | |
1274 | tasklet_kill(&hdsp->midi_tasklet); | |
1275 | } | |
1276 | ||
1277 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1278 | spin_unlock_irqrestore (&hdsp->lock, flags); | |
1279 | } | |
1280 | ||
1281 | static void snd_hdsp_midi_output_timer(unsigned long data) | |
1282 | { | |
1283 | hdsp_midi_t *hmidi = (hdsp_midi_t *) data; | |
1284 | unsigned long flags; | |
1285 | ||
1286 | snd_hdsp_midi_output_write(hmidi); | |
1287 | spin_lock_irqsave (&hmidi->lock, flags); | |
1288 | ||
1289 | /* this does not bump hmidi->istimer, because the | |
1290 | kernel automatically removed the timer when it | |
1291 | expired, and we are now adding it back, thus | |
1292 | leaving istimer wherever it was set before. | |
1293 | */ | |
1294 | ||
1295 | if (hmidi->istimer) { | |
1296 | hmidi->timer.expires = 1 + jiffies; | |
1297 | add_timer(&hmidi->timer); | |
1298 | } | |
1299 | ||
1300 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1301 | } | |
1302 | ||
1303 | static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up) | |
1304 | { | |
1305 | hdsp_midi_t *hmidi; | |
1306 | unsigned long flags; | |
1307 | ||
1308 | hmidi = (hdsp_midi_t *) substream->rmidi->private_data; | |
1309 | spin_lock_irqsave (&hmidi->lock, flags); | |
1310 | if (up) { | |
1311 | if (!hmidi->istimer) { | |
1312 | init_timer(&hmidi->timer); | |
1313 | hmidi->timer.function = snd_hdsp_midi_output_timer; | |
1314 | hmidi->timer.data = (unsigned long) hmidi; | |
1315 | hmidi->timer.expires = 1 + jiffies; | |
1316 | add_timer(&hmidi->timer); | |
1317 | hmidi->istimer++; | |
1318 | } | |
1319 | } else { | |
1320 | if (hmidi->istimer && --hmidi->istimer <= 0) { | |
1321 | del_timer (&hmidi->timer); | |
1322 | } | |
1323 | } | |
1324 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1325 | if (up) | |
1326 | snd_hdsp_midi_output_write(hmidi); | |
1327 | } | |
1328 | ||
1329 | static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream) | |
1330 | { | |
1331 | hdsp_midi_t *hmidi; | |
1332 | ||
1333 | hmidi = (hdsp_midi_t *) substream->rmidi->private_data; | |
1334 | spin_lock_irq (&hmidi->lock); | |
1335 | snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); | |
1336 | hmidi->input = substream; | |
1337 | spin_unlock_irq (&hmidi->lock); | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream) | |
1343 | { | |
1344 | hdsp_midi_t *hmidi; | |
1345 | ||
1346 | hmidi = (hdsp_midi_t *) substream->rmidi->private_data; | |
1347 | spin_lock_irq (&hmidi->lock); | |
1348 | hmidi->output = substream; | |
1349 | spin_unlock_irq (&hmidi->lock); | |
1350 | ||
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream) | |
1355 | { | |
1356 | hdsp_midi_t *hmidi; | |
1357 | ||
1358 | snd_hdsp_midi_input_trigger (substream, 0); | |
1359 | ||
1360 | hmidi = (hdsp_midi_t *) substream->rmidi->private_data; | |
1361 | spin_lock_irq (&hmidi->lock); | |
1362 | hmidi->input = NULL; | |
1363 | spin_unlock_irq (&hmidi->lock); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream) | |
1369 | { | |
1370 | hdsp_midi_t *hmidi; | |
1371 | ||
1372 | snd_hdsp_midi_output_trigger (substream, 0); | |
1373 | ||
1374 | hmidi = (hdsp_midi_t *) substream->rmidi->private_data; | |
1375 | spin_lock_irq (&hmidi->lock); | |
1376 | hmidi->output = NULL; | |
1377 | spin_unlock_irq (&hmidi->lock); | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | static snd_rawmidi_ops_t snd_hdsp_midi_output = | |
1383 | { | |
1384 | .open = snd_hdsp_midi_output_open, | |
1385 | .close = snd_hdsp_midi_output_close, | |
1386 | .trigger = snd_hdsp_midi_output_trigger, | |
1387 | }; | |
1388 | ||
1389 | static snd_rawmidi_ops_t snd_hdsp_midi_input = | |
1390 | { | |
1391 | .open = snd_hdsp_midi_input_open, | |
1392 | .close = snd_hdsp_midi_input_close, | |
1393 | .trigger = snd_hdsp_midi_input_trigger, | |
1394 | }; | |
1395 | ||
1396 | static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id) | |
1397 | { | |
1398 | char buf[32]; | |
1399 | ||
1400 | hdsp->midi[id].id = id; | |
1401 | hdsp->midi[id].rmidi = NULL; | |
1402 | hdsp->midi[id].input = NULL; | |
1403 | hdsp->midi[id].output = NULL; | |
1404 | hdsp->midi[id].hdsp = hdsp; | |
1405 | hdsp->midi[id].istimer = 0; | |
1406 | hdsp->midi[id].pending = 0; | |
1407 | spin_lock_init (&hdsp->midi[id].lock); | |
1408 | ||
1409 | sprintf (buf, "%s MIDI %d", card->shortname, id+1); | |
1410 | if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) { | |
1411 | return -1; | |
1412 | } | |
1413 | ||
1414 | sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1); | |
1415 | hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; | |
1416 | ||
1417 | snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); | |
1418 | snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); | |
1419 | ||
1420 | hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | | |
1421 | SNDRV_RAWMIDI_INFO_INPUT | | |
1422 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | /*----------------------------------------------------------------------------- | |
1428 | Control Interface | |
1429 | ----------------------------------------------------------------------------*/ | |
1430 | ||
1431 | static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes) | |
1432 | { | |
1433 | u32 val = 0; | |
1434 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; | |
1435 | val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; | |
1436 | if (val & HDSP_SPDIFProfessional) | |
1437 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; | |
1438 | else | |
1439 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; | |
1440 | return val; | |
1441 | } | |
1442 | ||
1443 | static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val) | |
1444 | { | |
1445 | aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | | |
1446 | ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); | |
1447 | if (val & HDSP_SPDIFProfessional) | |
1448 | aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; | |
1449 | else | |
1450 | aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; | |
1451 | } | |
1452 | ||
1453 | static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1454 | { | |
1455 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1456 | uinfo->count = 1; | |
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1461 | { | |
1462 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1463 | ||
1464 | snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); | |
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1469 | { | |
1470 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1471 | int change; | |
1472 | u32 val; | |
1473 | ||
1474 | val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); | |
1475 | spin_lock_irq(&hdsp->lock); | |
1476 | change = val != hdsp->creg_spdif; | |
1477 | hdsp->creg_spdif = val; | |
1478 | spin_unlock_irq(&hdsp->lock); | |
1479 | return change; | |
1480 | } | |
1481 | ||
1482 | static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1483 | { | |
1484 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1485 | uinfo->count = 1; | |
1486 | return 0; | |
1487 | } | |
1488 | ||
1489 | static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1490 | { | |
1491 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1492 | ||
1493 | snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); | |
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1498 | { | |
1499 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1500 | int change; | |
1501 | u32 val; | |
1502 | ||
1503 | val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); | |
1504 | spin_lock_irq(&hdsp->lock); | |
1505 | change = val != hdsp->creg_spdif_stream; | |
1506 | hdsp->creg_spdif_stream = val; | |
1507 | hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); | |
1508 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); | |
1509 | spin_unlock_irq(&hdsp->lock); | |
1510 | return change; | |
1511 | } | |
1512 | ||
1513 | static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1514 | { | |
1515 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1516 | uinfo->count = 1; | |
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1521 | { | |
1522 | ucontrol->value.iec958.status[0] = kcontrol->private_value; | |
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | #define HDSP_SPDIF_IN(xname, xindex) \ | |
1527 | { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ | |
1528 | .name = xname, \ | |
1529 | .index = xindex, \ | |
1530 | .info = snd_hdsp_info_spdif_in, \ | |
1531 | .get = snd_hdsp_get_spdif_in, \ | |
1532 | .put = snd_hdsp_put_spdif_in } | |
1533 | ||
1534 | static unsigned int hdsp_spdif_in(hdsp_t *hdsp) | |
1535 | { | |
1536 | return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); | |
1537 | } | |
1538 | ||
1539 | static int hdsp_set_spdif_input(hdsp_t *hdsp, int in) | |
1540 | { | |
1541 | hdsp->control_register &= ~HDSP_SPDIFInputMask; | |
1542 | hdsp->control_register |= hdsp_encode_spdif_in(in); | |
1543 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1548 | { | |
1549 | static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; | |
1550 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1551 | ||
1552 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1553 | uinfo->count = 1; | |
1554 | uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); | |
1555 | if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) | |
1556 | uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); | |
1557 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1562 | { | |
1563 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1564 | ||
1565 | ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); | |
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1570 | { | |
1571 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1572 | int change; | |
1573 | unsigned int val; | |
1574 | ||
1575 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1576 | return -EBUSY; | |
1577 | val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); | |
1578 | spin_lock_irq(&hdsp->lock); | |
1579 | change = val != hdsp_spdif_in(hdsp); | |
1580 | if (change) | |
1581 | hdsp_set_spdif_input(hdsp, val); | |
1582 | spin_unlock_irq(&hdsp->lock); | |
1583 | return change; | |
1584 | } | |
1585 | ||
1586 | #define HDSP_SPDIF_OUT(xname, xindex) \ | |
1587 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ | |
1588 | .info = snd_hdsp_info_spdif_bits, \ | |
1589 | .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } | |
1590 | ||
1591 | static int hdsp_spdif_out(hdsp_t *hdsp) | |
1592 | { | |
1593 | return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0; | |
1594 | } | |
1595 | ||
1596 | static int hdsp_set_spdif_output(hdsp_t *hdsp, int out) | |
1597 | { | |
1598 | if (out) { | |
1599 | hdsp->control_register |= HDSP_SPDIFOpticalOut; | |
1600 | } else { | |
1601 | hdsp->control_register &= ~HDSP_SPDIFOpticalOut; | |
1602 | } | |
1603 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1608 | { | |
1609 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
1610 | uinfo->count = 1; | |
1611 | uinfo->value.integer.min = 0; | |
1612 | uinfo->value.integer.max = 1; | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1617 | { | |
1618 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1619 | ||
1620 | ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); | |
1621 | return 0; | |
1622 | } | |
1623 | ||
1624 | static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1625 | { | |
1626 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1627 | int change; | |
1628 | unsigned int val; | |
1629 | ||
1630 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1631 | return -EBUSY; | |
1632 | val = ucontrol->value.integer.value[0] & 1; | |
1633 | spin_lock_irq(&hdsp->lock); | |
1634 | change = (int)val != hdsp_spdif_out(hdsp); | |
1635 | hdsp_set_spdif_output(hdsp, val); | |
1636 | spin_unlock_irq(&hdsp->lock); | |
1637 | return change; | |
1638 | } | |
1639 | ||
1640 | #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ | |
1641 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ | |
1642 | .info = snd_hdsp_info_spdif_bits, \ | |
1643 | .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } | |
1644 | ||
1645 | static int hdsp_spdif_professional(hdsp_t *hdsp) | |
1646 | { | |
1647 | return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; | |
1648 | } | |
1649 | ||
1650 | static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val) | |
1651 | { | |
1652 | if (val) { | |
1653 | hdsp->control_register |= HDSP_SPDIFProfessional; | |
1654 | } else { | |
1655 | hdsp->control_register &= ~HDSP_SPDIFProfessional; | |
1656 | } | |
1657 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1662 | { | |
1663 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1664 | ||
1665 | ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); | |
1666 | return 0; | |
1667 | } | |
1668 | ||
1669 | static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1670 | { | |
1671 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1672 | int change; | |
1673 | unsigned int val; | |
1674 | ||
1675 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1676 | return -EBUSY; | |
1677 | val = ucontrol->value.integer.value[0] & 1; | |
1678 | spin_lock_irq(&hdsp->lock); | |
1679 | change = (int)val != hdsp_spdif_professional(hdsp); | |
1680 | hdsp_set_spdif_professional(hdsp, val); | |
1681 | spin_unlock_irq(&hdsp->lock); | |
1682 | return change; | |
1683 | } | |
1684 | ||
1685 | #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ | |
1686 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ | |
1687 | .info = snd_hdsp_info_spdif_bits, \ | |
1688 | .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } | |
1689 | ||
1690 | static int hdsp_spdif_emphasis(hdsp_t *hdsp) | |
1691 | { | |
1692 | return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; | |
1693 | } | |
1694 | ||
1695 | static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val) | |
1696 | { | |
1697 | if (val) { | |
1698 | hdsp->control_register |= HDSP_SPDIFEmphasis; | |
1699 | } else { | |
1700 | hdsp->control_register &= ~HDSP_SPDIFEmphasis; | |
1701 | } | |
1702 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1707 | { | |
1708 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1709 | ||
1710 | ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); | |
1711 | return 0; | |
1712 | } | |
1713 | ||
1714 | static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1715 | { | |
1716 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1717 | int change; | |
1718 | unsigned int val; | |
1719 | ||
1720 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1721 | return -EBUSY; | |
1722 | val = ucontrol->value.integer.value[0] & 1; | |
1723 | spin_lock_irq(&hdsp->lock); | |
1724 | change = (int)val != hdsp_spdif_emphasis(hdsp); | |
1725 | hdsp_set_spdif_emphasis(hdsp, val); | |
1726 | spin_unlock_irq(&hdsp->lock); | |
1727 | return change; | |
1728 | } | |
1729 | ||
1730 | #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ | |
1731 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \ | |
1732 | .info = snd_hdsp_info_spdif_bits, \ | |
1733 | .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } | |
1734 | ||
1735 | static int hdsp_spdif_nonaudio(hdsp_t *hdsp) | |
1736 | { | |
1737 | return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; | |
1738 | } | |
1739 | ||
1740 | static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val) | |
1741 | { | |
1742 | if (val) { | |
1743 | hdsp->control_register |= HDSP_SPDIFNonAudio; | |
1744 | } else { | |
1745 | hdsp->control_register &= ~HDSP_SPDIFNonAudio; | |
1746 | } | |
1747 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
1748 | return 0; | |
1749 | } | |
1750 | ||
1751 | static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1752 | { | |
1753 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1754 | ||
1755 | ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); | |
1756 | return 0; | |
1757 | } | |
1758 | ||
1759 | static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1760 | { | |
1761 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1762 | int change; | |
1763 | unsigned int val; | |
1764 | ||
1765 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
1766 | return -EBUSY; | |
1767 | val = ucontrol->value.integer.value[0] & 1; | |
1768 | spin_lock_irq(&hdsp->lock); | |
1769 | change = (int)val != hdsp_spdif_nonaudio(hdsp); | |
1770 | hdsp_set_spdif_nonaudio(hdsp, val); | |
1771 | spin_unlock_irq(&hdsp->lock); | |
1772 | return change; | |
1773 | } | |
1774 | ||
1775 | #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ | |
1776 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
1777 | .name = xname, \ | |
1778 | .index = xindex, \ | |
1779 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1780 | .info = snd_hdsp_info_spdif_sample_rate, \ | |
1781 | .get = snd_hdsp_get_spdif_sample_rate \ | |
1782 | } | |
1783 | ||
1784 | static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1785 | { | |
1786 | static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; | |
1787 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1788 | ||
1789 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1790 | uinfo->count = 1; | |
1791 | uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; | |
1792 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1793 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1794 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1799 | { | |
1800 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1801 | ||
1802 | switch (hdsp_spdif_sample_rate(hdsp)) { | |
1803 | case 32000: | |
1804 | ucontrol->value.enumerated.item[0] = 0; | |
1805 | break; | |
1806 | case 44100: | |
1807 | ucontrol->value.enumerated.item[0] = 1; | |
1808 | break; | |
1809 | case 48000: | |
1810 | ucontrol->value.enumerated.item[0] = 2; | |
1811 | break; | |
1812 | case 64000: | |
1813 | ucontrol->value.enumerated.item[0] = 3; | |
1814 | break; | |
1815 | case 88200: | |
1816 | ucontrol->value.enumerated.item[0] = 4; | |
1817 | break; | |
1818 | case 96000: | |
1819 | ucontrol->value.enumerated.item[0] = 5; | |
1820 | break; | |
1821 | case 128000: | |
1822 | ucontrol->value.enumerated.item[0] = 7; | |
1823 | break; | |
1824 | case 176400: | |
1825 | ucontrol->value.enumerated.item[0] = 8; | |
1826 | break; | |
1827 | case 192000: | |
1828 | ucontrol->value.enumerated.item[0] = 9; | |
1829 | break; | |
1830 | default: | |
1831 | ucontrol->value.enumerated.item[0] = 6; | |
1832 | } | |
1833 | return 0; | |
1834 | } | |
1835 | ||
1836 | #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ | |
1837 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
1838 | .name = xname, \ | |
1839 | .index = xindex, \ | |
1840 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1841 | .info = snd_hdsp_info_system_sample_rate, \ | |
1842 | .get = snd_hdsp_get_system_sample_rate \ | |
1843 | } | |
1844 | ||
1845 | static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1846 | { | |
1847 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1848 | uinfo->count = 1; | |
1849 | return 0; | |
1850 | } | |
1851 | ||
1852 | static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1853 | { | |
1854 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1855 | ||
1856 | ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; | |
1857 | return 0; | |
1858 | } | |
1859 | ||
1860 | #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ | |
1861 | { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ | |
1862 | .name = xname, \ | |
1863 | .index = xindex, \ | |
1864 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1865 | .info = snd_hdsp_info_autosync_sample_rate, \ | |
1866 | .get = snd_hdsp_get_autosync_sample_rate \ | |
1867 | } | |
1868 | ||
1869 | static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1870 | { | |
1871 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1872 | static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; | |
1873 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1874 | uinfo->count = 1; | |
1875 | uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; | |
1876 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1877 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1878 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1883 | { | |
1884 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1885 | ||
1886 | switch (hdsp_external_sample_rate(hdsp)) { | |
1887 | case 32000: | |
1888 | ucontrol->value.enumerated.item[0] = 0; | |
1889 | break; | |
1890 | case 44100: | |
1891 | ucontrol->value.enumerated.item[0] = 1; | |
1892 | break; | |
1893 | case 48000: | |
1894 | ucontrol->value.enumerated.item[0] = 2; | |
1895 | break; | |
1896 | case 64000: | |
1897 | ucontrol->value.enumerated.item[0] = 3; | |
1898 | break; | |
1899 | case 88200: | |
1900 | ucontrol->value.enumerated.item[0] = 4; | |
1901 | break; | |
1902 | case 96000: | |
1903 | ucontrol->value.enumerated.item[0] = 5; | |
1904 | break; | |
1905 | case 128000: | |
1906 | ucontrol->value.enumerated.item[0] = 7; | |
1907 | break; | |
1908 | case 176400: | |
1909 | ucontrol->value.enumerated.item[0] = 8; | |
1910 | break; | |
1911 | case 192000: | |
1912 | ucontrol->value.enumerated.item[0] = 9; | |
1913 | break; | |
1914 | default: | |
1915 | ucontrol->value.enumerated.item[0] = 6; | |
1916 | } | |
1917 | return 0; | |
1918 | } | |
1919 | ||
1920 | #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ | |
1921 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
1922 | .name = xname, \ | |
1923 | .index = xindex, \ | |
1924 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1925 | .info = snd_hdsp_info_system_clock_mode, \ | |
1926 | .get = snd_hdsp_get_system_clock_mode \ | |
1927 | } | |
1928 | ||
1929 | static int hdsp_system_clock_mode(hdsp_t *hdsp) | |
1930 | { | |
1931 | if (hdsp->control_register & HDSP_ClockModeMaster) { | |
1932 | return 0; | |
1933 | } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) { | |
1934 | return 0; | |
1935 | } | |
1936 | return 1; | |
1937 | } | |
1938 | ||
1939 | static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
1940 | { | |
1941 | static char *texts[] = {"Master", "Slave" }; | |
1942 | ||
1943 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1944 | uinfo->count = 1; | |
1945 | uinfo->value.enumerated.items = 2; | |
1946 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1947 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
1948 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
1953 | { | |
1954 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
1955 | ||
1956 | ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); | |
1957 | return 0; | |
1958 | } | |
1959 | ||
1960 | #define HDSP_CLOCK_SOURCE(xname, xindex) \ | |
1961 | { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \ | |
1962 | .name = xname, \ | |
1963 | .index = xindex, \ | |
1964 | .info = snd_hdsp_info_clock_source, \ | |
1965 | .get = snd_hdsp_get_clock_source, \ | |
1966 | .put = snd_hdsp_put_clock_source \ | |
1967 | } | |
1968 | ||
1969 | static int hdsp_clock_source(hdsp_t *hdsp) | |
1970 | { | |
1971 | if (hdsp->control_register & HDSP_ClockModeMaster) { | |
1972 | switch (hdsp->system_sample_rate) { | |
1973 | case 32000: | |
1974 | return 1; | |
1975 | case 44100: | |
1976 | return 2; | |
1977 | case 48000: | |
1978 | return 3; | |
1979 | case 64000: | |
1980 | return 4; | |
1981 | case 88200: | |
1982 | return 5; | |
1983 | case 96000: | |
1984 | return 6; | |
1985 | case 128000: | |
1986 | return 7; | |
1987 | case 176400: | |
1988 | return 8; | |
1989 | case 192000: | |
1990 | return 9; | |
1991 | default: | |
1992 | return 3; | |
1993 | } | |
1994 | } else { | |
1995 | return 0; | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | static int hdsp_set_clock_source(hdsp_t *hdsp, int mode) | |
2000 | { | |
2001 | int rate; | |
2002 | switch (mode) { | |
2003 | case HDSP_CLOCK_SOURCE_AUTOSYNC: | |
2004 | if (hdsp_external_sample_rate(hdsp) != 0) { | |
2005 | if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { | |
2006 | hdsp->control_register &= ~HDSP_ClockModeMaster; | |
2007 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2008 | return 0; | |
2009 | } | |
2010 | } | |
2011 | return -1; | |
2012 | case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: | |
2013 | rate = 32000; | |
2014 | break; | |
2015 | case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
2016 | rate = 44100; | |
2017 | break; | |
2018 | case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: | |
2019 | rate = 48000; | |
2020 | break; | |
2021 | case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: | |
2022 | rate = 64000; | |
2023 | break; | |
2024 | case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
2025 | rate = 88200; | |
2026 | break; | |
2027 | case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: | |
2028 | rate = 96000; | |
2029 | break; | |
2030 | case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: | |
2031 | rate = 128000; | |
2032 | break; | |
2033 | case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
2034 | rate = 176400; | |
2035 | break; | |
2036 | case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: | |
2037 | rate = 192000; | |
2038 | break; | |
2039 | default: | |
2040 | rate = 48000; | |
2041 | } | |
2042 | hdsp->control_register |= HDSP_ClockModeMaster; | |
2043 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2044 | hdsp_set_rate(hdsp, rate, 1); | |
2045 | return 0; | |
2046 | } | |
2047 | ||
2048 | static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2049 | { | |
2050 | static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; | |
2051 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2052 | ||
2053 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2054 | uinfo->count = 1; | |
2055 | if (hdsp->io_type == H9632) | |
2056 | uinfo->value.enumerated.items = 10; | |
2057 | else | |
2058 | uinfo->value.enumerated.items = 7; | |
2059 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2060 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2061 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2062 | return 0; | |
2063 | } | |
2064 | ||
2065 | static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2066 | { | |
2067 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2068 | ||
2069 | ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); | |
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2074 | { | |
2075 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2076 | int change; | |
2077 | int val; | |
2078 | ||
2079 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2080 | return -EBUSY; | |
2081 | val = ucontrol->value.enumerated.item[0]; | |
2082 | if (val < 0) val = 0; | |
2083 | if (hdsp->io_type == H9632) { | |
2084 | if (val > 9) val = 9; | |
2085 | } else { | |
2086 | if (val > 6) val = 6; | |
2087 | } | |
2088 | spin_lock_irq(&hdsp->lock); | |
2089 | if (val != hdsp_clock_source(hdsp)) { | |
2090 | change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; | |
2091 | } else { | |
2092 | change = 0; | |
2093 | } | |
2094 | spin_unlock_irq(&hdsp->lock); | |
2095 | return change; | |
2096 | } | |
2097 | ||
2098 | #define HDSP_DA_GAIN(xname, xindex) \ | |
2099 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2100 | .name = xname, \ | |
2101 | .index = xindex, \ | |
2102 | .info = snd_hdsp_info_da_gain, \ | |
2103 | .get = snd_hdsp_get_da_gain, \ | |
2104 | .put = snd_hdsp_put_da_gain \ | |
2105 | } | |
2106 | ||
2107 | static int hdsp_da_gain(hdsp_t *hdsp) | |
2108 | { | |
2109 | switch (hdsp->control_register & HDSP_DAGainMask) { | |
2110 | case HDSP_DAGainHighGain: | |
2111 | return 0; | |
2112 | case HDSP_DAGainPlus4dBu: | |
2113 | return 1; | |
2114 | case HDSP_DAGainMinus10dBV: | |
2115 | return 2; | |
2116 | default: | |
2117 | return 1; | |
2118 | } | |
2119 | } | |
2120 | ||
2121 | static int hdsp_set_da_gain(hdsp_t *hdsp, int mode) | |
2122 | { | |
2123 | hdsp->control_register &= ~HDSP_DAGainMask; | |
2124 | switch (mode) { | |
2125 | case 0: | |
2126 | hdsp->control_register |= HDSP_DAGainHighGain; | |
2127 | break; | |
2128 | case 1: | |
2129 | hdsp->control_register |= HDSP_DAGainPlus4dBu; | |
2130 | break; | |
2131 | case 2: | |
2132 | hdsp->control_register |= HDSP_DAGainMinus10dBV; | |
2133 | break; | |
2134 | default: | |
2135 | return -1; | |
2136 | ||
2137 | } | |
2138 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2139 | return 0; | |
2140 | } | |
2141 | ||
2142 | static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2143 | { | |
2144 | static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; | |
2145 | ||
2146 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2147 | uinfo->count = 1; | |
2148 | uinfo->value.enumerated.items = 3; | |
2149 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2150 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2151 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2152 | return 0; | |
2153 | } | |
2154 | ||
2155 | static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2156 | { | |
2157 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2158 | ||
2159 | ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); | |
2160 | return 0; | |
2161 | } | |
2162 | ||
2163 | static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2164 | { | |
2165 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2166 | int change; | |
2167 | int val; | |
2168 | ||
2169 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2170 | return -EBUSY; | |
2171 | val = ucontrol->value.enumerated.item[0]; | |
2172 | if (val < 0) val = 0; | |
2173 | if (val > 2) val = 2; | |
2174 | spin_lock_irq(&hdsp->lock); | |
2175 | if (val != hdsp_da_gain(hdsp)) { | |
2176 | change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; | |
2177 | } else { | |
2178 | change = 0; | |
2179 | } | |
2180 | spin_unlock_irq(&hdsp->lock); | |
2181 | return change; | |
2182 | } | |
2183 | ||
2184 | #define HDSP_AD_GAIN(xname, xindex) \ | |
2185 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2186 | .name = xname, \ | |
2187 | .index = xindex, \ | |
2188 | .info = snd_hdsp_info_ad_gain, \ | |
2189 | .get = snd_hdsp_get_ad_gain, \ | |
2190 | .put = snd_hdsp_put_ad_gain \ | |
2191 | } | |
2192 | ||
2193 | static int hdsp_ad_gain(hdsp_t *hdsp) | |
2194 | { | |
2195 | switch (hdsp->control_register & HDSP_ADGainMask) { | |
2196 | case HDSP_ADGainMinus10dBV: | |
2197 | return 0; | |
2198 | case HDSP_ADGainPlus4dBu: | |
2199 | return 1; | |
2200 | case HDSP_ADGainLowGain: | |
2201 | return 2; | |
2202 | default: | |
2203 | return 1; | |
2204 | } | |
2205 | } | |
2206 | ||
2207 | static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode) | |
2208 | { | |
2209 | hdsp->control_register &= ~HDSP_ADGainMask; | |
2210 | switch (mode) { | |
2211 | case 0: | |
2212 | hdsp->control_register |= HDSP_ADGainMinus10dBV; | |
2213 | break; | |
2214 | case 1: | |
2215 | hdsp->control_register |= HDSP_ADGainPlus4dBu; | |
2216 | break; | |
2217 | case 2: | |
2218 | hdsp->control_register |= HDSP_ADGainLowGain; | |
2219 | break; | |
2220 | default: | |
2221 | return -1; | |
2222 | ||
2223 | } | |
2224 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2229 | { | |
2230 | static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; | |
2231 | ||
2232 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2233 | uinfo->count = 1; | |
2234 | uinfo->value.enumerated.items = 3; | |
2235 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2236 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2237 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2238 | return 0; | |
2239 | } | |
2240 | ||
2241 | static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2242 | { | |
2243 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2244 | ||
2245 | ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); | |
2246 | return 0; | |
2247 | } | |
2248 | ||
2249 | static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2250 | { | |
2251 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2252 | int change; | |
2253 | int val; | |
2254 | ||
2255 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2256 | return -EBUSY; | |
2257 | val = ucontrol->value.enumerated.item[0]; | |
2258 | if (val < 0) val = 0; | |
2259 | if (val > 2) val = 2; | |
2260 | spin_lock_irq(&hdsp->lock); | |
2261 | if (val != hdsp_ad_gain(hdsp)) { | |
2262 | change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; | |
2263 | } else { | |
2264 | change = 0; | |
2265 | } | |
2266 | spin_unlock_irq(&hdsp->lock); | |
2267 | return change; | |
2268 | } | |
2269 | ||
2270 | #define HDSP_PHONE_GAIN(xname, xindex) \ | |
2271 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2272 | .name = xname, \ | |
2273 | .index = xindex, \ | |
2274 | .info = snd_hdsp_info_phone_gain, \ | |
2275 | .get = snd_hdsp_get_phone_gain, \ | |
2276 | .put = snd_hdsp_put_phone_gain \ | |
2277 | } | |
2278 | ||
2279 | static int hdsp_phone_gain(hdsp_t *hdsp) | |
2280 | { | |
2281 | switch (hdsp->control_register & HDSP_PhoneGainMask) { | |
2282 | case HDSP_PhoneGain0dB: | |
2283 | return 0; | |
2284 | case HDSP_PhoneGainMinus6dB: | |
2285 | return 1; | |
2286 | case HDSP_PhoneGainMinus12dB: | |
2287 | return 2; | |
2288 | default: | |
2289 | return 0; | |
2290 | } | |
2291 | } | |
2292 | ||
2293 | static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode) | |
2294 | { | |
2295 | hdsp->control_register &= ~HDSP_PhoneGainMask; | |
2296 | switch (mode) { | |
2297 | case 0: | |
2298 | hdsp->control_register |= HDSP_PhoneGain0dB; | |
2299 | break; | |
2300 | case 1: | |
2301 | hdsp->control_register |= HDSP_PhoneGainMinus6dB; | |
2302 | break; | |
2303 | case 2: | |
2304 | hdsp->control_register |= HDSP_PhoneGainMinus12dB; | |
2305 | break; | |
2306 | default: | |
2307 | return -1; | |
2308 | ||
2309 | } | |
2310 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2315 | { | |
2316 | static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; | |
2317 | ||
2318 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2319 | uinfo->count = 1; | |
2320 | uinfo->value.enumerated.items = 3; | |
2321 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2322 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2323 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2324 | return 0; | |
2325 | } | |
2326 | ||
2327 | static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2328 | { | |
2329 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2330 | ||
2331 | ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); | |
2332 | return 0; | |
2333 | } | |
2334 | ||
2335 | static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2336 | { | |
2337 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2338 | int change; | |
2339 | int val; | |
2340 | ||
2341 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2342 | return -EBUSY; | |
2343 | val = ucontrol->value.enumerated.item[0]; | |
2344 | if (val < 0) val = 0; | |
2345 | if (val > 2) val = 2; | |
2346 | spin_lock_irq(&hdsp->lock); | |
2347 | if (val != hdsp_phone_gain(hdsp)) { | |
2348 | change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; | |
2349 | } else { | |
2350 | change = 0; | |
2351 | } | |
2352 | spin_unlock_irq(&hdsp->lock); | |
2353 | return change; | |
2354 | } | |
2355 | ||
2356 | #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ | |
2357 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2358 | .name = xname, \ | |
2359 | .index = xindex, \ | |
2360 | .info = snd_hdsp_info_xlr_breakout_cable, \ | |
2361 | .get = snd_hdsp_get_xlr_breakout_cable, \ | |
2362 | .put = snd_hdsp_put_xlr_breakout_cable \ | |
2363 | } | |
2364 | ||
2365 | static int hdsp_xlr_breakout_cable(hdsp_t *hdsp) | |
2366 | { | |
2367 | if (hdsp->control_register & HDSP_XLRBreakoutCable) { | |
2368 | return 1; | |
2369 | } | |
2370 | return 0; | |
2371 | } | |
2372 | ||
2373 | static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode) | |
2374 | { | |
2375 | if (mode) { | |
2376 | hdsp->control_register |= HDSP_XLRBreakoutCable; | |
2377 | } else { | |
2378 | hdsp->control_register &= ~HDSP_XLRBreakoutCable; | |
2379 | } | |
2380 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2381 | return 0; | |
2382 | } | |
2383 | ||
2384 | static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2385 | { | |
2386 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2387 | uinfo->count = 1; | |
2388 | uinfo->value.integer.min = 0; | |
2389 | uinfo->value.integer.max = 1; | |
2390 | return 0; | |
2391 | } | |
2392 | ||
2393 | static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2394 | { | |
2395 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2396 | ||
2397 | ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); | |
2398 | return 0; | |
2399 | } | |
2400 | ||
2401 | static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2402 | { | |
2403 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2404 | int change; | |
2405 | int val; | |
2406 | ||
2407 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2408 | return -EBUSY; | |
2409 | val = ucontrol->value.integer.value[0] & 1; | |
2410 | spin_lock_irq(&hdsp->lock); | |
2411 | change = (int)val != hdsp_xlr_breakout_cable(hdsp); | |
2412 | hdsp_set_xlr_breakout_cable(hdsp, val); | |
2413 | spin_unlock_irq(&hdsp->lock); | |
2414 | return change; | |
2415 | } | |
2416 | ||
2417 | /* (De)activates old RME Analog Extension Board | |
2418 | These are connected to the internal ADAT connector | |
2419 | Switching this on desactivates external ADAT | |
2420 | */ | |
2421 | #define HDSP_AEB(xname, xindex) \ | |
2422 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2423 | .name = xname, \ | |
2424 | .index = xindex, \ | |
2425 | .info = snd_hdsp_info_aeb, \ | |
2426 | .get = snd_hdsp_get_aeb, \ | |
2427 | .put = snd_hdsp_put_aeb \ | |
2428 | } | |
2429 | ||
2430 | static int hdsp_aeb(hdsp_t *hdsp) | |
2431 | { | |
2432 | if (hdsp->control_register & HDSP_AnalogExtensionBoard) { | |
2433 | return 1; | |
2434 | } | |
2435 | return 0; | |
2436 | } | |
2437 | ||
2438 | static int hdsp_set_aeb(hdsp_t *hdsp, int mode) | |
2439 | { | |
2440 | if (mode) { | |
2441 | hdsp->control_register |= HDSP_AnalogExtensionBoard; | |
2442 | } else { | |
2443 | hdsp->control_register &= ~HDSP_AnalogExtensionBoard; | |
2444 | } | |
2445 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2446 | return 0; | |
2447 | } | |
2448 | ||
2449 | static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2450 | { | |
2451 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2452 | uinfo->count = 1; | |
2453 | uinfo->value.integer.min = 0; | |
2454 | uinfo->value.integer.max = 1; | |
2455 | return 0; | |
2456 | } | |
2457 | ||
2458 | static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2459 | { | |
2460 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2461 | ||
2462 | ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); | |
2463 | return 0; | |
2464 | } | |
2465 | ||
2466 | static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2467 | { | |
2468 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2469 | int change; | |
2470 | int val; | |
2471 | ||
2472 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2473 | return -EBUSY; | |
2474 | val = ucontrol->value.integer.value[0] & 1; | |
2475 | spin_lock_irq(&hdsp->lock); | |
2476 | change = (int)val != hdsp_aeb(hdsp); | |
2477 | hdsp_set_aeb(hdsp, val); | |
2478 | spin_unlock_irq(&hdsp->lock); | |
2479 | return change; | |
2480 | } | |
2481 | ||
2482 | #define HDSP_PREF_SYNC_REF(xname, xindex) \ | |
2483 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2484 | .name = xname, \ | |
2485 | .index = xindex, \ | |
2486 | .info = snd_hdsp_info_pref_sync_ref, \ | |
2487 | .get = snd_hdsp_get_pref_sync_ref, \ | |
2488 | .put = snd_hdsp_put_pref_sync_ref \ | |
2489 | } | |
2490 | ||
2491 | static int hdsp_pref_sync_ref(hdsp_t *hdsp) | |
2492 | { | |
2493 | /* Notice that this looks at the requested sync source, | |
2494 | not the one actually in use. | |
2495 | */ | |
2496 | ||
2497 | switch (hdsp->control_register & HDSP_SyncRefMask) { | |
2498 | case HDSP_SyncRef_ADAT1: | |
2499 | return HDSP_SYNC_FROM_ADAT1; | |
2500 | case HDSP_SyncRef_ADAT2: | |
2501 | return HDSP_SYNC_FROM_ADAT2; | |
2502 | case HDSP_SyncRef_ADAT3: | |
2503 | return HDSP_SYNC_FROM_ADAT3; | |
2504 | case HDSP_SyncRef_SPDIF: | |
2505 | return HDSP_SYNC_FROM_SPDIF; | |
2506 | case HDSP_SyncRef_WORD: | |
2507 | return HDSP_SYNC_FROM_WORD; | |
2508 | case HDSP_SyncRef_ADAT_SYNC: | |
2509 | return HDSP_SYNC_FROM_ADAT_SYNC; | |
2510 | default: | |
2511 | return HDSP_SYNC_FROM_WORD; | |
2512 | } | |
2513 | return 0; | |
2514 | } | |
2515 | ||
2516 | static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref) | |
2517 | { | |
2518 | hdsp->control_register &= ~HDSP_SyncRefMask; | |
2519 | switch (pref) { | |
2520 | case HDSP_SYNC_FROM_ADAT1: | |
2521 | hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ | |
2522 | break; | |
2523 | case HDSP_SYNC_FROM_ADAT2: | |
2524 | hdsp->control_register |= HDSP_SyncRef_ADAT2; | |
2525 | break; | |
2526 | case HDSP_SYNC_FROM_ADAT3: | |
2527 | hdsp->control_register |= HDSP_SyncRef_ADAT3; | |
2528 | break; | |
2529 | case HDSP_SYNC_FROM_SPDIF: | |
2530 | hdsp->control_register |= HDSP_SyncRef_SPDIF; | |
2531 | break; | |
2532 | case HDSP_SYNC_FROM_WORD: | |
2533 | hdsp->control_register |= HDSP_SyncRef_WORD; | |
2534 | break; | |
2535 | case HDSP_SYNC_FROM_ADAT_SYNC: | |
2536 | hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; | |
2537 | break; | |
2538 | default: | |
2539 | return -1; | |
2540 | } | |
2541 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2542 | return 0; | |
2543 | } | |
2544 | ||
2545 | static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2546 | { | |
2547 | static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; | |
2548 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2549 | ||
2550 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2551 | uinfo->count = 1; | |
2552 | ||
2553 | switch (hdsp->io_type) { | |
2554 | case Digiface: | |
2555 | case H9652: | |
2556 | uinfo->value.enumerated.items = 6; | |
2557 | break; | |
2558 | case Multiface: | |
2559 | uinfo->value.enumerated.items = 4; | |
2560 | break; | |
2561 | case H9632: | |
2562 | uinfo->value.enumerated.items = 3; | |
2563 | break; | |
2564 | default: | |
2565 | uinfo->value.enumerated.items = 0; | |
2566 | break; | |
2567 | } | |
2568 | ||
2569 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2570 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2571 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2572 | return 0; | |
2573 | } | |
2574 | ||
2575 | static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2576 | { | |
2577 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2578 | ||
2579 | ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); | |
2580 | return 0; | |
2581 | } | |
2582 | ||
2583 | static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2584 | { | |
2585 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2586 | int change, max; | |
2587 | unsigned int val; | |
2588 | ||
2589 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2590 | return -EBUSY; | |
2591 | ||
2592 | switch (hdsp->io_type) { | |
2593 | case Digiface: | |
2594 | case H9652: | |
2595 | max = 6; | |
2596 | break; | |
2597 | case Multiface: | |
2598 | max = 4; | |
2599 | break; | |
2600 | case H9632: | |
2601 | max = 3; | |
2602 | break; | |
2603 | default: | |
2604 | return -EIO; | |
2605 | } | |
2606 | ||
2607 | val = ucontrol->value.enumerated.item[0] % max; | |
2608 | spin_lock_irq(&hdsp->lock); | |
2609 | change = (int)val != hdsp_pref_sync_ref(hdsp); | |
2610 | hdsp_set_pref_sync_ref(hdsp, val); | |
2611 | spin_unlock_irq(&hdsp->lock); | |
2612 | return change; | |
2613 | } | |
2614 | ||
2615 | #define HDSP_AUTOSYNC_REF(xname, xindex) \ | |
2616 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2617 | .name = xname, \ | |
2618 | .index = xindex, \ | |
2619 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2620 | .info = snd_hdsp_info_autosync_ref, \ | |
2621 | .get = snd_hdsp_get_autosync_ref, \ | |
2622 | } | |
2623 | ||
2624 | static int hdsp_autosync_ref(hdsp_t *hdsp) | |
2625 | { | |
2626 | /* This looks at the autosync selected sync reference */ | |
2627 | unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
2628 | ||
2629 | switch (status2 & HDSP_SelSyncRefMask) { | |
2630 | case HDSP_SelSyncRef_WORD: | |
2631 | return HDSP_AUTOSYNC_FROM_WORD; | |
2632 | case HDSP_SelSyncRef_ADAT_SYNC: | |
2633 | return HDSP_AUTOSYNC_FROM_ADAT_SYNC; | |
2634 | case HDSP_SelSyncRef_SPDIF: | |
2635 | return HDSP_AUTOSYNC_FROM_SPDIF; | |
2636 | case HDSP_SelSyncRefMask: | |
2637 | return HDSP_AUTOSYNC_FROM_NONE; | |
2638 | case HDSP_SelSyncRef_ADAT1: | |
2639 | return HDSP_AUTOSYNC_FROM_ADAT1; | |
2640 | case HDSP_SelSyncRef_ADAT2: | |
2641 | return HDSP_AUTOSYNC_FROM_ADAT2; | |
2642 | case HDSP_SelSyncRef_ADAT3: | |
2643 | return HDSP_AUTOSYNC_FROM_ADAT3; | |
2644 | default: | |
2645 | return HDSP_AUTOSYNC_FROM_WORD; | |
2646 | } | |
2647 | return 0; | |
2648 | } | |
2649 | ||
2650 | static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2651 | { | |
2652 | static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; | |
2653 | ||
2654 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2655 | uinfo->count = 1; | |
2656 | uinfo->value.enumerated.items = 7; | |
2657 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2658 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2659 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2660 | return 0; | |
2661 | } | |
2662 | ||
2663 | static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2664 | { | |
2665 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2666 | ||
2667 | ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); | |
2668 | return 0; | |
2669 | } | |
2670 | ||
2671 | #define HDSP_LINE_OUT(xname, xindex) \ | |
2672 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2673 | .name = xname, \ | |
2674 | .index = xindex, \ | |
2675 | .info = snd_hdsp_info_line_out, \ | |
2676 | .get = snd_hdsp_get_line_out, \ | |
2677 | .put = snd_hdsp_put_line_out \ | |
2678 | } | |
2679 | ||
2680 | static int hdsp_line_out(hdsp_t *hdsp) | |
2681 | { | |
2682 | return (hdsp->control_register & HDSP_LineOut) ? 1 : 0; | |
2683 | } | |
2684 | ||
2685 | static int hdsp_set_line_output(hdsp_t *hdsp, int out) | |
2686 | { | |
2687 | if (out) { | |
2688 | hdsp->control_register |= HDSP_LineOut; | |
2689 | } else { | |
2690 | hdsp->control_register &= ~HDSP_LineOut; | |
2691 | } | |
2692 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
2693 | return 0; | |
2694 | } | |
2695 | ||
2696 | static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2697 | { | |
2698 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2699 | uinfo->count = 1; | |
2700 | uinfo->value.integer.min = 0; | |
2701 | uinfo->value.integer.max = 1; | |
2702 | return 0; | |
2703 | } | |
2704 | ||
2705 | static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2706 | { | |
2707 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2708 | ||
2709 | spin_lock_irq(&hdsp->lock); | |
2710 | ucontrol->value.integer.value[0] = hdsp_line_out(hdsp); | |
2711 | spin_unlock_irq(&hdsp->lock); | |
2712 | return 0; | |
2713 | } | |
2714 | ||
2715 | static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2716 | { | |
2717 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2718 | int change; | |
2719 | unsigned int val; | |
2720 | ||
2721 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2722 | return -EBUSY; | |
2723 | val = ucontrol->value.integer.value[0] & 1; | |
2724 | spin_lock_irq(&hdsp->lock); | |
2725 | change = (int)val != hdsp_line_out(hdsp); | |
2726 | hdsp_set_line_output(hdsp, val); | |
2727 | spin_unlock_irq(&hdsp->lock); | |
2728 | return change; | |
2729 | } | |
2730 | ||
2731 | #define HDSP_PRECISE_POINTER(xname, xindex) \ | |
2732 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2733 | .name = xname, \ | |
2734 | .index = xindex, \ | |
2735 | .info = snd_hdsp_info_precise_pointer, \ | |
2736 | .get = snd_hdsp_get_precise_pointer, \ | |
2737 | .put = snd_hdsp_put_precise_pointer \ | |
2738 | } | |
2739 | ||
2740 | static int hdsp_set_precise_pointer(hdsp_t *hdsp, int precise) | |
2741 | { | |
2742 | if (precise) { | |
2743 | hdsp->precise_ptr = 1; | |
2744 | } else { | |
2745 | hdsp->precise_ptr = 0; | |
2746 | } | |
2747 | return 0; | |
2748 | } | |
2749 | ||
2750 | static int snd_hdsp_info_precise_pointer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2751 | { | |
2752 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2753 | uinfo->count = 1; | |
2754 | uinfo->value.integer.min = 0; | |
2755 | uinfo->value.integer.max = 1; | |
2756 | return 0; | |
2757 | } | |
2758 | ||
2759 | static int snd_hdsp_get_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2760 | { | |
2761 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2762 | ||
2763 | spin_lock_irq(&hdsp->lock); | |
2764 | ucontrol->value.integer.value[0] = hdsp->precise_ptr; | |
2765 | spin_unlock_irq(&hdsp->lock); | |
2766 | return 0; | |
2767 | } | |
2768 | ||
2769 | static int snd_hdsp_put_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2770 | { | |
2771 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2772 | int change; | |
2773 | unsigned int val; | |
2774 | ||
2775 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2776 | return -EBUSY; | |
2777 | val = ucontrol->value.integer.value[0] & 1; | |
2778 | spin_lock_irq(&hdsp->lock); | |
2779 | change = (int)val != hdsp->precise_ptr; | |
2780 | hdsp_set_precise_pointer(hdsp, val); | |
2781 | spin_unlock_irq(&hdsp->lock); | |
2782 | return change; | |
2783 | } | |
2784 | ||
2785 | #define HDSP_USE_MIDI_TASKLET(xname, xindex) \ | |
2786 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2787 | .name = xname, \ | |
2788 | .index = xindex, \ | |
2789 | .info = snd_hdsp_info_use_midi_tasklet, \ | |
2790 | .get = snd_hdsp_get_use_midi_tasklet, \ | |
2791 | .put = snd_hdsp_put_use_midi_tasklet \ | |
2792 | } | |
2793 | ||
2794 | static int hdsp_set_use_midi_tasklet(hdsp_t *hdsp, int use_tasklet) | |
2795 | { | |
2796 | if (use_tasklet) { | |
2797 | hdsp->use_midi_tasklet = 1; | |
2798 | } else { | |
2799 | hdsp->use_midi_tasklet = 0; | |
2800 | } | |
2801 | return 0; | |
2802 | } | |
2803 | ||
2804 | static int snd_hdsp_info_use_midi_tasklet(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2805 | { | |
2806 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2807 | uinfo->count = 1; | |
2808 | uinfo->value.integer.min = 0; | |
2809 | uinfo->value.integer.max = 1; | |
2810 | return 0; | |
2811 | } | |
2812 | ||
2813 | static int snd_hdsp_get_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2814 | { | |
2815 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2816 | ||
2817 | spin_lock_irq(&hdsp->lock); | |
2818 | ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet; | |
2819 | spin_unlock_irq(&hdsp->lock); | |
2820 | return 0; | |
2821 | } | |
2822 | ||
2823 | static int snd_hdsp_put_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2824 | { | |
2825 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2826 | int change; | |
2827 | unsigned int val; | |
2828 | ||
2829 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2830 | return -EBUSY; | |
2831 | val = ucontrol->value.integer.value[0] & 1; | |
2832 | spin_lock_irq(&hdsp->lock); | |
2833 | change = (int)val != hdsp->use_midi_tasklet; | |
2834 | hdsp_set_use_midi_tasklet(hdsp, val); | |
2835 | spin_unlock_irq(&hdsp->lock); | |
2836 | return change; | |
2837 | } | |
2838 | ||
2839 | #define HDSP_MIXER(xname, xindex) \ | |
2840 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2841 | .name = xname, \ | |
2842 | .index = xindex, \ | |
2843 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ | |
2844 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2845 | .info = snd_hdsp_info_mixer, \ | |
2846 | .get = snd_hdsp_get_mixer, \ | |
2847 | .put = snd_hdsp_put_mixer \ | |
2848 | } | |
2849 | ||
2850 | static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2851 | { | |
2852 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2853 | uinfo->count = 3; | |
2854 | uinfo->value.integer.min = 0; | |
2855 | uinfo->value.integer.max = 65536; | |
2856 | uinfo->value.integer.step = 1; | |
2857 | return 0; | |
2858 | } | |
2859 | ||
2860 | static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2861 | { | |
2862 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2863 | int source; | |
2864 | int destination; | |
2865 | int addr; | |
2866 | ||
2867 | source = ucontrol->value.integer.value[0]; | |
2868 | destination = ucontrol->value.integer.value[1]; | |
2869 | ||
2870 | if (source >= hdsp->max_channels) { | |
2871 | addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); | |
2872 | } else { | |
2873 | addr = hdsp_input_to_output_key(hdsp,source, destination); | |
2874 | } | |
2875 | ||
2876 | spin_lock_irq(&hdsp->lock); | |
2877 | ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); | |
2878 | spin_unlock_irq(&hdsp->lock); | |
2879 | return 0; | |
2880 | } | |
2881 | ||
2882 | static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2883 | { | |
2884 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2885 | int change; | |
2886 | int source; | |
2887 | int destination; | |
2888 | int gain; | |
2889 | int addr; | |
2890 | ||
2891 | if (!snd_hdsp_use_is_exclusive(hdsp)) | |
2892 | return -EBUSY; | |
2893 | ||
2894 | source = ucontrol->value.integer.value[0]; | |
2895 | destination = ucontrol->value.integer.value[1]; | |
2896 | ||
2897 | if (source >= hdsp->max_channels) { | |
2898 | addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); | |
2899 | } else { | |
2900 | addr = hdsp_input_to_output_key(hdsp,source, destination); | |
2901 | } | |
2902 | ||
2903 | gain = ucontrol->value.integer.value[2]; | |
2904 | ||
2905 | spin_lock_irq(&hdsp->lock); | |
2906 | change = gain != hdsp_read_gain(hdsp, addr); | |
2907 | if (change) | |
2908 | hdsp_write_gain(hdsp, addr, gain); | |
2909 | spin_unlock_irq(&hdsp->lock); | |
2910 | return change; | |
2911 | } | |
2912 | ||
2913 | #define HDSP_WC_SYNC_CHECK(xname, xindex) \ | |
2914 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2915 | .name = xname, \ | |
2916 | .index = xindex, \ | |
2917 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2918 | .info = snd_hdsp_info_sync_check, \ | |
2919 | .get = snd_hdsp_get_wc_sync_check \ | |
2920 | } | |
2921 | ||
2922 | static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) | |
2923 | { | |
2924 | static char *texts[] = {"No Lock", "Lock", "Sync" }; | |
2925 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2926 | uinfo->count = 1; | |
2927 | uinfo->value.enumerated.items = 3; | |
2928 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2929 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2930 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2931 | return 0; | |
2932 | } | |
2933 | ||
2934 | static int hdsp_wc_sync_check(hdsp_t *hdsp) | |
2935 | { | |
2936 | int status2 = hdsp_read(hdsp, HDSP_status2Register); | |
2937 | if (status2 & HDSP_wc_lock) { | |
2938 | if (status2 & HDSP_wc_sync) { | |
2939 | return 2; | |
2940 | } else { | |
2941 | return 1; | |
2942 | } | |
2943 | } else { | |
2944 | return 0; | |
2945 | } | |
2946 | return 0; | |
2947 | } | |
2948 | ||
2949 | static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2950 | { | |
2951 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2952 | ||
2953 | ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); | |
2954 | return 0; | |
2955 | } | |
2956 | ||
2957 | #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ | |
2958 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2959 | .name = xname, \ | |
2960 | .index = xindex, \ | |
2961 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2962 | .info = snd_hdsp_info_sync_check, \ | |
2963 | .get = snd_hdsp_get_spdif_sync_check \ | |
2964 | } | |
2965 | ||
2966 | static int hdsp_spdif_sync_check(hdsp_t *hdsp) | |
2967 | { | |
2968 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
2969 | if (status & HDSP_SPDIFErrorFlag) { | |
2970 | return 0; | |
2971 | } else { | |
2972 | if (status & HDSP_SPDIFSync) { | |
2973 | return 2; | |
2974 | } else { | |
2975 | return 1; | |
2976 | } | |
2977 | } | |
2978 | return 0; | |
2979 | } | |
2980 | ||
2981 | static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
2982 | { | |
2983 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
2984 | ||
2985 | ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); | |
2986 | return 0; | |
2987 | } | |
2988 | ||
2989 | #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ | |
2990 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2991 | .name = xname, \ | |
2992 | .index = xindex, \ | |
2993 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2994 | .info = snd_hdsp_info_sync_check, \ | |
2995 | .get = snd_hdsp_get_adatsync_sync_check \ | |
2996 | } | |
2997 | ||
2998 | static int hdsp_adatsync_sync_check(hdsp_t *hdsp) | |
2999 | { | |
3000 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
3001 | if (status & HDSP_TimecodeLock) { | |
3002 | if (status & HDSP_TimecodeSync) { | |
3003 | return 2; | |
3004 | } else { | |
3005 | return 1; | |
3006 | } | |
3007 | } else { | |
3008 | return 0; | |
3009 | } | |
3010 | } | |
3011 | ||
3012 | static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
3013 | { | |
3014 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
3015 | ||
3016 | ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); | |
3017 | return 0; | |
3018 | } | |
3019 | ||
3020 | #define HDSP_ADAT_SYNC_CHECK \ | |
3021 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
3022 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3023 | .info = snd_hdsp_info_sync_check, \ | |
3024 | .get = snd_hdsp_get_adat_sync_check \ | |
3025 | } | |
3026 | ||
3027 | static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx) | |
3028 | { | |
3029 | int status = hdsp_read(hdsp, HDSP_statusRegister); | |
3030 | ||
3031 | if (status & (HDSP_Lock0>>idx)) { | |
3032 | if (status & (HDSP_Sync0>>idx)) { | |
3033 | return 2; | |
3034 | } else { | |
3035 | return 1; | |
3036 | } | |
3037 | } else { | |
3038 | return 0; | |
3039 | } | |
3040 | } | |
3041 | ||
3042 | static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) | |
3043 | { | |
3044 | int offset; | |
3045 | hdsp_t *hdsp = snd_kcontrol_chip(kcontrol); | |
3046 | ||
3047 | offset = ucontrol->id.index - 1; | |
3048 | snd_assert(offset >= 0); | |
3049 | ||
3050 | switch (hdsp->io_type) { | |
3051 | case Digiface: | |
3052 | case H9652: | |
3053 | if (offset >= 3) | |
3054 | return -EINVAL; | |
3055 | break; | |
3056 | case Multiface: | |
3057 | case H9632: | |
3058 | if (offset >= 1) | |
3059 | return -EINVAL; | |
3060 | break; | |
3061 | default: | |
3062 | return -EIO; | |
3063 | } | |
3064 | ||
3065 | ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); | |
3066 | return 0; | |
3067 | } | |
3068 | ||
3069 | static snd_kcontrol_new_t snd_hdsp_9632_controls[] = { | |
3070 | HDSP_DA_GAIN("DA Gain", 0), | |
3071 | HDSP_AD_GAIN("AD Gain", 0), | |
3072 | HDSP_PHONE_GAIN("Phones Gain", 0), | |
3073 | HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0) | |
3074 | }; | |
3075 | ||
3076 | static snd_kcontrol_new_t snd_hdsp_controls[] = { | |
3077 | { | |
3078 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
3079 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), | |
3080 | .info = snd_hdsp_control_spdif_info, | |
3081 | .get = snd_hdsp_control_spdif_get, | |
3082 | .put = snd_hdsp_control_spdif_put, | |
3083 | }, | |
3084 | { | |
3085 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
3086 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
3087 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), | |
3088 | .info = snd_hdsp_control_spdif_stream_info, | |
3089 | .get = snd_hdsp_control_spdif_stream_get, | |
3090 | .put = snd_hdsp_control_spdif_stream_put, | |
3091 | }, | |
3092 | { | |
3093 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
3094 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
3095 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), | |
3096 | .info = snd_hdsp_control_spdif_mask_info, | |
3097 | .get = snd_hdsp_control_spdif_mask_get, | |
3098 | .private_value = IEC958_AES0_NONAUDIO | | |
3099 | IEC958_AES0_PROFESSIONAL | | |
3100 | IEC958_AES0_CON_EMPHASIS, | |
3101 | }, | |
3102 | { | |
3103 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
3104 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
3105 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), | |
3106 | .info = snd_hdsp_control_spdif_mask_info, | |
3107 | .get = snd_hdsp_control_spdif_mask_get, | |
3108 | .private_value = IEC958_AES0_NONAUDIO | | |
3109 | IEC958_AES0_PROFESSIONAL | | |
3110 | IEC958_AES0_PRO_EMPHASIS, | |
3111 | }, | |
3112 | HDSP_MIXER("Mixer", 0), | |
3113 | HDSP_SPDIF_IN("IEC958 Input Connector", 0), | |
3114 | HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), | |
3115 | HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), | |
3116 | HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), | |
3117 | HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), | |
3118 | /* 'Sample Clock Source' complies with the alsa control naming scheme */ | |
3119 | HDSP_CLOCK_SOURCE("Sample Clock Source", 0), | |
3120 | HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
3121 | HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
3122 | HDSP_AUTOSYNC_REF("AutoSync Reference", 0), | |
3123 | HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), | |
3124 | HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
3125 | /* 'External Rate' complies with the alsa control naming scheme */ | |
3126 | HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
3127 | HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), | |
3128 | HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), | |
3129 | HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), | |
3130 | HDSP_LINE_OUT("Line Out", 0), | |
3131 | HDSP_PRECISE_POINTER("Precise Pointer", 0), | |
3132 | HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0), | |
3133 | }; | |
3134 | ||
3135 | static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); | |
3136 | static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; | |
3137 | ||
3138 | static int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp) | |
3139 | { | |
3140 | unsigned int idx; | |
3141 | int err; | |
3142 | snd_kcontrol_t *kctl; | |
3143 | ||
3144 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { | |
3145 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) { | |
3146 | return err; | |
3147 | } | |
3148 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ | |
3149 | hdsp->spdif_ctl = kctl; | |
3150 | } | |
3151 | ||
3152 | /* ADAT SyncCheck status */ | |
3153 | snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; | |
3154 | snd_hdsp_adat_sync_check.index = 1; | |
3155 | if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) { | |
3156 | return err; | |
3157 | } | |
3158 | if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { | |
3159 | for (idx = 1; idx < 3; ++idx) { | |
3160 | snd_hdsp_adat_sync_check.index = idx+1; | |
3161 | if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) { | |
3162 | return err; | |
3163 | } | |
3164 | } | |
3165 | } | |
3166 | ||
3167 | /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ | |
3168 | if (hdsp->io_type == H9632) { | |
3169 | for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { | |
3170 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) { | |
3171 | return err; | |
3172 | } | |
3173 | } | |
3174 | } | |
3175 | ||
3176 | /* AEB control for H96xx card */ | |
3177 | if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { | |
3178 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) { | |
3179 | return err; | |
3180 | } | |
3181 | } | |
3182 | ||
3183 | return 0; | |
3184 | } | |
3185 | ||
3186 | /*------------------------------------------------------------ | |
3187 | /proc interface | |
3188 | ------------------------------------------------------------*/ | |
3189 | ||
3190 | static void | |
3191 | snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer) | |
3192 | { | |
3193 | hdsp_t *hdsp = (hdsp_t *) entry->private_data; | |
3194 | unsigned int status; | |
3195 | unsigned int status2; | |
3196 | char *pref_sync_ref; | |
3197 | char *autosync_ref; | |
3198 | char *system_clock_mode; | |
3199 | char *clock_source; | |
3200 | int x; | |
3201 | ||
3202 | if (hdsp_check_for_iobox (hdsp)) { | |
3203 | snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n"); | |
3204 | return; | |
3205 | } | |
3206 | ||
3207 | if (hdsp_check_for_firmware(hdsp)) { | |
3208 | if (hdsp->state & HDSP_FirmwareCached) { | |
3209 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
3210 | snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n"); | |
3211 | return; | |
3212 | } | |
3213 | } else { | |
3214 | snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n"); | |
3215 | return; | |
3216 | } | |
3217 | } | |
3218 | ||
3219 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
3220 | status2 = hdsp_read(hdsp, HDSP_status2Register); | |
3221 | ||
3222 | snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1); | |
3223 | snd_iprintf(buffer, "Buffers: capture %p playback %p\n", | |
3224 | hdsp->capture_buffer, hdsp->playback_buffer); | |
3225 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
3226 | hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); | |
3227 | snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); | |
3228 | snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register); | |
3229 | snd_iprintf(buffer, "Status register: 0x%x\n", status); | |
3230 | snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); | |
3231 | snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); | |
3232 | snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); | |
3233 | snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); | |
3234 | snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); | |
3235 | snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); | |
3236 | snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off"); | |
3237 | ||
3238 | snd_iprintf(buffer, "\n"); | |
3239 | ||
3240 | x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); | |
3241 | ||
3242 | snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); | |
3243 | snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); | |
3244 | snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); | |
3245 | snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); | |
3246 | ||
3247 | snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); | |
3248 | ||
3249 | snd_iprintf(buffer, "\n"); | |
3250 | ||
3251 | ||
3252 | switch (hdsp_clock_source(hdsp)) { | |
3253 | case HDSP_CLOCK_SOURCE_AUTOSYNC: | |
3254 | clock_source = "AutoSync"; | |
3255 | break; | |
3256 | case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: | |
3257 | clock_source = "Internal 32 kHz"; | |
3258 | break; | |
3259 | case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
3260 | clock_source = "Internal 44.1 kHz"; | |
3261 | break; | |
3262 | case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: | |
3263 | clock_source = "Internal 48 kHz"; | |
3264 | break; | |
3265 | case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: | |
3266 | clock_source = "Internal 64 kHz"; | |
3267 | break; | |
3268 | case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
3269 | clock_source = "Internal 88.2 kHz"; | |
3270 | break; | |
3271 | case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: | |
3272 | clock_source = "Internal 96 kHz"; | |
3273 | break; | |
3274 | case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: | |
3275 | clock_source = "Internal 128 kHz"; | |
3276 | break; | |
3277 | case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
3278 | clock_source = "Internal 176.4 kHz"; | |
3279 | break; | |
3280 | case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: | |
3281 | clock_source = "Internal 192 kHz"; | |
3282 | break; | |
3283 | default: | |
3284 | clock_source = "Error"; | |
3285 | } | |
3286 | snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); | |
3287 | ||
3288 | if (hdsp_system_clock_mode(hdsp)) { | |
3289 | system_clock_mode = "Slave"; | |
3290 | } else { | |
3291 | system_clock_mode = "Master"; | |
3292 | } | |
3293 | ||
3294 | switch (hdsp_pref_sync_ref (hdsp)) { | |
3295 | case HDSP_SYNC_FROM_WORD: | |
3296 | pref_sync_ref = "Word Clock"; | |
3297 | break; | |
3298 | case HDSP_SYNC_FROM_ADAT_SYNC: | |
3299 | pref_sync_ref = "ADAT Sync"; | |
3300 | break; | |
3301 | case HDSP_SYNC_FROM_SPDIF: | |
3302 | pref_sync_ref = "SPDIF"; | |
3303 | break; | |
3304 | case HDSP_SYNC_FROM_ADAT1: | |
3305 | pref_sync_ref = "ADAT1"; | |
3306 | break; | |
3307 | case HDSP_SYNC_FROM_ADAT2: | |
3308 | pref_sync_ref = "ADAT2"; | |
3309 | break; | |
3310 | case HDSP_SYNC_FROM_ADAT3: | |
3311 | pref_sync_ref = "ADAT3"; | |
3312 | break; | |
3313 | default: | |
3314 | pref_sync_ref = "Word Clock"; | |
3315 | break; | |
3316 | } | |
3317 | snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); | |
3318 | ||
3319 | switch (hdsp_autosync_ref (hdsp)) { | |
3320 | case HDSP_AUTOSYNC_FROM_WORD: | |
3321 | autosync_ref = "Word Clock"; | |
3322 | break; | |
3323 | case HDSP_AUTOSYNC_FROM_ADAT_SYNC: | |
3324 | autosync_ref = "ADAT Sync"; | |
3325 | break; | |
3326 | case HDSP_AUTOSYNC_FROM_SPDIF: | |
3327 | autosync_ref = "SPDIF"; | |
3328 | break; | |
3329 | case HDSP_AUTOSYNC_FROM_NONE: | |
3330 | autosync_ref = "None"; | |
3331 | break; | |
3332 | case HDSP_AUTOSYNC_FROM_ADAT1: | |
3333 | autosync_ref = "ADAT1"; | |
3334 | break; | |
3335 | case HDSP_AUTOSYNC_FROM_ADAT2: | |
3336 | autosync_ref = "ADAT2"; | |
3337 | break; | |
3338 | case HDSP_AUTOSYNC_FROM_ADAT3: | |
3339 | autosync_ref = "ADAT3"; | |
3340 | break; | |
3341 | default: | |
3342 | autosync_ref = "---"; | |
3343 | break; | |
3344 | } | |
3345 | snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); | |
3346 | ||
3347 | snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); | |
3348 | ||
3349 | snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); | |
3350 | ||
3351 | snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); | |
3352 | ||
3353 | snd_iprintf(buffer, "\n"); | |
3354 | ||
3355 | switch (hdsp_spdif_in(hdsp)) { | |
3356 | case HDSP_SPDIFIN_OPTICAL: | |
3357 | snd_iprintf(buffer, "IEC958 input: Optical\n"); | |
3358 | break; | |
3359 | case HDSP_SPDIFIN_COAXIAL: | |
3360 | snd_iprintf(buffer, "IEC958 input: Coaxial\n"); | |
3361 | break; | |
3362 | case HDSP_SPDIFIN_INTERNAL: | |
3363 | snd_iprintf(buffer, "IEC958 input: Internal\n"); | |
3364 | break; | |
3365 | case HDSP_SPDIFIN_AES: | |
3366 | snd_iprintf(buffer, "IEC958 input: AES\n"); | |
3367 | break; | |
3368 | default: | |
3369 | snd_iprintf(buffer, "IEC958 input: ???\n"); | |
3370 | break; | |
3371 | } | |
3372 | ||
3373 | if (hdsp->control_register & HDSP_SPDIFOpticalOut) { | |
3374 | snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); | |
3375 | } else { | |
3376 | snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); | |
3377 | } | |
3378 | ||
3379 | if (hdsp->control_register & HDSP_SPDIFProfessional) { | |
3380 | snd_iprintf(buffer, "IEC958 quality: Professional\n"); | |
3381 | } else { | |
3382 | snd_iprintf(buffer, "IEC958 quality: Consumer\n"); | |
3383 | } | |
3384 | ||
3385 | if (hdsp->control_register & HDSP_SPDIFEmphasis) { | |
3386 | snd_iprintf(buffer, "IEC958 emphasis: on\n"); | |
3387 | } else { | |
3388 | snd_iprintf(buffer, "IEC958 emphasis: off\n"); | |
3389 | } | |
3390 | ||
3391 | if (hdsp->control_register & HDSP_SPDIFNonAudio) { | |
3392 | snd_iprintf(buffer, "IEC958 NonAudio: on\n"); | |
3393 | } else { | |
3394 | snd_iprintf(buffer, "IEC958 NonAudio: off\n"); | |
3395 | } | |
3396 | if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) { | |
3397 | snd_iprintf (buffer, "IEC958 sample rate: %d\n", x); | |
3398 | } else { | |
3399 | snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n"); | |
3400 | } | |
3401 | ||
3402 | snd_iprintf(buffer, "\n"); | |
3403 | ||
3404 | /* Sync Check */ | |
3405 | x = status & HDSP_Sync0; | |
3406 | if (status & HDSP_Lock0) { | |
3407 | snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); | |
3408 | } else { | |
3409 | snd_iprintf(buffer, "ADAT1: No Lock\n"); | |
3410 | } | |
3411 | ||
3412 | switch (hdsp->io_type) { | |
3413 | case Digiface: | |
3414 | case H9652: | |
3415 | x = status & HDSP_Sync1; | |
3416 | if (status & HDSP_Lock1) { | |
3417 | snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); | |
3418 | } else { | |
3419 | snd_iprintf(buffer, "ADAT2: No Lock\n"); | |
3420 | } | |
3421 | x = status & HDSP_Sync2; | |
3422 | if (status & HDSP_Lock2) { | |
3423 | snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); | |
3424 | } else { | |
3425 | snd_iprintf(buffer, "ADAT3: No Lock\n"); | |
3426 | } | |
3427 | default: | |
3428 | /* relax */ | |
3429 | break; | |
3430 | } | |
3431 | ||
3432 | x = status & HDSP_SPDIFSync; | |
3433 | if (status & HDSP_SPDIFErrorFlag) { | |
3434 | snd_iprintf (buffer, "SPDIF: No Lock\n"); | |
3435 | } else { | |
3436 | snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); | |
3437 | } | |
3438 | ||
3439 | x = status2 & HDSP_wc_sync; | |
3440 | if (status2 & HDSP_wc_lock) { | |
3441 | snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); | |
3442 | } else { | |
3443 | snd_iprintf (buffer, "Word Clock: No Lock\n"); | |
3444 | } | |
3445 | ||
3446 | x = status & HDSP_TimecodeSync; | |
3447 | if (status & HDSP_TimecodeLock) { | |
3448 | snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); | |
3449 | } else { | |
3450 | snd_iprintf(buffer, "ADAT Sync: No Lock\n"); | |
3451 | } | |
3452 | ||
3453 | snd_iprintf(buffer, "\n"); | |
3454 | ||
3455 | /* Informations about H9632 specific controls */ | |
3456 | if (hdsp->io_type == H9632) { | |
3457 | char *tmp; | |
3458 | ||
3459 | switch (hdsp_ad_gain(hdsp)) { | |
3460 | case 0: | |
3461 | tmp = "-10 dBV"; | |
3462 | break; | |
3463 | case 1: | |
3464 | tmp = "+4 dBu"; | |
3465 | break; | |
3466 | default: | |
3467 | tmp = "Lo Gain"; | |
3468 | break; | |
3469 | } | |
3470 | snd_iprintf(buffer, "AD Gain : %s\n", tmp); | |
3471 | ||
3472 | switch (hdsp_da_gain(hdsp)) { | |
3473 | case 0: | |
3474 | tmp = "Hi Gain"; | |
3475 | break; | |
3476 | case 1: | |
3477 | tmp = "+4 dBu"; | |
3478 | break; | |
3479 | default: | |
3480 | tmp = "-10 dBV"; | |
3481 | break; | |
3482 | } | |
3483 | snd_iprintf(buffer, "DA Gain : %s\n", tmp); | |
3484 | ||
3485 | switch (hdsp_phone_gain(hdsp)) { | |
3486 | case 0: | |
3487 | tmp = "0 dB"; | |
3488 | break; | |
3489 | case 1: | |
3490 | tmp = "-6 dB"; | |
3491 | break; | |
3492 | default: | |
3493 | tmp = "-12 dB"; | |
3494 | break; | |
3495 | } | |
3496 | snd_iprintf(buffer, "Phones Gain : %s\n", tmp); | |
3497 | ||
3498 | snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); | |
3499 | ||
3500 | if (hdsp->control_register & HDSP_AnalogExtensionBoard) { | |
3501 | snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); | |
3502 | } else { | |
3503 | snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); | |
3504 | } | |
3505 | snd_iprintf(buffer, "\n"); | |
3506 | } | |
3507 | ||
3508 | } | |
3509 | ||
3510 | static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp) | |
3511 | { | |
3512 | snd_info_entry_t *entry; | |
3513 | ||
3514 | if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) | |
3515 | snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read); | |
3516 | } | |
3517 | ||
3518 | static void snd_hdsp_free_buffers(hdsp_t *hdsp) | |
3519 | { | |
3520 | snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); | |
3521 | snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); | |
3522 | } | |
3523 | ||
3524 | static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp) | |
3525 | { | |
3526 | unsigned long pb_bus, cb_bus; | |
3527 | ||
3528 | if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || | |
3529 | snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { | |
3530 | if (hdsp->capture_dma_buf.area) | |
3531 | snd_dma_free_pages(&hdsp->capture_dma_buf); | |
3532 | printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name); | |
3533 | return -ENOMEM; | |
3534 | } | |
3535 | ||
3536 | /* Align to bus-space 64K boundary */ | |
3537 | ||
3538 | cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl; | |
3539 | pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl; | |
3540 | ||
3541 | /* Tell the card where it is */ | |
3542 | ||
3543 | hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); | |
3544 | hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); | |
3545 | ||
3546 | hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); | |
3547 | hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); | |
3548 | ||
3549 | return 0; | |
3550 | } | |
3551 | ||
3552 | static int snd_hdsp_set_defaults(hdsp_t *hdsp) | |
3553 | { | |
3554 | unsigned int i; | |
3555 | ||
3556 | /* ASSUMPTION: hdsp->lock is either held, or | |
3557 | there is no need to hold it (e.g. during module | |
3558 | initalization). | |
3559 | */ | |
3560 | ||
3561 | /* set defaults: | |
3562 | ||
3563 | SPDIF Input via Coax | |
3564 | Master clock mode | |
3565 | maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, | |
3566 | which implies 2 4096 sample, 32Kbyte periods). | |
3567 | Enable line out. | |
3568 | */ | |
3569 | ||
3570 | hdsp->control_register = HDSP_ClockModeMaster | | |
3571 | HDSP_SPDIFInputCoaxial | | |
3572 | hdsp_encode_latency(7) | | |
3573 | HDSP_LineOut; | |
3574 | ||
3575 | ||
3576 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3577 | ||
3578 | #ifdef SNDRV_BIG_ENDIAN | |
3579 | hdsp->control2_register = HDSP_BIGENDIAN_MODE; | |
3580 | #else | |
3581 | hdsp->control2_register = 0; | |
3582 | #endif | |
3583 | if (hdsp->io_type == H9652) { | |
3584 | snd_hdsp_9652_enable_mixer (hdsp); | |
3585 | } else { | |
3586 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
3587 | } | |
3588 | ||
3589 | hdsp_reset_hw_pointer(hdsp); | |
3590 | hdsp_compute_period_size(hdsp); | |
3591 | ||
3592 | /* silence everything */ | |
3593 | ||
3594 | for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) { | |
3595 | hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; | |
3596 | } | |
3597 | ||
3598 | for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { | |
3599 | if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) { | |
3600 | return -EIO; | |
3601 | } | |
3602 | } | |
3603 | ||
3604 | /* H9632 specific defaults */ | |
3605 | if (hdsp->io_type == H9632) { | |
3606 | hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); | |
3607 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3608 | } | |
3609 | ||
3610 | /* set a default rate so that the channel map is set up. | |
3611 | */ | |
3612 | ||
3613 | hdsp_set_rate(hdsp, 48000, 1); | |
3614 | ||
3615 | return 0; | |
3616 | } | |
3617 | ||
3618 | static void hdsp_midi_tasklet(unsigned long arg) | |
3619 | { | |
3620 | hdsp_t *hdsp = (hdsp_t *)arg; | |
3621 | ||
3622 | if (hdsp->midi[0].pending) { | |
3623 | snd_hdsp_midi_input_read (&hdsp->midi[0]); | |
3624 | } | |
3625 | if (hdsp->midi[1].pending) { | |
3626 | snd_hdsp_midi_input_read (&hdsp->midi[1]); | |
3627 | } | |
3628 | } | |
3629 | ||
3630 | static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
3631 | { | |
3632 | hdsp_t *hdsp = (hdsp_t *) dev_id; | |
3633 | unsigned int status; | |
3634 | int audio; | |
3635 | int midi0; | |
3636 | int midi1; | |
3637 | unsigned int midi0status; | |
3638 | unsigned int midi1status; | |
3639 | int schedule = 0; | |
3640 | ||
3641 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
3642 | ||
3643 | audio = status & HDSP_audioIRQPending; | |
3644 | midi0 = status & HDSP_midi0IRQPending; | |
3645 | midi1 = status & HDSP_midi1IRQPending; | |
3646 | ||
3647 | if (!audio && !midi0 && !midi1) { | |
3648 | return IRQ_NONE; | |
3649 | } | |
3650 | ||
3651 | hdsp_write(hdsp, HDSP_interruptConfirmation, 0); | |
3652 | ||
3653 | midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; | |
3654 | midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; | |
3655 | ||
3656 | if (audio) { | |
3657 | if (hdsp->capture_substream) { | |
3658 | snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); | |
3659 | } | |
3660 | ||
3661 | if (hdsp->playback_substream) { | |
3662 | snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); | |
3663 | } | |
3664 | } | |
3665 | ||
3666 | if (midi0 && midi0status) { | |
3667 | if (hdsp->use_midi_tasklet) { | |
3668 | /* we disable interrupts for this input until processing is done */ | |
3669 | hdsp->control_register &= ~HDSP_Midi0InterruptEnable; | |
3670 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3671 | hdsp->midi[0].pending = 1; | |
3672 | schedule = 1; | |
3673 | } else { | |
3674 | snd_hdsp_midi_input_read (&hdsp->midi[0]); | |
3675 | } | |
3676 | } | |
3677 | if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) { | |
3678 | if (hdsp->use_midi_tasklet) { | |
3679 | /* we disable interrupts for this input until processing is done */ | |
3680 | hdsp->control_register &= ~HDSP_Midi1InterruptEnable; | |
3681 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); | |
3682 | hdsp->midi[1].pending = 1; | |
3683 | schedule = 1; | |
3684 | } else { | |
3685 | snd_hdsp_midi_input_read (&hdsp->midi[1]); | |
3686 | } | |
3687 | } | |
3688 | if (hdsp->use_midi_tasklet && schedule) | |
3689 | tasklet_hi_schedule(&hdsp->midi_tasklet); | |
3690 | return IRQ_HANDLED; | |
3691 | } | |
3692 | ||
3693 | static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream) | |
3694 | { | |
3695 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3696 | return hdsp_hw_pointer(hdsp); | |
3697 | } | |
3698 | ||
3699 | static char *hdsp_channel_buffer_location(hdsp_t *hdsp, | |
3700 | int stream, | |
3701 | int channel) | |
3702 | ||
3703 | { | |
3704 | int mapped_channel; | |
3705 | ||
3706 | snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL); | |
3707 | ||
3708 | if ((mapped_channel = hdsp->channel_map[channel]) < 0) { | |
3709 | return NULL; | |
3710 | } | |
3711 | ||
3712 | if (stream == SNDRV_PCM_STREAM_CAPTURE) { | |
3713 | return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); | |
3714 | } else { | |
3715 | return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); | |
3716 | } | |
3717 | } | |
3718 | ||
3719 | static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel, | |
3720 | snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) | |
3721 | { | |
3722 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3723 | char *channel_buf; | |
3724 | ||
3725 | snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); | |
3726 | ||
3727 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
3728 | snd_assert(channel_buf != NULL, return -EIO); | |
3729 | if (copy_from_user(channel_buf + pos * 4, src, count * 4)) | |
3730 | return -EFAULT; | |
3731 | return count; | |
3732 | } | |
3733 | ||
3734 | static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel, | |
3735 | snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) | |
3736 | { | |
3737 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3738 | char *channel_buf; | |
3739 | ||
3740 | snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); | |
3741 | ||
3742 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
3743 | snd_assert(channel_buf != NULL, return -EIO); | |
3744 | if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) | |
3745 | return -EFAULT; | |
3746 | return count; | |
3747 | } | |
3748 | ||
3749 | static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel, | |
3750 | snd_pcm_uframes_t pos, snd_pcm_uframes_t count) | |
3751 | { | |
3752 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3753 | char *channel_buf; | |
3754 | ||
3755 | channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); | |
3756 | snd_assert(channel_buf != NULL, return -EIO); | |
3757 | memset(channel_buf + pos * 4, 0, count * 4); | |
3758 | return count; | |
3759 | } | |
3760 | ||
3761 | static int snd_hdsp_reset(snd_pcm_substream_t *substream) | |
3762 | { | |
3763 | snd_pcm_runtime_t *runtime = substream->runtime; | |
3764 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3765 | snd_pcm_substream_t *other; | |
3766 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3767 | other = hdsp->capture_substream; | |
3768 | else | |
3769 | other = hdsp->playback_substream; | |
3770 | if (hdsp->running) | |
3771 | runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); | |
3772 | else | |
3773 | runtime->status->hw_ptr = 0; | |
3774 | if (other) { | |
3775 | struct list_head *pos; | |
3776 | snd_pcm_substream_t *s; | |
3777 | snd_pcm_runtime_t *oruntime = other->runtime; | |
3778 | snd_pcm_group_for_each(pos, substream) { | |
3779 | s = snd_pcm_group_substream_entry(pos); | |
3780 | if (s == other) { | |
3781 | oruntime->status->hw_ptr = runtime->status->hw_ptr; | |
3782 | break; | |
3783 | } | |
3784 | } | |
3785 | } | |
3786 | return 0; | |
3787 | } | |
3788 | ||
3789 | static int snd_hdsp_hw_params(snd_pcm_substream_t *substream, | |
3790 | snd_pcm_hw_params_t *params) | |
3791 | { | |
3792 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3793 | int err; | |
3794 | pid_t this_pid; | |
3795 | pid_t other_pid; | |
3796 | ||
3797 | if (hdsp_check_for_iobox (hdsp)) { | |
3798 | return -EIO; | |
3799 | } | |
3800 | ||
3801 | if (hdsp_check_for_firmware(hdsp)) { | |
3802 | if (hdsp->state & HDSP_FirmwareCached) { | |
3803 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
3804 | snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n"); | |
3805 | } | |
3806 | } else { | |
3807 | snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n"); | |
3808 | } | |
3809 | return -EIO; | |
3810 | } | |
3811 | ||
3812 | spin_lock_irq(&hdsp->lock); | |
3813 | ||
3814 | if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
3815 | hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); | |
3816 | hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); | |
3817 | this_pid = hdsp->playback_pid; | |
3818 | other_pid = hdsp->capture_pid; | |
3819 | } else { | |
3820 | this_pid = hdsp->capture_pid; | |
3821 | other_pid = hdsp->playback_pid; | |
3822 | } | |
3823 | ||
3824 | if ((other_pid > 0) && (this_pid != other_pid)) { | |
3825 | ||
3826 | /* The other stream is open, and not by the same | |
3827 | task as this one. Make sure that the parameters | |
3828 | that matter are the same. | |
3829 | */ | |
3830 | ||
3831 | if (params_rate(params) != hdsp->system_sample_rate) { | |
3832 | spin_unlock_irq(&hdsp->lock); | |
3833 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); | |
3834 | return -EBUSY; | |
3835 | } | |
3836 | ||
3837 | if (params_period_size(params) != hdsp->period_bytes / 4) { | |
3838 | spin_unlock_irq(&hdsp->lock); | |
3839 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
3840 | return -EBUSY; | |
3841 | } | |
3842 | ||
3843 | /* We're fine. */ | |
3844 | ||
3845 | spin_unlock_irq(&hdsp->lock); | |
3846 | return 0; | |
3847 | ||
3848 | } else { | |
3849 | spin_unlock_irq(&hdsp->lock); | |
3850 | } | |
3851 | ||
3852 | /* how to make sure that the rate matches an externally-set one ? | |
3853 | */ | |
3854 | ||
3855 | spin_lock_irq(&hdsp->lock); | |
3856 | if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { | |
3857 | spin_unlock_irq(&hdsp->lock); | |
3858 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); | |
3859 | return err; | |
3860 | } else { | |
3861 | spin_unlock_irq(&hdsp->lock); | |
3862 | } | |
3863 | ||
3864 | if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { | |
3865 | _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
3866 | return err; | |
3867 | } | |
3868 | ||
3869 | return 0; | |
3870 | } | |
3871 | ||
3872 | static int snd_hdsp_channel_info(snd_pcm_substream_t *substream, | |
3873 | snd_pcm_channel_info_t *info) | |
3874 | { | |
3875 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3876 | int mapped_channel; | |
3877 | ||
3878 | snd_assert(info->channel < hdsp->max_channels, return -EINVAL); | |
3879 | ||
3880 | if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) { | |
3881 | return -EINVAL; | |
3882 | } | |
3883 | ||
3884 | info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; | |
3885 | info->first = 0; | |
3886 | info->step = 32; | |
3887 | return 0; | |
3888 | } | |
3889 | ||
3890 | static int snd_hdsp_ioctl(snd_pcm_substream_t *substream, | |
3891 | unsigned int cmd, void *arg) | |
3892 | { | |
3893 | switch (cmd) { | |
3894 | case SNDRV_PCM_IOCTL1_RESET: | |
3895 | { | |
3896 | return snd_hdsp_reset(substream); | |
3897 | } | |
3898 | case SNDRV_PCM_IOCTL1_CHANNEL_INFO: | |
3899 | { | |
3900 | snd_pcm_channel_info_t *info = arg; | |
3901 | return snd_hdsp_channel_info(substream, info); | |
3902 | } | |
3903 | default: | |
3904 | break; | |
3905 | } | |
3906 | ||
3907 | return snd_pcm_lib_ioctl(substream, cmd, arg); | |
3908 | } | |
3909 | ||
3910 | static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd) | |
3911 | { | |
3912 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3913 | snd_pcm_substream_t *other; | |
3914 | int running; | |
3915 | ||
3916 | if (hdsp_check_for_iobox (hdsp)) { | |
3917 | return -EIO; | |
3918 | } | |
3919 | ||
3920 | if (hdsp_check_for_firmware(hdsp)) { | |
3921 | if (hdsp->state & HDSP_FirmwareCached) { | |
3922 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
3923 | snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n"); | |
3924 | } | |
3925 | } else { | |
3926 | snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n"); | |
3927 | } | |
3928 | return -EIO; | |
3929 | } | |
3930 | ||
3931 | spin_lock(&hdsp->lock); | |
3932 | running = hdsp->running; | |
3933 | switch (cmd) { | |
3934 | case SNDRV_PCM_TRIGGER_START: | |
3935 | running |= 1 << substream->stream; | |
3936 | break; | |
3937 | case SNDRV_PCM_TRIGGER_STOP: | |
3938 | running &= ~(1 << substream->stream); | |
3939 | break; | |
3940 | default: | |
3941 | snd_BUG(); | |
3942 | spin_unlock(&hdsp->lock); | |
3943 | return -EINVAL; | |
3944 | } | |
3945 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3946 | other = hdsp->capture_substream; | |
3947 | else | |
3948 | other = hdsp->playback_substream; | |
3949 | ||
3950 | if (other) { | |
3951 | struct list_head *pos; | |
3952 | snd_pcm_substream_t *s; | |
3953 | snd_pcm_group_for_each(pos, substream) { | |
3954 | s = snd_pcm_group_substream_entry(pos); | |
3955 | if (s == other) { | |
3956 | snd_pcm_trigger_done(s, substream); | |
3957 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
3958 | running |= 1 << s->stream; | |
3959 | else | |
3960 | running &= ~(1 << s->stream); | |
3961 | goto _ok; | |
3962 | } | |
3963 | } | |
3964 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
3965 | if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && | |
3966 | substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
3967 | hdsp_silence_playback(hdsp); | |
3968 | } else { | |
3969 | if (running && | |
3970 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3971 | hdsp_silence_playback(hdsp); | |
3972 | } | |
3973 | } else { | |
3974 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
3975 | hdsp_silence_playback(hdsp); | |
3976 | } | |
3977 | _ok: | |
3978 | snd_pcm_trigger_done(substream, substream); | |
3979 | if (!hdsp->running && running) | |
3980 | hdsp_start_audio(hdsp); | |
3981 | else if (hdsp->running && !running) | |
3982 | hdsp_stop_audio(hdsp); | |
3983 | hdsp->running = running; | |
3984 | spin_unlock(&hdsp->lock); | |
3985 | ||
3986 | return 0; | |
3987 | } | |
3988 | ||
3989 | static int snd_hdsp_prepare(snd_pcm_substream_t *substream) | |
3990 | { | |
3991 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
3992 | int result = 0; | |
3993 | ||
3994 | if (hdsp_check_for_iobox (hdsp)) { | |
3995 | return -EIO; | |
3996 | } | |
3997 | ||
3998 | if (hdsp_check_for_firmware(hdsp)) { | |
3999 | if (hdsp->state & HDSP_FirmwareCached) { | |
4000 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
4001 | snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n"); | |
4002 | } | |
4003 | } else { | |
4004 | snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n"); | |
4005 | } | |
4006 | return -EIO; | |
4007 | } | |
4008 | ||
4009 | spin_lock_irq(&hdsp->lock); | |
4010 | if (!hdsp->running) | |
4011 | hdsp_reset_hw_pointer(hdsp); | |
4012 | spin_unlock_irq(&hdsp->lock); | |
4013 | return result; | |
4014 | } | |
4015 | ||
4016 | static snd_pcm_hardware_t snd_hdsp_playback_subinfo = | |
4017 | { | |
4018 | .info = (SNDRV_PCM_INFO_MMAP | | |
4019 | SNDRV_PCM_INFO_MMAP_VALID | | |
4020 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
4021 | SNDRV_PCM_INFO_SYNC_START | | |
4022 | SNDRV_PCM_INFO_DOUBLE), | |
4023 | #ifdef SNDRV_BIG_ENDIAN | |
4024 | .formats = SNDRV_PCM_FMTBIT_S32_BE, | |
4025 | #else | |
4026 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
4027 | #endif | |
4028 | .rates = (SNDRV_PCM_RATE_32000 | | |
4029 | SNDRV_PCM_RATE_44100 | | |
4030 | SNDRV_PCM_RATE_48000 | | |
4031 | SNDRV_PCM_RATE_64000 | | |
4032 | SNDRV_PCM_RATE_88200 | | |
4033 | SNDRV_PCM_RATE_96000), | |
4034 | .rate_min = 32000, | |
4035 | .rate_max = 96000, | |
4036 | .channels_min = 14, | |
4037 | .channels_max = HDSP_MAX_CHANNELS, | |
4038 | .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, | |
4039 | .period_bytes_min = (64 * 4) * 10, | |
4040 | .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, | |
4041 | .periods_min = 2, | |
4042 | .periods_max = 2, | |
4043 | .fifo_size = 0 | |
4044 | }; | |
4045 | ||
4046 | static snd_pcm_hardware_t snd_hdsp_capture_subinfo = | |
4047 | { | |
4048 | .info = (SNDRV_PCM_INFO_MMAP | | |
4049 | SNDRV_PCM_INFO_MMAP_VALID | | |
4050 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
4051 | SNDRV_PCM_INFO_SYNC_START), | |
4052 | #ifdef SNDRV_BIG_ENDIAN | |
4053 | .formats = SNDRV_PCM_FMTBIT_S32_BE, | |
4054 | #else | |
4055 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
4056 | #endif | |
4057 | .rates = (SNDRV_PCM_RATE_32000 | | |
4058 | SNDRV_PCM_RATE_44100 | | |
4059 | SNDRV_PCM_RATE_48000 | | |
4060 | SNDRV_PCM_RATE_64000 | | |
4061 | SNDRV_PCM_RATE_88200 | | |
4062 | SNDRV_PCM_RATE_96000), | |
4063 | .rate_min = 32000, | |
4064 | .rate_max = 96000, | |
4065 | .channels_min = 14, | |
4066 | .channels_max = HDSP_MAX_CHANNELS, | |
4067 | .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, | |
4068 | .period_bytes_min = (64 * 4) * 10, | |
4069 | .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, | |
4070 | .periods_min = 2, | |
4071 | .periods_max = 2, | |
4072 | .fifo_size = 0 | |
4073 | }; | |
4074 | ||
4075 | static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; | |
4076 | ||
4077 | static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = { | |
4078 | .count = ARRAY_SIZE(hdsp_period_sizes), | |
4079 | .list = hdsp_period_sizes, | |
4080 | .mask = 0 | |
4081 | }; | |
4082 | ||
4083 | static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; | |
4084 | ||
4085 | static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = { | |
4086 | .count = ARRAY_SIZE(hdsp_9632_sample_rates), | |
4087 | .list = hdsp_9632_sample_rates, | |
4088 | .mask = 0 | |
4089 | }; | |
4090 | ||
4091 | static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params, | |
4092 | snd_pcm_hw_rule_t *rule) | |
4093 | { | |
4094 | hdsp_t *hdsp = rule->private; | |
4095 | snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4096 | if (hdsp->io_type == H9632) { | |
4097 | unsigned int list[3]; | |
4098 | list[0] = hdsp->qs_in_channels; | |
4099 | list[1] = hdsp->ds_in_channels; | |
4100 | list[2] = hdsp->ss_in_channels; | |
4101 | return snd_interval_list(c, 3, list, 0); | |
4102 | } else { | |
4103 | unsigned int list[2]; | |
4104 | list[0] = hdsp->ds_in_channels; | |
4105 | list[1] = hdsp->ss_in_channels; | |
4106 | return snd_interval_list(c, 2, list, 0); | |
4107 | } | |
4108 | } | |
4109 | ||
4110 | static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params, | |
4111 | snd_pcm_hw_rule_t *rule) | |
4112 | { | |
4113 | unsigned int list[3]; | |
4114 | hdsp_t *hdsp = rule->private; | |
4115 | snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4116 | if (hdsp->io_type == H9632) { | |
4117 | list[0] = hdsp->qs_out_channels; | |
4118 | list[1] = hdsp->ds_out_channels; | |
4119 | list[2] = hdsp->ss_out_channels; | |
4120 | return snd_interval_list(c, 3, list, 0); | |
4121 | } else { | |
4122 | list[0] = hdsp->ds_out_channels; | |
4123 | list[1] = hdsp->ss_out_channels; | |
4124 | } | |
4125 | return snd_interval_list(c, 2, list, 0); | |
4126 | } | |
4127 | ||
4128 | static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params, | |
4129 | snd_pcm_hw_rule_t *rule) | |
4130 | { | |
4131 | hdsp_t *hdsp = rule->private; | |
4132 | snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4133 | snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
4134 | if (r->min > 96000 && hdsp->io_type == H9632) { | |
4135 | snd_interval_t t = { | |
4136 | .min = hdsp->qs_in_channels, | |
4137 | .max = hdsp->qs_in_channels, | |
4138 | .integer = 1, | |
4139 | }; | |
4140 | return snd_interval_refine(c, &t); | |
4141 | } else if (r->min > 48000 && r->max <= 96000) { | |
4142 | snd_interval_t t = { | |
4143 | .min = hdsp->ds_in_channels, | |
4144 | .max = hdsp->ds_in_channels, | |
4145 | .integer = 1, | |
4146 | }; | |
4147 | return snd_interval_refine(c, &t); | |
4148 | } else if (r->max < 64000) { | |
4149 | snd_interval_t t = { | |
4150 | .min = hdsp->ss_in_channels, | |
4151 | .max = hdsp->ss_in_channels, | |
4152 | .integer = 1, | |
4153 | }; | |
4154 | return snd_interval_refine(c, &t); | |
4155 | } | |
4156 | return 0; | |
4157 | } | |
4158 | ||
4159 | static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params, | |
4160 | snd_pcm_hw_rule_t *rule) | |
4161 | { | |
4162 | hdsp_t *hdsp = rule->private; | |
4163 | snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4164 | snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
4165 | if (r->min > 96000 && hdsp->io_type == H9632) { | |
4166 | snd_interval_t t = { | |
4167 | .min = hdsp->qs_out_channels, | |
4168 | .max = hdsp->qs_out_channels, | |
4169 | .integer = 1, | |
4170 | }; | |
4171 | return snd_interval_refine(c, &t); | |
4172 | } else if (r->min > 48000 && r->max <= 96000) { | |
4173 | snd_interval_t t = { | |
4174 | .min = hdsp->ds_out_channels, | |
4175 | .max = hdsp->ds_out_channels, | |
4176 | .integer = 1, | |
4177 | }; | |
4178 | return snd_interval_refine(c, &t); | |
4179 | } else if (r->max < 64000) { | |
4180 | snd_interval_t t = { | |
4181 | .min = hdsp->ss_out_channels, | |
4182 | .max = hdsp->ss_out_channels, | |
4183 | .integer = 1, | |
4184 | }; | |
4185 | return snd_interval_refine(c, &t); | |
4186 | } | |
4187 | return 0; | |
4188 | } | |
4189 | ||
4190 | static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params, | |
4191 | snd_pcm_hw_rule_t *rule) | |
4192 | { | |
4193 | hdsp_t *hdsp = rule->private; | |
4194 | snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4195 | snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
4196 | if (c->min >= hdsp->ss_out_channels) { | |
4197 | snd_interval_t t = { | |
4198 | .min = 32000, | |
4199 | .max = 48000, | |
4200 | .integer = 1, | |
4201 | }; | |
4202 | return snd_interval_refine(r, &t); | |
4203 | } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { | |
4204 | snd_interval_t t = { | |
4205 | .min = 128000, | |
4206 | .max = 192000, | |
4207 | .integer = 1, | |
4208 | }; | |
4209 | return snd_interval_refine(r, &t); | |
4210 | } else if (c->max <= hdsp->ds_out_channels) { | |
4211 | snd_interval_t t = { | |
4212 | .min = 64000, | |
4213 | .max = 96000, | |
4214 | .integer = 1, | |
4215 | }; | |
4216 | return snd_interval_refine(r, &t); | |
4217 | } | |
4218 | return 0; | |
4219 | } | |
4220 | ||
4221 | static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params, | |
4222 | snd_pcm_hw_rule_t *rule) | |
4223 | { | |
4224 | hdsp_t *hdsp = rule->private; | |
4225 | snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
4226 | snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
4227 | if (c->min >= hdsp->ss_in_channels) { | |
4228 | snd_interval_t t = { | |
4229 | .min = 32000, | |
4230 | .max = 48000, | |
4231 | .integer = 1, | |
4232 | }; | |
4233 | return snd_interval_refine(r, &t); | |
4234 | } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { | |
4235 | snd_interval_t t = { | |
4236 | .min = 128000, | |
4237 | .max = 192000, | |
4238 | .integer = 1, | |
4239 | }; | |
4240 | return snd_interval_refine(r, &t); | |
4241 | } else if (c->max <= hdsp->ds_in_channels) { | |
4242 | snd_interval_t t = { | |
4243 | .min = 64000, | |
4244 | .max = 96000, | |
4245 | .integer = 1, | |
4246 | }; | |
4247 | return snd_interval_refine(r, &t); | |
4248 | } | |
4249 | return 0; | |
4250 | } | |
4251 | ||
4252 | static int snd_hdsp_playback_open(snd_pcm_substream_t *substream) | |
4253 | { | |
4254 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
4255 | snd_pcm_runtime_t *runtime = substream->runtime; | |
4256 | ||
4257 | if (hdsp_check_for_iobox (hdsp)) { | |
4258 | return -EIO; | |
4259 | } | |
4260 | ||
4261 | if (hdsp_check_for_firmware(hdsp)) { | |
4262 | if (hdsp->state & HDSP_FirmwareCached) { | |
4263 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
4264 | snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n"); | |
4265 | } | |
4266 | } else { | |
4267 | snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n"); | |
4268 | } | |
4269 | return -EIO; | |
4270 | } | |
4271 | ||
4272 | spin_lock_irq(&hdsp->lock); | |
4273 | ||
4274 | snd_pcm_set_sync(substream); | |
4275 | ||
4276 | runtime->hw = snd_hdsp_playback_subinfo; | |
4277 | runtime->dma_area = hdsp->playback_buffer; | |
4278 | runtime->dma_bytes = HDSP_DMA_AREA_BYTES; | |
4279 | ||
4280 | hdsp->playback_pid = current->pid; | |
4281 | hdsp->playback_substream = substream; | |
4282 | ||
4283 | spin_unlock_irq(&hdsp->lock); | |
4284 | ||
4285 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4286 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); | |
4287 | if (hdsp->io_type == H9632) { | |
4288 | runtime->hw.channels_min = hdsp->qs_out_channels; | |
4289 | runtime->hw.channels_max = hdsp->ss_out_channels; | |
4290 | runtime->hw.rate_max = 192000; | |
4291 | runtime->hw.rates = SNDRV_PCM_RATE_KNOT; | |
4292 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); | |
4293 | } | |
4294 | ||
4295 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4296 | snd_hdsp_hw_rule_out_channels, hdsp, | |
4297 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4298 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4299 | snd_hdsp_hw_rule_out_channels_rate, hdsp, | |
4300 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4301 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4302 | snd_hdsp_hw_rule_rate_out_channels, hdsp, | |
4303 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4304 | ||
4305 | hdsp->creg_spdif_stream = hdsp->creg_spdif; | |
4306 | hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
4307 | snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
4308 | SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); | |
4309 | return 0; | |
4310 | } | |
4311 | ||
4312 | static int snd_hdsp_playback_release(snd_pcm_substream_t *substream) | |
4313 | { | |
4314 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
4315 | ||
4316 | spin_lock_irq(&hdsp->lock); | |
4317 | ||
4318 | hdsp->playback_pid = -1; | |
4319 | hdsp->playback_substream = NULL; | |
4320 | ||
4321 | spin_unlock_irq(&hdsp->lock); | |
4322 | ||
4323 | hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
4324 | snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
4325 | SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); | |
4326 | return 0; | |
4327 | } | |
4328 | ||
4329 | ||
4330 | static int snd_hdsp_capture_open(snd_pcm_substream_t *substream) | |
4331 | { | |
4332 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
4333 | snd_pcm_runtime_t *runtime = substream->runtime; | |
4334 | ||
4335 | if (hdsp_check_for_iobox (hdsp)) { | |
4336 | return -EIO; | |
4337 | } | |
4338 | ||
4339 | if (hdsp_check_for_firmware(hdsp)) { | |
4340 | if (hdsp->state & HDSP_FirmwareCached) { | |
4341 | if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { | |
4342 | snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n"); | |
4343 | } | |
4344 | } else { | |
4345 | snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n"); | |
4346 | } | |
4347 | return -EIO; | |
4348 | } | |
4349 | ||
4350 | spin_lock_irq(&hdsp->lock); | |
4351 | ||
4352 | snd_pcm_set_sync(substream); | |
4353 | ||
4354 | runtime->hw = snd_hdsp_capture_subinfo; | |
4355 | runtime->dma_area = hdsp->capture_buffer; | |
4356 | runtime->dma_bytes = HDSP_DMA_AREA_BYTES; | |
4357 | ||
4358 | hdsp->capture_pid = current->pid; | |
4359 | hdsp->capture_substream = substream; | |
4360 | ||
4361 | spin_unlock_irq(&hdsp->lock); | |
4362 | ||
4363 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4364 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); | |
4365 | if (hdsp->io_type == H9632) { | |
4366 | runtime->hw.channels_min = hdsp->qs_in_channels; | |
4367 | runtime->hw.channels_max = hdsp->ss_in_channels; | |
4368 | runtime->hw.rate_max = 192000; | |
4369 | runtime->hw.rates = SNDRV_PCM_RATE_KNOT; | |
4370 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); | |
4371 | } | |
4372 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4373 | snd_hdsp_hw_rule_in_channels, hdsp, | |
4374 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4375 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4376 | snd_hdsp_hw_rule_in_channels_rate, hdsp, | |
4377 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4378 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4379 | snd_hdsp_hw_rule_rate_in_channels, hdsp, | |
4380 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4381 | return 0; | |
4382 | } | |
4383 | ||
4384 | static int snd_hdsp_capture_release(snd_pcm_substream_t *substream) | |
4385 | { | |
4386 | hdsp_t *hdsp = snd_pcm_substream_chip(substream); | |
4387 | ||
4388 | spin_lock_irq(&hdsp->lock); | |
4389 | ||
4390 | hdsp->capture_pid = -1; | |
4391 | hdsp->capture_substream = NULL; | |
4392 | ||
4393 | spin_unlock_irq(&hdsp->lock); | |
4394 | return 0; | |
4395 | } | |
4396 | ||
4397 | static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file) | |
4398 | { | |
4399 | /* we have nothing to initialize but the call is required */ | |
4400 | return 0; | |
4401 | } | |
4402 | ||
4403 | ||
4404 | /* helper functions for copying meter values */ | |
4405 | static inline int copy_u32_le(void __user *dest, void __iomem *src) | |
4406 | { | |
4407 | u32 val = readl(src); | |
4408 | return copy_to_user(dest, &val, 4); | |
4409 | } | |
4410 | ||
4411 | static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) | |
4412 | { | |
4413 | u32 rms_low, rms_high; | |
4414 | u64 rms; | |
4415 | rms_low = readl(src_low); | |
4416 | rms_high = readl(src_high); | |
4417 | rms = ((u64)rms_high << 32) | rms_low; | |
4418 | return copy_to_user(dest, &rms, 8); | |
4419 | } | |
4420 | ||
4421 | static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) | |
4422 | { | |
4423 | u32 rms_low, rms_high; | |
4424 | u64 rms; | |
4425 | rms_low = readl(src_low) & 0xffffff00; | |
4426 | rms_high = readl(src_high) & 0xffffff00; | |
4427 | rms = ((u64)rms_high << 32) | rms_low; | |
4428 | return copy_to_user(dest, &rms, 8); | |
4429 | } | |
4430 | ||
4431 | static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms) | |
4432 | { | |
4433 | int doublespeed = 0; | |
4434 | int i, j, channels, ofs; | |
4435 | ||
4436 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) | |
4437 | doublespeed = 1; | |
4438 | channels = doublespeed ? 14 : 26; | |
4439 | for (i = 0, j = 0; i < 26; ++i) { | |
4440 | if (doublespeed && (i & 4)) | |
4441 | continue; | |
4442 | ofs = HDSP_9652_peakBase - j * 4; | |
4443 | if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) | |
4444 | return -EFAULT; | |
4445 | ofs -= channels * 4; | |
4446 | if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) | |
4447 | return -EFAULT; | |
4448 | ofs -= channels * 4; | |
4449 | if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) | |
4450 | return -EFAULT; | |
4451 | ofs = HDSP_9652_rmsBase + j * 8; | |
4452 | if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, | |
4453 | hdsp->iobase + ofs + 4)) | |
4454 | return -EFAULT; | |
4455 | ofs += channels * 8; | |
4456 | if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, | |
4457 | hdsp->iobase + ofs + 4)) | |
4458 | return -EFAULT; | |
4459 | ofs += channels * 8; | |
4460 | if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, | |
4461 | hdsp->iobase + ofs + 4)) | |
4462 | return -EFAULT; | |
4463 | j++; | |
4464 | } | |
4465 | return 0; | |
4466 | } | |
4467 | ||
4468 | static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms) | |
4469 | { | |
4470 | int i, j; | |
4471 | hdsp_9632_meters_t __iomem *m; | |
4472 | int doublespeed = 0; | |
4473 | ||
4474 | if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) | |
4475 | doublespeed = 1; | |
4476 | m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase); | |
4477 | for (i = 0, j = 0; i < 16; ++i, ++j) { | |
4478 | if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) | |
4479 | return -EFAULT; | |
4480 | if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) | |
4481 | return -EFAULT; | |
4482 | if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) | |
4483 | return -EFAULT; | |
4484 | if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], | |
4485 | &m->input_rms_high[j])) | |
4486 | return -EFAULT; | |
4487 | if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], | |
4488 | &m->playback_rms_high[j])) | |
4489 | return -EFAULT; | |
4490 | if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], | |
4491 | &m->output_rms_high[j])) | |
4492 | return -EFAULT; | |
4493 | if (doublespeed && i == 3) i += 4; | |
4494 | } | |
4495 | return 0; | |
4496 | } | |
4497 | ||
4498 | static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms) | |
4499 | { | |
4500 | int i; | |
4501 | ||
4502 | for (i = 0; i < 26; i++) { | |
4503 | if (copy_u32_le(&peak_rms->playback_peaks[i], | |
4504 | hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) | |
4505 | return -EFAULT; | |
4506 | if (copy_u32_le(&peak_rms->input_peaks[i], | |
4507 | hdsp->iobase + HDSP_inputPeakLevel + i * 4)) | |
4508 | return -EFAULT; | |
4509 | } | |
4510 | for (i = 0; i < 28; i++) { | |
4511 | if (copy_u32_le(&peak_rms->output_peaks[i], | |
4512 | hdsp->iobase + HDSP_outputPeakLevel + i * 4)) | |
4513 | return -EFAULT; | |
4514 | } | |
4515 | for (i = 0; i < 26; ++i) { | |
4516 | if (copy_u64_le(&peak_rms->playback_rms[i], | |
4517 | hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, | |
4518 | hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) | |
4519 | return -EFAULT; | |
4520 | if (copy_u64_le(&peak_rms->input_rms[i], | |
4521 | hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, | |
4522 | hdsp->iobase + HDSP_inputRmsLevel + i * 8)) | |
4523 | return -EFAULT; | |
4524 | } | |
4525 | return 0; | |
4526 | } | |
4527 | ||
4528 | static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg) | |
4529 | { | |
4530 | hdsp_t *hdsp = (hdsp_t *)hw->private_data; | |
4531 | void __user *argp = (void __user *)arg; | |
4532 | ||
4533 | switch (cmd) { | |
4534 | case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { | |
4535 | hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg; | |
4536 | ||
4537 | if (!(hdsp->state & HDSP_FirmwareLoaded)) { | |
4538 | snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); | |
4539 | return -EINVAL; | |
4540 | } | |
4541 | ||
4542 | switch (hdsp->io_type) { | |
4543 | case H9652: | |
4544 | return hdsp_9652_get_peak(hdsp, peak_rms); | |
4545 | case H9632: | |
4546 | return hdsp_9632_get_peak(hdsp, peak_rms); | |
4547 | default: | |
4548 | return hdsp_get_peak(hdsp, peak_rms); | |
4549 | } | |
4550 | } | |
4551 | case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { | |
4552 | hdsp_config_info_t info; | |
4553 | unsigned long flags; | |
4554 | int i; | |
4555 | ||
4556 | if (!(hdsp->state & HDSP_FirmwareLoaded)) { | |
4557 | snd_printk("Hammerfall-DSP: Firmware needs to be uploaded to the card.\n"); | |
4558 | return -EINVAL; | |
4559 | } | |
4560 | spin_lock_irqsave(&hdsp->lock, flags); | |
4561 | info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); | |
4562 | info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); | |
4563 | if (hdsp->io_type != H9632) { | |
4564 | info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); | |
4565 | } | |
4566 | info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); | |
4567 | for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) { | |
4568 | info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); | |
4569 | } | |
4570 | info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); | |
4571 | info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); | |
4572 | info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); | |
4573 | info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); | |
4574 | info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); | |
4575 | info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); | |
4576 | info.system_sample_rate = hdsp->system_sample_rate; | |
4577 | info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); | |
4578 | info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); | |
4579 | info.clock_source = (unsigned char)hdsp_clock_source(hdsp); | |
4580 | info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); | |
4581 | info.line_out = (unsigned char)hdsp_line_out(hdsp); | |
4582 | if (hdsp->io_type == H9632) { | |
4583 | info.da_gain = (unsigned char)hdsp_da_gain(hdsp); | |
4584 | info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); | |
4585 | info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); | |
4586 | info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); | |
4587 | ||
4588 | } | |
4589 | if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { | |
4590 | info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); | |
4591 | } | |
4592 | spin_unlock_irqrestore(&hdsp->lock, flags); | |
4593 | if (copy_to_user(argp, &info, sizeof(info))) | |
4594 | return -EFAULT; | |
4595 | break; | |
4596 | } | |
4597 | case SNDRV_HDSP_IOCTL_GET_9632_AEB: { | |
4598 | hdsp_9632_aeb_t h9632_aeb; | |
4599 | ||
4600 | if (hdsp->io_type != H9632) return -EINVAL; | |
4601 | h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; | |
4602 | h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; | |
4603 | if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) | |
4604 | return -EFAULT; | |
4605 | break; | |
4606 | } | |
4607 | case SNDRV_HDSP_IOCTL_GET_VERSION: { | |
4608 | hdsp_version_t hdsp_version; | |
4609 | int err; | |
4610 | ||
4611 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; | |
4612 | if (hdsp->io_type == Undefined) { | |
4613 | if ((err = hdsp_get_iobox_version(hdsp)) < 0) { | |
4614 | return err; | |
4615 | } | |
4616 | } | |
4617 | hdsp_version.io_type = hdsp->io_type; | |
4618 | hdsp_version.firmware_rev = hdsp->firmware_rev; | |
4619 | if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) { | |
4620 | return -EFAULT; | |
4621 | } | |
4622 | break; | |
4623 | } | |
4624 | case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { | |
4625 | hdsp_firmware_t __user *firmware; | |
4626 | u32 __user *firmware_data; | |
4627 | int err; | |
4628 | ||
4629 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; | |
4630 | /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ | |
4631 | if (hdsp->io_type == Undefined) return -EINVAL; | |
4632 | ||
4633 | if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) | |
4634 | return -EBUSY; | |
4635 | ||
4636 | snd_printk("Hammerfall-DSP: initializing firmware upload\n"); | |
4637 | firmware = (hdsp_firmware_t __user *)argp; | |
4638 | ||
4639 | if (get_user(firmware_data, &firmware->firmware_data)) { | |
4640 | return -EFAULT; | |
4641 | } | |
4642 | ||
4643 | if (hdsp_check_for_iobox (hdsp)) { | |
4644 | return -EIO; | |
4645 | } | |
4646 | ||
4647 | if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) { | |
4648 | return -EFAULT; | |
4649 | } | |
4650 | ||
4651 | hdsp->state |= HDSP_FirmwareCached; | |
4652 | ||
4653 | if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) { | |
4654 | return err; | |
4655 | } | |
4656 | ||
4657 | if (!(hdsp->state & HDSP_InitializationComplete)) { | |
4658 | if ((err = snd_hdsp_enable_io(hdsp)) < 0) { | |
4659 | return err; | |
4660 | } | |
4661 | ||
4662 | snd_hdsp_initialize_channels(hdsp); | |
4663 | snd_hdsp_initialize_midi_flush(hdsp); | |
4664 | ||
4665 | if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { | |
4666 | snd_printk("Hammerfall-DSP: error creating alsa devices\n"); | |
4667 | return err; | |
4668 | } | |
4669 | } | |
4670 | break; | |
4671 | } | |
4672 | case SNDRV_HDSP_IOCTL_GET_MIXER: { | |
4673 | hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp; | |
4674 | if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) | |
4675 | return -EFAULT; | |
4676 | break; | |
4677 | } | |
4678 | default: | |
4679 | return -EINVAL; | |
4680 | } | |
4681 | return 0; | |
4682 | } | |
4683 | ||
4684 | static snd_pcm_ops_t snd_hdsp_playback_ops = { | |
4685 | .open = snd_hdsp_playback_open, | |
4686 | .close = snd_hdsp_playback_release, | |
4687 | .ioctl = snd_hdsp_ioctl, | |
4688 | .hw_params = snd_hdsp_hw_params, | |
4689 | .prepare = snd_hdsp_prepare, | |
4690 | .trigger = snd_hdsp_trigger, | |
4691 | .pointer = snd_hdsp_hw_pointer, | |
4692 | .copy = snd_hdsp_playback_copy, | |
4693 | .silence = snd_hdsp_hw_silence, | |
4694 | }; | |
4695 | ||
4696 | static snd_pcm_ops_t snd_hdsp_capture_ops = { | |
4697 | .open = snd_hdsp_capture_open, | |
4698 | .close = snd_hdsp_capture_release, | |
4699 | .ioctl = snd_hdsp_ioctl, | |
4700 | .hw_params = snd_hdsp_hw_params, | |
4701 | .prepare = snd_hdsp_prepare, | |
4702 | .trigger = snd_hdsp_trigger, | |
4703 | .pointer = snd_hdsp_hw_pointer, | |
4704 | .copy = snd_hdsp_capture_copy, | |
4705 | }; | |
4706 | ||
4707 | static int __devinit snd_hdsp_create_hwdep(snd_card_t *card, | |
4708 | hdsp_t *hdsp) | |
4709 | { | |
4710 | snd_hwdep_t *hw; | |
4711 | int err; | |
4712 | ||
4713 | if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) | |
4714 | return err; | |
4715 | ||
4716 | hdsp->hwdep = hw; | |
4717 | hw->private_data = hdsp; | |
4718 | strcpy(hw->name, "HDSP hwdep interface"); | |
4719 | ||
4720 | hw->ops.open = snd_hdsp_hwdep_dummy_op; | |
4721 | hw->ops.ioctl = snd_hdsp_hwdep_ioctl; | |
4722 | hw->ops.release = snd_hdsp_hwdep_dummy_op; | |
4723 | ||
4724 | return 0; | |
4725 | } | |
4726 | ||
4727 | static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp) | |
4728 | { | |
4729 | snd_pcm_t *pcm; | |
4730 | int err; | |
4731 | ||
4732 | if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0) | |
4733 | return err; | |
4734 | ||
4735 | hdsp->pcm = pcm; | |
4736 | pcm->private_data = hdsp; | |
4737 | strcpy(pcm->name, hdsp->card_name); | |
4738 | ||
4739 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); | |
4740 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); | |
4741 | ||
4742 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
4743 | ||
4744 | return 0; | |
4745 | } | |
4746 | ||
4747 | static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp) | |
4748 | { | |
4749 | hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; | |
4750 | hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); | |
4751 | } | |
4752 | ||
4753 | static int snd_hdsp_enable_io (hdsp_t *hdsp) | |
4754 | { | |
4755 | int i; | |
4756 | ||
4757 | if (hdsp_fifo_wait (hdsp, 0, 100)) { | |
4758 | snd_printk("Hammerfall-DSP: enable_io fifo_wait failed\n"); | |
4759 | return -EIO; | |
4760 | } | |
4761 | ||
4762 | for (i = 0; i < hdsp->max_channels; ++i) { | |
4763 | hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); | |
4764 | hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); | |
4765 | } | |
4766 | ||
4767 | return 0; | |
4768 | } | |
4769 | ||
4770 | static void snd_hdsp_initialize_channels(hdsp_t *hdsp) | |
4771 | { | |
4772 | int status, aebi_channels, aebo_channels; | |
4773 | ||
4774 | switch (hdsp->io_type) { | |
4775 | case Digiface: | |
4776 | hdsp->card_name = "RME Hammerfall DSP + Digiface"; | |
4777 | hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; | |
4778 | hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; | |
4779 | break; | |
4780 | ||
4781 | case H9652: | |
4782 | hdsp->card_name = "RME Hammerfall HDSP 9652"; | |
4783 | hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; | |
4784 | hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; | |
4785 | break; | |
4786 | ||
4787 | case H9632: | |
4788 | status = hdsp_read(hdsp, HDSP_statusRegister); | |
4789 | /* HDSP_AEBx bits are low when AEB are connected */ | |
4790 | aebi_channels = (status & HDSP_AEBI) ? 0 : 4; | |
4791 | aebo_channels = (status & HDSP_AEBO) ? 0 : 4; | |
4792 | hdsp->card_name = "RME Hammerfall HDSP 9632"; | |
4793 | hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; | |
4794 | hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; | |
4795 | hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; | |
4796 | hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; | |
4797 | hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; | |
4798 | hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; | |
4799 | break; | |
4800 | ||
4801 | case Multiface: | |
4802 | hdsp->card_name = "RME Hammerfall DSP + Multiface"; | |
4803 | hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; | |
4804 | hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; | |
4805 | break; | |
4806 | ||
4807 | default: | |
4808 | /* should never get here */ | |
4809 | break; | |
4810 | } | |
4811 | } | |
4812 | ||
4813 | static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp) | |
4814 | { | |
4815 | snd_hdsp_flush_midi_input (hdsp, 0); | |
4816 | snd_hdsp_flush_midi_input (hdsp, 1); | |
4817 | } | |
4818 | ||
4819 | static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp) | |
4820 | { | |
4821 | int err; | |
4822 | ||
4823 | if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { | |
4824 | snd_printk("Hammerfall-DSP: Error creating pcm interface\n"); | |
4825 | return err; | |
4826 | } | |
4827 | ||
4828 | ||
4829 | if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { | |
4830 | snd_printk("Hammerfall-DSP: Error creating first midi interface\n"); | |
4831 | return err; | |
4832 | } | |
4833 | ||
4834 | if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { | |
4835 | if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { | |
4836 | snd_printk("Hammerfall-DSP: Error creating second midi interface\n"); | |
4837 | return err; | |
4838 | } | |
4839 | } | |
4840 | ||
4841 | if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { | |
4842 | snd_printk("Hammerfall-DSP: Error creating ctl interface\n"); | |
4843 | return err; | |
4844 | } | |
4845 | ||
4846 | snd_hdsp_proc_init(hdsp); | |
4847 | ||
4848 | hdsp->system_sample_rate = -1; | |
4849 | hdsp->playback_pid = -1; | |
4850 | hdsp->capture_pid = -1; | |
4851 | hdsp->capture_substream = NULL; | |
4852 | hdsp->playback_substream = NULL; | |
4853 | ||
4854 | if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { | |
4855 | snd_printk("Hammerfall-DSP: Error setting default values\n"); | |
4856 | return err; | |
4857 | } | |
4858 | ||
4859 | if (!(hdsp->state & HDSP_InitializationComplete)) { | |
4860 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, | |
4861 | hdsp->port, hdsp->irq); | |
4862 | ||
4863 | if ((err = snd_card_register(card)) < 0) { | |
4864 | snd_printk("Hammerfall-DSP: error registering card\n"); | |
4865 | return err; | |
4866 | } | |
4867 | hdsp->state |= HDSP_InitializationComplete; | |
4868 | } | |
4869 | ||
4870 | return 0; | |
4871 | } | |
4872 | ||
4873 | #ifdef HDSP_FW_LOADER | |
4874 | /* load firmware via hotplug fw loader */ | |
4875 | static int __devinit hdsp_request_fw_loader(hdsp_t *hdsp) | |
4876 | { | |
4877 | const char *fwfile; | |
4878 | const struct firmware *fw; | |
4879 | int err; | |
4880 | ||
4881 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) | |
4882 | return 0; | |
4883 | if (hdsp->io_type == Undefined) { | |
4884 | if ((err = hdsp_get_iobox_version(hdsp)) < 0) | |
4885 | return err; | |
4886 | if (hdsp->io_type == H9652 || hdsp->io_type == H9632) | |
4887 | return 0; | |
4888 | } | |
4889 | ||
4890 | /* caution: max length of firmware filename is 30! */ | |
4891 | switch (hdsp->io_type) { | |
4892 | case Multiface: | |
4893 | if (hdsp->firmware_rev == 0xa) | |
4894 | fwfile = "multiface_firmware.bin"; | |
4895 | else | |
4896 | fwfile = "multiface_firmware_rev11.bin"; | |
4897 | break; | |
4898 | case Digiface: | |
4899 | if (hdsp->firmware_rev == 0xa) | |
4900 | fwfile = "digiface_firmware.bin"; | |
4901 | else | |
4902 | fwfile = "digiface_firmware_rev11.bin"; | |
4903 | break; | |
4904 | default: | |
4905 | snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type); | |
4906 | return -EINVAL; | |
4907 | } | |
4908 | ||
4909 | if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { | |
4910 | snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile); | |
4911 | return -ENOENT; | |
4912 | } | |
4913 | if (fw->size < sizeof(hdsp->firmware_cache)) { | |
4914 | snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", | |
4915 | (int)fw->size, (int)sizeof(hdsp->firmware_cache)); | |
4916 | release_firmware(fw); | |
4917 | return -EINVAL; | |
4918 | } | |
7679a030 | 4919 | |
1da177e4 | 4920 | memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache)); |
7679a030 | 4921 | |
1da177e4 LT |
4922 | release_firmware(fw); |
4923 | ||
4924 | hdsp->state |= HDSP_FirmwareCached; | |
4925 | ||
4926 | if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) | |
4927 | return err; | |
4928 | ||
4929 | if (!(hdsp->state & HDSP_InitializationComplete)) { | |
4930 | if ((err = snd_hdsp_enable_io(hdsp)) < 0) { | |
4931 | return err; | |
4932 | } | |
4933 | ||
4934 | if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) { | |
4935 | snd_printk("Hammerfall-DSP: error creating hwdep device\n"); | |
4936 | return err; | |
4937 | } | |
4938 | snd_hdsp_initialize_channels(hdsp); | |
4939 | snd_hdsp_initialize_midi_flush(hdsp); | |
4940 | if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { | |
4941 | snd_printk("Hammerfall-DSP: error creating alsa devices\n"); | |
4942 | return err; | |
4943 | } | |
4944 | } | |
4945 | return 0; | |
4946 | } | |
4947 | #endif | |
4948 | ||
4949 | static int __devinit snd_hdsp_create(snd_card_t *card, | |
4950 | hdsp_t *hdsp) | |
4951 | { | |
4952 | struct pci_dev *pci = hdsp->pci; | |
4953 | int err; | |
4954 | int is_9652 = 0; | |
4955 | int is_9632 = 0; | |
4956 | ||
4957 | hdsp->irq = -1; | |
4958 | hdsp->state = 0; | |
4959 | hdsp->midi[0].rmidi = NULL; | |
4960 | hdsp->midi[1].rmidi = NULL; | |
4961 | hdsp->midi[0].input = NULL; | |
4962 | hdsp->midi[1].input = NULL; | |
4963 | hdsp->midi[0].output = NULL; | |
4964 | hdsp->midi[1].output = NULL; | |
4965 | hdsp->midi[0].pending = 0; | |
4966 | hdsp->midi[1].pending = 0; | |
4967 | spin_lock_init(&hdsp->midi[0].lock); | |
4968 | spin_lock_init(&hdsp->midi[1].lock); | |
4969 | hdsp->iobase = NULL; | |
4970 | hdsp->control_register = 0; | |
4971 | hdsp->control2_register = 0; | |
4972 | hdsp->io_type = Undefined; | |
4973 | hdsp->max_channels = 26; | |
4974 | ||
4975 | hdsp->card = card; | |
4976 | ||
4977 | spin_lock_init(&hdsp->lock); | |
4978 | ||
4979 | tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); | |
4980 | ||
4981 | pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); | |
4982 | hdsp->firmware_rev &= 0xff; | |
4983 | ||
4984 | /* From Martin Bjoernsen : | |
4985 | "It is important that the card's latency timer register in | |
4986 | the PCI configuration space is set to a value much larger | |
4987 | than 0 by the computer's BIOS or the driver. | |
4988 | The windows driver always sets this 8 bit register [...] | |
4989 | to its maximum 255 to avoid problems with some computers." | |
4990 | */ | |
4991 | pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); | |
4992 | ||
4993 | strcpy(card->driver, "H-DSP"); | |
4994 | strcpy(card->mixername, "Xilinx FPGA"); | |
4995 | ||
4996 | if (hdsp->firmware_rev < 0xa) { | |
4997 | return -ENODEV; | |
4998 | } else if (hdsp->firmware_rev < 0x64) { | |
4999 | hdsp->card_name = "RME Hammerfall DSP"; | |
5000 | } else if (hdsp->firmware_rev < 0x96) { | |
5001 | hdsp->card_name = "RME HDSP 9652"; | |
5002 | is_9652 = 1; | |
5003 | } else { | |
5004 | hdsp->card_name = "RME HDSP 9632"; | |
5005 | hdsp->max_channels = 16; | |
5006 | is_9632 = 1; | |
5007 | } | |
5008 | ||
5009 | if ((err = pci_enable_device(pci)) < 0) { | |
5010 | return err; | |
5011 | } | |
5012 | ||
5013 | pci_set_master(hdsp->pci); | |
5014 | ||
5015 | if ((err = pci_request_regions(pci, "hdsp")) < 0) | |
5016 | return err; | |
5017 | hdsp->port = pci_resource_start(pci, 0); | |
5018 | if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) { | |
5019 | snd_printk("Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); | |
5020 | return -EBUSY; | |
5021 | } | |
5022 | ||
5023 | if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) { | |
5024 | snd_printk("Hammerfall-DSP: unable to use IRQ %d\n", pci->irq); | |
5025 | return -EBUSY; | |
5026 | } | |
5027 | ||
5028 | hdsp->irq = pci->irq; | |
5029 | hdsp->precise_ptr = 1; | |
5030 | hdsp->use_midi_tasklet = 1; | |
5031 | ||
5032 | if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) { | |
5033 | return err; | |
5034 | } | |
5035 | ||
5036 | if (!is_9652 && !is_9632) { | |
5037 | /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */ | |
5038 | if ((1000 / HZ) < 2000) { | |
5039 | set_current_state(TASK_UNINTERRUPTIBLE); | |
5040 | schedule_timeout((2000 * HZ + 999) / 1000); | |
5041 | } else { | |
5042 | mdelay(2000); | |
5043 | } | |
5044 | ||
5045 | if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { | |
5046 | #ifdef HDSP_FW_LOADER | |
5047 | if ((err = hdsp_request_fw_loader(hdsp)) < 0) { | |
5048 | /* we don't fail as this can happen | |
5049 | if userspace is not ready for | |
5050 | firmware upload | |
5051 | */ | |
5052 | snd_printk("Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n"); | |
5053 | } else { | |
5054 | /* init is complete, we return */ | |
5055 | return 0; | |
5056 | } | |
5057 | #endif | |
5058 | /* no iobox connected, we defer initialization */ | |
5059 | snd_printk("Hammerfall-DSP: card initialization pending : waiting for firmware\n"); | |
5060 | if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) { | |
5061 | return err; | |
5062 | } | |
5063 | return 0; | |
5064 | } else { | |
5065 | snd_printk("Hammerfall-DSP: Firmware already present, initializing card.\n"); | |
5066 | if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) { | |
5067 | hdsp->io_type = Multiface; | |
5068 | } else { | |
5069 | hdsp->io_type = Digiface; | |
5070 | } | |
5071 | } | |
5072 | } | |
5073 | ||
5074 | if ((err = snd_hdsp_enable_io(hdsp)) != 0) { | |
5075 | return err; | |
5076 | } | |
5077 | ||
5078 | if (is_9652) { | |
5079 | hdsp->io_type = H9652; | |
5080 | } | |
5081 | ||
5082 | if (is_9632) { | |
5083 | hdsp->io_type = H9632; | |
5084 | } | |
5085 | ||
5086 | if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) { | |
5087 | return err; | |
5088 | } | |
5089 | ||
5090 | snd_hdsp_initialize_channels(hdsp); | |
5091 | snd_hdsp_initialize_midi_flush(hdsp); | |
5092 | ||
5093 | hdsp->state |= HDSP_FirmwareLoaded; | |
5094 | ||
5095 | if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) { | |
5096 | return err; | |
5097 | } | |
5098 | ||
5099 | return 0; | |
5100 | } | |
5101 | ||
5102 | static int snd_hdsp_free(hdsp_t *hdsp) | |
5103 | { | |
5104 | if (hdsp->port) { | |
5105 | /* stop the audio, and cancel all interrupts */ | |
5106 | tasklet_kill(&hdsp->midi_tasklet); | |
5107 | hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); | |
5108 | hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); | |
5109 | } | |
5110 | ||
5111 | if (hdsp->irq >= 0) | |
5112 | free_irq(hdsp->irq, (void *)hdsp); | |
5113 | ||
5114 | snd_hdsp_free_buffers(hdsp); | |
5115 | ||
5116 | if (hdsp->iobase) | |
5117 | iounmap(hdsp->iobase); | |
5118 | ||
5119 | if (hdsp->port) | |
5120 | pci_release_regions(hdsp->pci); | |
5121 | ||
5122 | pci_disable_device(hdsp->pci); | |
5123 | return 0; | |
5124 | } | |
5125 | ||
5126 | static void snd_hdsp_card_free(snd_card_t *card) | |
5127 | { | |
5128 | hdsp_t *hdsp = (hdsp_t *) card->private_data; | |
5129 | ||
5130 | if (hdsp) | |
5131 | snd_hdsp_free(hdsp); | |
5132 | } | |
5133 | ||
5134 | static int __devinit snd_hdsp_probe(struct pci_dev *pci, | |
5135 | const struct pci_device_id *pci_id) | |
5136 | { | |
5137 | static int dev; | |
5138 | hdsp_t *hdsp; | |
5139 | snd_card_t *card; | |
5140 | int err; | |
5141 | ||
5142 | if (dev >= SNDRV_CARDS) | |
5143 | return -ENODEV; | |
5144 | if (!enable[dev]) { | |
5145 | dev++; | |
5146 | return -ENOENT; | |
5147 | } | |
5148 | ||
5149 | if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t)))) | |
5150 | return -ENOMEM; | |
5151 | ||
5152 | hdsp = (hdsp_t *) card->private_data; | |
5153 | card->private_free = snd_hdsp_card_free; | |
5154 | hdsp->dev = dev; | |
5155 | hdsp->pci = pci; | |
5156 | snd_card_set_dev(card, &pci->dev); | |
5157 | ||
5158 | if ((err = snd_hdsp_create(card, hdsp)) < 0) { | |
5159 | snd_card_free(card); | |
5160 | return err; | |
5161 | } | |
5162 | ||
5163 | strcpy(card->shortname, "Hammerfall DSP"); | |
5164 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, | |
5165 | hdsp->port, hdsp->irq); | |
5166 | ||
5167 | if ((err = snd_card_register(card)) < 0) { | |
5168 | snd_card_free(card); | |
5169 | return err; | |
5170 | } | |
5171 | pci_set_drvdata(pci, card); | |
5172 | dev++; | |
5173 | return 0; | |
5174 | } | |
5175 | ||
5176 | static void __devexit snd_hdsp_remove(struct pci_dev *pci) | |
5177 | { | |
5178 | snd_card_free(pci_get_drvdata(pci)); | |
5179 | pci_set_drvdata(pci, NULL); | |
5180 | } | |
5181 | ||
5182 | static struct pci_driver driver = { | |
5183 | .name = "RME Hammerfall DSP", | |
5184 | .id_table = snd_hdsp_ids, | |
5185 | .probe = snd_hdsp_probe, | |
5186 | .remove = __devexit_p(snd_hdsp_remove), | |
5187 | }; | |
5188 | ||
5189 | static int __init alsa_card_hdsp_init(void) | |
5190 | { | |
01d25d46 | 5191 | return pci_register_driver(&driver); |
1da177e4 LT |
5192 | } |
5193 | ||
5194 | static void __exit alsa_card_hdsp_exit(void) | |
5195 | { | |
5196 | pci_unregister_driver(&driver); | |
5197 | } | |
5198 | ||
5199 | module_init(alsa_card_hdsp_init) | |
5200 | module_exit(alsa_card_hdsp_exit) |