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[ALSA] emu10k1 - Use 31 bit DMA mask for Audigy
[net-next-2.6.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/moduleparam.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/ac97_codec.h>
40#include <sound/info.h>
41#include <sound/initval.h>
42/* for 440MX workaround */
43#include <asm/pgtable.h>
44#include <asm/cacheflush.h>
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
c4c8ea94 58 "{Intel,ESB2},"
1da177e4
LT		 59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
b7fe4622
CL		 67static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
68static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
69static int ac97_clock = 0;
70static char *ac97_quirk;
71static int buggy_semaphore;
72static int buggy_irq;
73static int xbox;
74
75module_param(index, int, 0444);
1da177e4 76MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
b7fe4622 77module_param(id, charp, 0444);
1da177e4 78MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
b7fe4622 79module_param(ac97_clock, int, 0444);
1da177e4 80MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
b7fe4622 81module_param(ac97_quirk, charp, 0444);
1da177e4 82MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 83module_param(buggy_semaphore, bool, 0444);
a06147d2 84MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
b7fe4622 85module_param(buggy_irq, bool, 0444);
1da177e4 86MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
b7fe4622 87module_param(xbox, bool, 0444);
1da177e4
LT		 88MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
89
2b3e584b
TI		 90/* just for backward compatibility */
91static int enable;
698444f3 92module_param(enable, bool, 0444);
2b3e584b
TI		 93static int joystick;
94module_param(joystick, int, 0444);
95
1da177e4
LT		 96/*
97 * Direct registers
98 */
1da177e4
LT		 99enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
100
101#define ICHREG(x) ICH_REG_##x
102
103#define DEFINE_REGSET(name,base) \
104enum { \
105 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
106 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
107 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
108 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
109 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
110 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
111 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
112};
113
114/* busmaster blocks */
115DEFINE_REGSET(OFF, 0); /* offset */
116DEFINE_REGSET(PI, 0x00); /* PCM in */
117DEFINE_REGSET(PO, 0x10); /* PCM out */
118DEFINE_REGSET(MC, 0x20); /* Mic in */
119
120/* ICH4 busmaster blocks */
121DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
122DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
123DEFINE_REGSET(SP, 0x60); /* SPDIF out */
124
125/* values for each busmaster block */
126
127/* LVI */
128#define ICH_REG_LVI_MASK 0x1f
129
130/* SR */
131#define ICH_FIFOE 0x10 /* FIFO error */
132#define ICH_BCIS 0x08 /* buffer completion interrupt status */
133#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
134#define ICH_CELV 0x02 /* current equals last valid */
135#define ICH_DCH 0x01 /* DMA controller halted */
136
137/* PIV */
138#define ICH_REG_PIV_MASK 0x1f /* mask */
139
140/* CR */
141#define ICH_IOCE 0x10 /* interrupt on completion enable */
142#define ICH_FEIE 0x08 /* fifo error interrupt enable */
143#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
144#define ICH_RESETREGS 0x02 /* reset busmaster registers */
145#define ICH_STARTBM 0x01 /* start busmaster operation */
146
147
148/* global block */
149#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
150#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
151#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
152#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
153#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
154#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
155#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
156#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
157#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
158#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
159#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
160#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
161#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
162#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
163#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
164#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
165#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
166#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
167#define ICH_ACLINK 0x00000008 /* AClink shut off */
168#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
169#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
170#define ICH_GIE 0x00000001 /* GPI interrupt enable */
171#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
172#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
173#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
174#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
175#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
176#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
177#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
178#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
179#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
180#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
181#define ICH_MD3 0x00020000 /* modem power down semaphore */
182#define ICH_AD3 0x00010000 /* audio power down semaphore */
183#define ICH_RCS 0x00008000 /* read completion status */
184#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
185#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
186#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
187#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
188#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
189#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
190#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
191#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
192#define ICH_POINT 0x00000040 /* playback interrupt */
193#define ICH_PIINT 0x00000020 /* capture interrupt */
194#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
195#define ICH_MOINT 0x00000004 /* modem playback interrupt */
196#define ICH_MIINT 0x00000002 /* modem capture interrupt */
197#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
198#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
199#define ICH_CAS 0x01 /* codec access semaphore */
200#define ICH_REG_SDM 0x80
201#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
202#define ICH_DI2L_SHIFT 6
203#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
204#define ICH_DI1L_SHIFT 4
205#define ICH_SE 0x00000008 /* steer enable */
206#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
207
208#define ICH_MAX_FRAGS 32 /* max hw frags */
209
210
211/*
212 * registers for Ali5455
213 */
214
215/* ALi 5455 busmaster blocks */
216DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
217DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
218DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
219DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
220DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
221DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
222DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
223DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
224DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
225DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
226DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
227
228enum {
229 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
230 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
231 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
232 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
233 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
234 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
235 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
236 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
237 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
238 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
239 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
240 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
241 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
242 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
243 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
244 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
245 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
246 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
247 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
248 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
249 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
250};
251
252#define ALI_CAS_SEM_BUSY 0x80000000
253#define ALI_CPR_ADDR_SECONDARY 0x100
254#define ALI_CPR_ADDR_READ 0x80
255#define ALI_CSPSR_CODEC_READY 0x08
256#define ALI_CSPSR_READ_OK 0x02
257#define ALI_CSPSR_WRITE_OK 0x01
258
259/* interrupts for the whole chip by interrupt status register finish */
260
261#define ALI_INT_MICIN2 (1<<26)
262#define ALI_INT_PCMIN2 (1<<25)
263#define ALI_INT_I2SIN (1<<24)
264#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
265#define ALI_INT_SPDIFIN (1<<22)
266#define ALI_INT_LFEOUT (1<<21)
267#define ALI_INT_CENTEROUT (1<<20)
268#define ALI_INT_CODECSPDIFOUT (1<<19)
269#define ALI_INT_MICIN (1<<18)
270#define ALI_INT_PCMOUT (1<<17)
271#define ALI_INT_PCMIN (1<<16)
272#define ALI_INT_CPRAIS (1<<7) /* command port available */
273#define ALI_INT_SPRAIS (1<<5) /* status port available */
274#define ALI_INT_GPIO (1<<1)
275#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
276
277#define ICH_ALI_SC_RESET (1<<31) /* master reset */
278#define ICH_ALI_SC_AC97_DBL (1<<30)
279#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
280#define ICH_ALI_SC_IN_BITS (3<<18)
281#define ICH_ALI_SC_OUT_BITS (3<<16)
282#define ICH_ALI_SC_6CH_CFG (3<<14)
283#define ICH_ALI_SC_PCM_4 (1<<8)
284#define ICH_ALI_SC_PCM_6 (2<<8)
285#define ICH_ALI_SC_PCM_246_MASK (3<<8)
286
287#define ICH_ALI_SS_SEC_ID (3<<5)
288#define ICH_ALI_SS_PRI_ID (3<<3)
289
290#define ICH_ALI_IF_AC97SP (1<<21)
291#define ICH_ALI_IF_MC (1<<20)
292#define ICH_ALI_IF_PI (1<<19)
293#define ICH_ALI_IF_MC2 (1<<18)
294#define ICH_ALI_IF_PI2 (1<<17)
295#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
296#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
297#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
298#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
299#define ICH_ALI_IF_PO_SPDF (1<<3)
300#define ICH_ALI_IF_PO (1<<1)
301
302/*
303 *
304 */
305
306enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
307enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
308enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
309
310#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
311
312typedef struct {
313 unsigned int ichd; /* ich device number */
314 unsigned long reg_offset; /* offset to bmaddr */
315 u32 *bdbar; /* CPU address (32bit) */
316 unsigned int bdbar_addr; /* PCI bus address (32bit) */
317 snd_pcm_substream_t *substream;
318 unsigned int physbuf; /* physical address (32bit) */
319 unsigned int size;
320 unsigned int fragsize;
321 unsigned int fragsize1;
322 unsigned int position;
323 unsigned int pos_shift;
324 int frags;
325 int lvi;
326 int lvi_frag;
327 int civ;
328 int ack;
329 int ack_reload;
330 unsigned int ack_bit;
331 unsigned int roff_sr;
332 unsigned int roff_picb;
333 unsigned int int_sta_mask; /* interrupt status mask */
334 unsigned int ali_slot; /* ALI DMA slot */
335 struct ac97_pcm *pcm;
336 int pcm_open_flag;
337 unsigned int page_attr_changed: 1;
1cfe43d2 338 unsigned int suspended: 1;
1da177e4
LT		 339} ichdev_t;
340
341typedef struct _snd_intel8x0 intel8x0_t;
342
343struct _snd_intel8x0 {
344 unsigned int device_type;
345
346 int irq;
347
348 unsigned int mmio;
349 unsigned long addr;
350 void __iomem *remap_addr;
351 unsigned int bm_mmio;
352 unsigned long bmaddr;
353 void __iomem *remap_bmaddr;
354
355 struct pci_dev *pci;
356 snd_card_t *card;
357
358 int pcm_devs;
359 snd_pcm_t *pcm[6];
360 ichdev_t ichd[6];
361
362 unsigned multi4: 1,
363 multi6: 1,
364 dra: 1,
365 smp20bit: 1;
366 unsigned in_ac97_init: 1,
367 in_sdin_init: 1;
368 unsigned in_measurement: 1; /* during ac97 clock measurement */
369 unsigned fix_nocache: 1; /* workaround for 440MX */
370 unsigned buggy_irq: 1; /* workaround for buggy mobos */
371 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 372 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
1da177e4
LT		 373
374 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 375 unsigned int sdm_saved; /* SDM reg value */
1da177e4
LT		 376
377 ac97_bus_t *ac97_bus;
378 ac97_t *ac97[3];
379 unsigned int ac97_sdin[3];
380
381 spinlock_t reg_lock;
382
383 u32 bdbars_count;
384 struct snd_dma_buffer bdbars;
385 u32 int_sta_reg; /* interrupt status register */
386 u32 int_sta_mask; /* interrupt status mask */
387};
388
389static struct pci_device_id snd_intel8x0_ids[] = {
390 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
391 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
392 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
393 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
394 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
395 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
396 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
397 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
398 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 399 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 400 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
401 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
402 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
403 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
404 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
405 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
406 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
407 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
408 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
409 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
410 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
411 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
412 { 0, }
413};
414
415MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
416
417/*
418 * Lowlevel I/O - busmaster
419 */
420
421static u8 igetbyte(intel8x0_t *chip, u32 offset)
422{
423 if (chip->bm_mmio)
424 return readb(chip->remap_bmaddr + offset);
425 else
426 return inb(chip->bmaddr + offset);
427}
428
429static u16 igetword(intel8x0_t *chip, u32 offset)
430{
431 if (chip->bm_mmio)
432 return readw(chip->remap_bmaddr + offset);
433 else
434 return inw(chip->bmaddr + offset);
435}
436
437static u32 igetdword(intel8x0_t *chip, u32 offset)
438{
439 if (chip->bm_mmio)
440 return readl(chip->remap_bmaddr + offset);
441 else
442 return inl(chip->bmaddr + offset);
443}
444
445static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
446{
447 if (chip->bm_mmio)
448 writeb(val, chip->remap_bmaddr + offset);
449 else
450 outb(val, chip->bmaddr + offset);
451}
452
453static void iputword(intel8x0_t *chip, u32 offset, u16 val)
454{
455 if (chip->bm_mmio)
456 writew(val, chip->remap_bmaddr + offset);
457 else
458 outw(val, chip->bmaddr + offset);
459}
460
461static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
462{
463 if (chip->bm_mmio)
464 writel(val, chip->remap_bmaddr + offset);
465 else
466 outl(val, chip->bmaddr + offset);
467}
468
469/*
470 * Lowlevel I/O - AC'97 registers
471 */
472
473static u16 iagetword(intel8x0_t *chip, u32 offset)
474{
475 if (chip->mmio)
476 return readw(chip->remap_addr + offset);
477 else
478 return inw(chip->addr + offset);
479}
480
481static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
482{
483 if (chip->mmio)
484 writew(val, chip->remap_addr + offset);
485 else
486 outw(val, chip->addr + offset);
487}
488
489/*
490 * Basic I/O
491 */
492
493/*
494 * access to AC97 codec via normal i/o (for ICH and SIS7012)
495 */
496
497/* return the GLOB_STA bit for the corresponding codec */
498static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
499{
500 static unsigned int codec_bit[3] = {
501 ICH_PCR, ICH_SCR, ICH_TCR
502 };
503 snd_assert(codec < 3, return ICH_PCR);
504 if (chip->device_type == DEVICE_INTEL_ICH4)
505 codec = chip->ac97_sdin[codec];
506 return codec_bit[codec];
507}
508
509static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
510{
511 int time;
512
513 if (codec > 2)
514 return -EIO;
515 if (chip->in_sdin_init) {
516 /* we don't know the ready bit assignment at the moment */
517 /* so we check any */
518 codec = ICH_PCR | ICH_SCR | ICH_TCR;
519 } else {
520 codec = get_ich_codec_bit(chip, codec);
521 }
522
523 /* codec ready ? */
524 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
525 return -EIO;
526
a06147d2
TI		 527 if (chip->buggy_semaphore)
528 return 0; /* just ignore ... */
529
1da177e4
LT		 530 /* Anyone holding a semaphore for 1 msec should be shot... */
531 time = 100;
532 do {
533 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
534 return 0;
535 udelay(10);
536 } while (time--);
537
538 /* access to some forbidden (non existant) ac97 registers will not
539 * reset the semaphore. So even if you don't get the semaphore, still
540 * continue the access. We don't need the semaphore anyway. */
99b359ba 541 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 542 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
543 iagetword(chip, 0); /* clear semaphore flag */
544 /* I don't care about the semaphore */
545 return -EBUSY;
546}
547
548static void snd_intel8x0_codec_write(ac97_t *ac97,
549 unsigned short reg,
550 unsigned short val)
551{
552 intel8x0_t *chip = ac97->private_data;
553
554 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
555 if (! chip->in_ac97_init)
99b359ba 556 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 557 }
558 iaputword(chip, reg + ac97->num * 0x80, val);
559}
560
561static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
562 unsigned short reg)
563{
564 intel8x0_t *chip = ac97->private_data;
565 unsigned short res;
566 unsigned int tmp;
567
568 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
569 if (! chip->in_ac97_init)
99b359ba 570 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 571 res = 0xffff;
572 } else {
573 res = iagetword(chip, reg + ac97->num * 0x80);
574 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
575 /* reset RCS and preserve other R/WC bits */
576 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
577 if (! chip->in_ac97_init)
99b359ba 578 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 579 res = 0xffff;
580 }
581 }
582 return res;
583}
584
585static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
586{
587 unsigned int tmp;
588
589 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
590 iagetword(chip, codec * 0x80);
591 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
592 /* reset RCS and preserve other R/WC bits */
593 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
594 }
595 }
596}
597
598/*
599 * access to AC97 for Ali5455
600 */
601static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
602{
603 int count = 0;
604 for (count = 0; count < 0x7f; count++) {
605 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
606 if (val & mask)
607 return 0;
608 }
79ba34b9
TI		 609 if (! chip->in_ac97_init)
610 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
1da177e4
LT		 611 return -EBUSY;
612}
613
614static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
615{
616 int time = 100;
79ba34b9
TI		 617 if (chip->buggy_semaphore)
618 return 0; /* just ignore ... */
1da177e4
LT		 619 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
620 udelay(1);
79ba34b9 621 if (! time && ! chip->in_ac97_init)
1da177e4
LT		 622 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
623 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
624}
625
626static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
627{
628 intel8x0_t *chip = ac97->private_data;
629 unsigned short data = 0xffff;
630
631 if (snd_intel8x0_ali_codec_semaphore(chip))
632 goto __err;
633 reg |= ALI_CPR_ADDR_READ;
634 if (ac97->num)
635 reg |= ALI_CPR_ADDR_SECONDARY;
636 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
637 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
638 goto __err;
639 data = igetword(chip, ICHREG(ALI_SPR));
640 __err:
641 return data;
642}
643
644static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
645{
646 intel8x0_t *chip = ac97->private_data;
647
648 if (snd_intel8x0_ali_codec_semaphore(chip))
649 return;
650 iputword(chip, ICHREG(ALI_CPR), val);
651 if (ac97->num)
652 reg |= ALI_CPR_ADDR_SECONDARY;
653 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
654 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
655}
656
657
658/*
659 * DMA I/O
660 */
661static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
662{
663 int idx;
664 u32 *bdbar = ichdev->bdbar;
665 unsigned long port = ichdev->reg_offset;
666
667 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
668 if (ichdev->size == ichdev->fragsize) {
669 ichdev->ack_reload = ichdev->ack = 2;
670 ichdev->fragsize1 = ichdev->fragsize >> 1;
671 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
672 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
673 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
674 ichdev->fragsize1 >> ichdev->pos_shift);
675 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
676 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
677 ichdev->fragsize1 >> ichdev->pos_shift);
678 }
679 ichdev->frags = 2;
680 } else {
681 ichdev->ack_reload = ichdev->ack = 1;
682 ichdev->fragsize1 = ichdev->fragsize;
683 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
684 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
685 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
686 ichdev->fragsize >> ichdev->pos_shift);
687 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
688 }
689 ichdev->frags = ichdev->size / ichdev->fragsize;
690 }
691 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
692 ichdev->civ = 0;
693 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
694 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
695 ichdev->position = 0;
696#if 0
697 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
698 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
699#endif
700 /* clear interrupts */
701 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
702}
703
704#ifdef __i386__
705/*
706 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
707 * which aborts PCI busmaster for audio transfer. A workaround is to set
708 * the pages as non-cached. For details, see the errata in
709 * http://www.intel.com/design/chipsets/specupdt/245051.htm
710 */
711static void fill_nocache(void *buf, int size, int nocache)
712{
713 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
714 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
715 global_flush_tlb();
716}
717#else
718#define fill_nocache(buf,size,nocache)
719#endif
720
721/*
722 * Interrupt handler
723 */
724
725static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
726{
727 unsigned long port = ichdev->reg_offset;
728 int status, civ, i, step;
729 int ack = 0;
730
731 spin_lock(&chip->reg_lock);
732 status = igetbyte(chip, port + ichdev->roff_sr);
733 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
734 if (!(status & ICH_BCIS)) {
735 step = 0;
736 } else if (civ == ichdev->civ) {
737 // snd_printd("civ same %d\n", civ);
738 step = 1;
739 ichdev->civ++;
740 ichdev->civ &= ICH_REG_LVI_MASK;
741 } else {
742 step = civ - ichdev->civ;
743 if (step < 0)
744 step += ICH_REG_LVI_MASK + 1;
745 // if (step != 1)
746 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
747 ichdev->civ = civ;
748 }
749
750 ichdev->position += step * ichdev->fragsize1;
751 if (! chip->in_measurement)
752 ichdev->position %= ichdev->size;
753 ichdev->lvi += step;
754 ichdev->lvi &= ICH_REG_LVI_MASK;
755 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
756 for (i = 0; i < step; i++) {
757 ichdev->lvi_frag++;
758 ichdev->lvi_frag %= ichdev->frags;
759 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
760 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
761 if (--ichdev->ack == 0) {
762 ichdev->ack = ichdev->ack_reload;
763 ack = 1;
764 }
765 }
766 spin_unlock(&chip->reg_lock);
767 if (ack && ichdev->substream) {
768 snd_pcm_period_elapsed(ichdev->substream);
769 }
770 iputbyte(chip, port + ichdev->roff_sr,
771 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
772}
773
774static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
775{
776 intel8x0_t *chip = dev_id;
777 ichdev_t *ichdev;
778 unsigned int status;
779 unsigned int i;
780
781 status = igetdword(chip, chip->int_sta_reg);
782 if (status == 0xffffffff) /* we are not yet resumed */
783 return IRQ_NONE;
784
785 if ((status & chip->int_sta_mask) == 0) {
786 if (status) {
787 /* ack */
788 iputdword(chip, chip->int_sta_reg, status);
789 if (! chip->buggy_irq)
790 status = 0;
791 }
792 return IRQ_RETVAL(status);
793 }
794
795 for (i = 0; i < chip->bdbars_count; i++) {
796 ichdev = &chip->ichd[i];
797 if (status & ichdev->int_sta_mask)
798 snd_intel8x0_update(chip, ichdev);
799 }
800
801 /* ack them */
802 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
803
804 return IRQ_HANDLED;
805}
806
807/*
808 * PCM part
809 */
810
811static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
812{
813 intel8x0_t *chip = snd_pcm_substream_chip(substream);
814 ichdev_t *ichdev = get_ichdev(substream);
815 unsigned char val = 0;
816 unsigned long port = ichdev->reg_offset;
817
818 switch (cmd) {
1da177e4 819 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 820 ichdev->suspended = 0;
821 /* fallthru */
822 case SNDRV_PCM_TRIGGER_START:
1da177e4
LT		 823 val = ICH_IOCE | ICH_STARTBM;
824 break;
1da177e4 825 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 826 ichdev->suspended = 1;
827 /* fallthru */
828 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 829 val = 0;
830 break;
831 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
832 val = ICH_IOCE;
833 break;
834 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
835 val = ICH_IOCE | ICH_STARTBM;
836 break;
837 default:
838 return -EINVAL;
839 }
840 iputbyte(chip, port + ICH_REG_OFF_CR, val);
841 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
842 /* wait until DMA stopped */
843 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
844 /* reset whole DMA things */
845 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
846 }
847 return 0;
848}
849
850static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
851{
852 intel8x0_t *chip = snd_pcm_substream_chip(substream);
853 ichdev_t *ichdev = get_ichdev(substream);
854 unsigned long port = ichdev->reg_offset;
855 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
856 unsigned int val, fifo;
857
858 val = igetdword(chip, ICHREG(ALI_DMACR));
859 switch (cmd) {
1cfe43d2
TI		 860 case SNDRV_PCM_TRIGGER_RESUME:
861 ichdev->suspended = 0;
862 /* fallthru */
1da177e4
LT		 863 case SNDRV_PCM_TRIGGER_START:
864 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 865 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
866 /* clear FIFO for synchronization of channels */
867 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
868 fifo &= ~(0xff << (ichdev->ali_slot % 4));
869 fifo |= 0x83 << (ichdev->ali_slot % 4);
870 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
871 }
872 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
873 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
874 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
875 break;
1cfe43d2
TI		 876 case SNDRV_PCM_TRIGGER_SUSPEND:
877 ichdev->suspended = 1;
878 /* fallthru */
1da177e4
LT		 879 case SNDRV_PCM_TRIGGER_STOP:
880 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1da177e4
LT		 881 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
882 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
883 while (igetbyte(chip, port + ICH_REG_OFF_CR))
884 ;
885 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
886 break;
887 /* reset whole DMA things */
888 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
889 /* clear interrupts */
890 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
891 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
892 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
893 break;
894 default:
895 return -EINVAL;
896 }
897 return 0;
898}
899
900static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
901 snd_pcm_hw_params_t * hw_params)
902{
903 intel8x0_t *chip = snd_pcm_substream_chip(substream);
904 ichdev_t *ichdev = get_ichdev(substream);
905 snd_pcm_runtime_t *runtime = substream->runtime;
906 int dbl = params_rate(hw_params) > 48000;
907 int err;
908
909 if (chip->fix_nocache && ichdev->page_attr_changed) {
910 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
911 ichdev->page_attr_changed = 0;
912 }
913 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
914 if (err < 0)
915 return err;
916 if (chip->fix_nocache) {
917 if (runtime->dma_area && ! ichdev->page_attr_changed) {
918 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
919 ichdev->page_attr_changed = 1;
920 }
921 }
922 if (ichdev->pcm_open_flag) {
923 snd_ac97_pcm_close(ichdev->pcm);
924 ichdev->pcm_open_flag = 0;
925 }
926 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
927 params_channels(hw_params),
928 ichdev->pcm->r[dbl].slots);
929 if (err >= 0) {
930 ichdev->pcm_open_flag = 1;
931 /* Force SPDIF setting */
932 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
933 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
934 }
935 return err;
936}
937
938static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
939{
940 intel8x0_t *chip = snd_pcm_substream_chip(substream);
941 ichdev_t *ichdev = get_ichdev(substream);
942
943 if (ichdev->pcm_open_flag) {
944 snd_ac97_pcm_close(ichdev->pcm);
945 ichdev->pcm_open_flag = 0;
946 }
947 if (chip->fix_nocache && ichdev->page_attr_changed) {
948 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
949 ichdev->page_attr_changed = 0;
950 }
951 return snd_pcm_lib_free_pages(substream);
952}
953
954static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
955 snd_pcm_runtime_t *runtime)
956{
957 unsigned int cnt;
958 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 959
960 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 961 switch (chip->device_type) {
962 case DEVICE_ALI:
963 cnt = igetdword(chip, ICHREG(ALI_SCR));
964 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
965 if (runtime->channels == 4 || dbl)
966 cnt |= ICH_ALI_SC_PCM_4;
967 else if (runtime->channels == 6)
968 cnt |= ICH_ALI_SC_PCM_6;
969 iputdword(chip, ICHREG(ALI_SCR), cnt);
970 break;
971 case DEVICE_SIS:
972 cnt = igetdword(chip, ICHREG(GLOB_CNT));
973 cnt &= ~ICH_SIS_PCM_246_MASK;
974 if (runtime->channels == 4 || dbl)
975 cnt |= ICH_SIS_PCM_4;
976 else if (runtime->channels == 6)
977 cnt |= ICH_SIS_PCM_6;
978 iputdword(chip, ICHREG(GLOB_CNT), cnt);
979 break;
980 default:
981 cnt = igetdword(chip, ICHREG(GLOB_CNT));
982 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
983 if (runtime->channels == 4 || dbl)
984 cnt |= ICH_PCM_4;
985 else if (runtime->channels == 6)
986 cnt |= ICH_PCM_6;
987 if (chip->device_type == DEVICE_NFORCE) {
988 /* reset to 2ch once to keep the 6 channel data in alignment,
989 * to start from Front Left always
990 */
991 if (cnt & ICH_PCM_246_MASK) {
992 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
993 spin_unlock_irq(&chip->reg_lock);
994 msleep(50); /* grrr... */
995 spin_lock_irq(&chip->reg_lock);
996 }
997 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
998 if (runtime->sample_bits > 16)
999 cnt |= ICH_PCM_20BIT;
1000 }
1001 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1002 break;
1003 }
1cfe43d2 1004 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1005}
1006
1007static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1008{
1009 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1010 snd_pcm_runtime_t *runtime = substream->runtime;
1011 ichdev_t *ichdev = get_ichdev(substream);
1012
1013 ichdev->physbuf = runtime->dma_addr;
1014 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1015 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1016 if (ichdev->ichd == ICHD_PCMOUT) {
1017 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1018 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1019 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1020 }
1021 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1022 return 0;
1023}
1024
1025static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1026{
1027 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1028 ichdev_t *ichdev = get_ichdev(substream);
1029 size_t ptr1, ptr;
1030 int civ, timeout = 100;
1031 unsigned int position;
1032
1033 spin_lock(&chip->reg_lock);
1034 do {
1035 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1036 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1037 position = ichdev->position;
1038 if (ptr1 == 0) {
1039 udelay(10);
1040 continue;
1041 }
1042 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1043 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1044 break;
1045 } while (timeout--);
1046 ptr1 <<= ichdev->pos_shift;
1047 ptr = ichdev->fragsize1 - ptr1;
1048 ptr += position;
1049 spin_unlock(&chip->reg_lock);
1050 if (ptr >= ichdev->size)
1051 return 0;
1052 return bytes_to_frames(substream->runtime, ptr);
1053}
1054
1055static snd_pcm_hardware_t snd_intel8x0_stream =
1056{
1057 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1058 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1059 SNDRV_PCM_INFO_MMAP_VALID |
1060 SNDRV_PCM_INFO_PAUSE |
1061 SNDRV_PCM_INFO_RESUME),
1062 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1063 .rates = SNDRV_PCM_RATE_48000,
1064 .rate_min = 48000,
1065 .rate_max = 48000,
1066 .channels_min = 2,
1067 .channels_max = 2,
1068 .buffer_bytes_max = 128 * 1024,
1069 .period_bytes_min = 32,
1070 .period_bytes_max = 128 * 1024,
1071 .periods_min = 1,
1072 .periods_max = 1024,
1073 .fifo_size = 0,
1074};
1075
1076static unsigned int channels4[] = {
1077 2, 4,
1078};
1079
1080static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1081 .count = ARRAY_SIZE(channels4),
1082 .list = channels4,
1083 .mask = 0,
1084};
1085
1086static unsigned int channels6[] = {
1087 2, 4, 6,
1088};
1089
1090static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1091 .count = ARRAY_SIZE(channels6),
1092 .list = channels6,
1093 .mask = 0,
1094};
1095
1096static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1097{
1098 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1099 snd_pcm_runtime_t *runtime = substream->runtime;
1100 int err;
1101
1102 ichdev->substream = substream;
1103 runtime->hw = snd_intel8x0_stream;
1104 runtime->hw.rates = ichdev->pcm->rates;
1105 snd_pcm_limit_hw_rates(runtime);
1106 if (chip->device_type == DEVICE_SIS) {
1107 runtime->hw.buffer_bytes_max = 64*1024;
1108 runtime->hw.period_bytes_max = 64*1024;
1109 }
1110 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1111 return err;
1112 runtime->private_data = ichdev;
1113 return 0;
1114}
1115
1116static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1117{
1118 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1119 snd_pcm_runtime_t *runtime = substream->runtime;
1120 int err;
1121
1122 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1123 if (err < 0)
1124 return err;
1125
1126 if (chip->multi6) {
1127 runtime->hw.channels_max = 6;
1128 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1129 } else if (chip->multi4) {
1130 runtime->hw.channels_max = 4;
1131 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1132 }
1133 if (chip->dra) {
1134 snd_ac97_pcm_double_rate_rules(runtime);
1135 }
1136 if (chip->smp20bit) {
1137 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1138 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1139 }
1140 return 0;
1141}
1142
1143static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1144{
1145 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1146
1147 chip->ichd[ICHD_PCMOUT].substream = NULL;
1148 return 0;
1149}
1150
1151static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1152{
1153 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1154
1155 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1156}
1157
1158static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1159{
1160 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1161
1162 chip->ichd[ICHD_PCMIN].substream = NULL;
1163 return 0;
1164}
1165
1166static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1167{
1168 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1169
1170 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1171}
1172
1173static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1174{
1175 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1176
1177 chip->ichd[ICHD_MIC].substream = NULL;
1178 return 0;
1179}
1180
1181static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1182{
1183 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1184
1185 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1186}
1187
1188static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1189{
1190 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1191
1192 chip->ichd[ICHD_MIC2].substream = NULL;
1193 return 0;
1194}
1195
1196static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1197{
1198 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1199
1200 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1201}
1202
1203static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1204{
1205 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1206
1207 chip->ichd[ICHD_PCM2IN].substream = NULL;
1208 return 0;
1209}
1210
1211static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1212{
1213 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1214 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1215
1216 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1217}
1218
1219static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1220{
1221 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1222 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1223
1224 chip->ichd[idx].substream = NULL;
1225 return 0;
1226}
1227
1228static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1229{
1230 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1231 unsigned int val;
1232
1233 spin_lock_irq(&chip->reg_lock);
1234 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1235 val |= ICH_ALI_IF_AC97SP;
1236 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1237 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1238 spin_unlock_irq(&chip->reg_lock);
1239
1240 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1241}
1242
1243static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1244{
1245 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1246 unsigned int val;
1247
1248 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1249 spin_lock_irq(&chip->reg_lock);
1250 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1251 val &= ~ICH_ALI_IF_AC97SP;
1252 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1253 spin_unlock_irq(&chip->reg_lock);
1254
1255 return 0;
1256}
1257
1258static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1259{
1260 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1261
1262 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1263}
1264
1265static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1266{
1267 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1268
1269 chip->ichd[ALID_SPDIFIN].substream = NULL;
1270 return 0;
1271}
1272
1273#if 0 // NYI
1274static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1275{
1276 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1277
1278 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1279}
1280
1281static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1282{
1283 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1284
1285 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1286 return 0;
1287}
1288#endif
1289
1290static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1291 .open = snd_intel8x0_playback_open,
1292 .close = snd_intel8x0_playback_close,
1293 .ioctl = snd_pcm_lib_ioctl,
1294 .hw_params = snd_intel8x0_hw_params,
1295 .hw_free = snd_intel8x0_hw_free,
1296 .prepare = snd_intel8x0_pcm_prepare,
1297 .trigger = snd_intel8x0_pcm_trigger,
1298 .pointer = snd_intel8x0_pcm_pointer,
1299};
1300
1301static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1302 .open = snd_intel8x0_capture_open,
1303 .close = snd_intel8x0_capture_close,
1304 .ioctl = snd_pcm_lib_ioctl,
1305 .hw_params = snd_intel8x0_hw_params,
1306 .hw_free = snd_intel8x0_hw_free,
1307 .prepare = snd_intel8x0_pcm_prepare,
1308 .trigger = snd_intel8x0_pcm_trigger,
1309 .pointer = snd_intel8x0_pcm_pointer,
1310};
1311
1312static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1313 .open = snd_intel8x0_mic_open,
1314 .close = snd_intel8x0_mic_close,
1315 .ioctl = snd_pcm_lib_ioctl,
1316 .hw_params = snd_intel8x0_hw_params,
1317 .hw_free = snd_intel8x0_hw_free,
1318 .prepare = snd_intel8x0_pcm_prepare,
1319 .trigger = snd_intel8x0_pcm_trigger,
1320 .pointer = snd_intel8x0_pcm_pointer,
1321};
1322
1323static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1324 .open = snd_intel8x0_mic2_open,
1325 .close = snd_intel8x0_mic2_close,
1326 .ioctl = snd_pcm_lib_ioctl,
1327 .hw_params = snd_intel8x0_hw_params,
1328 .hw_free = snd_intel8x0_hw_free,
1329 .prepare = snd_intel8x0_pcm_prepare,
1330 .trigger = snd_intel8x0_pcm_trigger,
1331 .pointer = snd_intel8x0_pcm_pointer,
1332};
1333
1334static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1335 .open = snd_intel8x0_capture2_open,
1336 .close = snd_intel8x0_capture2_close,
1337 .ioctl = snd_pcm_lib_ioctl,
1338 .hw_params = snd_intel8x0_hw_params,
1339 .hw_free = snd_intel8x0_hw_free,
1340 .prepare = snd_intel8x0_pcm_prepare,
1341 .trigger = snd_intel8x0_pcm_trigger,
1342 .pointer = snd_intel8x0_pcm_pointer,
1343};
1344
1345static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1346 .open = snd_intel8x0_spdif_open,
1347 .close = snd_intel8x0_spdif_close,
1348 .ioctl = snd_pcm_lib_ioctl,
1349 .hw_params = snd_intel8x0_hw_params,
1350 .hw_free = snd_intel8x0_hw_free,
1351 .prepare = snd_intel8x0_pcm_prepare,
1352 .trigger = snd_intel8x0_pcm_trigger,
1353 .pointer = snd_intel8x0_pcm_pointer,
1354};
1355
1356static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1357 .open = snd_intel8x0_playback_open,
1358 .close = snd_intel8x0_playback_close,
1359 .ioctl = snd_pcm_lib_ioctl,
1360 .hw_params = snd_intel8x0_hw_params,
1361 .hw_free = snd_intel8x0_hw_free,
1362 .prepare = snd_intel8x0_pcm_prepare,
1363 .trigger = snd_intel8x0_ali_trigger,
1364 .pointer = snd_intel8x0_pcm_pointer,
1365};
1366
1367static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1368 .open = snd_intel8x0_capture_open,
1369 .close = snd_intel8x0_capture_close,
1370 .ioctl = snd_pcm_lib_ioctl,
1371 .hw_params = snd_intel8x0_hw_params,
1372 .hw_free = snd_intel8x0_hw_free,
1373 .prepare = snd_intel8x0_pcm_prepare,
1374 .trigger = snd_intel8x0_ali_trigger,
1375 .pointer = snd_intel8x0_pcm_pointer,
1376};
1377
1378static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1379 .open = snd_intel8x0_mic_open,
1380 .close = snd_intel8x0_mic_close,
1381 .ioctl = snd_pcm_lib_ioctl,
1382 .hw_params = snd_intel8x0_hw_params,
1383 .hw_free = snd_intel8x0_hw_free,
1384 .prepare = snd_intel8x0_pcm_prepare,
1385 .trigger = snd_intel8x0_ali_trigger,
1386 .pointer = snd_intel8x0_pcm_pointer,
1387};
1388
1389static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1390 .open = snd_intel8x0_ali_ac97spdifout_open,
1391 .close = snd_intel8x0_ali_ac97spdifout_close,
1392 .ioctl = snd_pcm_lib_ioctl,
1393 .hw_params = snd_intel8x0_hw_params,
1394 .hw_free = snd_intel8x0_hw_free,
1395 .prepare = snd_intel8x0_pcm_prepare,
1396 .trigger = snd_intel8x0_ali_trigger,
1397 .pointer = snd_intel8x0_pcm_pointer,
1398};
1399
1400static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1401 .open = snd_intel8x0_ali_spdifin_open,
1402 .close = snd_intel8x0_ali_spdifin_close,
1403 .ioctl = snd_pcm_lib_ioctl,
1404 .hw_params = snd_intel8x0_hw_params,
1405 .hw_free = snd_intel8x0_hw_free,
1406 .prepare = snd_intel8x0_pcm_prepare,
1407 .trigger = snd_intel8x0_pcm_trigger,
1408 .pointer = snd_intel8x0_pcm_pointer,
1409};
1410
1411#if 0 // NYI
1412static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1413 .open = snd_intel8x0_ali_spdifout_open,
1414 .close = snd_intel8x0_ali_spdifout_close,
1415 .ioctl = snd_pcm_lib_ioctl,
1416 .hw_params = snd_intel8x0_hw_params,
1417 .hw_free = snd_intel8x0_hw_free,
1418 .prepare = snd_intel8x0_pcm_prepare,
1419 .trigger = snd_intel8x0_pcm_trigger,
1420 .pointer = snd_intel8x0_pcm_pointer,
1421};
1422#endif // NYI
1423
1424struct ich_pcm_table {
1425 char *suffix;
1426 snd_pcm_ops_t *playback_ops;
1427 snd_pcm_ops_t *capture_ops;
1428 size_t prealloc_size;
1429 size_t prealloc_max_size;
1430 int ac97_idx;
1431};
1432
1433static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1434{
1435 snd_pcm_t *pcm;
1436 int err;
1437 char name[32];
1438
1439 if (rec->suffix)
1440 sprintf(name, "Intel ICH - %s", rec->suffix);
1441 else
1442 strcpy(name, "Intel ICH");
1443 err = snd_pcm_new(chip->card, name, device,
1444 rec->playback_ops ? 1 : 0,
1445 rec->capture_ops ? 1 : 0, &pcm);
1446 if (err < 0)
1447 return err;
1448
1449 if (rec->playback_ops)
1450 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1451 if (rec->capture_ops)
1452 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1453
1454 pcm->private_data = chip;
1455 pcm->info_flags = 0;
1456 if (rec->suffix)
1457 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1458 else
1459 strcpy(pcm->name, chip->card->shortname);
1460 chip->pcm[device] = pcm;
1461
1462 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1463 rec->prealloc_size, rec->prealloc_max_size);
1464
1465 return 0;
1466}
1467
1468static struct ich_pcm_table intel_pcms[] __devinitdata = {
1469 {
1470 .playback_ops = &snd_intel8x0_playback_ops,
1471 .capture_ops = &snd_intel8x0_capture_ops,
1472 .prealloc_size = 64 * 1024,
1473 .prealloc_max_size = 128 * 1024,
1474 },
1475 {
1476 .suffix = "MIC ADC",
1477 .capture_ops = &snd_intel8x0_capture_mic_ops,
1478 .prealloc_size = 0,
1479 .prealloc_max_size = 128 * 1024,
1480 .ac97_idx = ICHD_MIC,
1481 },
1482 {
1483 .suffix = "MIC2 ADC",
1484 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1485 .prealloc_size = 0,
1486 .prealloc_max_size = 128 * 1024,
1487 .ac97_idx = ICHD_MIC2,
1488 },
1489 {
1490 .suffix = "ADC2",
1491 .capture_ops = &snd_intel8x0_capture2_ops,
1492 .prealloc_size = 0,
1493 .prealloc_max_size = 128 * 1024,
1494 .ac97_idx = ICHD_PCM2IN,
1495 },
1496 {
1497 .suffix = "IEC958",
1498 .playback_ops = &snd_intel8x0_spdif_ops,
1499 .prealloc_size = 64 * 1024,
1500 .prealloc_max_size = 128 * 1024,
1501 .ac97_idx = ICHD_SPBAR,
1502 },
1503};
1504
1505static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1506 {
1507 .playback_ops = &snd_intel8x0_playback_ops,
1508 .capture_ops = &snd_intel8x0_capture_ops,
1509 .prealloc_size = 64 * 1024,
1510 .prealloc_max_size = 128 * 1024,
1511 },
1512 {
1513 .suffix = "MIC ADC",
1514 .capture_ops = &snd_intel8x0_capture_mic_ops,
1515 .prealloc_size = 0,
1516 .prealloc_max_size = 128 * 1024,
1517 .ac97_idx = NVD_MIC,
1518 },
1519 {
1520 .suffix = "IEC958",
1521 .playback_ops = &snd_intel8x0_spdif_ops,
1522 .prealloc_size = 64 * 1024,
1523 .prealloc_max_size = 128 * 1024,
1524 .ac97_idx = NVD_SPBAR,
1525 },
1526};
1527
1528static struct ich_pcm_table ali_pcms[] __devinitdata = {
1529 {
1530 .playback_ops = &snd_intel8x0_ali_playback_ops,
1531 .capture_ops = &snd_intel8x0_ali_capture_ops,
1532 .prealloc_size = 64 * 1024,
1533 .prealloc_max_size = 128 * 1024,
1534 },
1535 {
1536 .suffix = "MIC ADC",
1537 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1538 .prealloc_size = 0,
1539 .prealloc_max_size = 128 * 1024,
1540 .ac97_idx = ALID_MIC,
1541 },
1542 {
1543 .suffix = "IEC958",
1544 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1545 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1546 .prealloc_size = 64 * 1024,
1547 .prealloc_max_size = 128 * 1024,
1548 .ac97_idx = ALID_AC97SPDIFOUT,
1549 },
1550#if 0 // NYI
1551 {
1552 .suffix = "HW IEC958",
1553 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1554 .prealloc_size = 64 * 1024,
1555 .prealloc_max_size = 128 * 1024,
1556 },
1557#endif
1558};
1559
1560static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1561{
1562 int i, tblsize, device, err;
1563 struct ich_pcm_table *tbl, *rec;
1564
1565 switch (chip->device_type) {
1566 case DEVICE_INTEL_ICH4:
1567 tbl = intel_pcms;
1568 tblsize = ARRAY_SIZE(intel_pcms);
1569 break;
1570 case DEVICE_NFORCE:
1571 tbl = nforce_pcms;
1572 tblsize = ARRAY_SIZE(nforce_pcms);
1573 break;
1574 case DEVICE_ALI:
1575 tbl = ali_pcms;
1576 tblsize = ARRAY_SIZE(ali_pcms);
1577 break;
1578 default:
1579 tbl = intel_pcms;
1580 tblsize = 2;
1581 break;
1582 }
1583
1584 device = 0;
1585 for (i = 0; i < tblsize; i++) {
1586 rec = tbl + i;
1587 if (i > 0 && rec->ac97_idx) {
1588 /* activate PCM only when associated AC'97 codec */
1589 if (! chip->ichd[rec->ac97_idx].pcm)
1590 continue;
1591 }
1592 err = snd_intel8x0_pcm1(chip, device, rec);
1593 if (err < 0)
1594 return err;
1595 device++;
1596 }
1597
1598 chip->pcm_devs = device;
1599 return 0;
1600}
1601
1602
1603/*
1604 * Mixer part
1605 */
1606
1607static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1608{
1609 intel8x0_t *chip = bus->private_data;
1610 chip->ac97_bus = NULL;
1611}
1612
1613static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1614{
1615 intel8x0_t *chip = ac97->private_data;
1616 chip->ac97[ac97->num] = NULL;
1617}
1618
1619static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1620 /* front PCM */
1621 {
1622 .exclusive = 1,
1623 .r = { {
1624 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1625 (1 << AC97_SLOT_PCM_RIGHT) |
1626 (1 << AC97_SLOT_PCM_CENTER) |
1627 (1 << AC97_SLOT_PCM_SLEFT) |
1628 (1 << AC97_SLOT_PCM_SRIGHT) |
1629 (1 << AC97_SLOT_LFE)
1630 },
1631 {
1632 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1633 (1 << AC97_SLOT_PCM_RIGHT) |
1634 (1 << AC97_SLOT_PCM_LEFT_0) |
1635 (1 << AC97_SLOT_PCM_RIGHT_0)
1636 }
1637 }
1638 },
1639 /* PCM IN #1 */
1640 {
1641 .stream = 1,
1642 .exclusive = 1,
1643 .r = { {
1644 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1645 (1 << AC97_SLOT_PCM_RIGHT)
1646 }
1647 }
1648 },
1649 /* MIC IN #1 */
1650 {
1651 .stream = 1,
1652 .exclusive = 1,
1653 .r = { {
1654 .slots = (1 << AC97_SLOT_MIC)
1655 }
1656 }
1657 },
1658 /* S/PDIF PCM */
1659 {
1660 .exclusive = 1,
1661 .spdif = 1,
1662 .r = { {
1663 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1664 (1 << AC97_SLOT_SPDIF_RIGHT2)
1665 }
1666 }
1667 },
1668 /* PCM IN #2 */
1669 {
1670 .stream = 1,
1671 .exclusive = 1,
1672 .r = { {
1673 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1674 (1 << AC97_SLOT_PCM_RIGHT)
1675 }
1676 }
1677 },
1678 /* MIC IN #2 */
1679 {
1680 .stream = 1,
1681 .exclusive = 1,
1682 .r = { {
1683 .slots = (1 << AC97_SLOT_MIC)
1684 }
1685 }
1686 },
1687};
1688
1689static struct ac97_quirk ac97_quirks[] __devinitdata = {
1690 {
6fd8b87f
JCD		 1691 .subvendor = 0x0e11,
1692 .subdevice = 0x008a,
1da177e4
LT		 1693 .name = "Compaq Evo W4000", /* AD1885 */
1694 .type = AC97_TUNE_HP_ONLY
1695 },
1696 {
6fd8b87f
JCD		 1697 .subvendor = 0x0e11,
1698 .subdevice = 0x00b8,
1da177e4
LT		 1699 .name = "Compaq Evo D510C",
1700 .type = AC97_TUNE_HP_ONLY
1701 },
1702 {
6fd8b87f
JCD		 1703 .subvendor = 0x0e11,
1704 .subdevice = 0x0860,
1da177e4
LT		 1705 .name = "HP/Compaq nx7010",
1706 .type = AC97_TUNE_MUTE_LED
1707 },
1708 {
6fd8b87f
JCD		 1709 .subvendor = 0x1014,
1710 .subdevice = 0x1f00,
1da177e4
LT		 1711 .name = "MS-9128",
1712 .type = AC97_TUNE_ALC_JACK
1713 },
5d529390
TI		 1714 {
1715 .subvendor = 0x1014,
1716 .subdevice = 0x0267,
1717 .name = "IBM NetVista A30p", /* AD1981B */
1718 .type = AC97_TUNE_HP_ONLY
1719 },
72c8986c
DS		 1720 {
1721 .subvendor = 0x1025,
1722 .subdevice = 0x0083,
1723 .name = "Acer Aspire 3003LCi",
1724 .type = AC97_TUNE_HP_ONLY
1725 },
1da177e4 1726 {
6fd8b87f
JCD		 1727 .subvendor = 0x1028,
1728 .subdevice = 0x00d8,
1da177e4
LT		 1729 .name = "Dell Precision 530", /* AD1885 */
1730 .type = AC97_TUNE_HP_ONLY
1731 },
1732 {
6fd8b87f
JCD		 1733 .subvendor = 0x1028,
1734 .subdevice = 0x010d,
1da177e4
LT		 1735 .name = "Dell", /* which model? AD1885 */
1736 .type = AC97_TUNE_HP_ONLY
1737 },
1738 {
6fd8b87f
JCD		 1739 .subvendor = 0x1028,
1740 .subdevice = 0x0126,
1da177e4
LT		 1741 .name = "Dell Optiplex GX260", /* AD1981A */
1742 .type = AC97_TUNE_HP_ONLY
1743 },
1744 {
6fd8b87f
JCD		 1745 .subvendor = 0x1028,
1746 .subdevice = 0x012c,
1da177e4
LT		 1747 .name = "Dell Precision 650", /* AD1981A */
1748 .type = AC97_TUNE_HP_ONLY
1749 },
1750 {
6fd8b87f
JCD		 1751 .subvendor = 0x1028,
1752 .subdevice = 0x012d,
1da177e4
LT		 1753 .name = "Dell Precision 450", /* AD1981B*/
1754 .type = AC97_TUNE_HP_ONLY
1755 },
1756 {
6fd8b87f
JCD		 1757 .subvendor = 0x1028,
1758 .subdevice = 0x0147,
1da177e4
LT		 1759 .name = "Dell", /* which model? AD1981B*/
1760 .type = AC97_TUNE_HP_ONLY
1761 },
1762 {
6fd8b87f
JCD		 1763 .subvendor = 0x1028,
1764 .subdevice = 0x0163,
1da177e4
LT		 1765 .name = "Dell Unknown", /* STAC9750/51 */
1766 .type = AC97_TUNE_HP_ONLY
1767 },
1768 {
6fd8b87f
JCD		 1769 .subvendor = 0x103c,
1770 .subdevice = 0x006d,
1da177e4
LT		 1771 .name = "HP zv5000",
1772 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1773 },
1774 { /* FIXME: which codec? */
6fd8b87f
JCD		 1775 .subvendor = 0x103c,
1776 .subdevice = 0x00c3,
1da177e4
LT		 1777 .name = "HP xw6000",
1778 .type = AC97_TUNE_HP_ONLY
1779 },
1780 {
6fd8b87f
JCD		 1781 .subvendor = 0x103c,
1782 .subdevice = 0x088c,
1da177e4
LT		 1783 .name = "HP nc8000",
1784 .type = AC97_TUNE_MUTE_LED
1785 },
1786 {
6fd8b87f
JCD		 1787 .subvendor = 0x103c,
1788 .subdevice = 0x0890,
1da177e4
LT		 1789 .name = "HP nc6000",
1790 .type = AC97_TUNE_MUTE_LED
1791 },
e0c93cf3
DH		 1792 {
1793 .subvendor = 0x103c,
1794 .subdevice = 0x0934,
1795 .name = "HP nx8220",
1796 .type = AC97_TUNE_MUTE_LED
1797 },
66d10647
SV		 1798 {
1799 .subvendor = 0x103c,
1800 .subdevice = 0x099c,
1801 .name = "HP nx6110", /* AD1981B */
1802 .type = AC97_TUNE_HP_ONLY
1803 },
1da177e4 1804 {
6fd8b87f
JCD		 1805 .subvendor = 0x103c,
1806 .subdevice = 0x129d,
1da177e4
LT		 1807 .name = "HP xw8000",
1808 .type = AC97_TUNE_HP_ONLY
1809 },
1810 {
6fd8b87f
JCD		 1811 .subvendor = 0x103c,
1812 .subdevice = 0x12f1,
1da177e4
LT		 1813 .name = "HP xw8200", /* AD1981B*/
1814 .type = AC97_TUNE_HP_ONLY
1815 },
1816 {
6fd8b87f
JCD		 1817 .subvendor = 0x103c,
1818 .subdevice = 0x12f2,
1da177e4
LT		 1819 .name = "HP xw6200",
1820 .type = AC97_TUNE_HP_ONLY
1821 },
1822 {
6fd8b87f
JCD		 1823 .subvendor = 0x103c,
1824 .subdevice = 0x3008,
1da177e4
LT		 1825 .name = "HP xw4200", /* AD1981B*/
1826 .type = AC97_TUNE_HP_ONLY
1827 },
1828 {
6fd8b87f
JCD		 1829 .subvendor = 0x104d,
1830 .subdevice = 0x8197,
1da177e4
LT		 1831 .name = "Sony S1XP",
1832 .type = AC97_TUNE_INV_EAPD
1833 },
1834 {
6fd8b87f
JCD		 1835 .subvendor = 0x1043,
1836 .subdevice = 0x80f3,
1da177e4
LT		 1837 .name = "ASUS ICH5/AD1985",
1838 .type = AC97_TUNE_AD_SHARING
1839 },
1840 {
6fd8b87f
JCD		 1841 .subvendor = 0x10cf,
1842 .subdevice = 0x11c3,
1da177e4
LT		 1843 .name = "Fujitsu-Siemens E4010",
1844 .type = AC97_TUNE_HP_ONLY
1845 },
98c7f212
TI		 1846 {
1847 .subvendor = 0x10cf,
1848 .subdevice = 0x1225,
1849 .name = "Fujitsu-Siemens T3010",
1850 .type = AC97_TUNE_HP_ONLY
1851 },
1da177e4 1852 {
6fd8b87f
JCD		 1853 .subvendor = 0x10cf,
1854 .subdevice = 0x1253,
1da177e4
LT		 1855 .name = "Fujitsu S6210", /* STAC9750/51 */
1856 .type = AC97_TUNE_HP_ONLY
1857 },
9970dce5
TI		 1858 {
1859 .subvendor = 0x10cf,
1860 .subdevice = 0x12ec,
1861 .name = "Fujitsu-Siemens 4010",
1862 .type = AC97_TUNE_HP_ONLY
1863 },
1da177e4 1864 {
6fd8b87f
JCD		 1865 .subvendor = 0x10f1,
1866 .subdevice = 0x2665,
1da177e4
LT		 1867 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1868 .type = AC97_TUNE_HP_ONLY
1869 },
1870 {
6fd8b87f
JCD		 1871 .subvendor = 0x10f1,
1872 .subdevice = 0x2885,
1da177e4
LT		 1873 .name = "AMD64 Mobo", /* ALC650 */
1874 .type = AC97_TUNE_HP_ONLY
1875 },
1876 {
6fd8b87f
JCD		 1877 .subvendor = 0x110a,
1878 .subdevice = 0x0056,
1da177e4
LT		 1879 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1880 .type = AC97_TUNE_HP_ONLY
1881 },
1882 {
6fd8b87f
JCD		 1883 .subvendor = 0x11d4,
1884 .subdevice = 0x5375,
1da177e4
LT		 1885 .name = "ADI AD1985 (discrete)",
1886 .type = AC97_TUNE_HP_ONLY
1887 },
1888 {
6fd8b87f
JCD		 1889 .subvendor = 0x1462,
1890 .subdevice = 0x5470,
1da177e4
LT		 1891 .name = "MSI P4 ATX 645 Ultra",
1892 .type = AC97_TUNE_HP_ONLY
1893 },
1894 {
6fd8b87f
JCD		 1895 .subvendor = 0x1734,
1896 .subdevice = 0x0088,
1da177e4
LT		 1897 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1898 .type = AC97_TUNE_HP_ONLY
1899 },
1900 {
6fd8b87f
JCD		 1901 .subvendor = 0x8086,
1902 .subdevice = 0x2000,
1da177e4
LT		 1903 .mask = 0xfff0,
1904 .name = "Intel ICH5/AD1985",
1905 .type = AC97_TUNE_AD_SHARING
1906 },
1907 {
6fd8b87f
JCD		 1908 .subvendor = 0x8086,
1909 .subdevice = 0x4000,
1da177e4
LT		 1910 .mask = 0xfff0,
1911 .name = "Intel ICH5/AD1985",
1912 .type = AC97_TUNE_AD_SHARING
1913 },
1914 {
6fd8b87f
JCD		 1915 .subvendor = 0x8086,
1916 .subdevice = 0x4856,
1da177e4
LT		 1917 .name = "Intel D845WN (82801BA)",
1918 .type = AC97_TUNE_SWAP_HP
1919 },
1920 {
6fd8b87f
JCD		 1921 .subvendor = 0x8086,
1922 .subdevice = 0x4d44,
1da177e4
LT		 1923 .name = "Intel D850EMV2", /* AD1885 */
1924 .type = AC97_TUNE_HP_ONLY
1925 },
1926 {
6fd8b87f
JCD		 1927 .subvendor = 0x8086,
1928 .subdevice = 0x4d56,
1da177e4
LT		 1929 .name = "Intel ICH/AD1885",
1930 .type = AC97_TUNE_HP_ONLY
1931 },
1932 {
6fd8b87f
JCD		 1933 .subvendor = 0x8086,
1934 .subdevice = 0x6000,
1da177e4
LT		 1935 .mask = 0xfff0,
1936 .name = "Intel ICH5/AD1985",
1937 .type = AC97_TUNE_AD_SHARING
1938 },
1939 {
6fd8b87f
JCD		 1940 .subvendor = 0x8086,
1941 .subdevice = 0xe000,
1da177e4
LT		 1942 .mask = 0xfff0,
1943 .name = "Intel ICH5/AD1985",
1944 .type = AC97_TUNE_AD_SHARING
1945 },
1946#if 0 /* FIXME: this seems wrong on most boards */
1947 {
6fd8b87f
JCD		 1948 .subvendor = 0x8086,
1949 .subdevice = 0xa000,
1da177e4
LT		 1950 .mask = 0xfff0,
1951 .name = "Intel ICH5/AD1985",
1952 .type = AC97_TUNE_HP_ONLY
1953 },
1954#endif
1955 { } /* terminator */
1956};
1957
1958static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1959{
1960 ac97_bus_t *pbus;
1961 ac97_template_t ac97;
1962 int err;
1963 unsigned int i, codecs;
1964 unsigned int glob_sta = 0;
1965 ac97_bus_ops_t *ops;
1966 static ac97_bus_ops_t standard_bus_ops = {
1967 .write = snd_intel8x0_codec_write,
1968 .read = snd_intel8x0_codec_read,
1969 };
1970 static ac97_bus_ops_t ali_bus_ops = {
1971 .write = snd_intel8x0_ali_codec_write,
1972 .read = snd_intel8x0_ali_codec_read,
1973 };
1974
1975 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1976 switch (chip->device_type) {
1977 case DEVICE_NFORCE:
1978 chip->spdif_idx = NVD_SPBAR;
1979 break;
1980 case DEVICE_ALI:
1981 chip->spdif_idx = ALID_AC97SPDIFOUT;
1982 break;
1983 case DEVICE_INTEL_ICH4:
1984 chip->spdif_idx = ICHD_SPBAR;
1985 break;
1986 };
1987
1988 chip->in_ac97_init = 1;
1989
1990 memset(&ac97, 0, sizeof(ac97));
1991 ac97.private_data = chip;
1992 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1993 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1994 if (chip->xbox)
1995 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1996 if (chip->device_type != DEVICE_ALI) {
1997 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1998 ops = &standard_bus_ops;
1999 if (chip->device_type == DEVICE_INTEL_ICH4) {
2000 codecs = 0;
2001 if (glob_sta & ICH_PCR)
2002 codecs++;
2003 if (glob_sta & ICH_SCR)
2004 codecs++;
2005 if (glob_sta & ICH_TCR)
2006 codecs++;
2007 chip->in_sdin_init = 1;
2008 for (i = 0; i < codecs; i++) {
2009 snd_intel8x0_codec_read_test(chip, i);
2010 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2011 }
2012 chip->in_sdin_init = 0;
2013 } else {
2014 codecs = glob_sta & ICH_SCR ? 2 : 1;
2015 }
2016 } else {
2017 ops = &ali_bus_ops;
2018 codecs = 1;
2019 /* detect the secondary codec */
2020 for (i = 0; i < 100; i++) {
2021 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2022 if (reg & 0x40) {
2023 codecs = 2;
2024 break;
2025 }
2026 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2027 udelay(1);
2028 }
2029 }
2030 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2031 goto __err;
2032 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2033 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2034 pbus->clock = ac97_clock;
2035 /* FIXME: my test board doesn't work well with VRA... */
2036 if (chip->device_type == DEVICE_ALI)
2037 pbus->no_vra = 1;
2038 else
2039 pbus->dra = 1;
2040 chip->ac97_bus = pbus;
2041
2042 ac97.pci = chip->pci;
2043 for (i = 0; i < codecs; i++) {
2044 ac97.num = i;
2045 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2046 if (err != -EACCES)
2047 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2048 if (i == 0)
2049 goto __err;
2050 continue;
2051 }
2052 }
2053 /* tune up the primary codec */
2054 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2055 /* enable separate SDINs for ICH4 */
2056 if (chip->device_type == DEVICE_INTEL_ICH4)
2057 pbus->isdin = 1;
2058 /* find the available PCM streams */
2059 i = ARRAY_SIZE(ac97_pcm_defs);
2060 if (chip->device_type != DEVICE_INTEL_ICH4)
2061 i -= 2; /* do not allocate PCM2IN and MIC2 */
2062 if (chip->spdif_idx < 0)
2063 i--; /* do not allocate S/PDIF */
2064 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2065 if (err < 0)
2066 goto __err;
2067 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2068 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2069 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2070 if (chip->spdif_idx >= 0)
2071 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2072 if (chip->device_type == DEVICE_INTEL_ICH4) {
2073 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2074 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2075 }
2076 /* enable separate SDINs for ICH4 */
2077 if (chip->device_type == DEVICE_INTEL_ICH4) {
2078 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2079 u8 tmp = igetbyte(chip, ICHREG(SDM));
2080 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2081 if (pcm) {
2082 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2083 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2084 for (i = 1; i < 4; i++) {
2085 if (pcm->r[0].codec[i]) {
2086 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2087 break;
2088 }
2089 }
2090 } else {
2091 tmp &= ~ICH_SE; /* steer disable */
2092 }
2093 iputbyte(chip, ICHREG(SDM), tmp);
2094 }
2095 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2096 chip->multi4 = 1;
2097 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2098 chip->multi6 = 1;
2099 }
2100 if (pbus->pcms[0].r[1].rslots[0]) {
2101 chip->dra = 1;
2102 }
2103 if (chip->device_type == DEVICE_INTEL_ICH4) {
2104 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2105 chip->smp20bit = 1;
2106 }
2107 if (chip->device_type == DEVICE_NFORCE) {
2108 /* 48kHz only */
2109 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2110 }
2111 if (chip->device_type == DEVICE_INTEL_ICH4) {
2112 /* use slot 10/11 for SPDIF */
2113 u32 val;
2114 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2115 val |= ICH_PCM_SPDIF_1011;
2116 iputdword(chip, ICHREG(GLOB_CNT), val);
2117 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2118 }
2119 chip->in_ac97_init = 0;
2120 return 0;
2121
2122 __err:
2123 /* clear the cold-reset bit for the next chance */
2124 if (chip->device_type != DEVICE_ALI)
2125 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2126 return err;
2127}
2128
2129
2130/*
2131 *
2132 */
2133
2134static void do_ali_reset(intel8x0_t *chip)
2135{
2136 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2137 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2138 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2139 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2140 iputdword(chip, ICHREG(ALI_INTERFACECR),
d78bec21 2141 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1da177e4
LT		 2142 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2143 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2144}
2145
2146#define do_delay(chip) do {\
8433a509 2147 schedule_timeout_uninterruptible(1);\
1da177e4
LT		 2148} while (0)
2149
2150static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2151{
2152 unsigned long end_time;
2153 unsigned int cnt, status, nstatus;
2154
2155 /* put logic to right state */
2156 /* first clear status bits */
2157 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2158 if (chip->device_type == DEVICE_NFORCE)
2159 status |= ICH_NVSPINT;
2160 cnt = igetdword(chip, ICHREG(GLOB_STA));
2161 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2162
2163 /* ACLink on, 2 channels */
2164 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2165 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2166 /* finish cold or do warm reset */
2167 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2168 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2169 end_time = (jiffies + (HZ / 4)) + 1;
2170 do {
2171 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2172 goto __ok;
2173 do_delay(chip);
2174 } while (time_after_eq(end_time, jiffies));
99b359ba 2175 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4
LT		 2176 return -EIO;
2177
2178 __ok:
2179 if (probing) {
2180 /* wait for any codec ready status.
2181 * Once it becomes ready it should remain ready
2182 * as long as we do not disable the ac97 link.
2183 */
2184 end_time = jiffies + HZ;
2185 do {
2186 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2187 if (status)
2188 break;
2189 do_delay(chip);
2190 } while (time_after_eq(end_time, jiffies));
2191 if (! status) {
2192 /* no codec is found */
2193 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2194 return -EIO;
2195 }
2196
2197 if (chip->device_type == DEVICE_INTEL_ICH4)
2198 /* ICH4 can have three codecs */
2199 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2200 else
2201 /* others up to two codecs */
2202 nstatus = ICH_PCR | ICH_SCR;
2203
2204 /* wait for other codecs ready status. */
2205 end_time = jiffies + HZ / 4;
2206 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2207 do_delay(chip);
2208 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2209 }
2210
2211 } else {
2212 /* resume phase */
2213 int i;
2214 status = 0;
2215 for (i = 0; i < 3; i++)
2216 if (chip->ac97[i])
2217 status |= get_ich_codec_bit(chip, i);
2218 /* wait until all the probed codecs are ready */
2219 end_time = jiffies + HZ;
2220 do {
2221 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2222 if (status == nstatus)
2223 break;
2224 do_delay(chip);
2225 } while (time_after_eq(end_time, jiffies));
2226 }
2227
2228 if (chip->device_type == DEVICE_SIS) {
2229 /* unmute the output on SIS7012 */
2230 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2231 }
2232 if (chip->device_type == DEVICE_NFORCE) {
2233 /* enable SPDIF interrupt */
2234 unsigned int val;
2235 pci_read_config_dword(chip->pci, 0x4c, &val);
2236 val |= 0x1000000;
2237 pci_write_config_dword(chip->pci, 0x4c, val);
2238 }
2239 return 0;
2240}
2241
2242static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2243{
2244 u32 reg;
2245 int i = 0;
2246
2247 reg = igetdword(chip, ICHREG(ALI_SCR));
2248 if ((reg & 2) == 0) /* Cold required */
2249 reg |= 2;
2250 else
2251 reg |= 1; /* Warm */
2252 reg &= ~0x80000000; /* ACLink on */
2253 iputdword(chip, ICHREG(ALI_SCR), reg);
2254
2255 for (i = 0; i < HZ / 2; i++) {
2256 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2257 goto __ok;
2258 do_delay(chip);
2259 }
2260 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2261 if (probing)
2262 return -EIO;
2263
2264 __ok:
2265 for (i = 0; i < HZ / 2; i++) {
2266 reg = igetdword(chip, ICHREG(ALI_RTSR));
2267 if (reg & 0x80) /* primary codec */
2268 break;
2269 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2270 do_delay(chip);
2271 }
2272
2273 do_ali_reset(chip);
2274 return 0;
2275}
2276
2277static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2278{
2279 unsigned int i;
2280 int err;
2281
2282 if (chip->device_type != DEVICE_ALI) {
2283 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2284 return err;
2285 iagetword(chip, 0); /* clear semaphore flag */
2286 } else {
2287 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2288 return err;
2289 }
2290
2291 /* disable interrupts */
2292 for (i = 0; i < chip->bdbars_count; i++)
2293 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2294 /* reset channels */
2295 for (i = 0; i < chip->bdbars_count; i++)
2296 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2297 /* initialize Buffer Descriptor Lists */
2298 for (i = 0; i < chip->bdbars_count; i++)
2299 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2300 return 0;
2301}
2302
2303static int snd_intel8x0_free(intel8x0_t *chip)
2304{
2305 unsigned int i;
2306
2307 if (chip->irq < 0)
2308 goto __hw_end;
2309 /* disable interrupts */
2310 for (i = 0; i < chip->bdbars_count; i++)
2311 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2312 /* reset channels */
2313 for (i = 0; i < chip->bdbars_count; i++)
2314 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2315 if (chip->device_type == DEVICE_NFORCE) {
2316 /* stop the spdif interrupt */
2317 unsigned int val;
2318 pci_read_config_dword(chip->pci, 0x4c, &val);
2319 val &= ~0x1000000;
2320 pci_write_config_dword(chip->pci, 0x4c, val);
2321 }
2322 /* --- */
2323 synchronize_irq(chip->irq);
2324 __hw_end:
2325 if (chip->irq >= 0)
2326 free_irq(chip->irq, (void *)chip);
2327 if (chip->bdbars.area) {
2328 if (chip->fix_nocache)
2329 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2330 snd_dma_free_pages(&chip->bdbars);
2331 }
2332 if (chip->remap_addr)
2333 iounmap(chip->remap_addr);
2334 if (chip->remap_bmaddr)
2335 iounmap(chip->remap_bmaddr);
2336 pci_release_regions(chip->pci);
2337 pci_disable_device(chip->pci);
2338 kfree(chip);
2339 return 0;
2340}
2341
2342#ifdef CONFIG_PM
2343/*
2344 * power management
2345 */
2346static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2347{
2348 intel8x0_t *chip = card->pm_private_data;
2349 int i;
2350
2351 for (i = 0; i < chip->pcm_devs; i++)
2352 snd_pcm_suspend_all(chip->pcm[i]);
2353 /* clear nocache */
2354 if (chip->fix_nocache) {
2355 for (i = 0; i < chip->bdbars_count; i++) {
2356 ichdev_t *ichdev = &chip->ichd[i];
2357 if (ichdev->substream && ichdev->page_attr_changed) {
2358 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2359 if (runtime->dma_area)
2360 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2361 }
2362 }
2363 }
2364 for (i = 0; i < 3; i++)
2365 if (chip->ac97[i])
2366 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2367 if (chip->device_type == DEVICE_INTEL_ICH4)
2368 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2369
90158b83
RW		 2370 if (chip->irq >= 0)
2371 free_irq(chip->irq, (void *)chip);
1da177e4
LT		 2372 pci_disable_device(chip->pci);
2373 return 0;
2374}
2375
2376static int intel8x0_resume(snd_card_t *card)
2377{
2378 intel8x0_t *chip = card->pm_private_data;
2379 int i;
2380
2381 pci_enable_device(chip->pci);
2382 pci_set_master(chip->pci);
90158b83
RW		 2383 request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2384 synchronize_irq(chip->irq);
2385 snd_intel8x0_chip_init(chip, 1);
1da177e4 2386
52b72388
TI		 2387 /* re-initialize mixer stuff */
2388 if (chip->device_type == DEVICE_INTEL_ICH4) {
2389 /* enable separate SDINs for ICH4 */
2390 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2391 /* use slot 10/11 for SPDIF */
2392 iputdword(chip, ICHREG(GLOB_CNT),
2393 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2394 ICH_PCM_SPDIF_1011);
2395 }
2396
1da177e4
LT		 2397 /* refill nocache */
2398 if (chip->fix_nocache)
2399 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2400
2401 for (i = 0; i < 3; i++)
2402 if (chip->ac97[i])
2403 snd_ac97_resume(chip->ac97[i]);
2404
2405 /* refill nocache */
2406 if (chip->fix_nocache) {
2407 for (i = 0; i < chip->bdbars_count; i++) {
2408 ichdev_t *ichdev = &chip->ichd[i];
2409 if (ichdev->substream && ichdev->page_attr_changed) {
2410 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2411 if (runtime->dma_area)
2412 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2413 }
2414 }
2415 }
2416
1cfe43d2
TI		 2417 /* resume status */
2418 for (i = 0; i < chip->bdbars_count; i++) {
2419 ichdev_t *ichdev = &chip->ichd[i];
2420 unsigned long port = ichdev->reg_offset;
2421 if (! ichdev->substream || ! ichdev->suspended)
2422 continue;
2423 if (ichdev->ichd == ICHD_PCMOUT)
2424 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2425 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2426 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2427 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2428 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2429 }
2430
1da177e4
LT		 2431 return 0;
2432}
2433#endif /* CONFIG_PM */
2434
2435#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2436
2437static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2438{
2439 snd_pcm_substream_t *subs;
2440 ichdev_t *ichdev;
2441 unsigned long port;
2442 unsigned long pos, t;
2443 struct timeval start_time, stop_time;
2444
2445 if (chip->ac97_bus->clock != 48000)
2446 return; /* specified in module option */
2447
2448 subs = chip->pcm[0]->streams[0].substream;
2449 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
99b359ba 2450 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
1da177e4
LT		 2451 return;
2452 }
2453 ichdev = &chip->ichd[ICHD_PCMOUT];
2454 ichdev->physbuf = subs->dma_buffer.addr;
2455 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2456 ichdev->substream = NULL; /* don't process interrupts */
2457
2458 /* set rate */
2459 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2460 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2461 return;
2462 }
2463 snd_intel8x0_setup_periods(chip, ichdev);
2464 port = ichdev->reg_offset;
2465 spin_lock_irq(&chip->reg_lock);
2466 chip->in_measurement = 1;
2467 /* trigger */
2468 if (chip->device_type != DEVICE_ALI)
2469 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2470 else {
2471 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2472 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2473 }
2474 do_gettimeofday(&start_time);
2475 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2476 msleep(50);
1da177e4
LT		 2477 spin_lock_irq(&chip->reg_lock);
2478 /* check the position */
2479 pos = ichdev->fragsize1;
2480 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2481 pos += ichdev->position;
2482 chip->in_measurement = 0;
2483 do_gettimeofday(&stop_time);
2484 /* stop */
2485 if (chip->device_type == DEVICE_ALI) {
d78bec21 2486 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
1da177e4
LT		 2487 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2488 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2489 ;
2490 } else {
2491 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2492 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2493 ;
2494 }
2495 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2496 spin_unlock_irq(&chip->reg_lock);
2497
2498 t = stop_time.tv_sec - start_time.tv_sec;
2499 t *= 1000000;
2500 t += stop_time.tv_usec - start_time.tv_usec;
2501 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2502 if (t == 0) {
2503 snd_printk(KERN_ERR "?? calculation error..\n");
2504 return;
2505 }
2506 pos = (pos / 4) * 1000;
2507 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2508 if (pos < 40000 || pos >= 60000)
2509 /* abnormal value. hw problem? */
2510 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2511 else if (pos < 47500 || pos > 48500)
2512 /* not 48000Hz, tuning the clock.. */
2513 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2514 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2515}
2516
2517static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2518 snd_info_buffer_t * buffer)
2519{
2520 intel8x0_t *chip = entry->private_data;
2521 unsigned int tmp;
2522
2523 snd_iprintf(buffer, "Intel8x0\n\n");
2524 if (chip->device_type == DEVICE_ALI)
2525 return;
2526 tmp = igetdword(chip, ICHREG(GLOB_STA));
2527 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2528 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2529 if (chip->device_type == DEVICE_INTEL_ICH4)
2530 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2531 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2532 tmp & ICH_PCR ? " primary" : "",
2533 tmp & ICH_SCR ? " secondary" : "",
2534 tmp & ICH_TCR ? " tertiary" : "",
2535 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2536 if (chip->device_type == DEVICE_INTEL_ICH4)
2537 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2538 chip->ac97_sdin[0],
2539 chip->ac97_sdin[1],
2540 chip->ac97_sdin[2]);
2541}
2542
2543static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2544{
2545 snd_info_entry_t *entry;
2546
2547 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2548 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2549}
2550
2551static int snd_intel8x0_dev_free(snd_device_t *device)
2552{
2553 intel8x0_t *chip = device->device_data;
2554 return snd_intel8x0_free(chip);
2555}
2556
2557struct ich_reg_info {
2558 unsigned int int_sta_mask;
2559 unsigned int offset;
2560};
2561
2562static int __devinit snd_intel8x0_create(snd_card_t * card,
2563 struct pci_dev *pci,
2564 unsigned long device_type,
2565 intel8x0_t ** r_intel8x0)
2566{
2567 intel8x0_t *chip;
2568 int err;
2569 unsigned int i;
2570 unsigned int int_sta_masks;
2571 ichdev_t *ichdev;
2572 static snd_device_ops_t ops = {
2573 .dev_free = snd_intel8x0_dev_free,
2574 };
2575
2576 static unsigned int bdbars[] = {
2577 3, /* DEVICE_INTEL */
2578 6, /* DEVICE_INTEL_ICH4 */
2579 3, /* DEVICE_SIS */
2580 6, /* DEVICE_ALI */
2581 4, /* DEVICE_NFORCE */
2582 };
2583 static struct ich_reg_info intel_regs[6] = {
2584 { ICH_PIINT, 0 },
2585 { ICH_POINT, 0x10 },
2586 { ICH_MCINT, 0x20 },
2587 { ICH_M2INT, 0x40 },
2588 { ICH_P2INT, 0x50 },
2589 { ICH_SPINT, 0x60 },
2590 };
2591 static struct ich_reg_info nforce_regs[4] = {
2592 { ICH_PIINT, 0 },
2593 { ICH_POINT, 0x10 },
2594 { ICH_MCINT, 0x20 },
2595 { ICH_NVSPINT, 0x70 },
2596 };
2597 static struct ich_reg_info ali_regs[6] = {
2598 { ALI_INT_PCMIN, 0x40 },
2599 { ALI_INT_PCMOUT, 0x50 },
2600 { ALI_INT_MICIN, 0x60 },
2601 { ALI_INT_CODECSPDIFOUT, 0x70 },
2602 { ALI_INT_SPDIFIN, 0xa0 },
2603 { ALI_INT_SPDIFOUT, 0xb0 },
2604 };
2605 struct ich_reg_info *tbl;
2606
2607 *r_intel8x0 = NULL;
2608
2609 if ((err = pci_enable_device(pci)) < 0)
2610 return err;
2611
e560d8d8 2612 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2613 if (chip == NULL) {
2614 pci_disable_device(pci);
2615 return -ENOMEM;
2616 }
2617 spin_lock_init(&chip->reg_lock);
2618 chip->device_type = device_type;
2619 chip->card = card;
2620 chip->pci = pci;
2621 chip->irq = -1;
c829b052
TI		 2622
2623 /* module parameters */
2624 chip->buggy_irq = buggy_irq;
2625 chip->buggy_semaphore = buggy_semaphore;
2626 if (xbox)
2627 chip->xbox = 1;
1da177e4
LT		 2628
2629 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2630 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2631 chip->fix_nocache = 1; /* enable workaround */
2632
2633 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2634 * Needs to return IRQ_HANDLED for unknown irqs.
2635 */
2636 if (device_type == DEVICE_NFORCE)
2637 chip->buggy_irq = 1;
2638
2639 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2640 kfree(chip);
2641 pci_disable_device(pci);
2642 return err;
2643 }
2644
2645 if (device_type == DEVICE_ALI) {
2646 /* ALI5455 has no ac97 region */
2647 chip->bmaddr = pci_resource_start(pci, 0);
2648 goto port_inited;
2649 }
2650
2651 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2652 chip->mmio = 1;
2653 chip->addr = pci_resource_start(pci, 2);
2654 chip->remap_addr = ioremap_nocache(chip->addr,
2655 pci_resource_len(pci, 2));
2656 if (chip->remap_addr == NULL) {
99b359ba 2657 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1da177e4
LT		 2658 snd_intel8x0_free(chip);
2659 return -EIO;
2660 }
2661 } else {
2662 chip->addr = pci_resource_start(pci, 0);
2663 }
2664 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2665 chip->bm_mmio = 1;
2666 chip->bmaddr = pci_resource_start(pci, 3);
2667 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2668 pci_resource_len(pci, 3));
2669 if (chip->remap_bmaddr == NULL) {
99b359ba 2670 snd_printk(KERN_ERR "Controller space ioremap problem\n");
1da177e4
LT		 2671 snd_intel8x0_free(chip);
2672 return -EIO;
2673 }
2674 } else {
2675 chip->bmaddr = pci_resource_start(pci, 1);
2676 }
2677
2678 port_inited:
2679 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
99b359ba 2680 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2681 snd_intel8x0_free(chip);
2682 return -EBUSY;
2683 }
2684 chip->irq = pci->irq;
2685 pci_set_master(pci);
2686 synchronize_irq(chip->irq);
2687
2688 chip->bdbars_count = bdbars[device_type];
2689
2690 /* initialize offsets */
2691 switch (device_type) {
2692 case DEVICE_NFORCE:
2693 tbl = nforce_regs;
2694 break;
2695 case DEVICE_ALI:
2696 tbl = ali_regs;
2697 break;
2698 default:
2699 tbl = intel_regs;
2700 break;
2701 }
2702 for (i = 0; i < chip->bdbars_count; i++) {
2703 ichdev = &chip->ichd[i];
2704 ichdev->ichd = i;
2705 ichdev->reg_offset = tbl[i].offset;
2706 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2707 if (device_type == DEVICE_SIS) {
2708 /* SiS 7012 swaps the registers */
2709 ichdev->roff_sr = ICH_REG_OFF_PICB;
2710 ichdev->roff_picb = ICH_REG_OFF_SR;
2711 } else {
2712 ichdev->roff_sr = ICH_REG_OFF_SR;
2713 ichdev->roff_picb = ICH_REG_OFF_PICB;
2714 }
2715 if (device_type == DEVICE_ALI)
2716 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2717 /* SIS7012 handles the pcm data in bytes, others are in samples */
2718 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2719 }
2720
2721 /* allocate buffer descriptor lists */
2722 /* the start of each lists must be aligned to 8 bytes */
2723 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2724 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2725 &chip->bdbars) < 0) {
2726 snd_intel8x0_free(chip);
2727 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2728 return -ENOMEM;
2729 }
2730 /* tables must be aligned to 8 bytes here, but the kernel pages
2731 are much bigger, so we don't care (on i386) */
2732 /* workaround for 440MX */
2733 if (chip->fix_nocache)
2734 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2735 int_sta_masks = 0;
2736 for (i = 0; i < chip->bdbars_count; i++) {
2737 ichdev = &chip->ichd[i];
2738 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2739 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2740 int_sta_masks |= ichdev->int_sta_mask;
2741 }
2742 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2743 chip->int_sta_mask = int_sta_masks;
2744
2745 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2746 snd_intel8x0_free(chip);
2747 return err;
2748 }
2749
2750 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2751
2752 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2753 snd_intel8x0_free(chip);
2754 return err;
2755 }
2756
2757 snd_card_set_dev(card, &pci->dev);
2758
2759 *r_intel8x0 = chip;
2760 return 0;
2761}
2762
2763static struct shortname_table {
2764 unsigned int id;
2765 const char *s;
2766} shortnames[] __devinitdata = {
8cdfd251
TI		 2767 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2768 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2769 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 2770 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 2771 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2772 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2773 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 2774 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2775 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2776 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 2777 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 2778 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 2779 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 2780 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2781 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2782 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2783 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2784 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2785 { 0x003a, "NVidia MCP04" },
2786 { 0x746d, "AMD AMD8111" },
2787 { 0x7445, "AMD AMD768" },
2788 { 0x5455, "ALi M5455" },
2789 { 0, NULL },
2790};
2791
2792static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2793 const struct pci_device_id *pci_id)
2794{
1da177e4
LT		 2795 snd_card_t *card;
2796 intel8x0_t *chip;
2797 int err;
2798 struct shortname_table *name;
2799
b7fe4622 2800 card = snd_card_new(index, id, THIS_MODULE, 0);
1da177e4
LT		 2801 if (card == NULL)
2802 return -ENOMEM;
2803
2804 switch (pci_id->driver_data) {
2805 case DEVICE_NFORCE:
2806 strcpy(card->driver, "NFORCE");
2807 break;
2808 case DEVICE_INTEL_ICH4:
2809 strcpy(card->driver, "ICH4");
2810 break;
2811 default:
2812 strcpy(card->driver, "ICH");
2813 break;
2814 }
2815
2816 strcpy(card->shortname, "Intel ICH");
2817 for (name = shortnames; name->id; name++) {
2818 if (pci->device == name->id) {
2819 strcpy(card->shortname, name->s);
2820 break;
2821 }
2822 }
2823
a06147d2 2824 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
c829b052 2825 &chip)) < 0) {
1da177e4
LT		 2826 snd_card_free(card);
2827 return err;
2828 }
1da177e4 2829
b7fe4622 2830 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
1da177e4
LT		 2831 snd_card_free(card);
2832 return err;
2833 }
2834 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2835 snd_card_free(card);
2836 return err;
2837 }
2838
2839 snd_intel8x0_proc_init(chip);
2840
2841 snprintf(card->longname, sizeof(card->longname),
2842 "%s with %s at %#lx, irq %i", card->shortname,
2843 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2844
b7fe4622 2845 if (! ac97_clock)
1da177e4
LT		 2846 intel8x0_measure_ac97_clock(chip);
2847
2848 if ((err = snd_card_register(card)) < 0) {
2849 snd_card_free(card);
2850 return err;
2851 }
2852 pci_set_drvdata(pci, card);
1da177e4
LT		 2853 return 0;
2854}
2855
2856static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2857{
2858 snd_card_free(pci_get_drvdata(pci));
2859 pci_set_drvdata(pci, NULL);
2860}
2861
2862static struct pci_driver driver = {
2863 .name = "Intel ICH",
3bcd4649 2864 .owner = THIS_MODULE,
1da177e4
LT		 2865 .id_table = snd_intel8x0_ids,
2866 .probe = snd_intel8x0_probe,
2867 .remove = __devexit_p(snd_intel8x0_remove),
2868 SND_PCI_PM_CALLBACKS
2869};
2870
2871
2872static int __init alsa_card_intel8x0_init(void)
2873{
01d25d46 2874 return pci_register_driver(&driver);
1da177e4
LT		 2875}
2876
2877static void __exit alsa_card_intel8x0_exit(void)
2878{
2879 pci_unregister_driver(&driver);
2880}
2881
2882module_init(alsa_card_intel8x0_init)
2883module_exit(alsa_card_intel8x0_exit)
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