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079d88cc WF |
1 | /* |
2 | * | |
3 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
4 | * | |
5 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
6 | * Copyright (c) 2006 ATI Technologies Inc. |
7 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
8 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
079d88cc WF |
9 | * |
10 | * Authors: | |
11 | * Wu Fengguang <wfg@linux.intel.com> | |
12 | * | |
13 | * Maintained by: | |
14 | * Wu Fengguang <wfg@linux.intel.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify it | |
17 | * under the terms of the GNU General Public License as published by the Free | |
18 | * Software Foundation; either version 2 of the License, or (at your option) | |
19 | * any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, but | |
22 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
23 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
24 | * for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software Foundation, | |
28 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
29 | */ | |
30 | ||
84eb01be TI |
31 | #include <linux/init.h> |
32 | #include <linux/delay.h> | |
33 | #include <linux/slab.h> | |
34 | #include <sound/core.h> | |
35 | #include "hda_codec.h" | |
36 | #include "hda_local.h" | |
37 | ||
38 | /* | |
39 | * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device | |
40 | * could support two independent pipes, each of them can be connected to one or | |
41 | * more ports (DVI, HDMI or DisplayPort). | |
42 | * | |
43 | * The HDA correspondence of pipes/ports are converter/pin nodes. | |
44 | */ | |
45 | #define MAX_HDMI_CVTS 3 | |
46 | #define MAX_HDMI_PINS 3 | |
079d88cc WF |
47 | |
48 | struct hdmi_spec { | |
49 | int num_cvts; | |
50 | int num_pins; | |
51 | hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */ | |
52 | hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */ | |
53 | ||
54 | /* | |
55 | * source connection for each pin | |
56 | */ | |
57 | hda_nid_t pin_cvt[MAX_HDMI_PINS+1]; | |
58 | ||
59 | /* | |
60 | * HDMI sink attached to each pin | |
61 | */ | |
62 | struct hdmi_eld sink_eld[MAX_HDMI_PINS]; | |
63 | ||
64 | /* | |
65 | * export one pcm per pipe | |
66 | */ | |
67 | struct hda_pcm pcm_rec[MAX_HDMI_CVTS]; | |
bbbe3390 | 68 | struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS]; |
079d88cc WF |
69 | |
70 | /* | |
84eb01be | 71 | * ati/nvhdmi specific |
079d88cc WF |
72 | */ |
73 | struct hda_multi_out multiout; | |
84eb01be | 74 | struct hda_pcm_stream *pcm_playback; |
38faddb1 TI |
75 | |
76 | /* misc flags */ | |
77 | /* PD bit indicates only the update, not the current state */ | |
78 | unsigned int old_pin_detect:1; | |
079d88cc WF |
79 | }; |
80 | ||
81 | ||
82 | struct hdmi_audio_infoframe { | |
83 | u8 type; /* 0x84 */ | |
84 | u8 ver; /* 0x01 */ | |
85 | u8 len; /* 0x0a */ | |
86 | ||
53d7d69d WF |
87 | u8 checksum; |
88 | ||
079d88cc WF |
89 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
90 | u8 SS01_SF24; | |
91 | u8 CXT04; | |
92 | u8 CA; | |
93 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
94 | }; |
95 | ||
96 | struct dp_audio_infoframe { | |
97 | u8 type; /* 0x84 */ | |
98 | u8 len; /* 0x1b */ | |
99 | u8 ver; /* 0x11 << 2 */ | |
100 | ||
101 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
102 | u8 SS01_SF24; | |
103 | u8 CXT04; | |
104 | u8 CA; | |
105 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
106 | }; |
107 | ||
108 | /* | |
109 | * CEA speaker placement: | |
110 | * | |
111 | * FLH FCH FRH | |
112 | * FLW FL FLC FC FRC FR FRW | |
113 | * | |
114 | * LFE | |
115 | * TC | |
116 | * | |
117 | * RL RLC RC RRC RR | |
118 | * | |
119 | * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to | |
120 | * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. | |
121 | */ | |
122 | enum cea_speaker_placement { | |
123 | FL = (1 << 0), /* Front Left */ | |
124 | FC = (1 << 1), /* Front Center */ | |
125 | FR = (1 << 2), /* Front Right */ | |
126 | FLC = (1 << 3), /* Front Left Center */ | |
127 | FRC = (1 << 4), /* Front Right Center */ | |
128 | RL = (1 << 5), /* Rear Left */ | |
129 | RC = (1 << 6), /* Rear Center */ | |
130 | RR = (1 << 7), /* Rear Right */ | |
131 | RLC = (1 << 8), /* Rear Left Center */ | |
132 | RRC = (1 << 9), /* Rear Right Center */ | |
133 | LFE = (1 << 10), /* Low Frequency Effect */ | |
134 | FLW = (1 << 11), /* Front Left Wide */ | |
135 | FRW = (1 << 12), /* Front Right Wide */ | |
136 | FLH = (1 << 13), /* Front Left High */ | |
137 | FCH = (1 << 14), /* Front Center High */ | |
138 | FRH = (1 << 15), /* Front Right High */ | |
139 | TC = (1 << 16), /* Top Center */ | |
140 | }; | |
141 | ||
142 | /* | |
143 | * ELD SA bits in the CEA Speaker Allocation data block | |
144 | */ | |
145 | static int eld_speaker_allocation_bits[] = { | |
146 | [0] = FL | FR, | |
147 | [1] = LFE, | |
148 | [2] = FC, | |
149 | [3] = RL | RR, | |
150 | [4] = RC, | |
151 | [5] = FLC | FRC, | |
152 | [6] = RLC | RRC, | |
153 | /* the following are not defined in ELD yet */ | |
154 | [7] = FLW | FRW, | |
155 | [8] = FLH | FRH, | |
156 | [9] = TC, | |
157 | [10] = FCH, | |
158 | }; | |
159 | ||
160 | struct cea_channel_speaker_allocation { | |
161 | int ca_index; | |
162 | int speakers[8]; | |
163 | ||
164 | /* derived values, just for convenience */ | |
165 | int channels; | |
166 | int spk_mask; | |
167 | }; | |
168 | ||
169 | /* | |
170 | * ALSA sequence is: | |
171 | * | |
172 | * surround40 surround41 surround50 surround51 surround71 | |
173 | * ch0 front left = = = = | |
174 | * ch1 front right = = = = | |
175 | * ch2 rear left = = = = | |
176 | * ch3 rear right = = = = | |
177 | * ch4 LFE center center center | |
178 | * ch5 LFE LFE | |
179 | * ch6 side left | |
180 | * ch7 side right | |
181 | * | |
182 | * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} | |
183 | */ | |
184 | static int hdmi_channel_mapping[0x32][8] = { | |
185 | /* stereo */ | |
186 | [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, | |
187 | /* 2.1 */ | |
188 | [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, | |
189 | /* Dolby Surround */ | |
190 | [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, | |
191 | /* surround40 */ | |
192 | [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, | |
193 | /* 4ch */ | |
194 | [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, | |
195 | /* surround41 */ | |
9396d317 | 196 | [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 }, |
079d88cc WF |
197 | /* surround50 */ |
198 | [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, | |
199 | /* surround51 */ | |
200 | [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, | |
201 | /* 7.1 */ | |
202 | [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, | |
203 | }; | |
204 | ||
205 | /* | |
206 | * This is an ordered list! | |
207 | * | |
208 | * The preceding ones have better chances to be selected by | |
53d7d69d | 209 | * hdmi_channel_allocation(). |
079d88cc WF |
210 | */ |
211 | static struct cea_channel_speaker_allocation channel_allocations[] = { | |
212 | /* channel: 7 6 5 4 3 2 1 0 */ | |
213 | { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, | |
214 | /* 2.1 */ | |
215 | { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, | |
216 | /* Dolby Surround */ | |
217 | { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, | |
218 | /* surround40 */ | |
219 | { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, | |
220 | /* surround41 */ | |
221 | { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, | |
222 | /* surround50 */ | |
223 | { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, | |
224 | /* surround51 */ | |
225 | { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, | |
226 | /* 6.1 */ | |
227 | { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, | |
228 | /* surround71 */ | |
229 | { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, | |
230 | ||
231 | { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, | |
232 | { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, | |
233 | { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, | |
234 | { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, | |
235 | { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, | |
236 | { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, | |
237 | { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, | |
238 | { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, | |
239 | { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, | |
240 | { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, | |
241 | { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, | |
242 | { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, | |
243 | { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, | |
244 | { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, | |
245 | { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, | |
246 | { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, | |
247 | { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, | |
248 | { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, | |
249 | { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, | |
250 | { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, | |
251 | { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, | |
252 | { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, | |
253 | { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, | |
254 | { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, | |
255 | { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, | |
256 | { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, | |
257 | { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, | |
258 | { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, | |
259 | { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, | |
260 | { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, | |
261 | { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, | |
262 | { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, | |
263 | { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, | |
264 | { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, | |
265 | { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, | |
266 | { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, | |
267 | { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, | |
268 | { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, | |
269 | { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, | |
270 | { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, | |
271 | { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, | |
272 | }; | |
273 | ||
274 | ||
275 | /* | |
276 | * HDMI routines | |
277 | */ | |
278 | ||
279 | static int hda_node_index(hda_nid_t *nids, hda_nid_t nid) | |
280 | { | |
281 | int i; | |
282 | ||
283 | for (i = 0; nids[i]; i++) | |
284 | if (nids[i] == nid) | |
285 | return i; | |
286 | ||
287 | snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid); | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
291 | static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid, | |
292 | struct hdmi_eld *eld) | |
293 | { | |
294 | if (!snd_hdmi_get_eld(eld, codec, pin_nid)) | |
295 | snd_hdmi_show_eld(eld); | |
296 | } | |
297 | ||
298 | #ifdef BE_PARANOID | |
299 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
300 | int *packet_index, int *byte_index) | |
301 | { | |
302 | int val; | |
303 | ||
304 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
305 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
306 | ||
307 | *packet_index = val >> 5; | |
308 | *byte_index = val & 0x1f; | |
309 | } | |
310 | #endif | |
311 | ||
312 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
313 | int packet_index, int byte_index) | |
314 | { | |
315 | int val; | |
316 | ||
317 | val = (packet_index << 5) | (byte_index & 0x1f); | |
318 | ||
319 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
320 | } | |
321 | ||
322 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
323 | unsigned char val) | |
324 | { | |
325 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
326 | } | |
327 | ||
328 | static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid) | |
329 | { | |
330 | /* Unmute */ | |
331 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
332 | snd_hda_codec_write(codec, pin_nid, 0, | |
333 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
334 | /* Enable pin out */ | |
335 | snd_hda_codec_write(codec, pin_nid, 0, | |
336 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
337 | } | |
338 | ||
339 | static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid) | |
340 | { | |
341 | return 1 + snd_hda_codec_read(codec, nid, 0, | |
342 | AC_VERB_GET_CVT_CHAN_COUNT, 0); | |
343 | } | |
344 | ||
345 | static void hdmi_set_channel_count(struct hda_codec *codec, | |
346 | hda_nid_t nid, int chs) | |
347 | { | |
348 | if (chs != hdmi_get_channel_count(codec, nid)) | |
349 | snd_hda_codec_write(codec, nid, 0, | |
350 | AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); | |
351 | } | |
352 | ||
353 | ||
354 | /* | |
355 | * Channel mapping routines | |
356 | */ | |
357 | ||
358 | /* | |
359 | * Compute derived values in channel_allocations[]. | |
360 | */ | |
361 | static void init_channel_allocations(void) | |
362 | { | |
363 | int i, j; | |
364 | struct cea_channel_speaker_allocation *p; | |
365 | ||
366 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
367 | p = channel_allocations + i; | |
368 | p->channels = 0; | |
369 | p->spk_mask = 0; | |
370 | for (j = 0; j < ARRAY_SIZE(p->speakers); j++) | |
371 | if (p->speakers[j]) { | |
372 | p->channels++; | |
373 | p->spk_mask |= p->speakers[j]; | |
374 | } | |
375 | } | |
376 | } | |
377 | ||
378 | /* | |
379 | * The transformation takes two steps: | |
380 | * | |
381 | * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask | |
382 | * spk_mask => (channel_allocations[]) => ai->CA | |
383 | * | |
384 | * TODO: it could select the wrong CA from multiple candidates. | |
385 | */ | |
53d7d69d WF |
386 | static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid, |
387 | int channels) | |
079d88cc WF |
388 | { |
389 | struct hdmi_spec *spec = codec->spec; | |
390 | struct hdmi_eld *eld; | |
391 | int i; | |
53d7d69d | 392 | int ca = 0; |
079d88cc | 393 | int spk_mask = 0; |
079d88cc WF |
394 | char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; |
395 | ||
396 | /* | |
397 | * CA defaults to 0 for basic stereo audio | |
398 | */ | |
399 | if (channels <= 2) | |
400 | return 0; | |
401 | ||
402 | i = hda_node_index(spec->pin_cvt, nid); | |
403 | if (i < 0) | |
404 | return 0; | |
405 | eld = &spec->sink_eld[i]; | |
406 | ||
407 | /* | |
408 | * HDMI sink's ELD info cannot always be retrieved for now, e.g. | |
409 | * in console or for audio devices. Assume the highest speakers | |
410 | * configuration, to _not_ prohibit multi-channel audio playback. | |
411 | */ | |
412 | if (!eld->spk_alloc) | |
413 | eld->spk_alloc = 0xffff; | |
414 | ||
415 | /* | |
416 | * expand ELD's speaker allocation mask | |
417 | * | |
418 | * ELD tells the speaker mask in a compact(paired) form, | |
419 | * expand ELD's notions to match the ones used by Audio InfoFrame. | |
420 | */ | |
421 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
422 | if (eld->spk_alloc & (1 << i)) | |
423 | spk_mask |= eld_speaker_allocation_bits[i]; | |
424 | } | |
425 | ||
426 | /* search for the first working match in the CA table */ | |
427 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
428 | if (channels == channel_allocations[i].channels && | |
429 | (spk_mask & channel_allocations[i].spk_mask) == | |
430 | channel_allocations[i].spk_mask) { | |
53d7d69d | 431 | ca = channel_allocations[i].ca_index; |
079d88cc WF |
432 | break; |
433 | } | |
434 | } | |
435 | ||
436 | snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf)); | |
2abbf439 | 437 | snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n", |
53d7d69d | 438 | ca, channels, buf); |
079d88cc | 439 | |
53d7d69d | 440 | return ca; |
079d88cc WF |
441 | } |
442 | ||
443 | static void hdmi_debug_channel_mapping(struct hda_codec *codec, | |
444 | hda_nid_t pin_nid) | |
445 | { | |
446 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
447 | int i; | |
448 | int slot; | |
449 | ||
450 | for (i = 0; i < 8; i++) { | |
451 | slot = snd_hda_codec_read(codec, pin_nid, 0, | |
452 | AC_VERB_GET_HDMI_CHAN_SLOT, i); | |
453 | printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n", | |
454 | slot >> 4, slot & 0xf); | |
455 | } | |
456 | #endif | |
457 | } | |
458 | ||
459 | ||
460 | static void hdmi_setup_channel_mapping(struct hda_codec *codec, | |
461 | hda_nid_t pin_nid, | |
53d7d69d | 462 | int ca) |
079d88cc WF |
463 | { |
464 | int i; | |
079d88cc WF |
465 | int err; |
466 | ||
467 | if (hdmi_channel_mapping[ca][1] == 0) { | |
468 | for (i = 0; i < channel_allocations[ca].channels; i++) | |
469 | hdmi_channel_mapping[ca][i] = i | (i << 4); | |
470 | for (; i < 8; i++) | |
471 | hdmi_channel_mapping[ca][i] = 0xf | (i << 4); | |
472 | } | |
473 | ||
474 | for (i = 0; i < 8; i++) { | |
475 | err = snd_hda_codec_write(codec, pin_nid, 0, | |
476 | AC_VERB_SET_HDMI_CHAN_SLOT, | |
477 | hdmi_channel_mapping[ca][i]); | |
478 | if (err) { | |
2abbf439 WF |
479 | snd_printdd(KERN_NOTICE |
480 | "HDMI: channel mapping failed\n"); | |
079d88cc WF |
481 | break; |
482 | } | |
483 | } | |
484 | ||
485 | hdmi_debug_channel_mapping(codec, pin_nid); | |
486 | } | |
487 | ||
488 | ||
489 | /* | |
490 | * Audio InfoFrame routines | |
491 | */ | |
492 | ||
493 | /* | |
494 | * Enable Audio InfoFrame Transmission | |
495 | */ | |
496 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
497 | hda_nid_t pin_nid) | |
498 | { | |
499 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
500 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
501 | AC_DIPXMIT_BEST); | |
502 | } | |
503 | ||
504 | /* | |
505 | * Disable Audio InfoFrame Transmission | |
506 | */ | |
507 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
508 | hda_nid_t pin_nid) | |
509 | { | |
510 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
511 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
512 | AC_DIPXMIT_DISABLE); | |
513 | } | |
514 | ||
515 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
516 | { | |
517 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
518 | int i; | |
519 | int size; | |
520 | ||
521 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
522 | printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size); | |
523 | ||
524 | for (i = 0; i < 8; i++) { | |
525 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
526 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
527 | printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size); | |
528 | } | |
529 | #endif | |
530 | } | |
531 | ||
532 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
533 | { | |
534 | #ifdef BE_PARANOID | |
535 | int i, j; | |
536 | int size; | |
537 | int pi, bi; | |
538 | for (i = 0; i < 8; i++) { | |
539 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
540 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
541 | if (size == 0) | |
542 | continue; | |
543 | ||
544 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
545 | for (j = 1; j < 1000; j++) { | |
546 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
547 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
548 | if (pi != i) | |
549 | snd_printd(KERN_INFO "dip index %d: %d != %d\n", | |
550 | bi, pi, i); | |
551 | if (bi == 0) /* byte index wrapped around */ | |
552 | break; | |
553 | } | |
554 | snd_printd(KERN_INFO | |
555 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", | |
556 | i, size, j); | |
557 | } | |
558 | #endif | |
559 | } | |
560 | ||
53d7d69d | 561 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 562 | { |
53d7d69d | 563 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
564 | u8 sum = 0; |
565 | int i; | |
566 | ||
53d7d69d | 567 | hdmi_ai->checksum = 0; |
079d88cc | 568 | |
53d7d69d | 569 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
570 | sum += bytes[i]; |
571 | ||
53d7d69d | 572 | hdmi_ai->checksum = -sum; |
079d88cc WF |
573 | } |
574 | ||
575 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
576 | hda_nid_t pin_nid, | |
53d7d69d | 577 | u8 *dip, int size) |
079d88cc | 578 | { |
079d88cc WF |
579 | int i; |
580 | ||
581 | hdmi_debug_dip_size(codec, pin_nid); | |
582 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
583 | ||
079d88cc | 584 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
585 | for (i = 0; i < size; i++) |
586 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
587 | } |
588 | ||
589 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 590 | u8 *dip, int size) |
079d88cc | 591 | { |
079d88cc WF |
592 | u8 val; |
593 | int i; | |
594 | ||
595 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
596 | != AC_DIPXMIT_BEST) | |
597 | return false; | |
598 | ||
599 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 600 | for (i = 0; i < size; i++) { |
079d88cc WF |
601 | val = snd_hda_codec_read(codec, pin_nid, 0, |
602 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 603 | if (val != dip[i]) |
079d88cc WF |
604 | return false; |
605 | } | |
606 | ||
607 | return true; | |
608 | } | |
609 | ||
610 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, | |
611 | struct snd_pcm_substream *substream) | |
612 | { | |
613 | struct hdmi_spec *spec = codec->spec; | |
614 | hda_nid_t pin_nid; | |
53d7d69d WF |
615 | int channels = substream->runtime->channels; |
616 | int ca; | |
079d88cc | 617 | int i; |
53d7d69d WF |
618 | u8 ai[max(sizeof(struct hdmi_audio_infoframe), |
619 | sizeof(struct dp_audio_infoframe))]; | |
079d88cc | 620 | |
53d7d69d | 621 | ca = hdmi_channel_allocation(codec, nid, channels); |
079d88cc WF |
622 | |
623 | for (i = 0; i < spec->num_pins; i++) { | |
624 | if (spec->pin_cvt[i] != nid) | |
625 | continue; | |
626 | if (!spec->sink_eld[i].monitor_present) | |
627 | continue; | |
628 | ||
629 | pin_nid = spec->pin[i]; | |
53d7d69d WF |
630 | |
631 | memset(ai, 0, sizeof(ai)); | |
632 | if (spec->sink_eld[i].conn_type == 0) { /* HDMI */ | |
633 | struct hdmi_audio_infoframe *hdmi_ai; | |
634 | ||
635 | hdmi_ai = (struct hdmi_audio_infoframe *)ai; | |
636 | hdmi_ai->type = 0x84; | |
637 | hdmi_ai->ver = 0x01; | |
638 | hdmi_ai->len = 0x0a; | |
639 | hdmi_ai->CC02_CT47 = channels - 1; | |
640 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
641 | } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */ | |
642 | struct dp_audio_infoframe *dp_ai; | |
643 | ||
644 | dp_ai = (struct dp_audio_infoframe *)ai; | |
645 | dp_ai->type = 0x84; | |
646 | dp_ai->len = 0x1b; | |
647 | dp_ai->ver = 0x11 << 2; | |
648 | dp_ai->CC02_CT47 = channels - 1; | |
649 | } else { | |
650 | snd_printd("HDMI: unknown connection type at pin %d\n", | |
651 | pin_nid); | |
652 | continue; | |
653 | } | |
654 | ||
655 | /* | |
656 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
657 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
658 | * the user switches between HDMI/DP monitors. | |
659 | */ | |
660 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai, sizeof(ai))) { | |
2abbf439 WF |
661 | snd_printdd("hdmi_setup_audio_infoframe: " |
662 | "cvt=%d pin=%d channels=%d\n", | |
663 | nid, pin_nid, | |
53d7d69d WF |
664 | channels); |
665 | hdmi_setup_channel_mapping(codec, pin_nid, ca); | |
079d88cc | 666 | hdmi_stop_infoframe_trans(codec, pin_nid); |
53d7d69d WF |
667 | hdmi_fill_audio_infoframe(codec, pin_nid, |
668 | ai, sizeof(ai)); | |
079d88cc WF |
669 | hdmi_start_infoframe_trans(codec, pin_nid); |
670 | } | |
671 | } | |
672 | } | |
673 | ||
674 | ||
675 | /* | |
676 | * Unsolicited events | |
677 | */ | |
678 | ||
38faddb1 TI |
679 | static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid, |
680 | struct hdmi_eld *eld); | |
681 | ||
079d88cc WF |
682 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) |
683 | { | |
684 | struct hdmi_spec *spec = codec->spec; | |
685 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
686 | int pind = !!(res & AC_UNSOL_RES_PD); | |
687 | int eldv = !!(res & AC_UNSOL_RES_ELDV); | |
688 | int index; | |
689 | ||
690 | printk(KERN_INFO | |
691 | "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n", | |
692 | tag, pind, eldv); | |
693 | ||
694 | index = hda_node_index(spec->pin, tag); | |
695 | if (index < 0) | |
696 | return; | |
697 | ||
38faddb1 TI |
698 | if (spec->old_pin_detect) { |
699 | if (pind) | |
700 | hdmi_present_sense(codec, tag, &spec->sink_eld[index]); | |
701 | pind = spec->sink_eld[index].monitor_present; | |
702 | } | |
703 | ||
079d88cc WF |
704 | spec->sink_eld[index].monitor_present = pind; |
705 | spec->sink_eld[index].eld_valid = eldv; | |
706 | ||
707 | if (pind && eldv) { | |
708 | hdmi_get_show_eld(codec, spec->pin[index], | |
709 | &spec->sink_eld[index]); | |
710 | /* TODO: do real things about ELD */ | |
711 | } | |
712 | } | |
713 | ||
714 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
715 | { | |
716 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
717 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
718 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
719 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
720 | ||
721 | printk(KERN_INFO | |
722 | "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", | |
723 | tag, | |
724 | subtag, | |
725 | cp_state, | |
726 | cp_ready); | |
727 | ||
728 | /* TODO */ | |
729 | if (cp_state) | |
730 | ; | |
731 | if (cp_ready) | |
732 | ; | |
733 | } | |
734 | ||
735 | ||
736 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
737 | { | |
738 | struct hdmi_spec *spec = codec->spec; | |
739 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
740 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
741 | ||
742 | if (hda_node_index(spec->pin, tag) < 0) { | |
743 | snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag); | |
744 | return; | |
745 | } | |
746 | ||
747 | if (subtag == 0) | |
748 | hdmi_intrinsic_event(codec, res); | |
749 | else | |
750 | hdmi_non_intrinsic_event(codec, res); | |
751 | } | |
752 | ||
753 | /* | |
754 | * Callbacks | |
755 | */ | |
756 | ||
92f10b3f TI |
757 | /* HBR should be Non-PCM, 8 channels */ |
758 | #define is_hbr_format(format) \ | |
759 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
760 | ||
ea87d1c4 | 761 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid, |
079d88cc WF |
762 | u32 stream_tag, int format) |
763 | { | |
ea87d1c4 | 764 | struct hdmi_spec *spec = codec->spec; |
ea87d1c4 AH |
765 | int pinctl; |
766 | int new_pinctl = 0; | |
767 | int i; | |
768 | ||
769 | for (i = 0; i < spec->num_pins; i++) { | |
770 | if (spec->pin_cvt[i] != nid) | |
771 | continue; | |
772 | if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR)) | |
773 | continue; | |
774 | ||
775 | pinctl = snd_hda_codec_read(codec, spec->pin[i], 0, | |
776 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
777 | ||
778 | new_pinctl = pinctl & ~AC_PINCTL_EPT; | |
92f10b3f | 779 | if (is_hbr_format(format)) |
ea87d1c4 AH |
780 | new_pinctl |= AC_PINCTL_EPT_HBR; |
781 | else | |
782 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
783 | ||
784 | snd_printdd("hdmi_setup_stream: " | |
785 | "NID=0x%x, %spinctl=0x%x\n", | |
786 | spec->pin[i], | |
787 | pinctl == new_pinctl ? "" : "new-", | |
788 | new_pinctl); | |
789 | ||
790 | if (pinctl != new_pinctl) | |
791 | snd_hda_codec_write(codec, spec->pin[i], 0, | |
792 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
793 | new_pinctl); | |
794 | } | |
795 | ||
92f10b3f | 796 | if (is_hbr_format(format) && !new_pinctl) { |
ea87d1c4 AH |
797 | snd_printdd("hdmi_setup_stream: HBR is not supported\n"); |
798 | return -EINVAL; | |
799 | } | |
079d88cc | 800 | |
4f347607 | 801 | snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format); |
ea87d1c4 | 802 | return 0; |
079d88cc WF |
803 | } |
804 | ||
bbbe3390 TI |
805 | /* |
806 | * HDA PCM callbacks | |
807 | */ | |
808 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
809 | struct hda_codec *codec, | |
810 | struct snd_pcm_substream *substream) | |
811 | { | |
812 | struct hdmi_spec *spec = codec->spec; | |
813 | struct hdmi_eld *eld; | |
814 | struct hda_pcm_stream *codec_pars; | |
815 | unsigned int idx; | |
816 | ||
817 | for (idx = 0; idx < spec->num_cvts; idx++) | |
818 | if (hinfo->nid == spec->cvt[idx]) | |
819 | break; | |
820 | if (snd_BUG_ON(idx >= spec->num_cvts) || | |
821 | snd_BUG_ON(idx >= spec->num_pins)) | |
822 | return -EINVAL; | |
823 | ||
824 | /* save the PCM info the codec provides */ | |
825 | codec_pars = &spec->codec_pcm_pars[idx]; | |
826 | if (!codec_pars->rates) | |
827 | *codec_pars = *hinfo; | |
828 | ||
829 | eld = &spec->sink_eld[idx]; | |
830 | if (eld->sad_count > 0) { | |
831 | hdmi_eld_update_pcm_info(eld, hinfo, codec_pars); | |
832 | if (hinfo->channels_min > hinfo->channels_max || | |
833 | !hinfo->rates || !hinfo->formats) | |
834 | return -ENODEV; | |
835 | } else { | |
836 | /* fallback to the codec default */ | |
837 | hinfo->channels_min = codec_pars->channels_min; | |
838 | hinfo->channels_max = codec_pars->channels_max; | |
839 | hinfo->rates = codec_pars->rates; | |
840 | hinfo->formats = codec_pars->formats; | |
841 | hinfo->maxbps = codec_pars->maxbps; | |
842 | } | |
843 | return 0; | |
844 | } | |
845 | ||
079d88cc WF |
846 | /* |
847 | * HDA/HDMI auto parsing | |
848 | */ | |
079d88cc WF |
849 | static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid) |
850 | { | |
851 | struct hdmi_spec *spec = codec->spec; | |
852 | hda_nid_t conn_list[HDA_MAX_CONNECTIONS]; | |
853 | int conn_len, curr; | |
854 | int index; | |
855 | ||
856 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
857 | snd_printk(KERN_WARNING | |
858 | "HDMI: pin %d wcaps %#x " | |
859 | "does not support connection list\n", | |
860 | pin_nid, get_wcaps(codec, pin_nid)); | |
861 | return -EINVAL; | |
862 | } | |
863 | ||
864 | conn_len = snd_hda_get_connections(codec, pin_nid, conn_list, | |
865 | HDA_MAX_CONNECTIONS); | |
866 | if (conn_len > 1) | |
867 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
868 | AC_VERB_GET_CONNECT_SEL, 0); | |
869 | else | |
870 | curr = 0; | |
871 | ||
872 | index = hda_node_index(spec->pin, pin_nid); | |
873 | if (index < 0) | |
874 | return -EINVAL; | |
875 | ||
876 | spec->pin_cvt[index] = conn_list[curr]; | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid, | |
882 | struct hdmi_eld *eld) | |
883 | { | |
884 | int present = snd_hda_pin_sense(codec, pin_nid); | |
885 | ||
886 | eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); | |
887 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); | |
888 | ||
889 | if (present & AC_PINSENSE_ELDV) | |
890 | hdmi_get_show_eld(codec, pin_nid, eld); | |
891 | } | |
892 | ||
893 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) | |
894 | { | |
895 | struct hdmi_spec *spec = codec->spec; | |
896 | ||
897 | if (spec->num_pins >= MAX_HDMI_PINS) { | |
898 | snd_printk(KERN_WARNING | |
899 | "HDMI: no space for pin %d\n", pin_nid); | |
3eaead57 | 900 | return -E2BIG; |
079d88cc WF |
901 | } |
902 | ||
903 | hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]); | |
904 | ||
905 | spec->pin[spec->num_pins] = pin_nid; | |
906 | spec->num_pins++; | |
907 | ||
908 | /* | |
909 | * It is assumed that converter nodes come first in the node list and | |
910 | * hence have been registered and usable now. | |
911 | */ | |
912 | return hdmi_read_pin_conn(codec, pin_nid); | |
913 | } | |
914 | ||
915 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid) | |
916 | { | |
917 | struct hdmi_spec *spec = codec->spec; | |
918 | ||
919 | if (spec->num_cvts >= MAX_HDMI_CVTS) { | |
920 | snd_printk(KERN_WARNING | |
921 | "HDMI: no space for converter %d\n", nid); | |
3eaead57 | 922 | return -E2BIG; |
079d88cc WF |
923 | } |
924 | ||
925 | spec->cvt[spec->num_cvts] = nid; | |
926 | spec->num_cvts++; | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
931 | static int hdmi_parse_codec(struct hda_codec *codec) | |
932 | { | |
933 | hda_nid_t nid; | |
934 | int i, nodes; | |
935 | ||
936 | nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid); | |
937 | if (!nid || nodes < 0) { | |
938 | snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n"); | |
939 | return -EINVAL; | |
940 | } | |
941 | ||
942 | for (i = 0; i < nodes; i++, nid++) { | |
943 | unsigned int caps; | |
944 | unsigned int type; | |
945 | ||
946 | caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP); | |
947 | type = get_wcaps_type(caps); | |
948 | ||
949 | if (!(caps & AC_WCAP_DIGITAL)) | |
950 | continue; | |
951 | ||
952 | switch (type) { | |
953 | case AC_WID_AUD_OUT: | |
3eaead57 | 954 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
955 | break; |
956 | case AC_WID_PIN: | |
957 | caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP); | |
958 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) | |
959 | continue; | |
3eaead57 | 960 | hdmi_add_pin(codec, nid); |
079d88cc WF |
961 | break; |
962 | } | |
963 | } | |
964 | ||
965 | /* | |
966 | * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event | |
967 | * can be lost and presence sense verb will become inaccurate if the | |
968 | * HDA link is powered off at hot plug or hw initialization time. | |
969 | */ | |
970 | #ifdef CONFIG_SND_HDA_POWER_SAVE | |
971 | if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) & | |
972 | AC_PWRST_EPSS)) | |
973 | codec->bus->power_keep_link_on = 1; | |
974 | #endif | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
84eb01be TI |
979 | /* |
980 | */ | |
981 | static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = { | |
982 | "HDMI 0", | |
983 | "HDMI 1", | |
984 | "HDMI 2", | |
985 | }; | |
986 | ||
987 | /* | |
988 | * HDMI callbacks | |
989 | */ | |
990 | ||
991 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
992 | struct hda_codec *codec, | |
993 | unsigned int stream_tag, | |
994 | unsigned int format, | |
995 | struct snd_pcm_substream *substream) | |
996 | { | |
997 | hdmi_set_channel_count(codec, hinfo->nid, | |
998 | substream->runtime->channels); | |
999 | ||
1000 | hdmi_setup_audio_infoframe(codec, hinfo->nid, substream); | |
1001 | ||
1002 | return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format); | |
1003 | } | |
1004 | ||
1005 | static struct hda_pcm_stream generic_hdmi_pcm_playback = { | |
1006 | .substreams = 1, | |
1007 | .channels_min = 2, | |
1008 | .ops = { | |
1009 | .open = hdmi_pcm_open, | |
1010 | .prepare = generic_hdmi_playback_pcm_prepare, | |
1011 | }, | |
1012 | }; | |
1013 | ||
1014 | static int generic_hdmi_build_pcms(struct hda_codec *codec) | |
1015 | { | |
1016 | struct hdmi_spec *spec = codec->spec; | |
1017 | struct hda_pcm *info = spec->pcm_rec; | |
1018 | int i; | |
1019 | ||
1020 | codec->num_pcms = spec->num_cvts; | |
1021 | codec->pcm_info = info; | |
1022 | ||
1023 | for (i = 0; i < codec->num_pcms; i++, info++) { | |
1024 | unsigned int chans; | |
1025 | struct hda_pcm_stream *pstr; | |
1026 | ||
1027 | chans = get_wcaps(codec, spec->cvt[i]); | |
1028 | chans = get_wcaps_channels(chans); | |
1029 | ||
1030 | info->name = generic_hdmi_pcm_names[i]; | |
1031 | info->pcm_type = HDA_PCM_TYPE_HDMI; | |
1032 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
1033 | if (spec->pcm_playback) | |
1034 | *pstr = *spec->pcm_playback; | |
1035 | else | |
1036 | *pstr = generic_hdmi_pcm_playback; | |
1037 | pstr->nid = spec->cvt[i]; | |
1038 | if (pstr->channels_max <= 2 && chans && chans <= 16) | |
1039 | pstr->channels_max = chans; | |
1040 | } | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int generic_hdmi_build_controls(struct hda_codec *codec) | |
1046 | { | |
1047 | struct hdmi_spec *spec = codec->spec; | |
1048 | int err; | |
1049 | int i; | |
1050 | ||
1051 | for (i = 0; i < codec->num_pcms; i++) { | |
1052 | err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]); | |
1053 | if (err < 0) | |
1054 | return err; | |
1055 | } | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static int generic_hdmi_init(struct hda_codec *codec) | |
1061 | { | |
1062 | struct hdmi_spec *spec = codec->spec; | |
1063 | int i; | |
1064 | ||
1065 | for (i = 0; spec->pin[i]; i++) { | |
1066 | hdmi_enable_output(codec, spec->pin[i]); | |
1067 | snd_hda_codec_write(codec, spec->pin[i], 0, | |
1068 | AC_VERB_SET_UNSOLICITED_ENABLE, | |
1069 | AC_USRSP_EN | spec->pin[i]); | |
1070 | } | |
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | static void generic_hdmi_free(struct hda_codec *codec) | |
1075 | { | |
1076 | struct hdmi_spec *spec = codec->spec; | |
1077 | int i; | |
1078 | ||
1079 | for (i = 0; i < spec->num_pins; i++) | |
1080 | snd_hda_eld_proc_free(codec, &spec->sink_eld[i]); | |
1081 | ||
1082 | kfree(spec); | |
1083 | } | |
1084 | ||
1085 | static struct hda_codec_ops generic_hdmi_patch_ops = { | |
1086 | .init = generic_hdmi_init, | |
1087 | .free = generic_hdmi_free, | |
1088 | .build_pcms = generic_hdmi_build_pcms, | |
1089 | .build_controls = generic_hdmi_build_controls, | |
1090 | .unsol_event = hdmi_unsol_event, | |
1091 | }; | |
1092 | ||
1093 | static int patch_generic_hdmi(struct hda_codec *codec) | |
1094 | { | |
1095 | struct hdmi_spec *spec; | |
1096 | int i; | |
1097 | ||
1098 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
1099 | if (spec == NULL) | |
1100 | return -ENOMEM; | |
1101 | ||
1102 | codec->spec = spec; | |
1103 | if (hdmi_parse_codec(codec) < 0) { | |
1104 | codec->spec = NULL; | |
1105 | kfree(spec); | |
1106 | return -EINVAL; | |
1107 | } | |
1108 | codec->patch_ops = generic_hdmi_patch_ops; | |
1109 | ||
1110 | for (i = 0; i < spec->num_pins; i++) | |
1111 | snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i); | |
1112 | ||
1113 | init_channel_allocations(); | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | /* | |
1119 | * Nvidia specific implementations | |
1120 | */ | |
1121 | ||
1122 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
1123 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
1124 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
1125 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
1126 | ||
1127 | #define nvhdmi_master_con_nid_7x 0x04 | |
1128 | #define nvhdmi_master_pin_nid_7x 0x05 | |
1129 | ||
1130 | static hda_nid_t nvhdmi_con_nids_7x[4] = { | |
1131 | /*front, rear, clfe, rear_surr */ | |
1132 | 0x6, 0x8, 0xa, 0xc, | |
1133 | }; | |
1134 | ||
1135 | static struct hda_verb nvhdmi_basic_init_7x[] = { | |
1136 | /* set audio protect on */ | |
1137 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
1138 | /* enable digital output on pin widget */ | |
1139 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
1140 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
1141 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
1142 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
1143 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
1144 | {} /* terminator */ | |
1145 | }; | |
1146 | ||
1147 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
1148 | /* support only the safe format and rate */ | |
1149 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
1150 | #define SUPPORTED_MAXBPS 16 | |
1151 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
1152 | #else | |
1153 | /* support all rates and formats */ | |
1154 | #define SUPPORTED_RATES \ | |
1155 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
1156 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
1157 | SNDRV_PCM_RATE_192000) | |
1158 | #define SUPPORTED_MAXBPS 24 | |
1159 | #define SUPPORTED_FORMATS \ | |
1160 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1161 | #endif | |
1162 | ||
1163 | static int nvhdmi_7x_init(struct hda_codec *codec) | |
1164 | { | |
1165 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x); | |
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, | |
1170 | struct hda_codec *codec, | |
1171 | struct snd_pcm_substream *substream) | |
1172 | { | |
1173 | struct hdmi_spec *spec = codec->spec; | |
1174 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); | |
1175 | } | |
1176 | ||
1177 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
1178 | struct hda_codec *codec, | |
1179 | struct snd_pcm_substream *substream) | |
1180 | { | |
1181 | struct hdmi_spec *spec = codec->spec; | |
1182 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
1183 | } | |
1184 | ||
1185 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1186 | struct hda_codec *codec, | |
1187 | unsigned int stream_tag, | |
1188 | unsigned int format, | |
1189 | struct snd_pcm_substream *substream) | |
1190 | { | |
1191 | struct hdmi_spec *spec = codec->spec; | |
1192 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
1193 | stream_tag, format, substream); | |
1194 | } | |
1195 | ||
1196 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, | |
1197 | struct hda_codec *codec, | |
1198 | struct snd_pcm_substream *substream) | |
1199 | { | |
1200 | struct hdmi_spec *spec = codec->spec; | |
1201 | int i; | |
1202 | ||
1203 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
1204 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
1205 | for (i = 0; i < 4; i++) { | |
1206 | /* set the stream id */ | |
1207 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
1208 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
1209 | /* set the stream format */ | |
1210 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
1211 | AC_VERB_SET_STREAM_FORMAT, 0); | |
1212 | } | |
1213 | ||
1214 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
1215 | } | |
1216 | ||
1217 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1218 | struct hda_codec *codec, | |
1219 | unsigned int stream_tag, | |
1220 | unsigned int format, | |
1221 | struct snd_pcm_substream *substream) | |
1222 | { | |
1223 | int chs; | |
1224 | unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id; | |
1225 | int i; | |
1226 | ||
1227 | mutex_lock(&codec->spdif_mutex); | |
1228 | ||
1229 | chs = substream->runtime->channels; | |
1230 | chan = chs ? (chs - 1) : 1; | |
1231 | ||
1232 | switch (chs) { | |
1233 | default: | |
1234 | case 0: | |
1235 | case 2: | |
1236 | chanmask = 0x00; | |
1237 | break; | |
1238 | case 4: | |
1239 | chanmask = 0x08; | |
1240 | break; | |
1241 | case 6: | |
1242 | chanmask = 0x0b; | |
1243 | break; | |
1244 | case 8: | |
1245 | chanmask = 0x13; | |
1246 | break; | |
1247 | } | |
1248 | dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT; | |
1249 | dataDCC2 = 0x2; | |
1250 | ||
1251 | /* set the Audio InforFrame Channel Allocation */ | |
1252 | snd_hda_codec_write(codec, 0x1, 0, | |
1253 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
1254 | ||
1255 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ | |
1256 | if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) | |
1257 | snd_hda_codec_write(codec, | |
1258 | nvhdmi_master_con_nid_7x, | |
1259 | 0, | |
1260 | AC_VERB_SET_DIGI_CONVERT_1, | |
1261 | codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff); | |
1262 | ||
1263 | /* set the stream id */ | |
1264 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
1265 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
1266 | ||
1267 | /* set the stream format */ | |
1268 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
1269 | AC_VERB_SET_STREAM_FORMAT, format); | |
1270 | ||
1271 | /* turn on again (if needed) */ | |
1272 | /* enable and set the channel status audio/data flag */ | |
1273 | if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) { | |
1274 | snd_hda_codec_write(codec, | |
1275 | nvhdmi_master_con_nid_7x, | |
1276 | 0, | |
1277 | AC_VERB_SET_DIGI_CONVERT_1, | |
1278 | codec->spdif_ctls & 0xff); | |
1279 | snd_hda_codec_write(codec, | |
1280 | nvhdmi_master_con_nid_7x, | |
1281 | 0, | |
1282 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
1283 | } | |
1284 | ||
1285 | for (i = 0; i < 4; i++) { | |
1286 | if (chs == 2) | |
1287 | channel_id = 0; | |
1288 | else | |
1289 | channel_id = i * 2; | |
1290 | ||
1291 | /* turn off SPDIF once; | |
1292 | *otherwise the IEC958 bits won't be updated | |
1293 | */ | |
1294 | if (codec->spdif_status_reset && | |
1295 | (codec->spdif_ctls & AC_DIG1_ENABLE)) | |
1296 | snd_hda_codec_write(codec, | |
1297 | nvhdmi_con_nids_7x[i], | |
1298 | 0, | |
1299 | AC_VERB_SET_DIGI_CONVERT_1, | |
1300 | codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff); | |
1301 | /* set the stream id */ | |
1302 | snd_hda_codec_write(codec, | |
1303 | nvhdmi_con_nids_7x[i], | |
1304 | 0, | |
1305 | AC_VERB_SET_CHANNEL_STREAMID, | |
1306 | (stream_tag << 4) | channel_id); | |
1307 | /* set the stream format */ | |
1308 | snd_hda_codec_write(codec, | |
1309 | nvhdmi_con_nids_7x[i], | |
1310 | 0, | |
1311 | AC_VERB_SET_STREAM_FORMAT, | |
1312 | format); | |
1313 | /* turn on again (if needed) */ | |
1314 | /* enable and set the channel status audio/data flag */ | |
1315 | if (codec->spdif_status_reset && | |
1316 | (codec->spdif_ctls & AC_DIG1_ENABLE)) { | |
1317 | snd_hda_codec_write(codec, | |
1318 | nvhdmi_con_nids_7x[i], | |
1319 | 0, | |
1320 | AC_VERB_SET_DIGI_CONVERT_1, | |
1321 | codec->spdif_ctls & 0xff); | |
1322 | snd_hda_codec_write(codec, | |
1323 | nvhdmi_con_nids_7x[i], | |
1324 | 0, | |
1325 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | /* set the Audio Info Frame Checksum */ | |
1330 | snd_hda_codec_write(codec, 0x1, 0, | |
1331 | Nv_VERB_SET_Info_Frame_Checksum, | |
1332 | (0x71 - chan - chanmask)); | |
1333 | ||
1334 | mutex_unlock(&codec->spdif_mutex); | |
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { | |
1339 | .substreams = 1, | |
1340 | .channels_min = 2, | |
1341 | .channels_max = 8, | |
1342 | .nid = nvhdmi_master_con_nid_7x, | |
1343 | .rates = SUPPORTED_RATES, | |
1344 | .maxbps = SUPPORTED_MAXBPS, | |
1345 | .formats = SUPPORTED_FORMATS, | |
1346 | .ops = { | |
1347 | .open = simple_playback_pcm_open, | |
1348 | .close = nvhdmi_8ch_7x_pcm_close, | |
1349 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
1350 | }, | |
1351 | }; | |
1352 | ||
1353 | static struct hda_pcm_stream nvhdmi_pcm_playback_2ch = { | |
1354 | .substreams = 1, | |
1355 | .channels_min = 2, | |
1356 | .channels_max = 2, | |
1357 | .nid = nvhdmi_master_con_nid_7x, | |
1358 | .rates = SUPPORTED_RATES, | |
1359 | .maxbps = SUPPORTED_MAXBPS, | |
1360 | .formats = SUPPORTED_FORMATS, | |
1361 | .ops = { | |
1362 | .open = simple_playback_pcm_open, | |
1363 | .close = simple_playback_pcm_close, | |
1364 | .prepare = simple_playback_pcm_prepare | |
1365 | }, | |
1366 | }; | |
1367 | ||
1368 | static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = { | |
1369 | .build_controls = generic_hdmi_build_controls, | |
1370 | .build_pcms = generic_hdmi_build_pcms, | |
1371 | .init = nvhdmi_7x_init, | |
1372 | .free = generic_hdmi_free, | |
1373 | }; | |
1374 | ||
1375 | static struct hda_codec_ops nvhdmi_patch_ops_2ch = { | |
1376 | .build_controls = generic_hdmi_build_controls, | |
1377 | .build_pcms = generic_hdmi_build_pcms, | |
1378 | .init = nvhdmi_7x_init, | |
1379 | .free = generic_hdmi_free, | |
1380 | }; | |
1381 | ||
1382 | static int patch_nvhdmi_8ch_89(struct hda_codec *codec) | |
1383 | { | |
1384 | struct hdmi_spec *spec; | |
1385 | int err = patch_generic_hdmi(codec); | |
1386 | ||
1387 | if (err < 0) | |
1388 | return err; | |
1389 | spec = codec->spec; | |
1390 | spec->old_pin_detect = 1; | |
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | static int patch_nvhdmi_2ch(struct hda_codec *codec) | |
1395 | { | |
1396 | struct hdmi_spec *spec; | |
1397 | ||
1398 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
1399 | if (spec == NULL) | |
1400 | return -ENOMEM; | |
1401 | ||
1402 | codec->spec = spec; | |
1403 | ||
1404 | spec->multiout.num_dacs = 0; /* no analog */ | |
1405 | spec->multiout.max_channels = 2; | |
1406 | spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x; | |
1407 | spec->old_pin_detect = 1; | |
1408 | spec->num_cvts = 1; | |
1409 | spec->cvt[0] = nvhdmi_master_con_nid_7x; | |
1410 | spec->pcm_playback = &nvhdmi_pcm_playback_2ch; | |
1411 | ||
1412 | codec->patch_ops = nvhdmi_patch_ops_2ch; | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) | |
1418 | { | |
1419 | struct hdmi_spec *spec; | |
1420 | int err = patch_nvhdmi_2ch(codec); | |
1421 | ||
1422 | if (err < 0) | |
1423 | return err; | |
1424 | spec = codec->spec; | |
1425 | spec->multiout.max_channels = 8; | |
1426 | spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x; | |
1427 | codec->patch_ops = nvhdmi_patch_ops_8ch_7x; | |
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | /* | |
1432 | * ATI-specific implementations | |
1433 | * | |
1434 | * FIXME: we may omit the whole this and use the generic code once after | |
1435 | * it's confirmed to work. | |
1436 | */ | |
1437 | ||
1438 | #define ATIHDMI_CVT_NID 0x02 /* audio converter */ | |
1439 | #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */ | |
1440 | ||
1441 | static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1442 | struct hda_codec *codec, | |
1443 | unsigned int stream_tag, | |
1444 | unsigned int format, | |
1445 | struct snd_pcm_substream *substream) | |
1446 | { | |
1447 | struct hdmi_spec *spec = codec->spec; | |
1448 | int chans = substream->runtime->channels; | |
1449 | int i, err; | |
1450 | ||
1451 | err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format, | |
1452 | substream); | |
1453 | if (err < 0) | |
1454 | return err; | |
1455 | snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT, | |
1456 | chans - 1); | |
1457 | /* FIXME: XXX */ | |
1458 | for (i = 0; i < chans; i++) { | |
1459 | snd_hda_codec_write(codec, spec->cvt[0], 0, | |
1460 | AC_VERB_SET_HDMI_CHAN_SLOT, | |
1461 | (i << 4) | i); | |
1462 | } | |
1463 | return 0; | |
1464 | } | |
1465 | ||
1466 | static struct hda_pcm_stream atihdmi_pcm_digital_playback = { | |
1467 | .substreams = 1, | |
1468 | .channels_min = 2, | |
1469 | .channels_max = 2, | |
1470 | .nid = ATIHDMI_CVT_NID, | |
1471 | .ops = { | |
1472 | .open = simple_playback_pcm_open, | |
1473 | .close = simple_playback_pcm_close, | |
1474 | .prepare = atihdmi_playback_pcm_prepare | |
1475 | }, | |
1476 | }; | |
1477 | ||
1478 | static struct hda_verb atihdmi_basic_init[] = { | |
1479 | /* enable digital output on pin widget */ | |
1480 | { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, | |
1481 | {} /* terminator */ | |
1482 | }; | |
1483 | ||
1484 | static int atihdmi_init(struct hda_codec *codec) | |
1485 | { | |
1486 | struct hdmi_spec *spec = codec->spec; | |
1487 | ||
1488 | snd_hda_sequence_write(codec, atihdmi_basic_init); | |
1489 | /* SI codec requires to unmute the pin */ | |
1490 | if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP) | |
1491 | snd_hda_codec_write(codec, spec->pin[0], 0, | |
1492 | AC_VERB_SET_AMP_GAIN_MUTE, | |
1493 | AMP_OUT_UNMUTE); | |
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | static struct hda_codec_ops atihdmi_patch_ops = { | |
1498 | .build_controls = generic_hdmi_build_controls, | |
1499 | .build_pcms = generic_hdmi_build_pcms, | |
1500 | .init = atihdmi_init, | |
1501 | .free = generic_hdmi_free, | |
1502 | }; | |
1503 | ||
1504 | ||
1505 | static int patch_atihdmi(struct hda_codec *codec) | |
1506 | { | |
1507 | struct hdmi_spec *spec; | |
1508 | ||
1509 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
1510 | if (spec == NULL) | |
1511 | return -ENOMEM; | |
1512 | ||
1513 | codec->spec = spec; | |
1514 | ||
1515 | spec->multiout.num_dacs = 0; /* no analog */ | |
1516 | spec->multiout.max_channels = 2; | |
1517 | spec->multiout.dig_out_nid = ATIHDMI_CVT_NID; | |
1518 | spec->num_cvts = 1; | |
1519 | spec->cvt[0] = ATIHDMI_CVT_NID; | |
1520 | spec->pin[0] = ATIHDMI_PIN_NID; | |
1521 | spec->pcm_playback = &atihdmi_pcm_digital_playback; | |
1522 | ||
1523 | codec->patch_ops = atihdmi_patch_ops; | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | ||
1529 | /* | |
1530 | * patch entries | |
1531 | */ | |
1532 | static struct hda_codec_preset snd_hda_preset_hdmi[] = { | |
1533 | { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi }, | |
1534 | { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi }, | |
1535 | { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi }, | |
1536 | { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi }, | |
1537 | { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi }, | |
1538 | { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi }, | |
1539 | { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi }, | |
1540 | { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, | |
1541 | { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, | |
1542 | { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, | |
1543 | { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x }, | |
1544 | { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x }, | |
1545 | { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1546 | { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1547 | { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi_8ch_89 }, | |
1548 | { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1549 | { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1550 | { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1551 | { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1552 | { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1553 | { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1554 | { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1555 | { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1556 | { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1557 | { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1558 | { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1559 | { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1560 | { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1561 | { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1562 | { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1563 | { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi_8ch_89 }, | |
1564 | { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch }, | |
1565 | { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch }, | |
1566 | { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi }, | |
1567 | { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi }, | |
1568 | { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi }, | |
1569 | { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi }, | |
1570 | { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi }, | |
1571 | { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi }, | |
1572 | { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi }, | |
1573 | {} /* terminator */ | |
1574 | }; | |
1575 | ||
1576 | MODULE_ALIAS("snd-hda-codec-id:1002793c"); | |
1577 | MODULE_ALIAS("snd-hda-codec-id:10027919"); | |
1578 | MODULE_ALIAS("snd-hda-codec-id:1002791a"); | |
1579 | MODULE_ALIAS("snd-hda-codec-id:1002aa01"); | |
1580 | MODULE_ALIAS("snd-hda-codec-id:10951390"); | |
1581 | MODULE_ALIAS("snd-hda-codec-id:10951392"); | |
1582 | MODULE_ALIAS("snd-hda-codec-id:10de0002"); | |
1583 | MODULE_ALIAS("snd-hda-codec-id:10de0003"); | |
1584 | MODULE_ALIAS("snd-hda-codec-id:10de0005"); | |
1585 | MODULE_ALIAS("snd-hda-codec-id:10de0006"); | |
1586 | MODULE_ALIAS("snd-hda-codec-id:10de0007"); | |
1587 | MODULE_ALIAS("snd-hda-codec-id:10de000a"); | |
1588 | MODULE_ALIAS("snd-hda-codec-id:10de000b"); | |
1589 | MODULE_ALIAS("snd-hda-codec-id:10de000c"); | |
1590 | MODULE_ALIAS("snd-hda-codec-id:10de000d"); | |
1591 | MODULE_ALIAS("snd-hda-codec-id:10de0010"); | |
1592 | MODULE_ALIAS("snd-hda-codec-id:10de0011"); | |
1593 | MODULE_ALIAS("snd-hda-codec-id:10de0012"); | |
1594 | MODULE_ALIAS("snd-hda-codec-id:10de0013"); | |
1595 | MODULE_ALIAS("snd-hda-codec-id:10de0014"); | |
1596 | MODULE_ALIAS("snd-hda-codec-id:10de0018"); | |
1597 | MODULE_ALIAS("snd-hda-codec-id:10de0019"); | |
1598 | MODULE_ALIAS("snd-hda-codec-id:10de001a"); | |
1599 | MODULE_ALIAS("snd-hda-codec-id:10de001b"); | |
1600 | MODULE_ALIAS("snd-hda-codec-id:10de001c"); | |
1601 | MODULE_ALIAS("snd-hda-codec-id:10de0040"); | |
1602 | MODULE_ALIAS("snd-hda-codec-id:10de0041"); | |
1603 | MODULE_ALIAS("snd-hda-codec-id:10de0042"); | |
1604 | MODULE_ALIAS("snd-hda-codec-id:10de0043"); | |
1605 | MODULE_ALIAS("snd-hda-codec-id:10de0044"); | |
1606 | MODULE_ALIAS("snd-hda-codec-id:10de0067"); | |
1607 | MODULE_ALIAS("snd-hda-codec-id:10de8001"); | |
1608 | MODULE_ALIAS("snd-hda-codec-id:17e80047"); | |
1609 | MODULE_ALIAS("snd-hda-codec-id:80860054"); | |
1610 | MODULE_ALIAS("snd-hda-codec-id:80862801"); | |
1611 | MODULE_ALIAS("snd-hda-codec-id:80862802"); | |
1612 | MODULE_ALIAS("snd-hda-codec-id:80862803"); | |
1613 | MODULE_ALIAS("snd-hda-codec-id:80862804"); | |
1614 | MODULE_ALIAS("snd-hda-codec-id:80862805"); | |
1615 | MODULE_ALIAS("snd-hda-codec-id:808629fb"); | |
1616 | ||
1617 | MODULE_LICENSE("GPL"); | |
1618 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
1619 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
1620 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
1621 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
1622 | ||
1623 | static struct hda_codec_preset_list intel_list = { | |
1624 | .preset = snd_hda_preset_hdmi, | |
1625 | .owner = THIS_MODULE, | |
1626 | }; | |
1627 | ||
1628 | static int __init patch_hdmi_init(void) | |
1629 | { | |
1630 | return snd_hda_add_codec_preset(&intel_list); | |
1631 | } | |
1632 | ||
1633 | static void __exit patch_hdmi_exit(void) | |
1634 | { | |
1635 | snd_hda_delete_codec_preset(&intel_list); | |
1636 | } | |
1637 | ||
1638 | module_init(patch_hdmi_init) | |
1639 | module_exit(patch_hdmi_exit) |