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1da177e4
LT		 1/*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
1da177e4
LT		 97#include <asm/io.h>
98#include <linux/delay.h>
99#include <linux/interrupt.h>
100#include <linux/init.h>
101#include <linux/pci.h>
9d2f928d 102#include <linux/dma-mapping.h>
1da177e4
LT		 103#include <linux/slab.h>
104#include <linux/gameport.h>
105#include <linux/moduleparam.h>
62932df8 106#include <linux/mutex.h>
5a5e02e5 107#include <linux/input.h>
62932df8 108
1da177e4
LT		 109#include <sound/core.h>
110#include <sound/pcm.h>
111#include <sound/mpu401.h>
112#include <sound/ac97_codec.h>
113#include <sound/initval.h>
114
115#define CARD_NAME "ESS Maestro1/2"
116#define DRIVER_NAME "ES1968"
117
118MODULE_DESCRIPTION("ESS Maestro");
119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
121 "{ESS,Maestro 2},"
122 "{ESS,Maestro 1},"
123 "{TerraTec,DMX}}");
124
125#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
126#define SUPPORT_JOYSTICK 1
127#endif
128
129static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
130static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
131static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
132static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
133static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
134static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
6581f4e7 135static int clock[SNDRV_CARDS];
1da177e4
LT		 136static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
137static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
138#ifdef SUPPORT_JOYSTICK
139static int joystick[SNDRV_CARDS];
140#endif
141
142module_param_array(index, int, NULL, 0444);
143MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
144module_param_array(id, charp, NULL, 0444);
145MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
148module_param_array(total_bufsize, int, NULL, 0444);
149MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
150module_param_array(pcm_substreams_p, int, NULL, 0444);
151MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
152module_param_array(pcm_substreams_c, int, NULL, 0444);
153MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
154module_param_array(clock, int, NULL, 0444);
155MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
156module_param_array(use_pm, int, NULL, 0444);
157MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
158module_param_array(enable_mpu, int, NULL, 0444);
159MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
160#ifdef SUPPORT_JOYSTICK
161module_param_array(joystick, bool, NULL, 0444);
162MODULE_PARM_DESC(joystick, "Enable joystick.");
163#endif
164
165
1da177e4
LT		 166#define NR_APUS 64
167#define NR_APU_REGS 16
168
169/* NEC Versas ? */
170#define NEC_VERSA_SUBID1 0x80581033
171#define NEC_VERSA_SUBID2 0x803c1033
172
173/* Mode Flags */
174#define ESS_FMT_STEREO 0x01
175#define ESS_FMT_16BIT 0x02
176
177#define DAC_RUNNING 1
178#define ADC_RUNNING 2
179
180/* Values for the ESM_LEGACY_AUDIO_CONTROL */
181
607da7f8 182#define ESS_DISABLE_AUDIO 0x8000
1da177e4
LT		 183#define ESS_ENABLE_SERIAL_IRQ 0x4000
184#define IO_ADRESS_ALIAS 0x0020
185#define MPU401_IRQ_ENABLE 0x0010
186#define MPU401_IO_ENABLE 0x0008
187#define GAME_IO_ENABLE 0x0004
188#define FM_IO_ENABLE 0x0002
189#define SB_IO_ENABLE 0x0001
190
191/* Values for the ESM_CONFIG_A */
192
193#define PIC_SNOOP1 0x4000
194#define PIC_SNOOP2 0x2000
195#define SAFEGUARD 0x0800
196#define DMA_CLEAR 0x0700
197#define DMA_DDMA 0x0000
198#define DMA_TDMA 0x0100
199#define DMA_PCPCI 0x0200
200#define POST_WRITE 0x0080
607da7f8 201#define PCI_TIMING 0x0040
1da177e4
LT		 202#define SWAP_LR 0x0020
203#define SUBTR_DECODE 0x0002
204
205/* Values for the ESM_CONFIG_B */
206
207#define SPDIF_CONFB 0x0100
208#define HWV_CONFB 0x0080
209#define DEBOUNCE 0x0040
210#define GPIO_CONFB 0x0020
211#define CHI_CONFB 0x0010
212#define IDMA_CONFB 0x0008 /*undoc */
213#define MIDI_FIX 0x0004 /*undoc */
214#define IRQ_TO_ISA 0x0001 /*undoc */
215
216/* Values for Ring Bus Control B */
217#define RINGB_2CODEC_ID_MASK 0x0003
218#define RINGB_DIS_VALIDATION 0x0008
219#define RINGB_EN_SPDIF 0x0010
220#define RINGB_EN_2CODEC 0x0020
221#define RINGB_SING_BIT_DUAL 0x0040
222
223/* ****Port Adresses**** */
224
225/* Write & Read */
226#define ESM_INDEX 0x02
227#define ESM_DATA 0x00
228
229/* AC97 + RingBus */
230#define ESM_AC97_INDEX 0x30
231#define ESM_AC97_DATA 0x32
232#define ESM_RING_BUS_DEST 0x34
233#define ESM_RING_BUS_CONTR_A 0x36
234#define ESM_RING_BUS_CONTR_B 0x38
235#define ESM_RING_BUS_SDO 0x3A
236
237/* WaveCache*/
238#define WC_INDEX 0x10
239#define WC_DATA 0x12
240#define WC_CONTROL 0x14
241
242/* ASSP*/
243#define ASSP_INDEX 0x80
244#define ASSP_MEMORY 0x82
245#define ASSP_DATA 0x84
246#define ASSP_CONTROL_A 0xA2
247#define ASSP_CONTROL_B 0xA4
248#define ASSP_CONTROL_C 0xA6
249#define ASSP_HOSTW_INDEX 0xA8
250#define ASSP_HOSTW_DATA 0xAA
251#define ASSP_HOSTW_IRQ 0xAC
252/* Midi */
253#define ESM_MPU401_PORT 0x98
254/* Others */
255#define ESM_PORT_HOST_IRQ 0x18
256
257#define IDR0_DATA_PORT 0x00
258#define IDR1_CRAM_POINTER 0x01
259#define IDR2_CRAM_DATA 0x02
260#define IDR3_WAVE_DATA 0x03
261#define IDR4_WAVE_PTR_LOW 0x04
262#define IDR5_WAVE_PTR_HI 0x05
263#define IDR6_TIMER_CTRL 0x06
264#define IDR7_WAVE_ROMRAM 0x07
265
266#define WRITEABLE_MAP 0xEFFFFF
267#define READABLE_MAP 0x64003F
268
269/* PCI Register */
270
271#define ESM_LEGACY_AUDIO_CONTROL 0x40
272#define ESM_ACPI_COMMAND 0x54
273#define ESM_CONFIG_A 0x50
274#define ESM_CONFIG_B 0x52
275#define ESM_DDMA 0x60
276
277/* Bob Bits */
278#define ESM_BOB_ENABLE 0x0001
279#define ESM_BOB_START 0x0001
280
281/* Host IRQ Control Bits */
282#define ESM_RESET_MAESTRO 0x8000
283#define ESM_RESET_DIRECTSOUND 0x4000
284#define ESM_HIRQ_ClkRun 0x0100
285#define ESM_HIRQ_HW_VOLUME 0x0040
286#define ESM_HIRQ_HARPO 0x0030 /* What's that? */
287#define ESM_HIRQ_ASSP 0x0010
288#define ESM_HIRQ_DSIE 0x0004
289#define ESM_HIRQ_MPU401 0x0002
290#define ESM_HIRQ_SB 0x0001
291
292/* Host IRQ Status Bits */
293#define ESM_MPU401_IRQ 0x02
294#define ESM_SB_IRQ 0x01
295#define ESM_SOUND_IRQ 0x04
296#define ESM_ASSP_IRQ 0x10
297#define ESM_HWVOL_IRQ 0x40
298
299#define ESS_SYSCLK 50000000
300#define ESM_BOB_FREQ 200
301#define ESM_BOB_FREQ_MAX 800
302
303#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
304#define ESM_FREQ_ESM2 (50000000L / 1024L)
305
306/* APU Modes: reg 0x00, bit 4-7 */
307#define ESM_APU_MODE_SHIFT 4
308#define ESM_APU_MODE_MASK (0xf << 4)
309#define ESM_APU_OFF 0x00
310#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
311#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
312#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
313#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
314#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
315#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
316#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
317#define ESM_APU_CORRELATOR 0x08 /* Correlator */
318#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
319#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
320#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
321#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
322#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
323#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
324#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
325
326/* reg 0x00 */
327#define ESM_APU_FILTER_Q_SHIFT 0
328#define ESM_APU_FILTER_Q_MASK (3 << 0)
329/* APU Filtey Q Control */
330#define ESM_APU_FILTER_LESSQ 0x00
331#define ESM_APU_FILTER_MOREQ 0x03
332
333#define ESM_APU_FILTER_TYPE_SHIFT 2
334#define ESM_APU_FILTER_TYPE_MASK (3 << 2)
335#define ESM_APU_ENV_TYPE_SHIFT 8
336#define ESM_APU_ENV_TYPE_MASK (3 << 8)
337#define ESM_APU_ENV_STATE_SHIFT 10
338#define ESM_APU_ENV_STATE_MASK (3 << 10)
339#define ESM_APU_END_CURVE (1 << 12)
340#define ESM_APU_INT_ON_LOOP (1 << 13)
341#define ESM_APU_DMA_ENABLE (1 << 14)
342
343/* reg 0x02 */
344#define ESM_APU_SUBMIX_GROUP_SHIRT 0
345#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
346#define ESM_APU_SUBMIX_MODE (1 << 3)
347#define ESM_APU_6dB (1 << 4)
348#define ESM_APU_DUAL_EFFECT (1 << 5)
349#define ESM_APU_EFFECT_CHANNELS_SHIFT 6
350#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
351
352/* reg 0x03 */
353#define ESM_APU_STEP_SIZE_MASK 0x0fff
354
355/* reg 0x04 */
356#define ESM_APU_PHASE_SHIFT 0
357#define ESM_APU_PHASE_MASK (0xff << 0)
358#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
359#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
360
361/* reg 0x05 - wave start offset */
362/* reg 0x06 - wave end offset */
363/* reg 0x07 - wave loop length */
364
365/* reg 0x08 */
366#define ESM_APU_EFFECT_GAIN_SHIFT 0
367#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
368#define ESM_APU_TREMOLO_DEPTH_SHIFT 8
369#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
370#define ESM_APU_TREMOLO_RATE_SHIFT 12
371#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
372
373/* reg 0x09 */
374/* bit 0-7 amplitude dest? */
375#define ESM_APU_AMPLITUDE_NOW_SHIFT 8
376#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
377
378/* reg 0x0a */
379#define ESM_APU_POLAR_PAN_SHIFT 0
380#define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
381/* Polar Pan Control */
382#define ESM_APU_PAN_CENTER_CIRCLE 0x00
383#define ESM_APU_PAN_MIDDLE_RADIUS 0x01
384#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
385
386#define ESM_APU_FILTER_TUNING_SHIFT 8
387#define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
388
389/* reg 0x0b */
390#define ESM_APU_DATA_SRC_A_SHIFT 0
391#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
392#define ESM_APU_INV_POL_A (1 << 7)
393#define ESM_APU_DATA_SRC_B_SHIFT 8
394#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
395#define ESM_APU_INV_POL_B (1 << 15)
396
397#define ESM_APU_VIBRATO_RATE_SHIFT 0
398#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
399#define ESM_APU_VIBRATO_DEPTH_SHIFT 4
400#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
401#define ESM_APU_VIBRATO_PHASE_SHIFT 8
402#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
403
404/* reg 0x0c */
405#define ESM_APU_RADIUS_SELECT (1 << 6)
406
407/* APU Filter Control */
408#define ESM_APU_FILTER_2POLE_LOPASS 0x00
409#define ESM_APU_FILTER_2POLE_BANDPASS 0x01
410#define ESM_APU_FILTER_2POLE_HIPASS 0x02
411#define ESM_APU_FILTER_1POLE_LOPASS 0x03
412#define ESM_APU_FILTER_1POLE_HIPASS 0x04
413#define ESM_APU_FILTER_OFF 0x05
414
415/* APU ATFP Type */
416#define ESM_APU_ATFP_AMPLITUDE 0x00
417#define ESM_APU_ATFP_TREMELO 0x01
418#define ESM_APU_ATFP_FILTER 0x02
419#define ESM_APU_ATFP_PAN 0x03
420
421/* APU ATFP Flags */
422#define ESM_APU_ATFP_FLG_OFF 0x00
423#define ESM_APU_ATFP_FLG_WAIT 0x01
424#define ESM_APU_ATFP_FLG_DONE 0x02
425#define ESM_APU_ATFP_FLG_INPROCESS 0x03
426
427
428/* capture mixing buffer size */
429#define ESM_MEM_ALIGN 0x1000
430#define ESM_MIXBUF_SIZE 0x400
431
432#define ESM_MODE_PLAY 0
433#define ESM_MODE_CAPTURE 1
434
1da177e4 435
1da177e4
LT		 436/* APU use in the driver */
437enum snd_enum_apu_type {
438 ESM_APU_PCM_PLAY,
439 ESM_APU_PCM_CAPTURE,
440 ESM_APU_PCM_RATECONV,
441 ESM_APU_FREE
442};
443
444/* chip type */
445enum {
446 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
447};
448
449/* DMA Hack! */
969165a8 450struct esm_memory {
1da177e4
LT		 451 struct snd_dma_buffer buf;
452 int empty; /* status */
453 struct list_head list;
454};
455
456/* Playback Channel */
969165a8 457struct esschan {
1da177e4
LT		 458 int running;
459
460 u8 apu[4];
461 u8 apu_mode[4];
462
463 /* playback/capture pcm buffer */
969165a8 464 struct esm_memory *memory;
1da177e4 465 /* capture mixer buffer */
969165a8 466 struct esm_memory *mixbuf;
1da177e4
LT		 467
468 unsigned int hwptr; /* current hw pointer in bytes */
469 unsigned int count; /* sample counter in bytes */
470 unsigned int dma_size; /* total buffer size in bytes */
471 unsigned int frag_size; /* period size in bytes */
472 unsigned int wav_shift;
473 u16 base[4]; /* offset for ptr */
474
475 /* stereo/16bit flag */
476 unsigned char fmt;
477 int mode; /* playback / capture */
478
479 int bob_freq; /* required timer frequency */
480
969165a8 481 struct snd_pcm_substream *substream;
1da177e4
LT		 482
483 /* linked list */
484 struct list_head list;
485
486#ifdef CONFIG_PM
487 u16 wc_map[4];
488#endif
489};
490
969165a8 491struct es1968 {
1da177e4
LT		 492 /* Module Config */
493 int total_bufsize; /* in bytes */
494
495 int playback_streams, capture_streams;
496
497 unsigned int clock; /* clock */
498 /* for clock measurement */
499 unsigned int in_measurement: 1;
500 unsigned int measure_apu;
501 unsigned int measure_lastpos;
502 unsigned int measure_count;
503
504 /* buffer */
505 struct snd_dma_buffer dma;
506
507 /* Resources... */
508 int irq;
509 unsigned long io_port;
510 int type;
511 struct pci_dev *pci;
969165a8
TI		 512 struct snd_card *card;
513 struct snd_pcm *pcm;
1da177e4
LT		 514 int do_pm; /* power-management enabled */
515
516 /* DMA memory block */
517 struct list_head buf_list;
518
519 /* ALSA Stuff */
969165a8 520 struct snd_ac97 *ac97;
969165a8 521 struct snd_rawmidi *rmidi;
1da177e4
LT		 522
523 spinlock_t reg_lock;
1da177e4
LT		 524 unsigned int in_suspend;
525
526 /* Maestro Stuff */
527 u16 maestro_map[32];
528 int bobclient; /* active timer instancs */
529 int bob_freq; /* timer frequency */
62932df8 530 struct mutex memory_mutex; /* memory lock */
1da177e4
LT		 531
532 /* APU states */
533 unsigned char apu[NR_APUS];
534
535 /* active substreams */
536 struct list_head substream_list;
537 spinlock_t substream_lock;
538
539#ifdef CONFIG_PM
540 u16 apu_map[NR_APUS][NR_APU_REGS];
541#endif
542
543#ifdef SUPPORT_JOYSTICK
544 struct gameport *gameport;
545#endif
5a5e02e5
HG		 546
547#ifdef CONFIG_SND_ES1968_INPUT
548 struct input_dev *input_dev;
549 char phys[64]; /* physical device path */
550#else
551 struct snd_kcontrol *master_switch; /* for h/w volume control */
552 struct snd_kcontrol *master_volume;
553 spinlock_t ac97_lock;
554 struct tasklet_struct hwvol_tq;
555#endif
1da177e4
LT		 556};
557
7d12e780 558static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
1da177e4 559
cebe41d4 560static DEFINE_PCI_DEVICE_TABLE(snd_es1968_ids) = {
1da177e4
LT		 561 /* Maestro 1 */
562 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
563 /* Maestro 2 */
564 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
565 /* Maestro 2E */
566 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
567 { 0, }
568};
569
570MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
571
572/* *********************
573 * Low Level Funcs! *
574 *********************/
575
576/* no spinlock */
969165a8 577static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
1da177e4
LT		 578{
579 outw(reg, chip->io_port + ESM_INDEX);
580 outw(data, chip->io_port + ESM_DATA);
581 chip->maestro_map[reg] = data;
582}
583
969165a8 584static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
1da177e4
LT		 585{
586 unsigned long flags;
587 spin_lock_irqsave(&chip->reg_lock, flags);
588 __maestro_write(chip, reg, data);
589 spin_unlock_irqrestore(&chip->reg_lock, flags);
590}
591
592/* no spinlock */
969165a8 593static u16 __maestro_read(struct es1968 *chip, u16 reg)
1da177e4
LT		 594{
595 if (READABLE_MAP & (1 << reg)) {
596 outw(reg, chip->io_port + ESM_INDEX);
597 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
598 }
599 return chip->maestro_map[reg];
600}
601
969165a8 602static inline u16 maestro_read(struct es1968 *chip, u16 reg)
1da177e4
LT		 603{
604 unsigned long flags;
605 u16 result;
606 spin_lock_irqsave(&chip->reg_lock, flags);
607 result = __maestro_read(chip, reg);
608 spin_unlock_irqrestore(&chip->reg_lock, flags);
609 return result;
610}
611
1da177e4 612/* Wait for the codec bus to be free */
969165a8 613static int snd_es1968_ac97_wait(struct es1968 *chip)
1da177e4
LT		 614{
615 int timeout = 100000;
616
617 while (timeout-- > 0) {
618 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
619 return 0;
620 cond_resched();
621 }
622 snd_printd("es1968: ac97 timeout\n");
623 return 1; /* timeout */
624}
625
4b47c971
AV		 626static int snd_es1968_ac97_wait_poll(struct es1968 *chip)
627{
628 int timeout = 100000;
629
630 while (timeout-- > 0) {
631 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
632 return 0;
633 }
634 snd_printd("es1968: ac97 timeout\n");
635 return 1; /* timeout */
636}
637
969165a8 638static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1da177e4 639{
969165a8 640 struct es1968 *chip = ac97->private_data;
5a5e02e5 641#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 642 unsigned long flags;
5a5e02e5 643#endif
1da177e4
LT		 644
645 snd_es1968_ac97_wait(chip);
646
647 /* Write the bus */
5a5e02e5 648#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 649 spin_lock_irqsave(&chip->ac97_lock, flags);
5a5e02e5 650#endif
1da177e4
LT		 651 outw(val, chip->io_port + ESM_AC97_DATA);
652 /*msleep(1);*/
653 outb(reg, chip->io_port + ESM_AC97_INDEX);
654 /*msleep(1);*/
5a5e02e5 655#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 656 spin_unlock_irqrestore(&chip->ac97_lock, flags);
5a5e02e5 657#endif
1da177e4
LT		 658}
659
969165a8 660static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4
LT		 661{
662 u16 data = 0;
969165a8 663 struct es1968 *chip = ac97->private_data;
5a5e02e5 664#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 665 unsigned long flags;
5a5e02e5 666#endif
1da177e4
LT		 667
668 snd_es1968_ac97_wait(chip);
669
5a5e02e5 670#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 671 spin_lock_irqsave(&chip->ac97_lock, flags);
5a5e02e5 672#endif
1da177e4
LT		 673 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
674 /*msleep(1);*/
675
4b47c971 676 if (!snd_es1968_ac97_wait_poll(chip)) {
1da177e4
LT		 677 data = inw(chip->io_port + ESM_AC97_DATA);
678 /*msleep(1);*/
679 }
5a5e02e5 680#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 681 spin_unlock_irqrestore(&chip->ac97_lock, flags);
5a5e02e5 682#endif
1da177e4
LT		 683
684 return data;
685}
686
687/* no spinlock */
969165a8 688static void apu_index_set(struct es1968 *chip, u16 index)
1da177e4
LT		 689{
690 int i;
691 __maestro_write(chip, IDR1_CRAM_POINTER, index);
692 for (i = 0; i < 1000; i++)
693 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
694 return;
695 snd_printd("es1968: APU register select failed. (Timeout)\n");
696}
697
698/* no spinlock */
969165a8 699static void apu_data_set(struct es1968 *chip, u16 data)
1da177e4
LT		 700{
701 int i;
702 for (i = 0; i < 1000; i++) {
703 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
704 return;
705 __maestro_write(chip, IDR0_DATA_PORT, data);
706 }
707 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
708}
709
710/* no spinlock */
969165a8 711static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
1da177e4 712{
da3cec35
TI		 713 if (snd_BUG_ON(channel >= NR_APUS))
714 return;
1da177e4
LT		 715#ifdef CONFIG_PM
716 chip->apu_map[channel][reg] = data;
717#endif
718 reg |= (channel << 4);
719 apu_index_set(chip, reg);
720 apu_data_set(chip, data);
721}
722
858119e1 723static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
1da177e4
LT		 724{
725 unsigned long flags;
726 spin_lock_irqsave(&chip->reg_lock, flags);
727 __apu_set_register(chip, channel, reg, data);
728 spin_unlock_irqrestore(&chip->reg_lock, flags);
729}
730
969165a8 731static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
1da177e4 732{
da3cec35
TI		 733 if (snd_BUG_ON(channel >= NR_APUS))
734 return 0;
1da177e4
LT		 735 reg |= (channel << 4);
736 apu_index_set(chip, reg);
737 return __maestro_read(chip, IDR0_DATA_PORT);
738}
739
858119e1 740static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
1da177e4
LT		 741{
742 unsigned long flags;
743 u16 v;
744 spin_lock_irqsave(&chip->reg_lock, flags);
745 v = __apu_get_register(chip, channel, reg);
746 spin_unlock_irqrestore(&chip->reg_lock, flags);
747 return v;
748}
749
750#if 0 /* ASSP is not supported */
751
969165a8 752static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
1da177e4
LT		 753{
754 unsigned long flags;
755
756 spin_lock_irqsave(&chip->reg_lock, flags);
757 outl(reg, chip->io_port + ASSP_INDEX);
758 outl(value, chip->io_port + ASSP_DATA);
759 spin_unlock_irqrestore(&chip->reg_lock, flags);
760}
761
969165a8 762static u32 assp_get_register(struct es1968 *chip, u32 reg)
1da177e4
LT		 763{
764 unsigned long flags;
765 u32 value;
766
767 spin_lock_irqsave(&chip->reg_lock, flags);
768 outl(reg, chip->io_port + ASSP_INDEX);
769 value = inl(chip->io_port + ASSP_DATA);
770 spin_unlock_irqrestore(&chip->reg_lock, flags);
771
772 return value;
773}
774
775#endif
776
969165a8 777static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
1da177e4
LT		 778{
779 unsigned long flags;
780
781 spin_lock_irqsave(&chip->reg_lock, flags);
782 outw(reg, chip->io_port + WC_INDEX);
783 outw(value, chip->io_port + WC_DATA);
784 spin_unlock_irqrestore(&chip->reg_lock, flags);
785}
786
969165a8 787static u16 wave_get_register(struct es1968 *chip, u16 reg)
1da177e4
LT		 788{
789 unsigned long flags;
790 u16 value;
791
792 spin_lock_irqsave(&chip->reg_lock, flags);
793 outw(reg, chip->io_port + WC_INDEX);
794 value = inw(chip->io_port + WC_DATA);
795 spin_unlock_irqrestore(&chip->reg_lock, flags);
796
797 return value;
798}
799
800/* *******************
801 * Bob the Timer! *
802 *******************/
803
969165a8 804static void snd_es1968_bob_stop(struct es1968 *chip)
1da177e4
LT		 805{
806 u16 reg;
807
808 reg = __maestro_read(chip, 0x11);
809 reg &= ~ESM_BOB_ENABLE;
810 __maestro_write(chip, 0x11, reg);
811 reg = __maestro_read(chip, 0x17);
812 reg &= ~ESM_BOB_START;
813 __maestro_write(chip, 0x17, reg);
814}
815
969165a8 816static void snd_es1968_bob_start(struct es1968 *chip)
1da177e4
LT		 817{
818 int prescale;
819 int divide;
820
821 /* compute ideal interrupt frequency for buffer size & play rate */
822 /* first, find best prescaler value to match freq */
823 for (prescale = 5; prescale < 12; prescale++)
824 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
825 break;
826
827 /* next, back off prescaler whilst getting divider into optimum range */
828 divide = 1;
829 while ((prescale > 5) && (divide < 32)) {
830 prescale--;
831 divide <<= 1;
832 }
833 divide >>= 1;
834
835 /* now fine-tune the divider for best match */
836 for (; divide < 31; divide++)
837 if (chip->bob_freq >
838 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
839
840 /* divide = 0 is illegal, but don't let prescale = 4! */
841 if (divide == 0) {
842 divide++;
843 if (prescale > 5)
844 prescale--;
845 } else if (divide > 1)
846 divide--;
847
848 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
849
850 /* Now set IDR 11/17 */
851 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
852 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
853}
854
855/* call with substream spinlock */
969165a8 856static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
1da177e4
LT		 857{
858 chip->bobclient++;
859 if (chip->bobclient == 1) {
860 chip->bob_freq = freq;
861 snd_es1968_bob_start(chip);
862 } else if (chip->bob_freq < freq) {
863 snd_es1968_bob_stop(chip);
864 chip->bob_freq = freq;
865 snd_es1968_bob_start(chip);
866 }
867}
868
869/* call with substream spinlock */
969165a8 870static void snd_es1968_bob_dec(struct es1968 *chip)
1da177e4
LT		 871{
872 chip->bobclient--;
873 if (chip->bobclient <= 0)
874 snd_es1968_bob_stop(chip);
875 else if (chip->bob_freq > ESM_BOB_FREQ) {
876 /* check reduction of timer frequency */
1da177e4 877 int max_freq = ESM_BOB_FREQ;
50f47ff1
MK		 878 struct esschan *es;
879 list_for_each_entry(es, &chip->substream_list, list) {
1da177e4
LT		 880 if (max_freq < es->bob_freq)
881 max_freq = es->bob_freq;
882 }
883 if (max_freq != chip->bob_freq) {
884 snd_es1968_bob_stop(chip);
885 chip->bob_freq = max_freq;
886 snd_es1968_bob_start(chip);
887 }
888 }
889}
890
891static int
969165a8
TI		 892snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
893 struct snd_pcm_runtime *runtime)
1da177e4
LT		 894{
895 /* we acquire 4 interrupts per period for precise control.. */
896 int freq = runtime->rate * 4;
897 if (es->fmt & ESS_FMT_STEREO)
898 freq <<= 1;
899 if (es->fmt & ESS_FMT_16BIT)
900 freq <<= 1;
901 freq /= es->frag_size;
902 if (freq < ESM_BOB_FREQ)
903 freq = ESM_BOB_FREQ;
904 else if (freq > ESM_BOB_FREQ_MAX)
905 freq = ESM_BOB_FREQ_MAX;
906 return freq;
907}
908
909
910/*************
911 * PCM Part *
912 *************/
913
969165a8 914static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
1da177e4
LT		 915{
916 u32 rate = (freq << 16) / chip->clock;
917#if 0 /* XXX: do we need this? */
918 if (rate > 0x10000)
919 rate = 0x10000;
920#endif
921 return rate;
922}
923
924/* get current pointer */
77933d72 925static inline unsigned int
969165a8 926snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
1da177e4
LT		 927{
928 unsigned int offset;
929
930 offset = apu_get_register(chip, es->apu[0], 5);
931
932 offset -= es->base[0];
933
934 return (offset & 0xFFFE); /* hardware is in words */
935}
936
969165a8 937static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
1da177e4
LT		 938{
939 apu_set_register(chip, apu, 2,
940 (apu_get_register(chip, apu, 2) & 0x00FF) |
941 ((freq & 0xff) << 8) | 0x10);
942 apu_set_register(chip, apu, 3, freq >> 8);
943}
944
945/* spin lock held */
969165a8 946static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
1da177e4
LT		 947{
948 /* set the APU mode */
949 __apu_set_register(esm, apu, 0,
950 (__apu_get_register(esm, apu, 0) & 0xff0f) |
951 (mode << 4));
952}
953
969165a8 954static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
1da177e4
LT		 955{
956 spin_lock(&chip->reg_lock);
957 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
958 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
959 if (es->mode == ESM_MODE_CAPTURE) {
960 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
961 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
962 }
963 if (es->fmt & ESS_FMT_STEREO) {
964 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
965 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
966 if (es->mode == ESM_MODE_CAPTURE) {
967 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
968 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
969 }
970 }
971 spin_unlock(&chip->reg_lock);
972}
973
969165a8 974static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
1da177e4
LT		 975{
976 spin_lock(&chip->reg_lock);
977 snd_es1968_trigger_apu(chip, es->apu[0], 0);
978 snd_es1968_trigger_apu(chip, es->apu[1], 0);
979 if (es->mode == ESM_MODE_CAPTURE) {
980 snd_es1968_trigger_apu(chip, es->apu[2], 0);
981 snd_es1968_trigger_apu(chip, es->apu[3], 0);
982 }
983 spin_unlock(&chip->reg_lock);
984}
985
986/* set the wavecache control reg */
969165a8 987static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
1da177e4
LT		 988 int channel, u32 addr, int capture)
989{
990 u32 tmpval = (addr - 0x10) & 0xFFF8;
991
992 if (! capture) {
993 if (!(es->fmt & ESS_FMT_16BIT))
994 tmpval |= 4; /* 8bit */
995 if (es->fmt & ESS_FMT_STEREO)
996 tmpval |= 2; /* stereo */
997 }
998
999 /* set the wavecache control reg */
1000 wave_set_register(chip, es->apu[channel] << 3, tmpval);
1001
1002#ifdef CONFIG_PM
1003 es->wc_map[channel] = tmpval;
1004#endif
1005}
1006
1007
969165a8
TI		 1008static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
1009 struct snd_pcm_runtime *runtime)
1da177e4
LT		 1010{
1011 u32 pa;
1012 int high_apu = 0;
1013 int channel, apu;
1014 int i, size;
1015 unsigned long flags;
1016 u32 freq;
1017
1018 size = es->dma_size >> es->wav_shift;
1019
1020 if (es->fmt & ESS_FMT_STEREO)
1021 high_apu++;
1022
1023 for (channel = 0; channel <= high_apu; channel++) {
1024 apu = es->apu[channel];
1025
1026 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1027
1028 /* Offset to PCMBAR */
1029 pa = es->memory->buf.addr;
1030 pa -= chip->dma.addr;
1031 pa >>= 1; /* words */
1032
1033 pa |= 0x00400000; /* System RAM (Bit 22) */
1034
1035 if (es->fmt & ESS_FMT_STEREO) {
1036 /* Enable stereo */
1037 if (channel)
1038 pa |= 0x00800000; /* (Bit 23) */
1039 if (es->fmt & ESS_FMT_16BIT)
1040 pa >>= 1;
1041 }
1042
1043 /* base offset of dma calcs when reading the pointer
1044 on this left one */
1045 es->base[channel] = pa & 0xFFFF;
1046
1047 for (i = 0; i < 16; i++)
1048 apu_set_register(chip, apu, i, 0x0000);
1049
1050 /* Load the buffer into the wave engine */
1051 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1052 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1053 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1054 /* setting loop == sample len */
1055 apu_set_register(chip, apu, 7, size);
1056
1057 /* clear effects/env.. */
1058 apu_set_register(chip, apu, 8, 0x0000);
1059 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1060 apu_set_register(chip, apu, 9, 0xD000);
1061
1062 /* clear routing stuff */
1063 apu_set_register(chip, apu, 11, 0x0000);
1064 /* dma on, no envelopes, filter to all 1s) */
1065 apu_set_register(chip, apu, 0, 0x400F);
1066
1067 if (es->fmt & ESS_FMT_16BIT)
1068 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1069 else
1070 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1071
1072 if (es->fmt & ESS_FMT_STEREO) {
1073 /* set panning: left or right */
1074 /* Check: different panning. On my Canyon 3D Chipset the
1075 Channels are swapped. I don't know, about the output
1076 to the SPDif Link. Perhaps you have to change this
1077 and not the APU Regs 4-5. */
1078 apu_set_register(chip, apu, 10,
1079 0x8F00 | (channel ? 0 : 0x10));
1080 es->apu_mode[channel] += 1; /* stereo */
1081 } else
1082 apu_set_register(chip, apu, 10, 0x8F08);
1083 }
1084
1085 spin_lock_irqsave(&chip->reg_lock, flags);
1086 /* clear WP interrupts */
1087 outw(1, chip->io_port + 0x04);
1088 /* enable WP ints */
1089 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1090 spin_unlock_irqrestore(&chip->reg_lock, flags);
1091
1092 freq = runtime->rate;
1093 /* set frequency */
1094 if (freq > 48000)
1095 freq = 48000;
1096 if (freq < 4000)
1097 freq = 4000;
1098
1099 /* hmmm.. */
1100 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1101 freq >>= 1;
1102
1103 freq = snd_es1968_compute_rate(chip, freq);
1104
1105 /* Load the frequency, turn on 6dB */
1106 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1107 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1108}
1109
1110
969165a8 1111static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1da177e4
LT		 1112 unsigned int pa, unsigned int bsize,
1113 int mode, int route)
1114{
1115 int i, apu = es->apu[channel];
1116
1117 es->apu_mode[channel] = mode;
1118
1119 /* set the wavecache control reg */
1120 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1121
1122 /* Offset to PCMBAR */
1123 pa -= chip->dma.addr;
1124 pa >>= 1; /* words */
1125
1126 /* base offset of dma calcs when reading the pointer
1127 on this left one */
1128 es->base[channel] = pa & 0xFFFF;
1129 pa |= 0x00400000; /* bit 22 -> System RAM */
1130
1131 /* Begin loading the APU */
1132 for (i = 0; i < 16; i++)
1133 apu_set_register(chip, apu, i, 0x0000);
1134
1135 /* need to enable subgroups.. and we should probably
1136 have different groups for different /dev/dsps.. */
1137 apu_set_register(chip, apu, 2, 0x8);
1138
1139 /* Load the buffer into the wave engine */
1140 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1141 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1142 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1143 apu_set_register(chip, apu, 7, bsize);
1144 /* clear effects/env.. */
1145 apu_set_register(chip, apu, 8, 0x00F0);
1146 /* amplitude now? sure. why not. */
1147 apu_set_register(chip, apu, 9, 0x0000);
1148 /* set filter tune, radius, polar pan */
1149 apu_set_register(chip, apu, 10, 0x8F08);
1150 /* route input */
1151 apu_set_register(chip, apu, 11, route);
1152 /* dma on, no envelopes, filter to all 1s) */
1153 apu_set_register(chip, apu, 0, 0x400F);
1154}
1155
969165a8
TI		 1156static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1157 struct snd_pcm_runtime *runtime)
1da177e4
LT		 1158{
1159 int size;
1160 u32 freq;
1161 unsigned long flags;
1162
1163 size = es->dma_size >> es->wav_shift;
1164
1165 /* APU assignments:
1166 0 = mono/left SRC
1167 1 = right SRC
1168 2 = mono/left Input Mixer
1169 3 = right Input Mixer
1170 */
1171 /* data seems to flow from the codec, through an apu into
1172 the 'mixbuf' bit of page, then through the SRC apu
1173 and out to the real 'buffer'. ok. sure. */
1174
1175 /* input mixer (left/mono) */
1176 /* parallel in crap, see maestro reg 0xC [8-11] */
1177 init_capture_apu(chip, es, 2,
1178 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1179 ESM_APU_INPUTMIXER, 0x14);
1180 /* SRC (left/mono); get input from inputing apu */
1181 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1182 ESM_APU_SRCONVERTOR, es->apu[2]);
1183 if (es->fmt & ESS_FMT_STEREO) {
1184 /* input mixer (right) */
1185 init_capture_apu(chip, es, 3,
1186 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1187 ESM_MIXBUF_SIZE/4, /* in words */
1188 ESM_APU_INPUTMIXER, 0x15);
1189 /* SRC (right) */
1190 init_capture_apu(chip, es, 1,
1191 es->memory->buf.addr + size*2, size,
1192 ESM_APU_SRCONVERTOR, es->apu[3]);
1193 }
1194
1195 freq = runtime->rate;
1196 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1197 if (freq > 47999)
1198 freq = 47999;
1199 if (freq < 4000)
1200 freq = 4000;
1201
1202 freq = snd_es1968_compute_rate(chip, freq);
1203
1204 /* Load the frequency, turn on 6dB */
1205 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1206 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1207
1208 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1209 freq = 0x10000;
1210 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1211 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1212
1213 spin_lock_irqsave(&chip->reg_lock, flags);
1214 /* clear WP interrupts */
1215 outw(1, chip->io_port + 0x04);
1216 /* enable WP ints */
1217 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1218 spin_unlock_irqrestore(&chip->reg_lock, flags);
1219}
1220
1221/*******************
1222 * ALSA Interface *
1223 *******************/
1224
969165a8 1225static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 1226{
969165a8
TI		 1227 struct es1968 *chip = snd_pcm_substream_chip(substream);
1228 struct snd_pcm_runtime *runtime = substream->runtime;
1229 struct esschan *es = runtime->private_data;
1da177e4
LT		 1230
1231 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1232 es->frag_size = snd_pcm_lib_period_bytes(substream);
1233
1234 es->wav_shift = 1; /* maestro handles always 16bit */
1235 es->fmt = 0;
1236 if (snd_pcm_format_width(runtime->format) == 16)
1237 es->fmt |= ESS_FMT_16BIT;
1238 if (runtime->channels > 1) {
1239 es->fmt |= ESS_FMT_STEREO;
1240 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1241 es->wav_shift++;
1242 }
1243 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1244
1245 switch (es->mode) {
1246 case ESM_MODE_PLAY:
1247 snd_es1968_playback_setup(chip, es, runtime);
1248 break;
1249 case ESM_MODE_CAPTURE:
1250 snd_es1968_capture_setup(chip, es, runtime);
1251 break;
1252 }
1253
1254 return 0;
1255}
1256
969165a8 1257static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 1258{
969165a8
TI		 1259 struct es1968 *chip = snd_pcm_substream_chip(substream);
1260 struct esschan *es = substream->runtime->private_data;
1da177e4
LT		 1261
1262 spin_lock(&chip->substream_lock);
1263 switch (cmd) {
1264 case SNDRV_PCM_TRIGGER_START:
1265 case SNDRV_PCM_TRIGGER_RESUME:
1266 if (es->running)
1267 break;
1268 snd_es1968_bob_inc(chip, es->bob_freq);
1269 es->count = 0;
1270 es->hwptr = 0;
1271 snd_es1968_pcm_start(chip, es);
1272 es->running = 1;
1273 break;
1274 case SNDRV_PCM_TRIGGER_STOP:
1275 case SNDRV_PCM_TRIGGER_SUSPEND:
1276 if (! es->running)
1277 break;
1278 snd_es1968_pcm_stop(chip, es);
1279 es->running = 0;
1280 snd_es1968_bob_dec(chip);
1281 break;
1282 }
1283 spin_unlock(&chip->substream_lock);
1284 return 0;
1285}
1286
969165a8 1287static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1288{
969165a8
TI		 1289 struct es1968 *chip = snd_pcm_substream_chip(substream);
1290 struct esschan *es = substream->runtime->private_data;
1da177e4
LT		 1291 unsigned int ptr;
1292
1293 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1294
1295 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1296}
1297
969165a8 1298static struct snd_pcm_hardware snd_es1968_playback = {
1da177e4
LT		 1299 .info = (SNDRV_PCM_INFO_MMAP |
1300 SNDRV_PCM_INFO_MMAP_VALID |
1301 SNDRV_PCM_INFO_INTERLEAVED |
1302 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1303 /*SNDRV_PCM_INFO_PAUSE |*/
1304 SNDRV_PCM_INFO_RESUME),
1305 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1306 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1307 .rate_min = 4000,
1308 .rate_max = 48000,
1309 .channels_min = 1,
1310 .channels_max = 2,
1311 .buffer_bytes_max = 65536,
1312 .period_bytes_min = 256,
1313 .period_bytes_max = 65536,
1314 .periods_min = 1,
1315 .periods_max = 1024,
1316 .fifo_size = 0,
1317};
1318
969165a8 1319static struct snd_pcm_hardware snd_es1968_capture = {
1da177e4
LT		 1320 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1321 SNDRV_PCM_INFO_MMAP |
1322 SNDRV_PCM_INFO_MMAP_VALID |
1323 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1324 /*SNDRV_PCM_INFO_PAUSE |*/
1325 SNDRV_PCM_INFO_RESUME),
1326 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1327 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1328 .rate_min = 4000,
1329 .rate_max = 48000,
1330 .channels_min = 1,
1331 .channels_max = 2,
1332 .buffer_bytes_max = 65536,
1333 .period_bytes_min = 256,
1334 .period_bytes_max = 65536,
1335 .periods_min = 1,
1336 .periods_max = 1024,
1337 .fifo_size = 0,
1338};
1339
1340/* *************************
1341 * DMA memory management *
1342 *************************/
1343
1344/* Because the Maestro can only take addresses relative to the PCM base address
1345 register :( */
1346
969165a8 1347static int calc_available_memory_size(struct es1968 *chip)
1da177e4 1348{
1da177e4 1349 int max_size = 0;
50f47ff1
MK		 1350 struct esm_memory *buf;
1351
62932df8 1352 mutex_lock(&chip->memory_mutex);
50f47ff1 1353 list_for_each_entry(buf, &chip->buf_list, list) {
1da177e4
LT		 1354 if (buf->empty && buf->buf.bytes > max_size)
1355 max_size = buf->buf.bytes;
1356 }
62932df8 1357 mutex_unlock(&chip->memory_mutex);
1da177e4
LT		 1358 if (max_size >= 128*1024)
1359 max_size = 127*1024;
1360 return max_size;
1361}
1362
1363/* allocate a new memory chunk with the specified size */
969165a8 1364static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1da177e4 1365{
969165a8 1366 struct esm_memory *buf;
50f47ff1 1367
7ab39926 1368 size = ALIGN(size, ESM_MEM_ALIGN);
62932df8 1369 mutex_lock(&chip->memory_mutex);
50f47ff1 1370 list_for_each_entry(buf, &chip->buf_list, list) {
1da177e4
LT		 1371 if (buf->empty && buf->buf.bytes >= size)
1372 goto __found;
1373 }
62932df8 1374 mutex_unlock(&chip->memory_mutex);
1da177e4
LT		 1375 return NULL;
1376
1377__found:
1378 if (buf->buf.bytes > size) {
969165a8 1379 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1da177e4 1380 if (chunk == NULL) {
62932df8 1381 mutex_unlock(&chip->memory_mutex);
1da177e4
LT		 1382 return NULL;
1383 }
1384 chunk->buf = buf->buf;
1385 chunk->buf.bytes -= size;
1386 chunk->buf.area += size;
1387 chunk->buf.addr += size;
1388 chunk->empty = 1;
1389 buf->buf.bytes = size;
1390 list_add(&chunk->list, &buf->list);
1391 }
1392 buf->empty = 0;
62932df8 1393 mutex_unlock(&chip->memory_mutex);
1da177e4
LT		 1394 return buf;
1395}
1396
1397/* free a memory chunk */
969165a8 1398static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1da177e4 1399{
969165a8 1400 struct esm_memory *chunk;
1da177e4 1401
62932df8 1402 mutex_lock(&chip->memory_mutex);
1da177e4
LT		 1403 buf->empty = 1;
1404 if (buf->list.prev != &chip->buf_list) {
969165a8 1405 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1da177e4
LT		 1406 if (chunk->empty) {
1407 chunk->buf.bytes += buf->buf.bytes;
1408 list_del(&buf->list);
1409 kfree(buf);
1410 buf = chunk;
1411 }
1412 }
1413 if (buf->list.next != &chip->buf_list) {
969165a8 1414 chunk = list_entry(buf->list.next, struct esm_memory, list);
1da177e4
LT		 1415 if (chunk->empty) {
1416 buf->buf.bytes += chunk->buf.bytes;
1417 list_del(&chunk->list);
1418 kfree(chunk);
1419 }
1420 }
62932df8 1421 mutex_unlock(&chip->memory_mutex);
1da177e4
LT		 1422}
1423
969165a8 1424static void snd_es1968_free_dmabuf(struct es1968 *chip)
1da177e4
LT		 1425{
1426 struct list_head *p;
1427
1428 if (! chip->dma.area)
1429 return;
1430 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1431 while ((p = chip->buf_list.next) != &chip->buf_list) {
969165a8 1432 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1da177e4
LT		 1433 list_del(p);
1434 kfree(chunk);
1435 }
1436}
1437
1438static int __devinit
969165a8 1439snd_es1968_init_dmabuf(struct es1968 *chip)
1da177e4
LT		 1440{
1441 int err;
969165a8 1442 struct esm_memory *chunk;
1da177e4
LT		 1443
1444 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1445 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1446 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1447 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1448 snd_dma_pci_data(chip->pci),
1449 chip->total_bufsize, &chip->dma);
1450 if (err < 0 || ! chip->dma.area) {
99b359ba 1451 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1da177e4
LT		 1452 chip->total_bufsize);
1453 return -ENOMEM;
1454 }
1455 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1456 snd_dma_free_pages(&chip->dma);
99b359ba 1457 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1da177e4
LT		 1458 return -ENOMEM;
1459 }
1460 }
1461
1462 INIT_LIST_HEAD(&chip->buf_list);
1463 /* allocate an empty chunk */
1464 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1465 if (chunk == NULL) {
1466 snd_es1968_free_dmabuf(chip);
1467 return -ENOMEM;
1468 }
1469 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1470 chunk->buf = chip->dma;
1471 chunk->buf.area += ESM_MEM_ALIGN;
1472 chunk->buf.addr += ESM_MEM_ALIGN;
1473 chunk->buf.bytes -= ESM_MEM_ALIGN;
1474 chunk->empty = 1;
1475 list_add(&chunk->list, &chip->buf_list);
1476
1477 return 0;
1478}
1479
1480/* setup the dma_areas */
1481/* buffer is extracted from the pre-allocated memory chunk */
969165a8
TI		 1482static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1483 struct snd_pcm_hw_params *hw_params)
1da177e4 1484{
969165a8
TI		 1485 struct es1968 *chip = snd_pcm_substream_chip(substream);
1486 struct snd_pcm_runtime *runtime = substream->runtime;
1487 struct esschan *chan = runtime->private_data;
1da177e4
LT		 1488 int size = params_buffer_bytes(hw_params);
1489
1490 if (chan->memory) {
1491 if (chan->memory->buf.bytes >= size) {
1492 runtime->dma_bytes = size;
1493 return 0;
1494 }
1495 snd_es1968_free_memory(chip, chan->memory);
1496 }
1497 chan->memory = snd_es1968_new_memory(chip, size);
1498 if (chan->memory == NULL) {
1499 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1500 return -ENOMEM;
1501 }
1502 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1503 return 1; /* area was changed */
1504}
1505
1506/* remove dma areas if allocated */
969165a8 1507static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1da177e4 1508{
969165a8
TI		 1509 struct es1968 *chip = snd_pcm_substream_chip(substream);
1510 struct snd_pcm_runtime *runtime = substream->runtime;
1511 struct esschan *chan;
1da177e4
LT		 1512
1513 if (runtime->private_data == NULL)
1514 return 0;
1515 chan = runtime->private_data;
1516 if (chan->memory) {
1517 snd_es1968_free_memory(chip, chan->memory);
1518 chan->memory = NULL;
1519 }
1520 return 0;
1521}
1522
1523
1524/*
1525 * allocate APU pair
1526 */
969165a8 1527static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1da177e4
LT		 1528{
1529 int apu;
1530
1531 for (apu = 0; apu < NR_APUS; apu += 2) {
1532 if (chip->apu[apu] == ESM_APU_FREE &&
1533 chip->apu[apu + 1] == ESM_APU_FREE) {
1534 chip->apu[apu] = chip->apu[apu + 1] = type;
1535 return apu;
1536 }
1537 }
1538 return -EBUSY;
1539}
1540
1541/*
1542 * release APU pair
1543 */
969165a8 1544static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1da177e4
LT		 1545{
1546 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1547}
1548
1549
1550/******************
1551 * PCM open/close *
1552 ******************/
1553
969165a8 1554static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1da177e4 1555{
969165a8
TI		 1556 struct es1968 *chip = snd_pcm_substream_chip(substream);
1557 struct snd_pcm_runtime *runtime = substream->runtime;
1558 struct esschan *es;
1da177e4
LT		 1559 int apu1;
1560
1561 /* search 2 APUs */
1562 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1563 if (apu1 < 0)
1564 return apu1;
1565
e560d8d8 1566 es = kzalloc(sizeof(*es), GFP_KERNEL);
1da177e4
LT		 1567 if (!es) {
1568 snd_es1968_free_apu_pair(chip, apu1);
1569 return -ENOMEM;
1570 }
1571
1572 es->apu[0] = apu1;
1573 es->apu[1] = apu1 + 1;
1574 es->apu_mode[0] = 0;
1575 es->apu_mode[1] = 0;
1576 es->running = 0;
1577 es->substream = substream;
1578 es->mode = ESM_MODE_PLAY;
1579
1580 runtime->private_data = es;
1581 runtime->hw = snd_es1968_playback;
1582 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1583 calc_available_memory_size(chip);
b942cf81 1584
1da177e4
LT		 1585 spin_lock_irq(&chip->substream_lock);
1586 list_add(&es->list, &chip->substream_list);
1587 spin_unlock_irq(&chip->substream_lock);
1588
1589 return 0;
1590}
1591
969165a8 1592static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1da177e4 1593{
969165a8
TI		 1594 struct snd_pcm_runtime *runtime = substream->runtime;
1595 struct es1968 *chip = snd_pcm_substream_chip(substream);
1596 struct esschan *es;
1da177e4
LT		 1597 int apu1, apu2;
1598
1599 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1600 if (apu1 < 0)
1601 return apu1;
1602 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1603 if (apu2 < 0) {
1604 snd_es1968_free_apu_pair(chip, apu1);
1605 return apu2;
1606 }
1607
e560d8d8 1608 es = kzalloc(sizeof(*es), GFP_KERNEL);
1da177e4
LT		 1609 if (!es) {
1610 snd_es1968_free_apu_pair(chip, apu1);
1611 snd_es1968_free_apu_pair(chip, apu2);
1612 return -ENOMEM;
1613 }
1614
1615 es->apu[0] = apu1;
1616 es->apu[1] = apu1 + 1;
1617 es->apu[2] = apu2;
1618 es->apu[3] = apu2 + 1;
1619 es->apu_mode[0] = 0;
1620 es->apu_mode[1] = 0;
1621 es->apu_mode[2] = 0;
1622 es->apu_mode[3] = 0;
1623 es->running = 0;
1624 es->substream = substream;
1625 es->mode = ESM_MODE_CAPTURE;
1626
1627 /* get mixbuffer */
1628 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1629 snd_es1968_free_apu_pair(chip, apu1);
1630 snd_es1968_free_apu_pair(chip, apu2);
1631 kfree(es);
1632 return -ENOMEM;
1633 }
1634 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1635
1636 runtime->private_data = es;
1637 runtime->hw = snd_es1968_capture;
1638 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1639 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
b942cf81
RH		 1640 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1641
1da177e4
LT		 1642 spin_lock_irq(&chip->substream_lock);
1643 list_add(&es->list, &chip->substream_list);
1644 spin_unlock_irq(&chip->substream_lock);
1645
1646 return 0;
1647}
1648
969165a8 1649static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1da177e4 1650{
969165a8
TI		 1651 struct es1968 *chip = snd_pcm_substream_chip(substream);
1652 struct esschan *es;
1da177e4
LT		 1653
1654 if (substream->runtime->private_data == NULL)
1655 return 0;
1656 es = substream->runtime->private_data;
1657 spin_lock_irq(&chip->substream_lock);
1658 list_del(&es->list);
1659 spin_unlock_irq(&chip->substream_lock);
1660 snd_es1968_free_apu_pair(chip, es->apu[0]);
1661 kfree(es);
1662
1663 return 0;
1664}
1665
969165a8 1666static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1da177e4 1667{
969165a8
TI		 1668 struct es1968 *chip = snd_pcm_substream_chip(substream);
1669 struct esschan *es;
1da177e4
LT		 1670
1671 if (substream->runtime->private_data == NULL)
1672 return 0;
1673 es = substream->runtime->private_data;
1674 spin_lock_irq(&chip->substream_lock);
1675 list_del(&es->list);
1676 spin_unlock_irq(&chip->substream_lock);
1677 snd_es1968_free_memory(chip, es->mixbuf);
1678 snd_es1968_free_apu_pair(chip, es->apu[0]);
1679 snd_es1968_free_apu_pair(chip, es->apu[2]);
1680 kfree(es);
1681
1682 return 0;
1683}
1684
969165a8 1685static struct snd_pcm_ops snd_es1968_playback_ops = {
1da177e4
LT		 1686 .open = snd_es1968_playback_open,
1687 .close = snd_es1968_playback_close,
1688 .ioctl = snd_pcm_lib_ioctl,
1689 .hw_params = snd_es1968_hw_params,
1690 .hw_free = snd_es1968_hw_free,
1691 .prepare = snd_es1968_pcm_prepare,
1692 .trigger = snd_es1968_pcm_trigger,
1693 .pointer = snd_es1968_pcm_pointer,
1694};
1695
969165a8 1696static struct snd_pcm_ops snd_es1968_capture_ops = {
1da177e4
LT		 1697 .open = snd_es1968_capture_open,
1698 .close = snd_es1968_capture_close,
1699 .ioctl = snd_pcm_lib_ioctl,
1700 .hw_params = snd_es1968_hw_params,
1701 .hw_free = snd_es1968_hw_free,
1702 .prepare = snd_es1968_pcm_prepare,
1703 .trigger = snd_es1968_pcm_trigger,
1704 .pointer = snd_es1968_pcm_pointer,
1705};
1706
1707
1708/*
1709 * measure clock
1710 */
1711#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1712
969165a8 1713static void __devinit es1968_measure_clock(struct es1968 *chip)
1da177e4
LT		 1714{
1715 int i, apu;
1716 unsigned int pa, offset, t;
969165a8 1717 struct esm_memory *memory;
1da177e4
LT		 1718 struct timeval start_time, stop_time;
1719
1720 if (chip->clock == 0)
1721 chip->clock = 48000; /* default clock value */
1722
1723 /* search 2 APUs (although one apu is enough) */
1724 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
99b359ba 1725 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1da177e4
LT		 1726 return;
1727 }
1728 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
99b359ba 1729 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1da177e4
LT		 1730 snd_es1968_free_apu_pair(chip, apu);
1731 return;
1732 }
1733
1734 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1735
1736 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1737
1738 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1739 pa |= 0x00400000; /* System RAM (Bit 22) */
1740
1741 /* initialize apu */
1742 for (i = 0; i < 16; i++)
1743 apu_set_register(chip, apu, i, 0x0000);
1744
1745 apu_set_register(chip, apu, 0, 0x400f);
1746 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1747 apu_set_register(chip, apu, 5, pa & 0xffff);
1748 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1749 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1750 apu_set_register(chip, apu, 8, 0x0000);
1751 apu_set_register(chip, apu, 9, 0xD000);
1752 apu_set_register(chip, apu, 10, 0x8F08);
1753 apu_set_register(chip, apu, 11, 0x0000);
1754 spin_lock_irq(&chip->reg_lock);
1755 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1756 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1757 spin_unlock_irq(&chip->reg_lock);
1758
1759 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1760
1761 chip->in_measurement = 1;
1762 chip->measure_apu = apu;
1763 spin_lock_irq(&chip->reg_lock);
1764 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1765 __apu_set_register(chip, apu, 5, pa & 0xffff);
1766 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1767 do_gettimeofday(&start_time);
1768 spin_unlock_irq(&chip->reg_lock);
ef21ca24 1769 msleep(50);
1da177e4
LT		 1770 spin_lock_irq(&chip->reg_lock);
1771 offset = __apu_get_register(chip, apu, 5);
1772 do_gettimeofday(&stop_time);
1773 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1774 snd_es1968_bob_dec(chip);
1775 chip->in_measurement = 0;
1776 spin_unlock_irq(&chip->reg_lock);
1777
1778 /* check the current position */
1779 offset -= (pa & 0xffff);
1780 offset &= 0xfffe;
1781 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1782
1783 t = stop_time.tv_sec - start_time.tv_sec;
1784 t *= 1000000;
1785 if (stop_time.tv_usec < start_time.tv_usec)
1786 t -= start_time.tv_usec - stop_time.tv_usec;
1787 else
1788 t += stop_time.tv_usec - start_time.tv_usec;
1789 if (t == 0) {
99b359ba 1790 snd_printk(KERN_ERR "?? calculation error..\n");
1da177e4
LT		 1791 } else {
1792 offset *= 1000;
1793 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1794 if (offset < 47500 || offset > 48500) {
1795 if (offset >= 40000 && offset <= 50000)
1796 chip->clock = (chip->clock * offset) / 48000;
1797 }
1798 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1799 }
1800 snd_es1968_free_memory(chip, memory);
1801 snd_es1968_free_apu_pair(chip, apu);
1802}
1803
1804
1805/*
1806 */
1807
969165a8 1808static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1da177e4 1809{
969165a8 1810 struct es1968 *esm = pcm->private_data;
1da177e4
LT		 1811 snd_es1968_free_dmabuf(esm);
1812 esm->pcm = NULL;
1813}
1814
1815static int __devinit
969165a8 1816snd_es1968_pcm(struct es1968 *chip, int device)
1da177e4 1817{
969165a8 1818 struct snd_pcm *pcm;
1da177e4
LT		 1819 int err;
1820
1821 /* get DMA buffer */
1822 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1823 return err;
1824
1825 /* set PCMBAR */
1826 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1827 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1828 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1829 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1830
1831 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1832 chip->playback_streams,
1833 chip->capture_streams, &pcm)) < 0)
1834 return err;
1835
1836 pcm->private_data = chip;
1837 pcm->private_free = snd_es1968_pcm_free;
1838
1839 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1840 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1841
1842 pcm->info_flags = 0;
1843
1844 strcpy(pcm->name, "ESS Maestro");
1845
1846 chip->pcm = pcm;
1847
1848 return 0;
1849}
f24bfa53
AM		 1850/*
1851 * suppress jitter on some maestros when playing stereo
1852 */
1853static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es)
1854{
1855 unsigned int cp1;
1856 unsigned int cp2;
1857 unsigned int diff;
1858
1859 cp1 = __apu_get_register(chip, 0, 5);
1860 cp2 = __apu_get_register(chip, 1, 5);
1861 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1862
66c9aa60 1863 if (diff > 1)
f24bfa53 1864 __maestro_write(chip, IDR0_DATA_PORT, cp1);
f24bfa53 1865}
1da177e4
LT		 1866
1867/*
1868 * update pointer
1869 */
969165a8 1870static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1da177e4
LT		 1871{
1872 unsigned int hwptr;
1873 unsigned int diff;
969165a8 1874 struct snd_pcm_substream *subs = es->substream;
1da177e4
LT		 1875
1876 if (subs == NULL || !es->running)
1877 return;
1878
1879 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1880 hwptr %= es->dma_size;
1881
1882 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1883
1884 es->hwptr = hwptr;
1885 es->count += diff;
1886
1887 if (es->count > es->frag_size) {
1888 spin_unlock(&chip->substream_lock);
1889 snd_pcm_period_elapsed(subs);
1890 spin_lock(&chip->substream_lock);
1891 es->count %= es->frag_size;
1892 }
1893}
1894
5a5e02e5
HG		 1895/* The hardware volume works by incrementing / decrementing 2 counters
1896 (without wrap around) in response to volume button presses and then
1897 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1898 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1da177e4
LT		 1899static void es1968_update_hw_volume(unsigned long private_data)
1900{
969165a8 1901 struct es1968 *chip = (struct es1968 *) private_data;
1da177e4 1902 int x, val;
5a5e02e5 1903#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 1904 unsigned long flags;
5a5e02e5 1905#endif
1da177e4
LT		 1906
1907 /* Figure out which volume control button was pushed,
1908 based on differences from the default register
1909 values. */
679e28ee 1910 x = inb(chip->io_port + 0x1c) & 0xee;
1da177e4
LT		 1911 /* Reset the volume control registers. */
1912 outb(0x88, chip->io_port + 0x1c);
1913 outb(0x88, chip->io_port + 0x1d);
1914 outb(0x88, chip->io_port + 0x1e);
1915 outb(0x88, chip->io_port + 0x1f);
1916
1917 if (chip->in_suspend)
1918 return;
1919
5a5e02e5 1920#ifndef CONFIG_SND_ES1968_INPUT
1da177e4
LT		 1921 if (! chip->master_switch || ! chip->master_volume)
1922 return;
1923
1924 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1925 spin_lock_irqsave(&chip->ac97_lock, flags);
1926 val = chip->ac97->regs[AC97_MASTER];
679e28ee
VS		 1927 switch (x) {
1928 case 0x88:
1da177e4
LT		 1929 /* mute */
1930 val ^= 0x8000;
1931 chip->ac97->regs[AC97_MASTER] = val;
1932 outw(val, chip->io_port + ESM_AC97_DATA);
1933 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1934 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1935 &chip->master_switch->id);
679e28ee
VS		 1936 break;
1937 case 0xaa:
1938 /* volume up */
1939 if ((val & 0x7f) > 0)
1940 val--;
1941 if ((val & 0x7f00) > 0)
1942 val -= 0x0100;
1943 chip->ac97->regs[AC97_MASTER] = val;
1944 outw(val, chip->io_port + ESM_AC97_DATA);
1945 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1946 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1947 &chip->master_volume->id);
1948 break;
1949 case 0x66:
1950 /* volume down */
1951 if ((val & 0x7f) < 0x1f)
1952 val++;
1953 if ((val & 0x7f00) < 0x1f00)
1954 val += 0x0100;
1da177e4
LT		 1955 chip->ac97->regs[AC97_MASTER] = val;
1956 outw(val, chip->io_port + ESM_AC97_DATA);
1957 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1958 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1959 &chip->master_volume->id);
679e28ee 1960 break;
1da177e4
LT		 1961 }
1962 spin_unlock_irqrestore(&chip->ac97_lock, flags);
5a5e02e5
HG		 1963#else
1964 if (!chip->input_dev)
1965 return;
1966
1967 val = 0;
1968 switch (x) {
1969 case 0x88:
1970 /* The counters have not changed, yet we've received a HV
1971 interrupt. According to tests run by various people this
1972 happens when pressing the mute button. */
1973 val = KEY_MUTE;
1974 break;
1975 case 0xaa:
1976 /* counters increased by 1 -> volume up */
1977 val = KEY_VOLUMEUP;
1978 break;
1979 case 0x66:
1980 /* counters decreased by 1 -> volume down */
1981 val = KEY_VOLUMEDOWN;
1982 break;
1983 }
1984
1985 if (val) {
1986 input_report_key(chip->input_dev, val, 1);
1987 input_sync(chip->input_dev);
1988 input_report_key(chip->input_dev, val, 0);
1989 input_sync(chip->input_dev);
1990 }
1991#endif
1da177e4
LT		 1992}
1993
1994/*
1995 * interrupt handler
1996 */
7d12e780 1997static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1da177e4 1998{
969165a8 1999 struct es1968 *chip = dev_id;
1da177e4
LT		 2000 u32 event;
2001
2002 if (!(event = inb(chip->io_port + 0x1A)))
2003 return IRQ_NONE;
2004
2005 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
2006
2007 if (event & ESM_HWVOL_IRQ)
5a5e02e5
HG		 2008#ifdef CONFIG_SND_ES1968_INPUT
2009 es1968_update_hw_volume((unsigned long)chip);
2010#else
1f04128a 2011 tasklet_schedule(&chip->hwvol_tq); /* we'll do this later */
5a5e02e5 2012#endif
1da177e4
LT		 2013
2014 /* else ack 'em all, i imagine */
2015 outb(0xFF, chip->io_port + 0x1A);
2016
2017 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
7d12e780 2018 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1da177e4
LT		 2019 }
2020
2021 if (event & ESM_SOUND_IRQ) {
50f47ff1 2022 struct esschan *es;
1da177e4 2023 spin_lock(&chip->substream_lock);
50f47ff1 2024 list_for_each_entry(es, &chip->substream_list, list) {
f24bfa53 2025 if (es->running) {
1da177e4 2026 snd_es1968_update_pcm(chip, es);
f24bfa53
AM		 2027 if (es->fmt & ESS_FMT_STEREO)
2028 snd_es1968_suppress_jitter(chip, es);
2029 }
1da177e4
LT		 2030 }
2031 spin_unlock(&chip->substream_lock);
2032 if (chip->in_measurement) {
2033 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
2034 if (curp < chip->measure_lastpos)
2035 chip->measure_count++;
2036 chip->measure_lastpos = curp;
2037 }
2038 }
2039
2040 return IRQ_HANDLED;
2041}
2042
2043/*
2044 * Mixer stuff
2045 */
2046
2047static int __devinit
969165a8 2048snd_es1968_mixer(struct es1968 *chip)
1da177e4 2049{
969165a8
TI		 2050 struct snd_ac97_bus *pbus;
2051 struct snd_ac97_template ac97;
5a5e02e5 2052#ifndef CONFIG_SND_ES1968_INPUT
3463d8fa 2053 struct snd_ctl_elem_id elem_id;
5a5e02e5 2054#endif
1da177e4 2055 int err;
969165a8 2056 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 2057 .write = snd_es1968_ac97_write,
2058 .read = snd_es1968_ac97_read,
2059 };
2060
2061 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2062 return err;
2063 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2064
2065 memset(&ac97, 0, sizeof(ac97));
2066 ac97.private_data = chip;
2067 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2068 return err;
2069
5a5e02e5 2070#ifndef CONFIG_SND_ES1968_INPUT
1da177e4 2071 /* attach master switch / volumes for h/w volume control */
3463d8fa
HH		 2072 memset(&elem_id, 0, sizeof(elem_id));
2073 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2074 strcpy(elem_id.name, "Master Playback Switch");
2075 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2076 memset(&elem_id, 0, sizeof(elem_id));
2077 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2078 strcpy(elem_id.name, "Master Playback Volume");
2079 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
5a5e02e5 2080#endif
1da177e4
LT		 2081
2082 return 0;
2083}
2084
2085/*
2086 * reset ac97 codec
2087 */
2088
969165a8 2089static void snd_es1968_ac97_reset(struct es1968 *chip)
1da177e4
LT		 2090{
2091 unsigned long ioaddr = chip->io_port;
2092
2093 unsigned short save_ringbus_a;
2094 unsigned short save_68;
2095 unsigned short w;
2096 unsigned int vend;
2097
2098 /* save configuration */
2099 save_ringbus_a = inw(ioaddr + 0x36);
2100
2101 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2102 /* set command/status address i/o to 1st codec */
2103 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2104 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2105
2106 /* disable ac link */
2107 outw(0x0000, ioaddr + 0x36);
2108 save_68 = inw(ioaddr + 0x68);
2109 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2110 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2111 if (w & 1)
2112 save_68 |= 0x10;
2113 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2114 outw(0x0001, ioaddr + 0x68); /* gpio write */
2115 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2116 udelay(20);
2117 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
ef21ca24 2118 msleep(20);
1da177e4
LT		 2119
2120 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2121 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2122 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2123 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2124
2125 /* now the second codec */
2126 /* disable ac link */
2127 outw(0x0000, ioaddr + 0x36);
2128 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2129 save_68 = inw(ioaddr + 0x68);
2130 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2131 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2132 udelay(20);
2133 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
ef21ca24 2134 msleep(500);
1da177e4
LT		 2135 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2136 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2137 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2138
2139#if 0 /* the loop here needs to be much better if we want it.. */
99b359ba 2140 snd_printk(KERN_INFO "trying software reset\n");
1da177e4
LT		 2141 /* try and do a software reset */
2142 outb(0x80 | 0x7c, ioaddr + 0x30);
2143 for (w = 0;; w++) {
2144 if ((inw(ioaddr + 0x30) & 1) == 0) {
2145 if (inb(ioaddr + 0x32) != 0)
2146 break;
2147
2148 outb(0x80 | 0x7d, ioaddr + 0x30);
2149 if (((inw(ioaddr + 0x30) & 1) == 0)
2150 && (inb(ioaddr + 0x32) != 0))
2151 break;
2152 outb(0x80 | 0x7f, ioaddr + 0x30);
2153 if (((inw(ioaddr + 0x30) & 1) == 0)
2154 && (inb(ioaddr + 0x32) != 0))
2155 break;
2156 }
2157
2158 if (w > 10000) {
2159 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
ef21ca24 2160 msleep(500); /* oh my.. */
1da177e4
LT		 2161 outb(inb(ioaddr + 0x37) & ~0x08,
2162 ioaddr + 0x37);
2163 udelay(1);
2164 outw(0x80, ioaddr + 0x30);
2165 for (w = 0; w < 10000; w++) {
2166 if ((inw(ioaddr + 0x30) & 1) == 0)
2167 break;
2168 }
2169 }
2170 }
2171#endif
2172 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2173 /* turn on external amp? */
2174 outw(0xf9ff, ioaddr + 0x64);
2175 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2176 outw(0x0209, ioaddr + 0x60);
2177 }
2178
2179 /* restore.. */
2180 outw(save_ringbus_a, ioaddr + 0x36);
2181
2182 /* Turn on the 978 docking chip.
2183 First frob the "master output enable" bit,
2184 then set most of the playback volume control registers to max. */
2185 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2186 outb(0xff, ioaddr+0xc3);
2187 outb(0xff, ioaddr+0xc4);
2188 outb(0xff, ioaddr+0xc6);
2189 outb(0xff, ioaddr+0xc8);
2190 outb(0x3f, ioaddr+0xcf);
2191 outb(0x3f, ioaddr+0xd0);
2192}
2193
969165a8 2194static void snd_es1968_reset(struct es1968 *chip)
1da177e4
LT		 2195{
2196 /* Reset */
2197 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2198 chip->io_port + ESM_PORT_HOST_IRQ);
2199 udelay(10);
2200 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2201 udelay(10);
2202}
2203
1da177e4
LT		 2204/*
2205 * initialize maestro chip
2206 */
969165a8 2207static void snd_es1968_chip_init(struct es1968 *chip)
1da177e4
LT		 2208{
2209 struct pci_dev *pci = chip->pci;
2210 int i;
2211 unsigned long iobase = chip->io_port;
2212 u16 w;
2213 u32 n;
2214
2215 /* We used to muck around with pci config space that
2216 * we had no business messing with. We don't know enough
2217 * about the machine to know which DMA mode is appropriate,
2218 * etc. We were guessing wrong on some machines and making
2219 * them unhappy. We now trust in the BIOS to do things right,
2220 * which almost certainly means a new host of problems will
2221 * arise with broken BIOS implementations. screw 'em.
2222 * We're already intolerant of machines that don't assign
2223 * IRQs.
2224 */
2225
1da177e4
LT		 2226 /* Config Reg A */
2227 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2228
1da177e4 2229 w &= ~DMA_CLEAR; /* Clear DMA bits */
1da177e4
LT		 2230 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2231 w &= ~SAFEGUARD; /* Safeguard off */
2232 w |= POST_WRITE; /* Posted write */
607da7f8 2233 w |= PCI_TIMING; /* PCI timing on */
1da177e4
LT		 2234 /* XXX huh? claims to be reserved.. */
2235 w &= ~SWAP_LR; /* swap left/right
2236 seems to only have effect on SB
2237 Emulation */
2238 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2239
2240 pci_write_config_word(pci, ESM_CONFIG_A, w);
2241
2242 /* Config Reg B */
2243
2244 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2245
2246 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2247 /* XXX how do we know which to use? */
2248 w &= ~(1 << 14); /* External clock */
2249
2250 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2251 w |= HWV_CONFB; /* HWV on */
2252 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2253 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2254 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2255 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2256 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2257 w &= ~(1 << 1); /* reserved, always write 0 */
2258 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2259
2260 pci_write_config_word(pci, ESM_CONFIG_B, w);
2261
2262 /* DDMA off */
2263
2264 pci_read_config_word(pci, ESM_DDMA, &w);
2265 w &= ~(1 << 0);
2266 pci_write_config_word(pci, ESM_DDMA, w);
2267
2268 /*
2269 * Legacy mode
2270 */
2271
2272 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2273
607da7f8 2274 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
1da177e4
LT		 2275 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2276 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2277
2278 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2279
2280 /* Set up 978 docking control chip. */
2281 pci_read_config_word(pci, 0x58, &w);
2282 w|=1<<2; /* Enable 978. */
2283 w|=1<<3; /* Turn on 978 hardware volume control. */
2284 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2285 pci_write_config_word(pci, 0x58, w);
2286
2287 /* Sound Reset */
2288
2289 snd_es1968_reset(chip);
2290
2291 /*
2292 * Ring Bus Setup
2293 */
2294
2295 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2296 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2297 udelay(20);
2298 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2299 udelay(20);
2300
2301 /*
2302 * Reset the CODEC
2303 */
2304
2305 snd_es1968_ac97_reset(chip);
2306
2307 /* Ring Bus Control B */
2308
2309 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2310 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2311 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2312 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2313
2314 /* Set hardware volume control registers to midpoints.
2315 We can tell which button was pushed based on how they change. */
2316 outb(0x88, iobase+0x1c);
2317 outb(0x88, iobase+0x1d);
2318 outb(0x88, iobase+0x1e);
2319 outb(0x88, iobase+0x1f);
2320
2321 /* it appears some maestros (dell 7500) only work if these are set,
2322 regardless of wether we use the assp or not. */
2323
2324 outb(0, iobase + ASSP_CONTROL_B);
2325 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2326 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2327
2328 /*
2329 * set up wavecache
2330 */
2331 for (i = 0; i < 16; i++) {
2332 /* Write 0 into the buffer area 0x1E0->1EF */
2333 outw(0x01E0 + i, iobase + WC_INDEX);
2334 outw(0x0000, iobase + WC_DATA);
2335
2336 /* The 1.10 test program seem to write 0 into the buffer area
2337 * 0x1D0-0x1DF too.*/
2338 outw(0x01D0 + i, iobase + WC_INDEX);
2339 outw(0x0000, iobase + WC_DATA);
2340 }
2341 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2342 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2343 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2344 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2345 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2346 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2347 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2348 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2349
2350
2351 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2352 /* Now back to the DirectSound stuff */
2353 /* audio serial configuration.. ? */
2354 maestro_write(chip, 0x08, 0xB004);
2355 maestro_write(chip, 0x09, 0x001B);
2356 maestro_write(chip, 0x0A, 0x8000);
2357 maestro_write(chip, 0x0B, 0x3F37);
2358 maestro_write(chip, 0x0C, 0x0098);
2359
2360 /* parallel in, has something to do with recording :) */
2361 maestro_write(chip, 0x0C,
2362 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2363 /* parallel out */
2364 maestro_write(chip, 0x0C,
2365 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2366
2367 maestro_write(chip, 0x0D, 0x7632);
2368
2369 /* Wave cache control on - test off, sg off,
2370 enable, enable extra chans 1Mb */
2371
2372 w = inw(iobase + WC_CONTROL);
2373
2374 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2375 w |= 0xA000; /* reserved... I don't know */
2376 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2377 Seems to crash the Computer if enabled... */
2378 w |= 0x0100; /* Wave Cache Operation Enabled */
2379 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2380 w &= ~0x0060; /* Clear Wavtable Size */
2381 w |= 0x0020; /* Wavetable Size : 1MB */
2382 /* Bit 4 is reserved */
2383 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2384 /* Bit 1 is reserved */
2385 w &= ~0x0001; /* Test Mode off */
2386
2387 outw(w, iobase + WC_CONTROL);
2388
2389 /* Now clear the APU control ram */
2390 for (i = 0; i < NR_APUS; i++) {
2391 for (w = 0; w < NR_APU_REGS; w++)
2392 apu_set_register(chip, i, w, 0);
2393
2394 }
2395}
2396
2397/* Enable IRQ's */
969165a8 2398static void snd_es1968_start_irq(struct es1968 *chip)
1da177e4
LT		 2399{
2400 unsigned short w;
2401 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2402 if (chip->rmidi)
2403 w |= ESM_HIRQ_MPU401;
6895b526 2404 outb(w, chip->io_port + 0x1A);
1da177e4
LT		 2405 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2406}
2407
2408#ifdef CONFIG_PM
2409/*
2410 * PM support
2411 */
1d4b822b 2412static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2413{
1d4b822b
TI		 2414 struct snd_card *card = pci_get_drvdata(pci);
2415 struct es1968 *chip = card->private_data;
1da177e4
LT		 2416
2417 if (! chip->do_pm)
2418 return 0;
2419
2420 chip->in_suspend = 1;
1d4b822b 2421 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 2422 snd_pcm_suspend_all(chip->pcm);
2423 snd_ac97_suspend(chip->ac97);
2424 snd_es1968_bob_stop(chip);
30b35399 2425
1d4b822b
TI		 2426 pci_disable_device(pci);
2427 pci_save_state(pci);
30b35399 2428 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2429 return 0;
2430}
2431
1d4b822b 2432static int es1968_resume(struct pci_dev *pci)
1da177e4 2433{
1d4b822b
TI		 2434 struct snd_card *card = pci_get_drvdata(pci);
2435 struct es1968 *chip = card->private_data;
50f47ff1 2436 struct esschan *es;
1da177e4
LT		 2437
2438 if (! chip->do_pm)
2439 return 0;
2440
2441 /* restore all our config */
30b35399 2442 pci_set_power_state(pci, PCI_D0);
1d4b822b 2443 pci_restore_state(pci);
30b35399
TI		 2444 if (pci_enable_device(pci) < 0) {
2445 printk(KERN_ERR "es1968: pci_enable_device failed, "
2446 "disabling device\n");
2447 snd_card_disconnect(card);
2448 return -EIO;
2449 }
1d4b822b 2450 pci_set_master(pci);
30b35399 2451
1da177e4
LT		 2452 snd_es1968_chip_init(chip);
2453
2454 /* need to restore the base pointers.. */
2455 if (chip->dma.addr) {
2456 /* set PCMBAR */
2457 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2458 }
2459
2460 snd_es1968_start_irq(chip);
2461
2462 /* restore ac97 state */
2463 snd_ac97_resume(chip->ac97);
2464
50f47ff1 2465 list_for_each_entry(es, &chip->substream_list, list) {
1da177e4
LT		 2466 switch (es->mode) {
2467 case ESM_MODE_PLAY:
2468 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2469 break;
2470 case ESM_MODE_CAPTURE:
2471 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2472 break;
2473 }
2474 }
2475
2476 /* start timer again */
2477 if (chip->bobclient)
2478 snd_es1968_bob_start(chip);
2479
1d4b822b 2480 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2481 chip->in_suspend = 0;
2482 return 0;
2483}
2484#endif /* CONFIG_PM */
2485
2486#ifdef SUPPORT_JOYSTICK
2487#define JOYSTICK_ADDR 0x200
969165a8 2488static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
1da177e4
LT		 2489{
2490 struct gameport *gp;
2491 struct resource *r;
2492 u16 val;
2493
2494 if (!joystick[dev])
2495 return -ENODEV;
2496
2497 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2498 if (!r)
2499 return -EBUSY;
2500
2501 chip->gameport = gp = gameport_allocate_port();
2502 if (!gp) {
2503 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
b1d5776d 2504 release_and_free_resource(r);
1da177e4
LT		 2505 return -ENOMEM;
2506 }
2507
2508 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2509 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2510
2511 gameport_set_name(gp, "ES1968 Gameport");
2512 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2513 gameport_set_dev_parent(gp, &chip->pci->dev);
2514 gp->io = JOYSTICK_ADDR;
2515 gameport_set_port_data(gp, r);
2516
2517 gameport_register_port(gp);
2518
2519 return 0;
2520}
2521
969165a8 2522static void snd_es1968_free_gameport(struct es1968 *chip)
1da177e4
LT		 2523{
2524 if (chip->gameport) {
2525 struct resource *r = gameport_get_port_data(chip->gameport);
2526
2527 gameport_unregister_port(chip->gameport);
2528 chip->gameport = NULL;
2529
b1d5776d 2530 release_and_free_resource(r);
1da177e4
LT		 2531 }
2532}
2533#else
969165a8
TI		 2534static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2535static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
1da177e4
LT		 2536#endif
2537
5a5e02e5
HG		 2538#ifdef CONFIG_SND_ES1968_INPUT
2539static int __devinit snd_es1968_input_register(struct es1968 *chip)
2540{
2541 struct input_dev *input_dev;
2542 int err;
2543
2544 input_dev = input_allocate_device();
2545 if (!input_dev)
2546 return -ENOMEM;
2547
2548 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2549 pci_name(chip->pci));
2550
2551 input_dev->name = chip->card->driver;
2552 input_dev->phys = chip->phys;
2553 input_dev->id.bustype = BUS_PCI;
2554 input_dev->id.vendor = chip->pci->vendor;
2555 input_dev->id.product = chip->pci->device;
2556 input_dev->dev.parent = &chip->pci->dev;
2557
2558 __set_bit(EV_KEY, input_dev->evbit);
2559 __set_bit(KEY_MUTE, input_dev->keybit);
2560 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2561 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2562
2563 err = input_register_device(input_dev);
2564 if (err) {
2565 input_free_device(input_dev);
2566 return err;
2567 }
2568
2569 chip->input_dev = input_dev;
2570 return 0;
2571}
2572#endif /* CONFIG_SND_ES1968_INPUT */
2573
969165a8 2574static int snd_es1968_free(struct es1968 *chip)
1da177e4 2575{
5a5e02e5
HG		 2576#ifdef CONFIG_SND_ES1968_INPUT
2577 if (chip->input_dev)
2578 input_unregister_device(chip->input_dev);
2579#endif
2580
1da177e4 2581 if (chip->io_port) {
f000fd80
JG		 2582 if (chip->irq >= 0)
2583 synchronize_irq(chip->irq);
1da177e4
LT		 2584 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2585 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2586 }
2587
2588 if (chip->irq >= 0)
437a5a46 2589 free_irq(chip->irq, chip);
1da177e4 2590 snd_es1968_free_gameport(chip);
1da177e4
LT		 2591 pci_release_regions(chip->pci);
2592 pci_disable_device(chip->pci);
2593 kfree(chip);
2594 return 0;
2595}
2596
969165a8 2597static int snd_es1968_dev_free(struct snd_device *device)
1da177e4 2598{
969165a8 2599 struct es1968 *chip = device->device_data;
1da177e4
LT		 2600 return snd_es1968_free(chip);
2601}
2602
2603struct ess_device_list {
2604 unsigned short type; /* chip type */
2605 unsigned short vendor; /* subsystem vendor id */
2606};
2607
2608static struct ess_device_list pm_whitelist[] __devinitdata = {
2609 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2610 { TYPE_MAESTRO2E, 0x1028 },
2611 { TYPE_MAESTRO2E, 0x103c },
2612 { TYPE_MAESTRO2E, 0x1179 },
2613 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
e6e514fa 2614 { TYPE_MAESTRO2E, 0x1558 },
1da177e4
LT		 2615};
2616
2617static struct ess_device_list mpu_blacklist[] __devinitdata = {
2618 { TYPE_MAESTRO2, 0x125d },
2619};
2620
969165a8 2621static int __devinit snd_es1968_create(struct snd_card *card,
1da177e4
LT		 2622 struct pci_dev *pci,
2623 int total_bufsize,
2624 int play_streams,
2625 int capt_streams,
2626 int chip_type,
2627 int do_pm,
969165a8 2628 struct es1968 **chip_ret)
1da177e4 2629{
969165a8 2630 static struct snd_device_ops ops = {
1da177e4
LT		 2631 .dev_free = snd_es1968_dev_free,
2632 };
969165a8 2633 struct es1968 *chip;
1da177e4
LT		 2634 int i, err;
2635
2636 *chip_ret = NULL;
2637
2638 /* enable PCI device */
2639 if ((err = pci_enable_device(pci)) < 0)
2640 return err;
2641 /* check, if we can restrict PCI DMA transfers to 28 bits */
ce0b6201
YH		 2642 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2643 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
99b359ba 2644 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
1da177e4
LT		 2645 pci_disable_device(pci);
2646 return -ENXIO;
2647 }
2648
e560d8d8 2649 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2650 if (! chip) {
2651 pci_disable_device(pci);
2652 return -ENOMEM;
2653 }
2654
2655 /* Set Vars */
2656 chip->type = chip_type;
2657 spin_lock_init(&chip->reg_lock);
2658 spin_lock_init(&chip->substream_lock);
2659 INIT_LIST_HEAD(&chip->buf_list);
2660 INIT_LIST_HEAD(&chip->substream_list);
62932df8 2661 mutex_init(&chip->memory_mutex);
5a5e02e5
HG		 2662#ifndef CONFIG_SND_ES1968_INPUT
2663 spin_lock_init(&chip->ac97_lock);
1da177e4 2664 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
5a5e02e5 2665#endif
1da177e4
LT		 2666 chip->card = card;
2667 chip->pci = pci;
2668 chip->irq = -1;
2669 chip->total_bufsize = total_bufsize; /* in bytes */
2670 chip->playback_streams = play_streams;
2671 chip->capture_streams = capt_streams;
2672
2673 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2674 kfree(chip);
2675 pci_disable_device(pci);
2676 return err;
2677 }
2678 chip->io_port = pci_resource_start(pci, 0);
437a5a46
TI		 2679 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2680 "ESS Maestro", chip)) {
99b359ba 2681 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2682 snd_es1968_free(chip);
2683 return -EBUSY;
2684 }
2685 chip->irq = pci->irq;
2686
2687 /* Clear Maestro_map */
2688 for (i = 0; i < 32; i++)
2689 chip->maestro_map[i] = 0;
2690
2691 /* Clear Apu Map */
2692 for (i = 0; i < NR_APUS; i++)
2693 chip->apu[i] = ESM_APU_FREE;
2694
2695 /* just to be sure */
2696 pci_set_master(pci);
2697
2698 if (do_pm > 1) {
2699 /* disable power-management if not on the whitelist */
2700 unsigned short vend;
2701 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2702 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2703 if (chip->type == pm_whitelist[i].type &&
2704 vend == pm_whitelist[i].vendor) {
2705 do_pm = 1;
2706 break;
2707 }
2708 }
2709 if (do_pm > 1) {
2710 /* not matched; disabling pm */
2711 printk(KERN_INFO "es1968: not attempting power management.\n");
2712 do_pm = 0;
2713 }
2714 }
2715 chip->do_pm = do_pm;
2716
2717 snd_es1968_chip_init(chip);
2718
1da177e4
LT		 2719 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2720 snd_es1968_free(chip);
2721 return err;
2722 }
2723
2724 snd_card_set_dev(card, &pci->dev);
2725
2726 *chip_ret = chip;
2727
2728 return 0;
2729}
2730
2731
2732/*
2733 */
2734static int __devinit snd_es1968_probe(struct pci_dev *pci,
2735 const struct pci_device_id *pci_id)
2736{
2737 static int dev;
969165a8
TI		 2738 struct snd_card *card;
2739 struct es1968 *chip;
1da177e4
LT		 2740 unsigned int i;
2741 int err;
2742
2743 if (dev >= SNDRV_CARDS)
2744 return -ENODEV;
2745 if (!enable[dev]) {
2746 dev++;
2747 return -ENOENT;
2748 }
2749
e58de7ba
TI		 2750 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2751 if (err < 0)
2752 return err;
1da177e4
LT		 2753
2754 if (total_bufsize[dev] < 128)
2755 total_bufsize[dev] = 128;
2756 if (total_bufsize[dev] > 4096)
2757 total_bufsize[dev] = 4096;
2758 if ((err = snd_es1968_create(card, pci,
2759 total_bufsize[dev] * 1024, /* in bytes */
2760 pcm_substreams_p[dev],
2761 pcm_substreams_c[dev],
2762 pci_id->driver_data,
2763 use_pm[dev],
2764 &chip)) < 0) {
2765 snd_card_free(card);
2766 return err;
2767 }
1d4b822b 2768 card->private_data = chip;
1da177e4
LT		 2769
2770 switch (chip->type) {
2771 case TYPE_MAESTRO2E:
2772 strcpy(card->driver, "ES1978");
2773 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2774 break;
2775 case TYPE_MAESTRO2:
2776 strcpy(card->driver, "ES1968");
2777 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2778 break;
2779 case TYPE_MAESTRO:
2780 strcpy(card->driver, "ESM1");
2781 strcpy(card->shortname, "ESS Maestro 1");
2782 break;
2783 }
2784
2785 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2786 snd_card_free(card);
2787 return err;
2788 }
2789
2790 if ((err = snd_es1968_mixer(chip)) < 0) {
2791 snd_card_free(card);
2792 return err;
2793 }
2794
2795 if (enable_mpu[dev] == 2) {
2796 /* check the black list */
2797 unsigned short vend;
2798 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2799 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2800 if (chip->type == mpu_blacklist[i].type &&
2801 vend == mpu_blacklist[i].vendor) {
2802 enable_mpu[dev] = 0;
2803 break;
2804 }
2805 }
2806 }
2807 if (enable_mpu[dev]) {
2808 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
302e4c2f
TI		 2809 chip->io_port + ESM_MPU401_PORT,
2810 MPU401_INFO_INTEGRATED,
1da177e4
LT		 2811 chip->irq, 0, &chip->rmidi)) < 0) {
2812 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2813 }
2814 }
2815
2816 snd_es1968_create_gameport(chip, dev);
2817
5a5e02e5
HG		 2818#ifdef CONFIG_SND_ES1968_INPUT
2819 err = snd_es1968_input_register(chip);
2820 if (err)
2821 snd_printk(KERN_WARNING "Input device registration "
2822 "failed with error %i", err);
2823#endif
2824
1da177e4
LT		 2825 snd_es1968_start_irq(chip);
2826
2827 chip->clock = clock[dev];
2828 if (! chip->clock)
2829 es1968_measure_clock(chip);
2830
2831 sprintf(card->longname, "%s at 0x%lx, irq %i",
2832 card->shortname, chip->io_port, chip->irq);
2833
2834 if ((err = snd_card_register(card)) < 0) {
2835 snd_card_free(card);
2836 return err;
2837 }
2838 pci_set_drvdata(pci, card);
2839 dev++;
2840 return 0;
2841}
2842
2843static void __devexit snd_es1968_remove(struct pci_dev *pci)
2844{
2845 snd_card_free(pci_get_drvdata(pci));
2846 pci_set_drvdata(pci, NULL);
2847}
2848
2849static struct pci_driver driver = {
2850 .name = "ES1968 (ESS Maestro)",
2851 .id_table = snd_es1968_ids,
2852 .probe = snd_es1968_probe,
2853 .remove = __devexit_p(snd_es1968_remove),
1d4b822b
TI		 2854#ifdef CONFIG_PM
2855 .suspend = es1968_suspend,
2856 .resume = es1968_resume,
2857#endif
1da177e4
LT		 2858};
2859
2860static int __init alsa_card_es1968_init(void)
2861{
01d25d46 2862 return pci_register_driver(&driver);
1da177e4
LT		 2863}
2864
2865static void __exit alsa_card_es1968_exit(void)
2866{
2867 pci_unregister_driver(&driver);
2868}
2869
2870module_init(alsa_card_es1968_init)
2871module_exit(alsa_card_es1968_exit)
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