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[ALSA] es1968 - Fix PM support
[net-next-2.6.git] / sound / pci / cs46xx / cs46xx_lib.c
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1da177e4
LT		 1/*
2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
4 * Cirrus Logic, Inc.
5 * Routines for control of Cirrus Logic CS461x chips
6 *
7 * KNOWN BUGS:
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer controll.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
14 *
15 * TODO:
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
20 *
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
24 *
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
36 *
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
41 *
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 *
46 */
47
48#include <sound/driver.h>
49#include <linux/delay.h>
50#include <linux/pci.h>
51#include <linux/pm.h>
52#include <linux/init.h>
53#include <linux/interrupt.h>
54#include <linux/slab.h>
55#include <linux/gameport.h>
56
57#include <sound/core.h>
58#include <sound/control.h>
59#include <sound/info.h>
60#include <sound/pcm.h>
61#include <sound/pcm_params.h>
62#include <sound/cs46xx.h>
63
64#include <asm/io.h>
65
66#include "cs46xx_lib.h"
67#include "dsp_spos.h"
68
3d19f804 69static void amp_voyetra(struct snd_cs46xx *chip, int change);
1da177e4
LT		 70
71#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804
TI		 72static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
73static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
74static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
75static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
76static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
77static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
1da177e4
LT		 78#endif
79
3d19f804
TI		 80static struct snd_pcm_ops snd_cs46xx_playback_ops;
81static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
82static struct snd_pcm_ops snd_cs46xx_capture_ops;
83static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
1da177e4 84
3d19f804 85static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
1da177e4
LT		 86 unsigned short reg,
87 int codec_index)
88{
89 int count;
90 unsigned short result,tmp;
91 u32 offset = 0;
92 snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
93 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
94 return -EINVAL);
95
96 chip->active_ctrl(chip, 1);
97
98 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
99 offset = CS46XX_SECONDARY_CODEC_OFFSET;
100
101 /*
102 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
103 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
104 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
105 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
106 * 5. if DCV not cleared, break and return error
107 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
108 */
109
110 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
111
112 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
113 if ((tmp & ACCTL_VFRM) == 0) {
114 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
115 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
116 msleep(50);
117 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
118 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
119
120 }
121
122 /*
123 * Setup the AC97 control registers on the CS461x to send the
124 * appropriate command to the AC97 to perform the read.
125 * ACCAD = Command Address Register = 46Ch
126 * ACCDA = Command Data Register = 470h
127 * ACCTL = Control Register = 460h
128 * set DCV - will clear when process completed
129 * set CRW - Read command
130 * set VFRM - valid frame enabled
131 * set ESYN - ASYNC generation enabled
132 * set RSTN - ARST# inactive, AC97 codec not reset
133 */
134
135 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
136 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
137 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
138 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
139 ACCTL_VFRM | ACCTL_ESYN |
140 ACCTL_RSTN);
141 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
142 ACCTL_VFRM | ACCTL_ESYN |
143 ACCTL_RSTN);
144 } else {
145 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
146 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
147 ACCTL_RSTN);
148 }
149
150 /*
151 * Wait for the read to occur.
152 */
153 for (count = 0; count < 1000; count++) {
154 /*
155 * First, we want to wait for a short time.
156 */
157 udelay(10);
158 /*
159 * Now, check to see if the read has completed.
160 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
161 */
162 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
163 goto ok1;
164 }
165
99b359ba 166 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
1da177e4
LT		 167 result = 0xffff;
168 goto end;
169
170 ok1:
171 /*
172 * Wait for the valid status bit to go active.
173 */
174 for (count = 0; count < 100; count++) {
175 /*
176 * Read the AC97 status register.
177 * ACSTS = Status Register = 464h
178 * VSTS - Valid Status
179 */
180 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
181 goto ok2;
182 udelay(10);
183 }
184
99b359ba 185 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
1da177e4
LT		 186 result = 0xffff;
187 goto end;
188
189 ok2:
190 /*
191 * Read the data returned from the AC97 register.
192 * ACSDA = Status Data Register = 474h
193 */
194#if 0
195 printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
196 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
197 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
198#endif
199
200 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
201 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
202 end:
203 chip->active_ctrl(chip, -1);
204 return result;
205}
206
3d19f804 207static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
1da177e4
LT		 208 unsigned short reg)
209{
3d19f804 210 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 211 unsigned short val;
212 int codec_index = ac97->num;
213
214 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
215 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
216 return 0xffff);
217
218 val = snd_cs46xx_codec_read(chip, reg, codec_index);
219
220 return val;
221}
222
223
3d19f804 224static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
1da177e4
LT		 225 unsigned short reg,
226 unsigned short val,
227 int codec_index)
228{
229 int count;
230
231 snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
232 (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
233 return);
234
235 chip->active_ctrl(chip, 1);
236
237 /*
238 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
239 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
240 * 3. Write ACCTL = Control Register = 460h for initiating the write
241 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
242 * 5. if DCV not cleared, break and return error
243 */
244
245 /*
246 * Setup the AC97 control registers on the CS461x to send the
247 * appropriate command to the AC97 to perform the read.
248 * ACCAD = Command Address Register = 46Ch
249 * ACCDA = Command Data Register = 470h
250 * ACCTL = Control Register = 460h
251 * set DCV - will clear when process completed
252 * reset CRW - Write command
253 * set VFRM - valid frame enabled
254 * set ESYN - ASYNC generation enabled
255 * set RSTN - ARST# inactive, AC97 codec not reset
256 */
257 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
259 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
260
261 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
262 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
263 ACCTL_ESYN | ACCTL_RSTN);
264 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
265 ACCTL_ESYN | ACCTL_RSTN);
266 } else {
267 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
268 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
269 }
270
271 for (count = 0; count < 4000; count++) {
272 /*
273 * First, we want to wait for a short time.
274 */
275 udelay(10);
276 /*
277 * Now, check to see if the write has completed.
278 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
279 */
280 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
281 goto end;
282 }
283 }
99b359ba 284 snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
1da177e4
LT		 285 end:
286 chip->active_ctrl(chip, -1);
287}
288
3d19f804 289static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 290 unsigned short reg,
291 unsigned short val)
292{
3d19f804 293 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 294 int codec_index = ac97->num;
295
296 snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
297 codec_index == CS46XX_SECONDARY_CODEC_INDEX,
298 return);
299
300 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301}
302
303
304/*
305 * Chip initialization
306 */
307
3d19f804 308int snd_cs46xx_download(struct snd_cs46xx *chip,
1da177e4
LT		 309 u32 *src,
310 unsigned long offset,
311 unsigned long len)
312{
313 void __iomem *dst;
314 unsigned int bank = offset >> 16;
315 offset = offset & 0xffff;
316
317 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
318 dst = chip->region.idx[bank+1].remap_addr + offset;
319 len /= sizeof(u32);
320
321 /* writel already converts 32-bit value to right endianess */
322 while (len-- > 0) {
323 writel(*src++, dst);
324 dst += sizeof(u32);
325 }
326 return 0;
327}
328
329#ifdef CONFIG_SND_CS46XX_NEW_DSP
330
331#include "imgs/cwc4630.h"
332#include "imgs/cwcasync.h"
333#include "imgs/cwcsnoop.h"
334#include "imgs/cwcbinhack.h"
335#include "imgs/cwcdma.h"
336
3d19f804 337int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
1da177e4
LT		 338 unsigned long offset,
339 unsigned long len)
340{
341 void __iomem *dst;
342 unsigned int bank = offset >> 16;
343 offset = offset & 0xffff;
344
345 snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
346 dst = chip->region.idx[bank+1].remap_addr + offset;
347 len /= sizeof(u32);
348
349 /* writel already converts 32-bit value to right endianess */
350 while (len-- > 0) {
351 writel(0, dst);
352 dst += sizeof(u32);
353 }
354 return 0;
355}
356
357#else /* old DSP image */
358
359#include "cs46xx_image.h"
360
3d19f804 361int snd_cs46xx_download_image(struct snd_cs46xx *chip)
1da177e4
LT		 362{
363 int idx, err;
364 unsigned long offset = 0;
365
366 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
367 if ((err = snd_cs46xx_download(chip,
368 &BA1Struct.map[offset],
369 BA1Struct.memory[idx].offset,
370 BA1Struct.memory[idx].size)) < 0)
371 return err;
372 offset += BA1Struct.memory[idx].size >> 2;
373 }
374 return 0;
375}
376#endif /* CONFIG_SND_CS46XX_NEW_DSP */
377
378/*
379 * Chip reset
380 */
381
3d19f804 382static void snd_cs46xx_reset(struct snd_cs46xx *chip)
1da177e4
LT		 383{
384 int idx;
385
386 /*
387 * Write the reset bit of the SP control register.
388 */
389 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
390
391 /*
392 * Write the control register.
393 */
394 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
395
396 /*
397 * Clear the trap registers.
398 */
399 for (idx = 0; idx < 8; idx++) {
400 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
401 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
402 }
403 snd_cs46xx_poke(chip, BA1_DREG, 0);
404
405 /*
406 * Set the frame timer to reflect the number of cycles per frame.
407 */
408 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
409}
410
3d19f804 411static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
1da177e4
LT		 412{
413 u32 i, status = 0;
414 /*
415 * Make sure the previous FIFO write operation has completed.
416 */
417 for(i = 0; i < 50; i++){
418 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
419
420 if( !(status & SERBST_WBSY) )
421 break;
422
423 mdelay(retry_timeout);
424 }
425
426 if(status & SERBST_WBSY) {
427 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
428
429 return -EINVAL;
430 }
431
432 return 0;
433}
434
3d19f804 435static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
1da177e4
LT		 436{
437 int idx, powerdown = 0;
438 unsigned int tmp;
439
440 /*
441 * See if the devices are powered down. If so, we must power them up first
442 * or they will not respond.
443 */
444 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
445 if (!(tmp & CLKCR1_SWCE)) {
446 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
447 powerdown = 1;
448 }
449
450 /*
451 * We want to clear out the serial port FIFOs so we don't end up playing
452 * whatever random garbage happens to be in them. We fill the sample FIFOS
453 * with zero (silence).
454 */
455 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
456
457 /*
458 * Fill all 256 sample FIFO locations.
459 */
460 for (idx = 0; idx < 0xFF; idx++) {
461 /*
462 * Make sure the previous FIFO write operation has completed.
463 */
464 if (cs46xx_wait_for_fifo(chip,1)) {
465 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
466
467 if (powerdown)
468 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
469
470 break;
471 }
472 /*
473 * Write the serial port FIFO index.
474 */
475 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
476 /*
477 * Tell the serial port to load the new value into the FIFO location.
478 */
479 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
480 }
481 /*
482 * Now, if we powered up the devices, then power them back down again.
483 * This is kinda ugly, but should never happen.
484 */
485 if (powerdown)
486 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
487}
488
3d19f804 489static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
1da177e4
LT		 490{
491 int cnt;
492
493 /*
494 * Set the frame timer to reflect the number of cycles per frame.
495 */
496 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
497 /*
498 * Turn on the run, run at frame, and DMA enable bits in the local copy of
499 * the SP control register.
500 */
501 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
502 /*
503 * Wait until the run at frame bit resets itself in the SP control
504 * register.
505 */
506 for (cnt = 0; cnt < 25; cnt++) {
507 udelay(50);
508 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
509 break;
510 }
511
512 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
99b359ba 513 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n");
1da177e4
LT		 514}
515
3d19f804 516static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
1da177e4
LT		 517{
518 /*
519 * Turn off the run, run at frame, and DMA enable bits in the local copy of
520 * the SP control register.
521 */
522 snd_cs46xx_poke(chip, BA1_SPCR, 0);
523}
524
525/*
526 * Sample rate routines
527 */
528
529#define GOF_PER_SEC 200
530
3d19f804 531static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 532{
533 unsigned long flags;
534 unsigned int tmp1, tmp2;
535 unsigned int phiIncr;
536 unsigned int correctionPerGOF, correctionPerSec;
537
538 /*
539 * Compute the values used to drive the actual sample rate conversion.
540 * The following formulas are being computed, using inline assembly
541 * since we need to use 64 bit arithmetic to compute the values:
542 *
543 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
544 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
545 * GOF_PER_SEC)
546 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
547 * GOF_PER_SEC * correctionPerGOF
548 *
549 * i.e.
550 *
551 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
552 * correctionPerGOF:correctionPerSec =
553 * dividend:remainder(ulOther / GOF_PER_SEC)
554 */
555 tmp1 = rate << 16;
556 phiIncr = tmp1 / 48000;
557 tmp1 -= phiIncr * 48000;
558 tmp1 <<= 10;
559 phiIncr <<= 10;
560 tmp2 = tmp1 / 48000;
561 phiIncr += tmp2;
562 tmp1 -= tmp2 * 48000;
563 correctionPerGOF = tmp1 / GOF_PER_SEC;
564 tmp1 -= correctionPerGOF * GOF_PER_SEC;
565 correctionPerSec = tmp1;
566
567 /*
568 * Fill in the SampleRateConverter control block.
569 */
570 spin_lock_irqsave(&chip->reg_lock, flags);
571 snd_cs46xx_poke(chip, BA1_PSRC,
572 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
573 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
574 spin_unlock_irqrestore(&chip->reg_lock, flags);
575}
576
3d19f804 577static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
1da177e4
LT		 578{
579 unsigned long flags;
580 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
581 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
582 unsigned int frameGroupLength, cnt;
583
584 /*
585 * We can only decimate by up to a factor of 1/9th the hardware rate.
586 * Correct the value if an attempt is made to stray outside that limit.
587 */
588 if ((rate * 9) < 48000)
589 rate = 48000 / 9;
590
591 /*
592 * We can not capture at at rate greater than the Input Rate (48000).
593 * Return an error if an attempt is made to stray outside that limit.
594 */
595 if (rate > 48000)
596 rate = 48000;
597
598 /*
599 * Compute the values used to drive the actual sample rate conversion.
600 * The following formulas are being computed, using inline assembly
601 * since we need to use 64 bit arithmetic to compute the values:
602 *
603 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
604 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
605 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
606 * GOF_PER_SEC)
607 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
608 * GOF_PER_SEC * correctionPerGOF
609 * initialDelay = ceil((24 * Fs,in) / Fs,out)
610 *
611 * i.e.
612 *
613 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
614 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
615 * correctionPerGOF:correctionPerSec =
616 * dividend:remainder(ulOther / GOF_PER_SEC)
617 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
618 */
619
620 tmp1 = rate << 16;
621 coeffIncr = tmp1 / 48000;
622 tmp1 -= coeffIncr * 48000;
623 tmp1 <<= 7;
624 coeffIncr <<= 7;
625 coeffIncr += tmp1 / 48000;
626 coeffIncr ^= 0xFFFFFFFF;
627 coeffIncr++;
628 tmp1 = 48000 << 16;
629 phiIncr = tmp1 / rate;
630 tmp1 -= phiIncr * rate;
631 tmp1 <<= 10;
632 phiIncr <<= 10;
633 tmp2 = tmp1 / rate;
634 phiIncr += tmp2;
635 tmp1 -= tmp2 * rate;
636 correctionPerGOF = tmp1 / GOF_PER_SEC;
637 tmp1 -= correctionPerGOF * GOF_PER_SEC;
638 correctionPerSec = tmp1;
639 initialDelay = ((48000 * 24) + rate - 1) / rate;
640
641 /*
642 * Fill in the VariDecimate control block.
643 */
644 spin_lock_irqsave(&chip->reg_lock, flags);
645 snd_cs46xx_poke(chip, BA1_CSRC,
646 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
647 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
648 snd_cs46xx_poke(chip, BA1_CD,
649 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
650 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
651 spin_unlock_irqrestore(&chip->reg_lock, flags);
652
653 /*
654 * Figure out the frame group length for the write back task. Basically,
655 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
656 * the output sample rate.
657 */
658 frameGroupLength = 1;
659 for (cnt = 2; cnt <= 64; cnt *= 2) {
660 if (((rate / cnt) * cnt) != rate)
661 frameGroupLength *= 2;
662 }
663 if (((rate / 3) * 3) != rate) {
664 frameGroupLength *= 3;
665 }
666 for (cnt = 5; cnt <= 125; cnt *= 5) {
667 if (((rate / cnt) * cnt) != rate)
668 frameGroupLength *= 5;
669 }
670
671 /*
672 * Fill in the WriteBack control block.
673 */
674 spin_lock_irqsave(&chip->reg_lock, flags);
675 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
676 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
677 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
678 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
679 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
680 spin_unlock_irqrestore(&chip->reg_lock, flags);
681}
682
683/*
684 * PCM part
685 */
686
3d19f804
TI		 687static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
688 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 689{
3d19f804
TI		 690 struct snd_pcm_runtime *runtime = substream->runtime;
691 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 692 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
693}
694
3d19f804 695static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
1da177e4 696{
3d19f804
TI		 697 struct snd_pcm_runtime *runtime = substream->runtime;
698 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
1da177e4
LT		 699 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
700 return 0;
701}
702
3d19f804
TI		 703static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
704 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 705{
3d19f804
TI		 706 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
707 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 708 memcpy(runtime->dma_area + rec->sw_data,
709 chip->capt.hw_buf.area + rec->hw_data, bytes);
710}
711
3d19f804 712static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
1da177e4 713{
3d19f804 714 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 715 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
716 return 0;
717}
718
3d19f804 719static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 720{
3d19f804 721 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 722 size_t ptr;
3d19f804 723 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 724 snd_assert (cpcm->pcm_channel,return -ENXIO);
725
726#ifdef CONFIG_SND_CS46XX_NEW_DSP
727 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
728#else
729 ptr = snd_cs46xx_peek(chip, BA1_PBA);
730#endif
731 ptr -= cpcm->hw_buf.addr;
732 return ptr >> cpcm->shift;
733}
734
3d19f804 735static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 736{
3d19f804 737 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4 738 size_t ptr;
3d19f804 739 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 740
741#ifdef CONFIG_SND_CS46XX_NEW_DSP
742 snd_assert (cpcm->pcm_channel,return -ENXIO);
743 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
744#else
745 ptr = snd_cs46xx_peek(chip, BA1_PBA);
746#endif
747 ptr -= cpcm->hw_buf.addr;
748 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
749}
750
3d19f804 751static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
1da177e4 752{
3d19f804 753 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 754 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
755 return ptr >> chip->capt.shift;
756}
757
3d19f804 758static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
1da177e4 759{
3d19f804 760 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 761 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
762 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
763}
764
3d19f804 765static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 766 int cmd)
767{
3d19f804
TI		 768 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
769 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
1da177e4
LT		 770 int result = 0;
771
772#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 773 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
1da177e4
LT		 774 if (! cpcm->pcm_channel) {
775 return -ENXIO;
776 }
777#endif
778 switch (cmd) {
779 case SNDRV_PCM_TRIGGER_START:
780 case SNDRV_PCM_TRIGGER_RESUME:
781#ifdef CONFIG_SND_CS46XX_NEW_DSP
782 /* magic value to unmute PCM stream playback volume */
783 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
784 SCBVolumeCtrl) << 2, 0x80008000);
785
786 if (cpcm->pcm_channel->unlinked)
787 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
788
789 if (substream->runtime->periods != CS46XX_FRAGS)
790 snd_cs46xx_playback_transfer(substream);
791#else
792 spin_lock(&chip->reg_lock);
793 if (substream->runtime->periods != CS46XX_FRAGS)
794 snd_cs46xx_playback_transfer(substream);
795 { unsigned int tmp;
796 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
797 tmp &= 0x0000ffff;
798 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
799 }
800 spin_unlock(&chip->reg_lock);
801#endif
802 break;
803 case SNDRV_PCM_TRIGGER_STOP:
804 case SNDRV_PCM_TRIGGER_SUSPEND:
805#ifdef CONFIG_SND_CS46XX_NEW_DSP
806 /* magic mute channel */
807 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
808 SCBVolumeCtrl) << 2, 0xffffffff);
809
810 if (!cpcm->pcm_channel->unlinked)
811 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
812#else
813 spin_lock(&chip->reg_lock);
814 { unsigned int tmp;
815 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
816 tmp &= 0x0000ffff;
817 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
818 }
819 spin_unlock(&chip->reg_lock);
820#endif
821 break;
822 default:
823 result = -EINVAL;
824 break;
825 }
826
827 return result;
828}
829
3d19f804 830static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 831 int cmd)
832{
3d19f804 833 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 834 unsigned int tmp;
835 int result = 0;
836
837 spin_lock(&chip->reg_lock);
838 switch (cmd) {
839 case SNDRV_PCM_TRIGGER_START:
840 case SNDRV_PCM_TRIGGER_RESUME:
841 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
842 tmp &= 0xffff0000;
843 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
844 break;
845 case SNDRV_PCM_TRIGGER_STOP:
846 case SNDRV_PCM_TRIGGER_SUSPEND:
847 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
848 tmp &= 0xffff0000;
849 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
850 break;
851 default:
852 result = -EINVAL;
853 break;
854 }
855 spin_unlock(&chip->reg_lock);
856
857 return result;
858}
859
860#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 861static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1da177e4
LT		 862 int sample_rate)
863{
864
865 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
866 if ( cpcm->pcm_channel == NULL) {
867 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
868 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
869 if (cpcm->pcm_channel == NULL) {
870 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
871 return -ENOMEM;
872 }
873 cpcm->pcm_channel->sample_rate = sample_rate;
874 } else
875 /* if sample rate is changed */
876 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
877 int unlinked = cpcm->pcm_channel->unlinked;
878 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
879
880 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
881 cpcm->hw_buf.addr,
882 cpcm->pcm_channel_id)) == NULL) {
883 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
884 return -ENOMEM;
885 }
886
887 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
888 cpcm->pcm_channel->sample_rate = sample_rate;
889 }
890
891 return 0;
892}
893#endif
894
895
3d19f804
TI		 896static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
897 struct snd_pcm_hw_params *hw_params)
1da177e4 898{
3d19f804
TI		 899 struct snd_pcm_runtime *runtime = substream->runtime;
900 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 901 int err;
902#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 903 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 904 int sample_rate = params_rate(hw_params);
905 int period_size = params_period_bytes(hw_params);
906#endif
907 cpcm = runtime->private_data;
908
909#ifdef CONFIG_SND_CS46XX_NEW_DSP
910 snd_assert (sample_rate != 0, return -ENXIO);
911
912 down (&chip->spos_mutex);
913
914 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
915 up (&chip->spos_mutex);
916 return -ENXIO;
917 }
918
919 snd_assert (cpcm->pcm_channel != NULL);
920 if (!cpcm->pcm_channel) {
921 up (&chip->spos_mutex);
922 return -ENXIO;
923 }
924
925
926 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
927 up (&chip->spos_mutex);
928 return -EINVAL;
929 }
930
931 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
932 period_size, params_periods(hw_params),
933 params_buffer_bytes(hw_params));
934#endif
935
936 if (params_periods(hw_params) == CS46XX_FRAGS) {
937 if (runtime->dma_area != cpcm->hw_buf.area)
938 snd_pcm_lib_free_pages(substream);
939 runtime->dma_area = cpcm->hw_buf.area;
940 runtime->dma_addr = cpcm->hw_buf.addr;
941 runtime->dma_bytes = cpcm->hw_buf.bytes;
942
943
944#ifdef CONFIG_SND_CS46XX_NEW_DSP
945 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
946 substream->ops = &snd_cs46xx_playback_ops;
947 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
948 substream->ops = &snd_cs46xx_playback_rear_ops;
949 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
950 substream->ops = &snd_cs46xx_playback_clfe_ops;
951 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
952 substream->ops = &snd_cs46xx_playback_iec958_ops;
953 } else {
954 snd_assert(0);
955 }
956#else
957 substream->ops = &snd_cs46xx_playback_ops;
958#endif
959
960 } else {
961 if (runtime->dma_area == cpcm->hw_buf.area) {
962 runtime->dma_area = NULL;
963 runtime->dma_addr = 0;
964 runtime->dma_bytes = 0;
965 }
966 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
967#ifdef CONFIG_SND_CS46XX_NEW_DSP
968 up (&chip->spos_mutex);
969#endif
970 return err;
971 }
972
973#ifdef CONFIG_SND_CS46XX_NEW_DSP
974 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
975 substream->ops = &snd_cs46xx_playback_indirect_ops;
976 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
977 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
978 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
979 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
980 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
981 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
982 } else {
983 snd_assert(0);
984 }
985#else
986 substream->ops = &snd_cs46xx_playback_indirect_ops;
987#endif
988
989 }
990
991#ifdef CONFIG_SND_CS46XX_NEW_DSP
992 up (&chip->spos_mutex);
993#endif
994
995 return 0;
996}
997
3d19f804 998static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1da177e4 999{
3d19f804
TI		 1000 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1001 struct snd_pcm_runtime *runtime = substream->runtime;
1002 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1003
1004 cpcm = runtime->private_data;
1005
1006 /* if play_back open fails, then this function
1007 is called and cpcm can actually be NULL here */
1008 if (!cpcm) return -ENXIO;
1009
1010 if (runtime->dma_area != cpcm->hw_buf.area)
1011 snd_pcm_lib_free_pages(substream);
1012
1013 runtime->dma_area = NULL;
1014 runtime->dma_addr = 0;
1015 runtime->dma_bytes = 0;
1016
1017 return 0;
1018}
1019
3d19f804 1020static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1021{
1022 unsigned int tmp;
1023 unsigned int pfie;
3d19f804
TI		 1024 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1025 struct snd_pcm_runtime *runtime = substream->runtime;
1026 struct snd_cs46xx_pcm *cpcm;
1da177e4
LT		 1027
1028 cpcm = runtime->private_data;
1029
1030#ifdef CONFIG_SND_CS46XX_NEW_DSP
1031 snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1032
1033 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1034 pfie &= ~0x0000f03f;
1035#else
1036 /* old dsp */
1037 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1038 pfie &= ~0x0000f03f;
1039#endif
1040
1041 cpcm->shift = 2;
1042 /* if to convert from stereo to mono */
1043 if (runtime->channels == 1) {
1044 cpcm->shift--;
1045 pfie |= 0x00002000;
1046 }
1047 /* if to convert from 8 bit to 16 bit */
1048 if (snd_pcm_format_width(runtime->format) == 8) {
1049 cpcm->shift--;
1050 pfie |= 0x00001000;
1051 }
1052 /* if to convert to unsigned */
1053 if (snd_pcm_format_unsigned(runtime->format))
1054 pfie |= 0x00008000;
1055
1056 /* Never convert byte order when sample stream is 8 bit */
1057 if (snd_pcm_format_width(runtime->format) != 8) {
1058 /* convert from big endian to little endian */
1059 if (snd_pcm_format_big_endian(runtime->format))
1060 pfie |= 0x00004000;
1061 }
1062
1063 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1064 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1065 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1066
1067#ifdef CONFIG_SND_CS46XX_NEW_DSP
1068
1069 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1070 tmp &= ~0x000003ff;
1071 tmp |= (4 << cpcm->shift) - 1;
1072 /* playback transaction count register */
1073 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1074
1075 /* playback format && interrupt enable */
1076 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1077#else
1078 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1079 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1080 tmp &= ~0x000003ff;
1081 tmp |= (4 << cpcm->shift) - 1;
1082 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1083 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1084 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1085#endif
1086
1087 return 0;
1088}
1089
3d19f804
TI		 1090static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1091 struct snd_pcm_hw_params *hw_params)
1da177e4 1092{
3d19f804
TI		 1093 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1094 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1095 int err;
1096
1097#ifdef CONFIG_SND_CS46XX_NEW_DSP
1098 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1099#endif
1100 if (runtime->periods == CS46XX_FRAGS) {
1101 if (runtime->dma_area != chip->capt.hw_buf.area)
1102 snd_pcm_lib_free_pages(substream);
1103 runtime->dma_area = chip->capt.hw_buf.area;
1104 runtime->dma_addr = chip->capt.hw_buf.addr;
1105 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1106 substream->ops = &snd_cs46xx_capture_ops;
1107 } else {
1108 if (runtime->dma_area == chip->capt.hw_buf.area) {
1109 runtime->dma_area = NULL;
1110 runtime->dma_addr = 0;
1111 runtime->dma_bytes = 0;
1112 }
1113 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1114 return err;
1115 substream->ops = &snd_cs46xx_capture_indirect_ops;
1116 }
1117
1118 return 0;
1119}
1120
3d19f804 1121static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1da177e4 1122{
3d19f804
TI		 1123 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1124 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1125
1126 if (runtime->dma_area != chip->capt.hw_buf.area)
1127 snd_pcm_lib_free_pages(substream);
1128 runtime->dma_area = NULL;
1129 runtime->dma_addr = 0;
1130 runtime->dma_bytes = 0;
1131
1132 return 0;
1133}
1134
3d19f804 1135static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1136{
3d19f804
TI		 1137 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1138 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1139
1140 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1141 chip->capt.shift = 2;
1142 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1143 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1144 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1145 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1146
1147 return 0;
1148}
1149
1150static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1151{
3d19f804 1152 struct snd_cs46xx *chip = dev_id;
1da177e4
LT		 1153 u32 status1;
1154#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1155 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1156 u32 status2;
1157 int i;
3d19f804 1158 struct snd_cs46xx_pcm *cpcm = NULL;
1da177e4
LT		 1159#endif
1160
1161 /*
1162 * Read the Interrupt Status Register to clear the interrupt
1163 */
1164 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1165 if ((status1 & 0x7fffffff) == 0) {
1166 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1167 return IRQ_NONE;
1168 }
1169
1170#ifdef CONFIG_SND_CS46XX_NEW_DSP
1171 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1172
1173 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1174 if (i <= 15) {
1175 if ( status1 & (1 << i) ) {
1176 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1177 if (chip->capt.substream)
1178 snd_pcm_period_elapsed(chip->capt.substream);
1179 } else {
1180 if (ins->pcm_channels[i].active &&
1181 ins->pcm_channels[i].private_data &&
1182 !ins->pcm_channels[i].unlinked) {
1183 cpcm = ins->pcm_channels[i].private_data;
1184 snd_pcm_period_elapsed(cpcm->substream);
1185 }
1186 }
1187 }
1188 } else {
1189 if ( status2 & (1 << (i - 16))) {
1190 if (ins->pcm_channels[i].active &&
1191 ins->pcm_channels[i].private_data &&
1192 !ins->pcm_channels[i].unlinked) {
1193 cpcm = ins->pcm_channels[i].private_data;
1194 snd_pcm_period_elapsed(cpcm->substream);
1195 }
1196 }
1197 }
1198 }
1199
1200#else
1201 /* old dsp */
1202 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1203 if (chip->playback_pcm->substream)
1204 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1205 }
1206 if ((status1 & HISR_VC1) && chip->pcm) {
1207 if (chip->capt.substream)
1208 snd_pcm_period_elapsed(chip->capt.substream);
1209 }
1210#endif
1211
1212 if ((status1 & HISR_MIDI) && chip->rmidi) {
1213 unsigned char c;
1214
1215 spin_lock(&chip->reg_lock);
1216 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1217 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1218 if ((chip->midcr & MIDCR_RIE) == 0)
1219 continue;
1220 snd_rawmidi_receive(chip->midi_input, &c, 1);
1221 }
1222 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1223 if ((chip->midcr & MIDCR_TIE) == 0)
1224 break;
1225 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1226 chip->midcr &= ~MIDCR_TIE;
1227 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1228 break;
1229 }
1230 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1231 }
1232 spin_unlock(&chip->reg_lock);
1233 }
1234 /*
1235 * EOI to the PCI part....reenables interrupts
1236 */
1237 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1238
1239 return IRQ_HANDLED;
1240}
1241
3d19f804 1242static struct snd_pcm_hardware snd_cs46xx_playback =
1da177e4
LT		 1243{
1244 .info = (SNDRV_PCM_INFO_MMAP |
1245 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c
JK		 1246 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1247 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT		 1248 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1249 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1250 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1251 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1252 .rate_min = 5500,
1253 .rate_max = 48000,
1254 .channels_min = 1,
1255 .channels_max = 2,
1256 .buffer_bytes_max = (256 * 1024),
1257 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1258 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1259 .periods_min = CS46XX_FRAGS,
1260 .periods_max = 1024,
1261 .fifo_size = 0,
1262};
1263
3d19f804 1264static struct snd_pcm_hardware snd_cs46xx_capture =
1da177e4
LT		 1265{
1266 .info = (SNDRV_PCM_INFO_MMAP |
1267 SNDRV_PCM_INFO_INTERLEAVED |
41e4845c
JK		 1268 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1269 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT		 1270 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1271 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1272 .rate_min = 5500,
1273 .rate_max = 48000,
1274 .channels_min = 2,
1275 .channels_max = 2,
1276 .buffer_bytes_max = (256 * 1024),
1277 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1278 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1279 .periods_min = CS46XX_FRAGS,
1280 .periods_max = 1024,
1281 .fifo_size = 0,
1282};
1283
1284#ifdef CONFIG_SND_CS46XX_NEW_DSP
1285
1286static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1287
3d19f804 1288static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1da177e4
LT		 1289 .count = ARRAY_SIZE(period_sizes),
1290 .list = period_sizes,
1291 .mask = 0
1292};
1293
1294#endif
1295
3d19f804 1296static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1da177e4 1297{
4d572776 1298 kfree(runtime->private_data);
1da177e4
LT		 1299}
1300
3d19f804 1301static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1da177e4 1302{
3d19f804
TI		 1303 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1304 struct snd_cs46xx_pcm * cpcm;
1305 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1306
e560d8d8 1307 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1da177e4
LT		 1308 if (cpcm == NULL)
1309 return -ENOMEM;
1310 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1311 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1312 kfree(cpcm);
1313 return -ENOMEM;
1314 }
1315
1316 runtime->hw = snd_cs46xx_playback;
1317 runtime->private_data = cpcm;
1318 runtime->private_free = snd_cs46xx_pcm_free_substream;
1319
1320 cpcm->substream = substream;
1321#ifdef CONFIG_SND_CS46XX_NEW_DSP
1322 down (&chip->spos_mutex);
1323 cpcm->pcm_channel = NULL;
1324 cpcm->pcm_channel_id = pcm_channel_id;
1325
1326
1327 snd_pcm_hw_constraint_list(runtime, 0,
1328 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1329 &hw_constraints_period_sizes);
1330
1331 up (&chip->spos_mutex);
1332#else
1333 chip->playback_pcm = cpcm; /* HACK */
1334#endif
1335
1336 if (chip->accept_valid)
1337 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1338 chip->active_ctrl(chip, 1);
1339
1340 return 0;
1341}
1342
3d19f804 1343static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1344{
1345 snd_printdd("open front channel\n");
1346 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1347}
1348
1349#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1350static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1da177e4
LT		 1351{
1352 snd_printdd("open rear channel\n");
1353
1354 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1355}
1356
3d19f804 1357static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1da177e4
LT		 1358{
1359 snd_printdd("open center - LFE channel\n");
1360
1361 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1362}
1363
3d19f804 1364static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1da177e4 1365{
3d19f804 1366 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1367
1368 snd_printdd("open raw iec958 channel\n");
1369
1370 down (&chip->spos_mutex);
1371 cs46xx_iec958_pre_open (chip);
1372 up (&chip->spos_mutex);
1373
1374 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1375}
1376
3d19f804 1377static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1da177e4 1378
3d19f804 1379static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1da177e4
LT		 1380{
1381 int err;
3d19f804 1382 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1383
1384 snd_printdd("close raw iec958 channel\n");
1385
1386 err = snd_cs46xx_playback_close(substream);
1387
1388 down (&chip->spos_mutex);
1389 cs46xx_iec958_post_close (chip);
1390 up (&chip->spos_mutex);
1391
1392 return err;
1393}
1394#endif
1395
3d19f804 1396static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1da177e4 1397{
3d19f804 1398 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1399
1400 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1401 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1402 return -ENOMEM;
1403 chip->capt.substream = substream;
1404 substream->runtime->hw = snd_cs46xx_capture;
1405
1406 if (chip->accept_valid)
1407 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1408
1409 chip->active_ctrl(chip, 1);
1410
1411#ifdef CONFIG_SND_CS46XX_NEW_DSP
1412 snd_pcm_hw_constraint_list(substream->runtime, 0,
1413 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1414 &hw_constraints_period_sizes);
1415#endif
1416 return 0;
1417}
1418
3d19f804 1419static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1da177e4 1420{
3d19f804
TI		 1421 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1422 struct snd_pcm_runtime *runtime = substream->runtime;
1423 struct snd_cs46xx_pcm * cpcm;
1da177e4
LT		 1424
1425 cpcm = runtime->private_data;
1426
1427 /* when playback_open fails, then cpcm can be NULL */
1428 if (!cpcm) return -ENXIO;
1429
1430#ifdef CONFIG_SND_CS46XX_NEW_DSP
1431 down (&chip->spos_mutex);
1432 if (cpcm->pcm_channel) {
1433 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1434 cpcm->pcm_channel = NULL;
1435 }
1436 up (&chip->spos_mutex);
1437#else
1438 chip->playback_pcm = NULL;
1439#endif
1440
1441 cpcm->substream = NULL;
1442 snd_dma_free_pages(&cpcm->hw_buf);
1443 chip->active_ctrl(chip, -1);
1444
1445 return 0;
1446}
1447
3d19f804 1448static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1da177e4 1449{
3d19f804 1450 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1451
1452 chip->capt.substream = NULL;
1453 snd_dma_free_pages(&chip->capt.hw_buf);
1454 chip->active_ctrl(chip, -1);
1455
1456 return 0;
1457}
1458
1459#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1460static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1da177e4
LT		 1461 .open = snd_cs46xx_playback_open_rear,
1462 .close = snd_cs46xx_playback_close,
1463 .ioctl = snd_pcm_lib_ioctl,
1464 .hw_params = snd_cs46xx_playback_hw_params,
1465 .hw_free = snd_cs46xx_playback_hw_free,
1466 .prepare = snd_cs46xx_playback_prepare,
1467 .trigger = snd_cs46xx_playback_trigger,
1468 .pointer = snd_cs46xx_playback_direct_pointer,
1469};
1470
3d19f804 1471static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1da177e4
LT		 1472 .open = snd_cs46xx_playback_open_rear,
1473 .close = snd_cs46xx_playback_close,
1474 .ioctl = snd_pcm_lib_ioctl,
1475 .hw_params = snd_cs46xx_playback_hw_params,
1476 .hw_free = snd_cs46xx_playback_hw_free,
1477 .prepare = snd_cs46xx_playback_prepare,
1478 .trigger = snd_cs46xx_playback_trigger,
1479 .pointer = snd_cs46xx_playback_indirect_pointer,
1480 .ack = snd_cs46xx_playback_transfer,
1481};
1482
3d19f804 1483static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1da177e4
LT		 1484 .open = snd_cs46xx_playback_open_clfe,
1485 .close = snd_cs46xx_playback_close,
1486 .ioctl = snd_pcm_lib_ioctl,
1487 .hw_params = snd_cs46xx_playback_hw_params,
1488 .hw_free = snd_cs46xx_playback_hw_free,
1489 .prepare = snd_cs46xx_playback_prepare,
1490 .trigger = snd_cs46xx_playback_trigger,
1491 .pointer = snd_cs46xx_playback_direct_pointer,
1492};
1493
3d19f804 1494static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1da177e4
LT		 1495 .open = snd_cs46xx_playback_open_clfe,
1496 .close = snd_cs46xx_playback_close,
1497 .ioctl = snd_pcm_lib_ioctl,
1498 .hw_params = snd_cs46xx_playback_hw_params,
1499 .hw_free = snd_cs46xx_playback_hw_free,
1500 .prepare = snd_cs46xx_playback_prepare,
1501 .trigger = snd_cs46xx_playback_trigger,
1502 .pointer = snd_cs46xx_playback_indirect_pointer,
1503 .ack = snd_cs46xx_playback_transfer,
1504};
1505
3d19f804 1506static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1da177e4
LT		 1507 .open = snd_cs46xx_playback_open_iec958,
1508 .close = snd_cs46xx_playback_close_iec958,
1509 .ioctl = snd_pcm_lib_ioctl,
1510 .hw_params = snd_cs46xx_playback_hw_params,
1511 .hw_free = snd_cs46xx_playback_hw_free,
1512 .prepare = snd_cs46xx_playback_prepare,
1513 .trigger = snd_cs46xx_playback_trigger,
1514 .pointer = snd_cs46xx_playback_direct_pointer,
1515};
1516
3d19f804 1517static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1da177e4
LT		 1518 .open = snd_cs46xx_playback_open_iec958,
1519 .close = snd_cs46xx_playback_close_iec958,
1520 .ioctl = snd_pcm_lib_ioctl,
1521 .hw_params = snd_cs46xx_playback_hw_params,
1522 .hw_free = snd_cs46xx_playback_hw_free,
1523 .prepare = snd_cs46xx_playback_prepare,
1524 .trigger = snd_cs46xx_playback_trigger,
1525 .pointer = snd_cs46xx_playback_indirect_pointer,
1526 .ack = snd_cs46xx_playback_transfer,
1527};
1528
1529#endif
1530
3d19f804 1531static struct snd_pcm_ops snd_cs46xx_playback_ops = {
1da177e4
LT		 1532 .open = snd_cs46xx_playback_open,
1533 .close = snd_cs46xx_playback_close,
1534 .ioctl = snd_pcm_lib_ioctl,
1535 .hw_params = snd_cs46xx_playback_hw_params,
1536 .hw_free = snd_cs46xx_playback_hw_free,
1537 .prepare = snd_cs46xx_playback_prepare,
1538 .trigger = snd_cs46xx_playback_trigger,
1539 .pointer = snd_cs46xx_playback_direct_pointer,
1540};
1541
3d19f804 1542static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1da177e4
LT		 1543 .open = snd_cs46xx_playback_open,
1544 .close = snd_cs46xx_playback_close,
1545 .ioctl = snd_pcm_lib_ioctl,
1546 .hw_params = snd_cs46xx_playback_hw_params,
1547 .hw_free = snd_cs46xx_playback_hw_free,
1548 .prepare = snd_cs46xx_playback_prepare,
1549 .trigger = snd_cs46xx_playback_trigger,
1550 .pointer = snd_cs46xx_playback_indirect_pointer,
1551 .ack = snd_cs46xx_playback_transfer,
1552};
1553
3d19f804 1554static struct snd_pcm_ops snd_cs46xx_capture_ops = {
1da177e4
LT		 1555 .open = snd_cs46xx_capture_open,
1556 .close = snd_cs46xx_capture_close,
1557 .ioctl = snd_pcm_lib_ioctl,
1558 .hw_params = snd_cs46xx_capture_hw_params,
1559 .hw_free = snd_cs46xx_capture_hw_free,
1560 .prepare = snd_cs46xx_capture_prepare,
1561 .trigger = snd_cs46xx_capture_trigger,
1562 .pointer = snd_cs46xx_capture_direct_pointer,
1563};
1564
3d19f804 1565static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1da177e4
LT		 1566 .open = snd_cs46xx_capture_open,
1567 .close = snd_cs46xx_capture_close,
1568 .ioctl = snd_pcm_lib_ioctl,
1569 .hw_params = snd_cs46xx_capture_hw_params,
1570 .hw_free = snd_cs46xx_capture_hw_free,
1571 .prepare = snd_cs46xx_capture_prepare,
1572 .trigger = snd_cs46xx_capture_trigger,
1573 .pointer = snd_cs46xx_capture_indirect_pointer,
1574 .ack = snd_cs46xx_capture_transfer,
1575};
1576
1da177e4 1577#ifdef CONFIG_SND_CS46XX_NEW_DSP
1da177e4
LT		 1578#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1579#else
1580#define MAX_PLAYBACK_CHANNELS 1
1581#endif
1582
3d19f804 1583int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1584{
3d19f804 1585 struct snd_pcm *pcm;
1da177e4
LT		 1586 int err;
1587
1588 if (rpcm)
1589 *rpcm = NULL;
1590 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1591 return err;
1592
1593 pcm->private_data = chip;
1da177e4
LT		 1594
1595 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1596 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1597
1598 /* global setup */
1599 pcm->info_flags = 0;
1600 strcpy(pcm->name, "CS46xx");
1601 chip->pcm = pcm;
1602
1603 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1604 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1605
1606 if (rpcm)
1607 *rpcm = pcm;
1608
1609 return 0;
1610}
1611
1612
1613#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 1614int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1615{
3d19f804 1616 struct snd_pcm *pcm;
1da177e4
LT		 1617 int err;
1618
1619 if (rpcm)
1620 *rpcm = NULL;
1621
1622 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1623 return err;
1624
1625 pcm->private_data = chip;
1da177e4
LT		 1626
1627 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1628
1629 /* global setup */
1630 pcm->info_flags = 0;
1631 strcpy(pcm->name, "CS46xx - Rear");
1632 chip->pcm_rear = pcm;
1633
1634 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1635 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1636
1637 if (rpcm)
1638 *rpcm = pcm;
1639
1640 return 0;
1641}
1642
3d19f804 1643int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1644{
3d19f804 1645 struct snd_pcm *pcm;
1da177e4
LT		 1646 int err;
1647
1648 if (rpcm)
1649 *rpcm = NULL;
1650
1651 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1652 return err;
1653
1654 pcm->private_data = chip;
1da177e4
LT		 1655
1656 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1657
1658 /* global setup */
1659 pcm->info_flags = 0;
1660 strcpy(pcm->name, "CS46xx - Center LFE");
1661 chip->pcm_center_lfe = pcm;
1662
1663 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1664 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1665
1666 if (rpcm)
1667 *rpcm = pcm;
1668
1669 return 0;
1670}
1671
3d19f804 1672int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1da177e4 1673{
3d19f804 1674 struct snd_pcm *pcm;
1da177e4
LT		 1675 int err;
1676
1677 if (rpcm)
1678 *rpcm = NULL;
1679
1680 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1681 return err;
1682
1683 pcm->private_data = chip;
1da177e4
LT		 1684
1685 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1686
1687 /* global setup */
1688 pcm->info_flags = 0;
1689 strcpy(pcm->name, "CS46xx - IEC958");
1690 chip->pcm_rear = pcm;
1691
1692 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1693 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1694
1695 if (rpcm)
1696 *rpcm = pcm;
1697
1698 return 0;
1699}
1700#endif
1701
1702/*
1703 * Mixer routines
1704 */
3d19f804 1705static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1706{
3d19f804 1707 struct snd_cs46xx *chip = bus->private_data;
1da177e4
LT		 1708
1709 chip->ac97_bus = NULL;
1710}
1711
3d19f804 1712static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1713{
3d19f804 1714 struct snd_cs46xx *chip = ac97->private_data;
1da177e4
LT		 1715
1716 snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1717 (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1718 return);
1719
1720 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1721 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1722 chip->eapd_switch = NULL;
1723 }
1724 else
1725 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1726}
1727
3d19f804
TI		 1728static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1729 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1730{
1731 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1732 uinfo->count = 2;
1733 uinfo->value.integer.min = 0;
1734 uinfo->value.integer.max = 0x7fff;
1735 return 0;
1736}
1737
3d19f804 1738static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1739{
3d19f804 1740 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1741 int reg = kcontrol->private_value;
1742 unsigned int val = snd_cs46xx_peek(chip, reg);
1743 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1744 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1745 return 0;
1746}
1747
3d19f804 1748static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1749{
3d19f804 1750 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1751 int reg = kcontrol->private_value;
1752 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1753 (0xffff - ucontrol->value.integer.value[1]));
1754 unsigned int old = snd_cs46xx_peek(chip, reg);
1755 int change = (old != val);
1756
1757 if (change) {
1758 snd_cs46xx_poke(chip, reg, val);
1759 }
1760
1761 return change;
1762}
1763
1764#ifdef CONFIG_SND_CS46XX_NEW_DSP
1765
3d19f804 1766static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1767{
3d19f804 1768 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1769
1770 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1771 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1772
1773 return 0;
1774}
1775
3d19f804 1776static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1777{
3d19f804 1778 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1779 int change = 0;
1780
1781 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1782 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1783 cs46xx_dsp_set_dac_volume(chip,
1784 ucontrol->value.integer.value[0],
1785 ucontrol->value.integer.value[1]);
1786 change = 1;
1787 }
1788
1789 return change;
1790}
1791
1792#if 0
3d19f804 1793static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1794{
3d19f804 1795 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1796
1797 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1798 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1799 return 0;
1800}
1801
3d19f804 1802static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1803{
3d19f804 1804 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1805 int change = 0;
1806
1807 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1808 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1809 cs46xx_dsp_set_iec958_volume (chip,
1810 ucontrol->value.integer.value[0],
1811 ucontrol->value.integer.value[1]);
1812 change = 1;
1813 }
1814
1815 return change;
1816}
1817#endif
1818
3d19f804
TI		 1819static int snd_mixer_boolean_info(struct snd_kcontrol *kcontrol,
1820 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1821{
1822 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1823 uinfo->count = 1;
1824 uinfo->value.integer.min = 0;
1825 uinfo->value.integer.max = 1;
1826 return 0;
1827}
1828
3d19f804
TI		 1829static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1830 struct snd_ctl_elem_value *ucontrol)
1da177e4 1831{
3d19f804 1832 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1833 int reg = kcontrol->private_value;
1834
1835 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1836 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1837 else
1838 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1839
1840 return 0;
1841}
1842
3d19f804
TI		 1843static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1844 struct snd_ctl_elem_value *ucontrol)
1da177e4 1845{
3d19f804 1846 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1847 int change, res;
1848
1849 switch (kcontrol->private_value) {
1850 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1851 down (&chip->spos_mutex);
1852 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1853 if (ucontrol->value.integer.value[0] && !change)
1854 cs46xx_dsp_enable_spdif_out(chip);
1855 else if (change && !ucontrol->value.integer.value[0])
1856 cs46xx_dsp_disable_spdif_out(chip);
1857
1858 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1859 up (&chip->spos_mutex);
1860 break;
1861 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1862 change = chip->dsp_spos_instance->spdif_status_in;
1863 if (ucontrol->value.integer.value[0] && !change) {
1864 cs46xx_dsp_enable_spdif_in(chip);
1865 /* restore volume */
1866 }
1867 else if (change && !ucontrol->value.integer.value[0])
1868 cs46xx_dsp_disable_spdif_in(chip);
1869
1870 res = (change != chip->dsp_spos_instance->spdif_status_in);
1871 break;
1872 default:
1873 res = -EINVAL;
1874 snd_assert(0, (void)0);
1875 }
1876
1877 return res;
1878}
1879
3d19f804
TI		 1880static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
1881 struct snd_ctl_elem_value *ucontrol)
1da177e4 1882{
3d19f804
TI		 1883 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1884 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1885
1886 if (ins->adc_input != NULL)
1887 ucontrol->value.integer.value[0] = 1;
1888 else
1889 ucontrol->value.integer.value[0] = 0;
1890
1891 return 0;
1892}
1893
3d19f804
TI		 1894static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_value *ucontrol)
1da177e4 1896{
3d19f804
TI		 1897 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1898 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1899 int change = 0;
1900
1901 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1902 cs46xx_dsp_enable_adc_capture(chip);
1903 change = 1;
1904 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1905 cs46xx_dsp_disable_adc_capture(chip);
1906 change = 1;
1907 }
1908 return change;
1909}
1910
3d19f804
TI		 1911static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
1912 struct snd_ctl_elem_value *ucontrol)
1da177e4 1913{
3d19f804
TI		 1914 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1915 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1916
1917 if (ins->pcm_input != NULL)
1918 ucontrol->value.integer.value[0] = 1;
1919 else
1920 ucontrol->value.integer.value[0] = 0;
1921
1922 return 0;
1923}
1924
1925
3d19f804
TI		 1926static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
1927 struct snd_ctl_elem_value *ucontrol)
1da177e4 1928{
3d19f804
TI		 1929 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1930 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1931 int change = 0;
1932
1933 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1934 cs46xx_dsp_enable_pcm_capture(chip);
1935 change = 1;
1936 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1937 cs46xx_dsp_disable_pcm_capture(chip);
1938 change = 1;
1939 }
1940
1941 return change;
1942}
1943
3d19f804
TI		 1944static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
1945 struct snd_ctl_elem_value *ucontrol)
1da177e4 1946{
3d19f804 1947 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1948
1949 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1950
1951 if (val1 & EGPIODR_GPOE0)
1952 ucontrol->value.integer.value[0] = 1;
1953 else
1954 ucontrol->value.integer.value[0] = 0;
1955
1956 return 0;
1957}
1958
1959/*
1960 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1961 */
3d19f804
TI		 1962static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
1963 struct snd_ctl_elem_value *ucontrol)
1da177e4 1964{
3d19f804 1965 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1966 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1967 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
1968
1969 if (ucontrol->value.integer.value[0]) {
1970 /* optical is default */
1971 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
1972 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
1973 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
1974 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
1975 } else {
1976 /* coaxial */
1977 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
1978 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
1979 }
1980
1981 /* checking diff from the EGPIO direction register
1982 should be enough */
1983 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
1984}
1985
1986
3d19f804 1987static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1988{
1989 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1990 uinfo->count = 1;
1991 return 0;
1992}
1993
3d19f804
TI		 1994static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
1995 struct snd_ctl_elem_value *ucontrol)
1da177e4 1996{
3d19f804
TI		 1997 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1998 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 1999
2000 down (&chip->spos_mutex);
2001 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2002 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2003 ucontrol->value.iec958.status[2] = 0;
2004 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2005 up (&chip->spos_mutex);
2006
2007 return 0;
2008}
2009
3d19f804
TI		 2010static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2011 struct snd_ctl_elem_value *ucontrol)
1da177e4 2012{
3d19f804
TI		 2013 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2014 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2015 unsigned int val;
2016 int change;
2017
2018 down (&chip->spos_mutex);
2019 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2020 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2021 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2022 /* left and right validity bit */
2023 (1 << 13) | (1 << 12);
2024
2025
2026 change = (unsigned int)ins->spdif_csuv_default != val;
2027 ins->spdif_csuv_default = val;
2028
2029 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2030 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2031
2032 up (&chip->spos_mutex);
2033
2034 return change;
2035}
2036
3d19f804
TI		 2037static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2038 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2039{
2040 ucontrol->value.iec958.status[0] = 0xff;
2041 ucontrol->value.iec958.status[1] = 0xff;
2042 ucontrol->value.iec958.status[2] = 0x00;
2043 ucontrol->value.iec958.status[3] = 0xff;
2044 return 0;
2045}
2046
3d19f804
TI		 2047static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2048 struct snd_ctl_elem_value *ucontrol)
1da177e4 2049{
3d19f804
TI		 2050 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2051 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2052
2053 down (&chip->spos_mutex);
2054 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2055 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2056 ucontrol->value.iec958.status[2] = 0;
2057 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2058 up (&chip->spos_mutex);
2059
2060 return 0;
2061}
2062
3d19f804
TI		 2063static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2064 struct snd_ctl_elem_value *ucontrol)
1da177e4 2065{
3d19f804
TI		 2066 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2067 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1da177e4
LT		 2068 unsigned int val;
2069 int change;
2070
2071 down (&chip->spos_mutex);
2072 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2073 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2074 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2075 /* left and right validity bit */
2076 (1 << 13) | (1 << 12);
2077
2078
2079 change = ins->spdif_csuv_stream != val;
2080 ins->spdif_csuv_stream = val;
2081
2082 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2083 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2084
2085 up (&chip->spos_mutex);
2086
2087 return change;
2088}
2089
2090#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2091
2092
2093#ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
3d19f804
TI		 2094static int snd_cs46xx_egpio_select_info(struct snd_kcontrol *kcontrol,
2095 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2096{
2097 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2098 uinfo->count = 1;
2099 uinfo->value.integer.min = 0;
2100 uinfo->value.integer.max = 8;
2101 return 0;
2102}
2103
3d19f804
TI		 2104static int snd_cs46xx_egpio_select_get(struct snd_kcontrol *kcontrol,
2105 struct snd_ctl_elem_value *ucontrol)
1da177e4 2106{
3d19f804 2107 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2108 ucontrol->value.integer.value[0] = chip->current_gpio;
2109
2110 return 0;
2111}
2112
3d19f804
TI		 2113static int snd_cs46xx_egpio_select_put(struct snd_kcontrol *kcontrol,
2114 struct snd_ctl_elem_value *ucontrol)
1da177e4 2115{
3d19f804 2116 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2117 int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2118 chip->current_gpio = ucontrol->value.integer.value[0];
2119
2120 return change;
2121}
2122
2123
3d19f804
TI		 2124static int snd_cs46xx_egpio_get(struct snd_kcontrol *kcontrol,
2125 struct snd_ctl_elem_value *ucontrol)
1da177e4 2126{
3d19f804 2127 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2128 int reg = kcontrol->private_value;
2129
2130 snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2131 ucontrol->value.integer.value[0] =
2132 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2133
2134 return 0;
2135}
2136
3d19f804
TI		 2137static int snd_cs46xx_egpio_put(struct snd_kcontrol *kcontrol,
2138 struct snd_ctl_elem_value *ucontrol)
1da177e4 2139{
3d19f804 2140 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2141 int reg = kcontrol->private_value;
2142 int val = snd_cs46xx_peekBA0(chip, reg);
2143 int oldval = val;
2144 snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2145
2146 if (ucontrol->value.integer.value[0])
2147 val |= (1 << chip->current_gpio);
2148 else
2149 val &= ~(1 << chip->current_gpio);
2150
2151 snd_cs46xx_pokeBA0(chip, reg,val);
2152 snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2153
2154 return (oldval != val);
2155}
2156#endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2157
3d19f804 2158static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = {
1da177e4
LT		 2159{
2160 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2161 .name = "DAC Volume",
2162 .info = snd_cs46xx_vol_info,
2163#ifndef CONFIG_SND_CS46XX_NEW_DSP
2164 .get = snd_cs46xx_vol_get,
2165 .put = snd_cs46xx_vol_put,
2166 .private_value = BA1_PVOL,
2167#else
2168 .get = snd_cs46xx_vol_dac_get,
2169 .put = snd_cs46xx_vol_dac_put,
2170#endif
2171},
2172
2173{
2174 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2175 .name = "ADC Volume",
2176 .info = snd_cs46xx_vol_info,
2177 .get = snd_cs46xx_vol_get,
2178 .put = snd_cs46xx_vol_put,
2179#ifndef CONFIG_SND_CS46XX_NEW_DSP
2180 .private_value = BA1_CVOL,
2181#else
2182 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2183#endif
2184},
2185#ifdef CONFIG_SND_CS46XX_NEW_DSP
2186{
2187 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2188 .name = "ADC Capture Switch",
2189 .info = snd_mixer_boolean_info,
2190 .get = snd_cs46xx_adc_capture_get,
2191 .put = snd_cs46xx_adc_capture_put
2192},
2193{
2194 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2195 .name = "DAC Capture Switch",
2196 .info = snd_mixer_boolean_info,
2197 .get = snd_cs46xx_pcm_capture_get,
2198 .put = snd_cs46xx_pcm_capture_put
2199},
2200{
2201 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2202 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
1da177e4
LT		 2203 .info = snd_mixer_boolean_info,
2204 .get = snd_cs46xx_iec958_get,
2205 .put = snd_cs46xx_iec958_put,
2206 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2207},
2208{
2209 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2210 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
1da177e4
LT		 2211 .info = snd_mixer_boolean_info,
2212 .get = snd_cs46xx_iec958_get,
2213 .put = snd_cs46xx_iec958_put,
2214 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2215},
2216#if 0
2217/* Input IEC958 volume does not work for the moment. (Benny) */
2218{
2219 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
10e8d78a 2220 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
1da177e4
LT		 2221 .info = snd_cs46xx_vol_info,
2222 .get = snd_cs46xx_vol_iec958_get,
2223 .put = snd_cs46xx_vol_iec958_put,
2224 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2225},
2226#endif
2227{
2228 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2229 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2230 .info = snd_cs46xx_spdif_info,
2231 .get = snd_cs46xx_spdif_default_get,
2232 .put = snd_cs46xx_spdif_default_put,
2233},
2234{
2235 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2236 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2237 .info = snd_cs46xx_spdif_info,
2238 .get = snd_cs46xx_spdif_mask_get,
2239 .access = SNDRV_CTL_ELEM_ACCESS_READ
2240},
2241{
2242 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2243 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2244 .info = snd_cs46xx_spdif_info,
2245 .get = snd_cs46xx_spdif_stream_get,
2246 .put = snd_cs46xx_spdif_stream_put
2247},
2248
2249#endif
2250#ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2251{
2252 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2253 .name = "EGPIO select",
2254 .info = snd_cs46xx_egpio_select_info,
2255 .get = snd_cs46xx_egpio_select_get,
2256 .put = snd_cs46xx_egpio_select_put,
2257 .private_value = 0,
2258},
2259{
2260 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2261 .name = "EGPIO Input/Output",
2262 .info = snd_mixer_boolean_info,
2263 .get = snd_cs46xx_egpio_get,
2264 .put = snd_cs46xx_egpio_put,
2265 .private_value = BA0_EGPIODR,
2266},
2267{
2268 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2269 .name = "EGPIO CMOS/Open drain",
2270 .info = snd_mixer_boolean_info,
2271 .get = snd_cs46xx_egpio_get,
2272 .put = snd_cs46xx_egpio_put,
2273 .private_value = BA0_EGPIOPTR,
2274},
2275{
2276 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2277 .name = "EGPIO On/Off",
2278 .info = snd_mixer_boolean_info,
2279 .get = snd_cs46xx_egpio_get,
2280 .put = snd_cs46xx_egpio_put,
2281 .private_value = BA0_EGPIOSR,
2282},
2283#endif
2284};
2285
2286#ifdef CONFIG_SND_CS46XX_NEW_DSP
2287/* set primary cs4294 codec into Extended Audio Mode */
3d19f804
TI		 2288static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2289 struct snd_ctl_elem_value *ucontrol)
1da177e4 2290{
3d19f804 2291 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2292 unsigned short val;
2293 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2294 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2295 return 0;
2296}
2297
3d19f804
TI		 2298static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2299 struct snd_ctl_elem_value *ucontrol)
1da177e4 2300{
3d19f804 2301 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2302 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2303 AC97_CSR_ACMODE, 0x200,
2304 ucontrol->value.integer.value[0] ? 0 : 0x200);
2305}
2306
3d19f804 2307static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
1da177e4
LT		 2308 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2309 .name = "Duplicate Front",
2310 .info = snd_mixer_boolean_info,
2311 .get = snd_cs46xx_front_dup_get,
2312 .put = snd_cs46xx_front_dup_put,
2313};
2314#endif
2315
2316#ifdef CONFIG_SND_CS46XX_NEW_DSP
2317/* Only available on the Hercules Game Theater XP soundcard */
3d19f804 2318static struct snd_kcontrol_new snd_hercules_controls[] __devinitdata = {
1da177e4
LT		 2319{
2320 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2321 .name = "Optical/Coaxial SPDIF Input Switch",
2322 .info = snd_mixer_boolean_info,
2323 .get = snd_herc_spdif_select_get,
2324 .put = snd_herc_spdif_select_put,
2325},
2326};
2327
2328
3d19f804 2329static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
1da177e4
LT		 2330{
2331 unsigned long end_time;
2332 int err;
2333
2334 /* reset to defaults */
2335 snd_ac97_write(ac97, AC97_RESET, 0);
2336
2337 /* set the desired CODEC mode */
2338 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2339 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2340 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2341 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2342 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2343 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2344 } else {
2345 snd_assert(0); /* should never happen ... */
2346 }
2347
2348 udelay(50);
2349
2350 /* it's necessary to wait awhile until registers are accessible after RESET */
2351 /* because the PCM or MASTER volume registers can be modified, */
2352 /* the REC_GAIN register is used for tests */
2353 end_time = jiffies + HZ;
2354 do {
2355 unsigned short ext_mid;
2356
2357 /* use preliminary reads to settle the communication */
2358 snd_ac97_read(ac97, AC97_RESET);
2359 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2360 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2361 /* modem? */
2362 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2363 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2364 return;
2365
2366 /* test if we can write to the record gain volume register */
2367 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2368 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2369 return;
2370
ef21ca24 2371 msleep(10);
1da177e4
LT		 2372 } while (time_after_eq(end_time, jiffies));
2373
99b359ba 2374 snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n");
1da177e4
LT		 2375}
2376#endif
2377
3d19f804 2378static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
1da177e4
LT		 2379{
2380 int idx, err;
3d19f804 2381 struct snd_ac97_template ac97;
1da177e4
LT		 2382
2383 memset(&ac97, 0, sizeof(ac97));
2384 ac97.private_data = chip;
2385 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2386 ac97.num = codec;
2387 if (chip->amplifier_ctrl == amp_voyetra)
2388 ac97.scaps = AC97_SCAP_INV_EAPD;
2389
2390 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2391 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2392 udelay(10);
2393 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2394 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2395 return -ENXIO;
2396 }
2397 }
2398
2399 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2400 for (idx = 0; idx < 100; ++idx) {
2401 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2402 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2403 return err;
2404 }
ef21ca24 2405 msleep(10);
1da177e4
LT		 2406 }
2407 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2408 return -ENXIO;
2409}
2410
3d19f804 2411int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
1da177e4 2412{
3d19f804
TI		 2413 struct snd_card *card = chip->card;
2414 struct snd_ctl_elem_id id;
1da177e4
LT		 2415 int err;
2416 unsigned int idx;
3d19f804 2417 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 2418#ifdef CONFIG_SND_CS46XX_NEW_DSP
2419 .reset = snd_cs46xx_codec_reset,
2420#endif
2421 .write = snd_cs46xx_ac97_write,
2422 .read = snd_cs46xx_ac97_read,
2423 };
2424
2425 /* detect primary codec */
2426 chip->nr_ac97_codecs = 0;
2427 snd_printdd("snd_cs46xx: detecting primary codec\n");
2428 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2429 return err;
2430 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2431
2432 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2433 return -ENXIO;
2434 chip->nr_ac97_codecs = 1;
2435
2436#ifdef CONFIG_SND_CS46XX_NEW_DSP
2437 snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2438 /* try detect a secondary codec */
2439 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2440 chip->nr_ac97_codecs = 2;
2441#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2442
2443 /* add cs4630 mixer controls */
2444 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
3d19f804 2445 struct snd_kcontrol *kctl;
1da177e4 2446 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
67ed4161
CL		 2447 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2448 kctl->id.device = spdif_device;
1da177e4
LT		 2449 if ((err = snd_ctl_add(card, kctl)) < 0)
2450 return err;
2451 }
2452
2453 /* get EAPD mixer switch (for voyetra hack) */
2454 memset(&id, 0, sizeof(id));
2455 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2456 strcpy(id.name, "External Amplifier");
2457 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2458
2459#ifdef CONFIG_SND_CS46XX_NEW_DSP
2460 if (chip->nr_ac97_codecs == 1) {
2461 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2462 if (id2 == 0x592b || id2 == 0x592d) {
2463 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2464 if (err < 0)
2465 return err;
2466 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2467 AC97_CSR_ACMODE, 0x200);
2468 }
2469 }
2470 /* do soundcard specific mixer setup */
2471 if (chip->mixer_init) {
2472 snd_printdd ("calling chip->mixer_init(chip);\n");
2473 chip->mixer_init(chip);
2474 }
2475#endif
2476
2477 /* turn on amplifier */
2478 chip->amplifier_ctrl(chip, 1);
2479
2480 return 0;
2481}
2482
2483/*
2484 * RawMIDI interface
2485 */
2486
3d19f804 2487static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
1da177e4
LT		 2488{
2489 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2490 udelay(100);
2491 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2492}
2493
3d19f804 2494static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
1da177e4 2495{
3d19f804 2496 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2497
2498 chip->active_ctrl(chip, 1);
2499 spin_lock_irq(&chip->reg_lock);
2500 chip->uartm |= CS46XX_MODE_INPUT;
2501 chip->midcr |= MIDCR_RXE;
2502 chip->midi_input = substream;
2503 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2504 snd_cs46xx_midi_reset(chip);
2505 } else {
2506 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2507 }
2508 spin_unlock_irq(&chip->reg_lock);
2509 return 0;
2510}
2511
3d19f804 2512static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
1da177e4 2513{
3d19f804 2514 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2515
2516 spin_lock_irq(&chip->reg_lock);
2517 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2518 chip->midi_input = NULL;
2519 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2520 snd_cs46xx_midi_reset(chip);
2521 } else {
2522 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2523 }
2524 chip->uartm &= ~CS46XX_MODE_INPUT;
2525 spin_unlock_irq(&chip->reg_lock);
2526 chip->active_ctrl(chip, -1);
2527 return 0;
2528}
2529
3d19f804 2530static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
1da177e4 2531{
3d19f804 2532 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2533
2534 chip->active_ctrl(chip, 1);
2535
2536 spin_lock_irq(&chip->reg_lock);
2537 chip->uartm |= CS46XX_MODE_OUTPUT;
2538 chip->midcr |= MIDCR_TXE;
2539 chip->midi_output = substream;
2540 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2541 snd_cs46xx_midi_reset(chip);
2542 } else {
2543 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2544 }
2545 spin_unlock_irq(&chip->reg_lock);
2546 return 0;
2547}
2548
3d19f804 2549static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
1da177e4 2550{
3d19f804 2551 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2552
2553 spin_lock_irq(&chip->reg_lock);
2554 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2555 chip->midi_output = NULL;
2556 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2557 snd_cs46xx_midi_reset(chip);
2558 } else {
2559 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2560 }
2561 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2562 spin_unlock_irq(&chip->reg_lock);
2563 chip->active_ctrl(chip, -1);
2564 return 0;
2565}
2566
3d19f804 2567static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2568{
2569 unsigned long flags;
3d19f804 2570 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2571
2572 spin_lock_irqsave(&chip->reg_lock, flags);
2573 if (up) {
2574 if ((chip->midcr & MIDCR_RIE) == 0) {
2575 chip->midcr |= MIDCR_RIE;
2576 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2577 }
2578 } else {
2579 if (chip->midcr & MIDCR_RIE) {
2580 chip->midcr &= ~MIDCR_RIE;
2581 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2582 }
2583 }
2584 spin_unlock_irqrestore(&chip->reg_lock, flags);
2585}
2586
3d19f804 2587static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1da177e4
LT		 2588{
2589 unsigned long flags;
3d19f804 2590 struct snd_cs46xx *chip = substream->rmidi->private_data;
1da177e4
LT		 2591 unsigned char byte;
2592
2593 spin_lock_irqsave(&chip->reg_lock, flags);
2594 if (up) {
2595 if ((chip->midcr & MIDCR_TIE) == 0) {
2596 chip->midcr |= MIDCR_TIE;
2597 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2598 while ((chip->midcr & MIDCR_TIE) &&
2599 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2600 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2601 chip->midcr &= ~MIDCR_TIE;
2602 } else {
2603 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2604 }
2605 }
2606 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2607 }
2608 } else {
2609 if (chip->midcr & MIDCR_TIE) {
2610 chip->midcr &= ~MIDCR_TIE;
2611 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2612 }
2613 }
2614 spin_unlock_irqrestore(&chip->reg_lock, flags);
2615}
2616
3d19f804 2617static struct snd_rawmidi_ops snd_cs46xx_midi_output =
1da177e4
LT		 2618{
2619 .open = snd_cs46xx_midi_output_open,
2620 .close = snd_cs46xx_midi_output_close,
2621 .trigger = snd_cs46xx_midi_output_trigger,
2622};
2623
3d19f804 2624static struct snd_rawmidi_ops snd_cs46xx_midi_input =
1da177e4
LT		 2625{
2626 .open = snd_cs46xx_midi_input_open,
2627 .close = snd_cs46xx_midi_input_close,
2628 .trigger = snd_cs46xx_midi_input_trigger,
2629};
2630
3d19f804 2631int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi)
1da177e4 2632{
3d19f804 2633 struct snd_rawmidi *rmidi;
1da177e4
LT		 2634 int err;
2635
2636 if (rrawmidi)
2637 *rrawmidi = NULL;
2638 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2639 return err;
2640 strcpy(rmidi->name, "CS46XX");
2641 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2642 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2643 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2644 rmidi->private_data = chip;
2645 chip->rmidi = rmidi;
2646 if (rrawmidi)
2647 *rrawmidi = NULL;
2648 return 0;
2649}
2650
2651
2652/*
2653 * gameport interface
2654 */
2655
2656#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2657
2658static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2659{
3d19f804 2660 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2661
2662 snd_assert(chip, return);
2663 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2664}
2665
2666static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2667{
3d19f804 2668 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2669
2670 snd_assert(chip, return 0);
2671 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2672}
2673
2674static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2675{
3d19f804 2676 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
1da177e4
LT		 2677 unsigned js1, js2, jst;
2678
2679 snd_assert(chip, return 0);
2680
2681 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2682 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2683 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2684
2685 *buttons = (~jst >> 4) & 0x0F;
2686
2687 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2688 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2689 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2690 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2691
2692 for(jst=0;jst<4;++jst)
2693 if(axes[jst]==0xFFFF) axes[jst] = -1;
2694 return 0;
2695}
2696
2697static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2698{
2699 switch (mode) {
2700 case GAMEPORT_MODE_COOKED:
2701 return 0;
2702 case GAMEPORT_MODE_RAW:
2703 return 0;
2704 default:
2705 return -1;
2706 }
2707 return 0;
2708}
2709
3d19f804 2710int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2711{
2712 struct gameport *gp;
2713
2714 chip->gameport = gp = gameport_allocate_port();
2715 if (!gp) {
2716 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
2717 return -ENOMEM;
2718 }
2719
2720 gameport_set_name(gp, "CS46xx Gameport");
2721 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2722 gameport_set_dev_parent(gp, &chip->pci->dev);
2723 gameport_set_port_data(gp, chip);
2724
2725 gp->open = snd_cs46xx_gameport_open;
2726 gp->read = snd_cs46xx_gameport_read;
2727 gp->trigger = snd_cs46xx_gameport_trigger;
2728 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2729
2730 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2731 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2732
2733 gameport_register_port(gp);
2734
2735 return 0;
2736}
2737
3d19f804 2738static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
1da177e4
LT		 2739{
2740 if (chip->gameport) {
2741 gameport_unregister_port(chip->gameport);
2742 chip->gameport = NULL;
2743 }
2744}
2745#else
3d19f804
TI		 2746int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2747static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
1da177e4
LT		 2748#endif /* CONFIG_GAMEPORT */
2749
2750/*
2751 * proc interface
2752 */
2753
3d19f804 2754static long snd_cs46xx_io_read(struct snd_info_entry *entry, void *file_private_data,
1da177e4
LT		 2755 struct file *file, char __user *buf,
2756 unsigned long count, unsigned long pos)
2757{
2758 long size;
3d19f804 2759 struct snd_cs46xx_region *region = entry->private_data;
1da177e4
LT		 2760
2761 size = count;
2762 if (pos + (size_t)size > region->size)
2763 size = region->size - pos;
2764 if (size > 0) {
2765 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2766 return -EFAULT;
2767 }
2768 return size;
2769}
2770
2771static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2772 .read = snd_cs46xx_io_read,
2773};
2774
3d19f804 2775static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
1da177e4 2776{
3d19f804 2777 struct snd_info_entry *entry;
1da177e4
LT		 2778 int idx;
2779
2780 for (idx = 0; idx < 5; idx++) {
3d19f804 2781 struct snd_cs46xx_region *region = &chip->region.idx[idx];
1da177e4
LT		 2782 if (! snd_card_proc_new(card, region->name, &entry)) {
2783 entry->content = SNDRV_INFO_CONTENT_DATA;
2784 entry->private_data = chip;
2785 entry->c.ops = &snd_cs46xx_proc_io_ops;
2786 entry->size = region->size;
2787 entry->mode = S_IFREG | S_IRUSR;
2788 }
2789 }
2790#ifdef CONFIG_SND_CS46XX_NEW_DSP
2791 cs46xx_dsp_proc_init(card, chip);
2792#endif
2793 return 0;
2794}
2795
3d19f804 2796static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
1da177e4
LT		 2797{
2798#ifdef CONFIG_SND_CS46XX_NEW_DSP
2799 cs46xx_dsp_proc_done(chip);
2800#endif
2801 return 0;
2802}
2803
2804/*
2805 * stop the h/w
2806 */
3d19f804 2807static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
1da177e4
LT		 2808{
2809 unsigned int tmp;
2810
2811 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2812 tmp &= ~0x0000f03f;
2813 tmp |= 0x00000010;
2814 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2815
2816 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2817 tmp &= ~0x0000003f;
2818 tmp |= 0x00000011;
2819 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2820
2821 /*
2822 * Stop playback DMA.
2823 */
2824 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2825 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2826
2827 /*
2828 * Stop capture DMA.
2829 */
2830 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2831 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2832
2833 /*
2834 * Reset the processor.
2835 */
2836 snd_cs46xx_reset(chip);
2837
2838 snd_cs46xx_proc_stop(chip);
2839
2840 /*
2841 * Power down the PLL.
2842 */
2843 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2844
2845 /*
2846 * Turn off the Processor by turning off the software clock enable flag in
2847 * the clock control register.
2848 */
2849 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2850 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2851}
2852
2853
3d19f804 2854static int snd_cs46xx_free(struct snd_cs46xx *chip)
1da177e4
LT		 2855{
2856 int idx;
2857
2858 snd_assert(chip != NULL, return -EINVAL);
2859
2860 if (chip->active_ctrl)
2861 chip->active_ctrl(chip, 1);
2862
2863 snd_cs46xx_remove_gameport(chip);
2864
2865 if (chip->amplifier_ctrl)
2866 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2867
2868 snd_cs46xx_proc_done(chip);
2869
2870 if (chip->region.idx[0].resource)
2871 snd_cs46xx_hw_stop(chip);
2872
2873 for (idx = 0; idx < 5; idx++) {
3d19f804 2874 struct snd_cs46xx_region *region = &chip->region.idx[idx];
1da177e4
LT		 2875 if (region->remap_addr)
2876 iounmap(region->remap_addr);
b1d5776d 2877 release_and_free_resource(region->resource);
1da177e4
LT		 2878 }
2879 if (chip->irq >= 0)
3d19f804 2880 free_irq(chip->irq, chip);
1da177e4
LT		 2881
2882 if (chip->active_ctrl)
2883 chip->active_ctrl(chip, -chip->amplifier);
2884
2885#ifdef CONFIG_SND_CS46XX_NEW_DSP
2886 if (chip->dsp_spos_instance) {
2887 cs46xx_dsp_spos_destroy(chip);
2888 chip->dsp_spos_instance = NULL;
2889 }
2890#endif
2891
2892 pci_disable_device(chip->pci);
2893 kfree(chip);
2894 return 0;
2895}
2896
3d19f804 2897static int snd_cs46xx_dev_free(struct snd_device *device)
1da177e4 2898{
3d19f804 2899 struct snd_cs46xx *chip = device->device_data;
1da177e4
LT		 2900 return snd_cs46xx_free(chip);
2901}
2902
2903/*
2904 * initialize chip
2905 */
3d19f804 2906static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
1da177e4
LT		 2907{
2908 int timeout;
2909
2910 /*
2911 * First, blast the clock control register to zero so that the PLL starts
2912 * out in a known state, and blast the master serial port control register
2913 * to zero so that the serial ports also start out in a known state.
2914 */
2915 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2916 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2917
2918 /*
2919 * If we are in AC97 mode, then we must set the part to a host controlled
2920 * AC-link. Otherwise, we won't be able to bring up the link.
2921 */
2922#ifdef CONFIG_SND_CS46XX_NEW_DSP
2923 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2924 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2925 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2926#else
2927 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2928#endif
2929
2930 /*
2931 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2932 * spec) and then drive it high. This is done for non AC97 modes since
2933 * there might be logic external to the CS461x that uses the ARST# line
2934 * for a reset.
2935 */
2936 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2937#ifdef CONFIG_SND_CS46XX_NEW_DSP
2938 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2939#endif
2940 udelay(50);
2941 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2942#ifdef CONFIG_SND_CS46XX_NEW_DSP
2943 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2944#endif
2945
2946 /*
2947 * The first thing we do here is to enable sync generation. As soon
2948 * as we start receiving bit clock, we'll start producing the SYNC
2949 * signal.
2950 */
2951 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2952#ifdef CONFIG_SND_CS46XX_NEW_DSP
2953 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2954#endif
2955
2956 /*
2957 * Now wait for a short while to allow the AC97 part to start
2958 * generating bit clock (so we don't try to start the PLL without an
2959 * input clock).
2960 */
2961 mdelay(10);
2962
2963 /*
2964 * Set the serial port timing configuration, so that
2965 * the clock control circuit gets its clock from the correct place.
2966 */
2967 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2968
2969 /*
2970 * Write the selected clock control setup to the hardware. Do not turn on
2971 * SWCE yet (if requested), so that the devices clocked by the output of
2972 * PLL are not clocked until the PLL is stable.
2973 */
2974 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2975 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2976 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2977
2978 /*
2979 * Power up the PLL.
2980 */
2981 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2982
2983 /*
2984 * Wait until the PLL has stabilized.
2985 */
ef21ca24 2986 msleep(100);
1da177e4
LT		 2987
2988 /*
2989 * Turn on clocking of the core so that we can setup the serial ports.
2990 */
2991 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2992
2993 /*
2994 * Enable FIFO Host Bypass
2995 */
2996 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
2997
2998 /*
2999 * Fill the serial port FIFOs with silence.
3000 */
3001 snd_cs46xx_clear_serial_FIFOs(chip);
3002
3003 /*
3004 * Set the serial port FIFO pointer to the first sample in the FIFO.
3005 */
3006 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3007
3008 /*
3009 * Write the serial port configuration to the part. The master
3010 * enable bit is not set until all other values have been written.
3011 */
3012 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3013 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3014 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3015
3016
3017#ifdef CONFIG_SND_CS46XX_NEW_DSP
3018 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3019 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3020 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3021 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3022 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3023#endif
3024
3025 mdelay(5);
3026
3027
3028 /*
3029 * Wait for the codec ready signal from the AC97 codec.
3030 */
3031 timeout = 150;
3032 while (timeout-- > 0) {
3033 /*
3034 * Read the AC97 status register to see if we've seen a CODEC READY
3035 * signal from the AC97 codec.
3036 */
3037 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3038 goto ok1;
ef21ca24 3039 msleep(10);
1da177e4
LT		 3040 }
3041
3042
99b359ba
TI		 3043 snd_printk(KERN_ERR "create - never read codec ready from AC'97\n");
3044 snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n");
1da177e4
LT		 3045 return -EIO;
3046 ok1:
3047#ifdef CONFIG_SND_CS46XX_NEW_DSP
3048 {
3049 int count;
3050 for (count = 0; count < 150; count++) {
3051 /* First, we want to wait for a short time. */
3052 udelay(25);
3053
3054 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3055 break;
3056 }
3057
3058 /*
3059 * Make sure CODEC is READY.
3060 */
3061 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3062 snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3063 }
3064#endif
3065
3066 /*
3067 * Assert the vaid frame signal so that we can start sending commands
3068 * to the AC97 codec.
3069 */
3070 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3071#ifdef CONFIG_SND_CS46XX_NEW_DSP
3072 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3073#endif
3074
3075
3076 /*
3077 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3078 * the codec is pumping ADC data across the AC-link.
3079 */
3080 timeout = 150;
3081 while (timeout-- > 0) {
3082 /*
3083 * Read the input slot valid register and see if input slots 3 and
3084 * 4 are valid yet.
3085 */
3086 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3087 goto ok2;
ef21ca24 3088 msleep(10);
1da177e4
LT		 3089 }
3090
3091#ifndef CONFIG_SND_CS46XX_NEW_DSP
99b359ba 3092 snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n");
1da177e4
LT		 3093 return -EIO;
3094#else
3095 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3096 Reloading the driver may help, if there's other soundcards
3097 with the same problem I would like to know. (Benny) */
3098
99b359ba
TI		 3099 snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3100 snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n");
3101 snd_printk(KERN_ERR " broken or not working on your soundcard upon\n");
3102 snd_printk(KERN_ERR " this message please report to alsa-devel@lists.sourceforge.net\n");
1da177e4
LT		 3103
3104 return -EIO;
3105#endif
3106 ok2:
3107
3108 /*
3109 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3110 * commense the transfer of digital audio data to the AC97 codec.
3111 */
3112
3113 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3114
3115
3116 /*
3117 * Power down the DAC and ADC. We will power them up (if) when we need
3118 * them.
3119 */
3120 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3121
3122 /*
3123 * Turn off the Processor by turning off the software clock enable flag in
3124 * the clock control register.
3125 */
3126 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3127 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3128
3129 return 0;
3130}
3131
3132/*
3133 * start and load DSP
3134 */
3d19f804 3135int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
1da177e4
LT		 3136{
3137 unsigned int tmp;
3138 /*
3139 * Reset the processor.
3140 */
3141 snd_cs46xx_reset(chip);
3142 /*
3143 * Download the image to the processor.
3144 */
3145#ifdef CONFIG_SND_CS46XX_NEW_DSP
3146#if 0
3147 if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3148 snd_printk(KERN_ERR "image download error\n");
3149 return -EIO;
3150 }
3151#endif
3152
3153 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3154 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3155 return -EIO;
3156 }
3157
3158 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3159 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3160 return -EIO;
3161 }
3162
3163 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3164 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3165 return -EIO;
3166 }
3167
3168 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3169 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3170 return -EIO;
3171 }
3172
3173 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3174 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3175 return -EIO;
3176 }
3177
3178 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3179 return -EIO;
3180#else
3181 /* old image */
3182 if (snd_cs46xx_download_image(chip) < 0) {
99b359ba 3183 snd_printk(KERN_ERR "image download error\n");
1da177e4
LT		 3184 return -EIO;
3185 }
3186
3187 /*
3188 * Stop playback DMA.
3189 */
3190 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3191 chip->play_ctl = tmp & 0xffff0000;
3192 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3193#endif
3194
3195 /*
3196 * Stop capture DMA.
3197 */
3198 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3199 chip->capt.ctl = tmp & 0x0000ffff;
3200 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3201
3202 mdelay(5);
3203
3204 snd_cs46xx_set_play_sample_rate(chip, 8000);
3205 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3206
3207 snd_cs46xx_proc_start(chip);
3208
3209 /*
3210 * Enable interrupts on the part.
3211 */
3212 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3213
3214 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3215 tmp &= ~0x0000f03f;
3216 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3217
3218 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3219 tmp &= ~0x0000003f;
3220 tmp |= 0x00000001;
3221 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3222
3223#ifndef CONFIG_SND_CS46XX_NEW_DSP
3224 /* set the attenuation to 0dB */
3225 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3226 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3227#endif
3228
3229 return 0;
3230}
3231
3232
3233/*
3234 * AMP control - null AMP
3235 */
3236
3d19f804 3237static void amp_none(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3238{
3239}
3240
3241#ifdef CONFIG_SND_CS46XX_NEW_DSP
3d19f804 3242static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
1da177e4
LT		 3243{
3244
3245 u32 idx, valid_slots,tmp,powerdown = 0;
3246 u16 modem_power,pin_config,logic_type;
3247
3248 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3249
3250 /*
3251 * See if the devices are powered down. If so, we must power them up first
3252 * or they will not respond.
3253 */
3254 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3255
3256 if (!(tmp & CLKCR1_SWCE)) {
3257 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3258 powerdown = 1;
3259 }
3260
3261 /*
3262 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3263 * stuff.
3264 */
3265 if(chip->nr_ac97_codecs != 2) {
3266 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3267 return -EINVAL;
3268 }
3269
3270 modem_power = snd_cs46xx_codec_read (chip,
3271 AC97_EXTENDED_MSTATUS,
3272 CS46XX_SECONDARY_CODEC_INDEX);
3273 modem_power &=0xFEFF;
3274
3275 snd_cs46xx_codec_write(chip,
3276 AC97_EXTENDED_MSTATUS, modem_power,
3277 CS46XX_SECONDARY_CODEC_INDEX);
3278
3279 /*
3280 * Set GPIO pin's 7 and 8 so that they are configured for output.
3281 */
3282 pin_config = snd_cs46xx_codec_read (chip,
3283 AC97_GPIO_CFG,
3284 CS46XX_SECONDARY_CODEC_INDEX);
3285 pin_config &=0x27F;
3286
3287 snd_cs46xx_codec_write(chip,
3288 AC97_GPIO_CFG, pin_config,
3289 CS46XX_SECONDARY_CODEC_INDEX);
3290
3291 /*
3292 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3293 */
3294
3295 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3296 CS46XX_SECONDARY_CODEC_INDEX);
3297 logic_type &=0x27F;
3298
3299 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3300 CS46XX_SECONDARY_CODEC_INDEX);
3301
3302 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3303 valid_slots |= 0x200;
3304 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3305
3306 if ( cs46xx_wait_for_fifo(chip,1) ) {
3307 snd_printdd("FIFO is busy\n");
3308
3309 return -EINVAL;
3310 }
3311
3312 /*
3313 * Fill slots 12 with the correct value for the GPIO pins.
3314 */
3315 for(idx = 0x90; idx <= 0x9F; idx++) {
3316 /*
3317 * Initialize the fifo so that bits 7 and 8 are on.
3318 *
3319 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3320 * the left. 0x1800 corresponds to bits 7 and 8.
3321 */
3322 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3323
3324 /*
3325 * Wait for command to complete
3326 */
3327 if ( cs46xx_wait_for_fifo(chip,200) ) {
3328 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3329
3330 return -EINVAL;
3331 }
3332
3333 /*
3334 * Write the serial port FIFO index.
3335 */
3336 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3337
3338 /*
3339 * Tell the serial port to load the new value into the FIFO location.
3340 */
3341 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3342 }
3343
3344 /* wait for last command to complete */
3345 cs46xx_wait_for_fifo(chip,200);
3346
3347 /*
3348 * Now, if we powered up the devices, then power them back down again.
3349 * This is kinda ugly, but should never happen.
3350 */
3351 if (powerdown)
3352 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3353
3354 return 0;
3355}
3356#endif
3357
3358/*
3359 * Crystal EAPD mode
3360 */
3361
3d19f804 3362static void amp_voyetra(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3363{
3364 /* Manage the EAPD bit on the Crystal 4297
3365 and the Analog AD1885 */
3366
3367#ifdef CONFIG_SND_CS46XX_NEW_DSP
3368 int old = chip->amplifier;
3369#endif
3370 int oval, val;
3371
3372 chip->amplifier += change;
3373 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3374 CS46XX_PRIMARY_CODEC_INDEX);
3375 val = oval;
3376 if (chip->amplifier) {
3377 /* Turn the EAPD amp on */
3378 val |= 0x8000;
3379 } else {
3380 /* Turn the EAPD amp off */
3381 val &= ~0x8000;
3382 }
3383 if (val != oval) {
3384 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3385 CS46XX_PRIMARY_CODEC_INDEX);
3386 if (chip->eapd_switch)
3387 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3388 &chip->eapd_switch->id);
3389 }
3390
3391#ifdef CONFIG_SND_CS46XX_NEW_DSP
3392 if (chip->amplifier && !old) {
3393 voyetra_setup_eapd_slot(chip);
3394 }
3395#endif
3396}
3397
3d19f804 3398static void hercules_init(struct snd_cs46xx *chip)
1da177e4
LT		 3399{
3400 /* default: AMP off, and SPDIF input optical */
3401 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3402 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3403}
3404
3405
3406/*
3407 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3408 */
3d19f804 3409static void amp_hercules(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3410{
3411 int old = chip->amplifier;
3412 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3413 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3414
3415 chip->amplifier += change;
3416 if (chip->amplifier && !old) {
3417 snd_printdd ("Hercules amplifier ON\n");
3418
3419 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3420 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3421 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3422 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3423 } else if (old && !chip->amplifier) {
3424 snd_printdd ("Hercules amplifier OFF\n");
3425 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3426 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3427 }
3428}
3429
3d19f804 3430static void voyetra_mixer_init (struct snd_cs46xx *chip)
1da177e4
LT		 3431{
3432 snd_printdd ("initializing Voyetra mixer\n");
3433
3434 /* Enable SPDIF out */
3435 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3436 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3437}
3438
3d19f804 3439static void hercules_mixer_init (struct snd_cs46xx *chip)
1da177e4
LT		 3440{
3441#ifdef CONFIG_SND_CS46XX_NEW_DSP
3442 unsigned int idx;
3443 int err;
3d19f804 3444 struct snd_card *card = chip->card;
1da177e4
LT		 3445#endif
3446
3447 /* set EGPIO to default */
3448 hercules_init(chip);
3449
3450 snd_printdd ("initializing Hercules mixer\n");
3451
3452#ifdef CONFIG_SND_CS46XX_NEW_DSP
3453 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3d19f804 3454 struct snd_kcontrol *kctl;
1da177e4
LT		 3455
3456 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3457 if ((err = snd_ctl_add(card, kctl)) < 0) {
3458 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3459 break;
3460 }
3461 }
3462#endif
3463}
3464
3465
3466#if 0
3467/*
3468 * Untested
3469 */
3470
3d19f804 3471static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3472{
3473 chip->amplifier += change;
3474
3475 if (chip->amplifier) {
3476 /* Switch the GPIO pins 7 and 8 to open drain */
3477 snd_cs46xx_codec_write(chip, 0x4C,
3478 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3479 snd_cs46xx_codec_write(chip, 0x4E,
3480 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3481 /* Now wake the AMP (this might be backwards) */
3482 snd_cs46xx_codec_write(chip, 0x54,
3483 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3484 } else {
3485 snd_cs46xx_codec_write(chip, 0x54,
3486 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3487 }
3488}
3489#endif
3490
3491
1da177e4
LT		 3492/*
3493 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3494 * whenever we need to beat on the chip.
3495 *
3496 * The original idea and code for this hack comes from David Kaiser at
3497 * Linuxcare. Perhaps one day Crystal will document their chips well
3498 * enough to make them useful.
3499 */
3500
3d19f804 3501static void clkrun_hack(struct snd_cs46xx *chip, int change)
1da177e4
LT		 3502{
3503 u16 control, nval;
3504
0dd119f7 3505 if (!chip->acpi_port)
1da177e4
LT		 3506 return;
3507
3508 chip->amplifier += change;
3509
3510 /* Read ACPI port */
3511 nval = control = inw(chip->acpi_port + 0x10);
3512
3513 /* Flip CLKRUN off while running */
3514 if (! chip->amplifier)
3515 nval |= 0x2000;
3516 else
3517 nval &= ~0x2000;
3518 if (nval != control)
3519 outw(nval, chip->acpi_port + 0x10);
3520}
3521
3522
3523/*
3524 * detect intel piix4
3525 */
3d19f804 3526static void clkrun_init(struct snd_cs46xx *chip)
1da177e4 3527{
0dd119f7 3528 struct pci_dev *pdev;
1da177e4
LT		 3529 u8 pp;
3530
0dd119f7
JS		 3531 chip->acpi_port = 0;
3532
3533 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3534 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3535 if (pdev == NULL)
1da177e4
LT		 3536 return; /* Not a thinkpad thats for sure */
3537
3538 /* Find the control port */
0dd119f7 3539 pci_read_config_byte(pdev, 0x41, &pp);
1da177e4 3540 chip->acpi_port = pp << 8;
0dd119f7 3541 pci_dev_put(pdev);
1da177e4
LT		 3542}
3543
3544
3545/*
3546 * Card subid table
3547 */
3548
3549struct cs_card_type
3550{
3551 u16 vendor;
3552 u16 id;
3553 char *name;
3d19f804
TI		 3554 void (*init)(struct snd_cs46xx *);
3555 void (*amp)(struct snd_cs46xx *, int);
3556 void (*active)(struct snd_cs46xx *, int);
3557 void (*mixer_init)(struct snd_cs46xx *);
1da177e4
LT		 3558};
3559
3560static struct cs_card_type __devinitdata cards[] = {
3561 {
3562 .vendor = 0x1489,
3563 .id = 0x7001,
3564 .name = "Genius Soundmaker 128 value",
3565 /* nothing special */
3566 },
3567 {
3568 .vendor = 0x5053,
3569 .id = 0x3357,
3570 .name = "Voyetra",
3571 .amp = amp_voyetra,
3572 .mixer_init = voyetra_mixer_init,
3573 },
3574 {
3575 .vendor = 0x1071,
3576 .id = 0x6003,
3577 .name = "Mitac MI6020/21",
3578 .amp = amp_voyetra,
3579 },
3580 {
3581 .vendor = 0x14AF,
3582 .id = 0x0050,
3583 .name = "Hercules Game Theatre XP",
3584 .amp = amp_hercules,
3585 .mixer_init = hercules_mixer_init,
3586 },
3587 {
3588 .vendor = 0x1681,
3589 .id = 0x0050,
3590 .name = "Hercules Game Theatre XP",
3591 .amp = amp_hercules,
3592 .mixer_init = hercules_mixer_init,
3593 },
3594 {
3595 .vendor = 0x1681,
3596 .id = 0x0051,
3597 .name = "Hercules Game Theatre XP",
3598 .amp = amp_hercules,
3599 .mixer_init = hercules_mixer_init,
3600
3601 },
3602 {
3603 .vendor = 0x1681,
3604 .id = 0x0052,
3605 .name = "Hercules Game Theatre XP",
3606 .amp = amp_hercules,
3607 .mixer_init = hercules_mixer_init,
3608 },
3609 {
3610 .vendor = 0x1681,
3611 .id = 0x0053,
3612 .name = "Hercules Game Theatre XP",
3613 .amp = amp_hercules,
3614 .mixer_init = hercules_mixer_init,
3615 },
3616 {
3617 .vendor = 0x1681,
3618 .id = 0x0054,
3619 .name = "Hercules Game Theatre XP",
3620 .amp = amp_hercules,
3621 .mixer_init = hercules_mixer_init,
3622 },
3623 /* Teratec */
3624 {
3625 .vendor = 0x153b,
3626 .id = 0x1136,
3627 .name = "Terratec SiXPack 5.1",
3628 },
3629 /* Not sure if the 570 needs the clkrun hack */
3630 {
3631 .vendor = PCI_VENDOR_ID_IBM,
3632 .id = 0x0132,
3633 .name = "Thinkpad 570",
3634 .init = clkrun_init,
3635 .active = clkrun_hack,
3636 },
3637 {
3638 .vendor = PCI_VENDOR_ID_IBM,
3639 .id = 0x0153,
3640 .name = "Thinkpad 600X/A20/T20",
3641 .init = clkrun_init,
3642 .active = clkrun_hack,
3643 },
3644 {
3645 .vendor = PCI_VENDOR_ID_IBM,
3646 .id = 0x1010,
3647 .name = "Thinkpad 600E (unsupported)",
3648 },
3649 {} /* terminator */
3650};
3651
3652
3653/*
3654 * APM support
3655 */
3656#ifdef CONFIG_PM
3d19f804 3657static int snd_cs46xx_suspend(struct snd_card *card, pm_message_t state)
1da177e4 3658{
3d19f804 3659 struct snd_cs46xx *chip = card->pm_private_data;
1da177e4
LT		 3660 int amp_saved;
3661
3662 snd_pcm_suspend_all(chip->pcm);
3663 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3664 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3665
3666 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3667 if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3668 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3669
3670 amp_saved = chip->amplifier;
3671 /* turn off amp */
3672 chip->amplifier_ctrl(chip, -chip->amplifier);
3673 snd_cs46xx_hw_stop(chip);
3674 /* disable CLKRUN */
3675 chip->active_ctrl(chip, -chip->amplifier);
3676 chip->amplifier = amp_saved; /* restore the status */
3677 pci_disable_device(chip->pci);
3678 return 0;
3679}
3680
3d19f804 3681static int snd_cs46xx_resume(struct snd_card *card)
1da177e4 3682{
3d19f804 3683 struct snd_cs46xx *chip = card->pm_private_data;
1da177e4
LT		 3684 int amp_saved;
3685
3686 pci_enable_device(chip->pci);
3687 pci_set_master(chip->pci);
3688 amp_saved = chip->amplifier;
3689 chip->amplifier = 0;
3690 chip->active_ctrl(chip, 1); /* force to on */
3691
3692 snd_cs46xx_chip_init(chip);
3693
3694#if 0
3695 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3696 chip->ac97_general_purpose);
3697 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3698 chip->ac97_powerdown);
3699 mdelay(10);
3700 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3701 chip->ac97_powerdown);
3702 mdelay(5);
3703#endif
3704
3705 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3706 if (chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])
3707 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3708
3709 if (amp_saved)
3710 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3711 else
3712 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3713 chip->amplifier = amp_saved;
3714 return 0;
3715}
3716#endif /* CONFIG_PM */
3717
3718
3719/*
3720 */
3721
3d19f804 3722int __devinit snd_cs46xx_create(struct snd_card *card,
1da177e4
LT		 3723 struct pci_dev * pci,
3724 int external_amp, int thinkpad,
3d19f804 3725 struct snd_cs46xx ** rchip)
1da177e4 3726{
3d19f804 3727 struct snd_cs46xx *chip;
1da177e4 3728 int err, idx;
3d19f804 3729 struct snd_cs46xx_region *region;
1da177e4
LT		 3730 struct cs_card_type *cp;
3731 u16 ss_card, ss_vendor;
3d19f804 3732 static struct snd_device_ops ops = {
1da177e4
LT		 3733 .dev_free = snd_cs46xx_dev_free,
3734 };
3735
3736 *rchip = NULL;
3737
3738 /* enable PCI device */
3739 if ((err = pci_enable_device(pci)) < 0)
3740 return err;
3741
e560d8d8 3742 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 3743 if (chip == NULL) {
3744 pci_disable_device(pci);
3745 return -ENOMEM;
3746 }
3747 spin_lock_init(&chip->reg_lock);
3748#ifdef CONFIG_SND_CS46XX_NEW_DSP
3749 init_MUTEX(&chip->spos_mutex);
3750#endif
3751 chip->card = card;
3752 chip->pci = pci;
3753 chip->irq = -1;
3754 chip->ba0_addr = pci_resource_start(pci, 0);
3755 chip->ba1_addr = pci_resource_start(pci, 1);
3756 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3757 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3d19f804
TI		 3758 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3759 chip->ba0_addr, chip->ba1_addr);
1da177e4
LT		 3760 snd_cs46xx_free(chip);
3761 return -ENOMEM;
3762 }
3763
3764 region = &chip->region.name.ba0;
3765 strcpy(region->name, "CS46xx_BA0");
3766 region->base = chip->ba0_addr;
3767 region->size = CS46XX_BA0_SIZE;
3768
3769 region = &chip->region.name.data0;
3770 strcpy(region->name, "CS46xx_BA1_data0");
3771 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3772 region->size = CS46XX_BA1_DATA0_SIZE;
3773
3774 region = &chip->region.name.data1;
3775 strcpy(region->name, "CS46xx_BA1_data1");
3776 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3777 region->size = CS46XX_BA1_DATA1_SIZE;
3778
3779 region = &chip->region.name.pmem;
3780 strcpy(region->name, "CS46xx_BA1_pmem");
3781 region->base = chip->ba1_addr + BA1_SP_PMEM;
3782 region->size = CS46XX_BA1_PRG_SIZE;
3783
3784 region = &chip->region.name.reg;
3785 strcpy(region->name, "CS46xx_BA1_reg");
3786 region->base = chip->ba1_addr + BA1_SP_REG;
3787 region->size = CS46XX_BA1_REG_SIZE;
3788
3789 /* set up amp and clkrun hack */
3790 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3791 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3792
3793 for (cp = &cards[0]; cp->name; cp++) {
3794 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3795 snd_printdd ("hack for %s enabled\n", cp->name);
3796
3797 chip->amplifier_ctrl = cp->amp;
3798 chip->active_ctrl = cp->active;
3799 chip->mixer_init = cp->mixer_init;
3800
3801 if (cp->init)
3802 cp->init(chip);
3803 break;
3804 }
3805 }
3806
3807 if (external_amp) {
99b359ba 3808 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n");
1da177e4
LT		 3809 chip->amplifier_ctrl = amp_voyetra;
3810 }
3811
3812 if (thinkpad) {
99b359ba 3813 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n");
1da177e4
LT		 3814 chip->active_ctrl = clkrun_hack;
3815 clkrun_init(chip);
3816 }
3817
3818 if (chip->amplifier_ctrl == NULL)
3819 chip->amplifier_ctrl = amp_none;
3820 if (chip->active_ctrl == NULL)
3821 chip->active_ctrl = amp_none;
3822
3823 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3824
3825 pci_set_master(pci);
3826
3827 for (idx = 0; idx < 5; idx++) {
3828 region = &chip->region.idx[idx];
3d19f804
TI		 3829 if ((region->resource = request_mem_region(region->base, region->size,
3830 region->name)) == NULL) {
3831 snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n",
3832 region->base, region->base + region->size - 1);
1da177e4
LT		 3833 snd_cs46xx_free(chip);
3834 return -EBUSY;
3835 }
3836 region->remap_addr = ioremap_nocache(region->base, region->size);
3837 if (region->remap_addr == NULL) {
99b359ba 3838 snd_printk(KERN_ERR "%s ioremap problem\n", region->name);
1da177e4
LT		 3839 snd_cs46xx_free(chip);
3840 return -ENOMEM;
3841 }
3842 }
3843
3d19f804
TI		 3844 if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ,
3845 "CS46XX", chip)) {
99b359ba 3846 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 3847 snd_cs46xx_free(chip);
3848 return -EBUSY;
3849 }
3850 chip->irq = pci->irq;
3851
3852#ifdef CONFIG_SND_CS46XX_NEW_DSP
3853 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3854 if (chip->dsp_spos_instance == NULL) {
3855 snd_cs46xx_free(chip);
3856 return -ENOMEM;
3857 }
3858#endif
3859
3860 err = snd_cs46xx_chip_init(chip);
3861 if (err < 0) {
3862 snd_cs46xx_free(chip);
3863 return err;
3864 }
3865
3866 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3867 snd_cs46xx_free(chip);
3868 return err;
3869 }
3870
3871 snd_cs46xx_proc_init(card, chip);
3872
3873 snd_card_set_pm_callback(card, snd_cs46xx_suspend, snd_cs46xx_resume, chip);
3874
3875 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3876
3877 snd_card_set_dev(card, &pci->dev);
3878
3879 *rchip = chip;
3880 return 0;
3881}
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