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[net-next-2.6.git] / sound / pci / asihpi / hpi6205.c
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719f82d3
EB		 1/******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 Hardware Programming Interface (HPI) for AudioScience
20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
21 These PCI and PCIe bus adapters are based on a
22 TMS320C6205 PCI bus mastering DSP,
23 and (except ASI50xx) TI TMS320C6xxx floating point DSP
24
25 Exported function:
26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
27
28(C) Copyright AudioScience Inc. 1998-2010
29*******************************************************************************/
30#define SOURCEFILE_NAME "hpi6205.c"
31
32#include "hpi_internal.h"
33#include "hpimsginit.h"
34#include "hpidebug.h"
35#include "hpi6205.h"
36#include "hpidspcd.h"
37#include "hpicmn.h"
38
39/*****************************************************************************/
40/* HPI6205 specific error codes */
41#define HPI6205_ERROR_BASE 1000
42/*#define HPI6205_ERROR_MEM_ALLOC 1001 */
43#define HPI6205_ERROR_6205_NO_IRQ 1002
44#define HPI6205_ERROR_6205_INIT_FAILED 1003
45/*#define HPI6205_ERROR_MISSING_DSPCODE 1004 */
46#define HPI6205_ERROR_UNKNOWN_PCI_DEVICE 1005
47#define HPI6205_ERROR_6205_REG 1006
48#define HPI6205_ERROR_6205_DSPPAGE 1007
49#define HPI6205_ERROR_BAD_DSPINDEX 1008
50#define HPI6205_ERROR_C6713_HPIC 1009
51#define HPI6205_ERROR_C6713_HPIA 1010
52#define HPI6205_ERROR_C6713_PLL 1011
53#define HPI6205_ERROR_DSP_INTMEM 1012
54#define HPI6205_ERROR_DSP_EXTMEM 1013
55#define HPI6205_ERROR_DSP_PLD 1014
56#define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
57#define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
58#define HPI6205_ERROR_6205_EEPROM 1017
59#define HPI6205_ERROR_DSP_EMIF 1018
60
61#define hpi6205_error(dsp_index, err) (err)
62/*****************************************************************************/
63/* for C6205 PCI i/f */
64/* Host Status Register (HSR) bitfields */
65#define C6205_HSR_INTSRC 0x01
66#define C6205_HSR_INTAVAL 0x02
67#define C6205_HSR_INTAM 0x04
68#define C6205_HSR_CFGERR 0x08
69#define C6205_HSR_EEREAD 0x10
70/* Host-to-DSP Control Register (HDCR) bitfields */
71#define C6205_HDCR_WARMRESET 0x01
72#define C6205_HDCR_DSPINT 0x02
73#define C6205_HDCR_PCIBOOT 0x04
74/* DSP Page Register (DSPP) bitfields, */
75/* defines 4 Mbyte page that BAR0 points to */
76#define C6205_DSPP_MAP1 0x400
77
78/* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
79 * BAR1 maps to non-prefetchable 8 Mbyte memory block
80 * of DSP memory mapped registers (starting at 0x01800000).
81 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
82 * needs to be added to the BAR1 base address set in the PCI config reg
83 */
84#define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
85#define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
86#define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
87#define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
88
89/* used to control LED (revA) and reset C6713 (revB) */
90#define C6205_BAR0_TIMER1_CTL (0x01980000L)
91
92/* For first 6713 in CE1 space, using DA17,16,2 */
93#define HPICL_ADDR 0x01400000L
94#define HPICH_ADDR 0x01400004L
95#define HPIAL_ADDR 0x01410000L
96#define HPIAH_ADDR 0x01410004L
97#define HPIDIL_ADDR 0x01420000L
98#define HPIDIH_ADDR 0x01420004L
99#define HPIDL_ADDR 0x01430000L
100#define HPIDH_ADDR 0x01430004L
101
102#define C6713_EMIF_GCTL 0x01800000
103#define C6713_EMIF_CE1 0x01800004
104#define C6713_EMIF_CE0 0x01800008
105#define C6713_EMIF_CE2 0x01800010
106#define C6713_EMIF_CE3 0x01800014
107#define C6713_EMIF_SDRAMCTL 0x01800018
108#define C6713_EMIF_SDRAMTIMING 0x0180001C
109#define C6713_EMIF_SDRAMEXT 0x01800020
110
111struct hpi_hw_obj {
112 /* PCI registers */
113 __iomem u32 *prHSR;
114 __iomem u32 *prHDCR;
115 __iomem u32 *prDSPP;
116
117 u32 dsp_page;
118
119 struct consistent_dma_area h_locked_mem;
120 struct bus_master_interface *p_interface_buffer;
121
122 u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
123 /* a non-NULL handle means there is an HPI allocated buffer */
124 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
125 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
126 /* non-zero size means a buffer exists, may be external */
127 u32 instream_host_buffer_size[HPI_MAX_STREAMS];
128 u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
129
130 struct consistent_dma_area h_control_cache;
131 struct consistent_dma_area h_async_event_buffer;
132/* struct hpi_control_cache_single *pControlCache; */
133 struct hpi_async_event *p_async_event_buffer;
134 struct hpi_control_cache *p_cache;
135};
136
137/*****************************************************************************/
138/* local prototypes */
139
140#define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
141
142static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
143
144static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
145
146static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
147 u32 *pos_error_code);
148
149static u16 message_response_sequence(struct hpi_adapter_obj *pao,
150 struct hpi_message *phm, struct hpi_response *phr);
151
152static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
153 struct hpi_response *phr);
154
155#define HPI6205_TIMEOUT 1000000
156
157static void subsys_create_adapter(struct hpi_message *phm,
158 struct hpi_response *phr);
159static void subsys_delete_adapter(struct hpi_message *phm,
160 struct hpi_response *phr);
161
162static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
163 u32 *pos_error_code);
164
165static void delete_adapter_obj(struct hpi_adapter_obj *pao);
166
167static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
168 struct hpi_message *phm, struct hpi_response *phr);
169
170static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
171 struct hpi_message *phm, struct hpi_response *phr);
172
173static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
174 struct hpi_message *phm, struct hpi_response *phr);
175static void outstream_write(struct hpi_adapter_obj *pao,
176 struct hpi_message *phm, struct hpi_response *phr);
177
178static void outstream_get_info(struct hpi_adapter_obj *pao,
179 struct hpi_message *phm, struct hpi_response *phr);
180
181static void outstream_start(struct hpi_adapter_obj *pao,
182 struct hpi_message *phm, struct hpi_response *phr);
183
184static void outstream_open(struct hpi_adapter_obj *pao,
185 struct hpi_message *phm, struct hpi_response *phr);
186
187static void outstream_reset(struct hpi_adapter_obj *pao,
188 struct hpi_message *phm, struct hpi_response *phr);
189
190static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
191 struct hpi_message *phm, struct hpi_response *phr);
192
193static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
194 struct hpi_message *phm, struct hpi_response *phr);
195
196static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
197 struct hpi_message *phm, struct hpi_response *phr);
198
199static void instream_read(struct hpi_adapter_obj *pao,
200 struct hpi_message *phm, struct hpi_response *phr);
201
202static void instream_get_info(struct hpi_adapter_obj *pao,
203 struct hpi_message *phm, struct hpi_response *phr);
204
205static void instream_start(struct hpi_adapter_obj *pao,
206 struct hpi_message *phm, struct hpi_response *phr);
207
208static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
209 u32 address);
210
211static u16 boot_loader_write_mem32(struct hpi_adapter_obj *pao, int dsp_index,
212 u32 address, u32 data);
213
214static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
215 int dsp_index);
216
217static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
218 u32 address, u32 length);
219
220static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
221 int dsp_index);
222
223static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
224 int dsp_index);
225
226static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
227
228/*****************************************************************************/
229
230static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
231{
232
233 switch (phm->function) {
234 case HPI_SUBSYS_OPEN:
235 case HPI_SUBSYS_CLOSE:
236 case HPI_SUBSYS_GET_INFO:
237 case HPI_SUBSYS_DRIVER_UNLOAD:
238 case HPI_SUBSYS_DRIVER_LOAD:
239 case HPI_SUBSYS_FIND_ADAPTERS:
240 /* messages that should not get here */
241 phr->error = HPI_ERROR_UNIMPLEMENTED;
242 break;
243 case HPI_SUBSYS_CREATE_ADAPTER:
244 subsys_create_adapter(phm, phr);
245 break;
246 case HPI_SUBSYS_DELETE_ADAPTER:
247 subsys_delete_adapter(phm, phr);
248 break;
249 default:
250 phr->error = HPI_ERROR_INVALID_FUNC;
251 break;
252 }
253}
254
255static void control_message(struct hpi_adapter_obj *pao,
256 struct hpi_message *phm, struct hpi_response *phr)
257{
258
259 struct hpi_hw_obj *phw = pao->priv;
260
261 switch (phm->function) {
262 case HPI_CONTROL_GET_STATE:
263 if (pao->has_control_cache) {
264 rmb(); /* make sure we see updates DM_aed from DSP */
265 if (hpi_check_control_cache(phw->p_cache, phm, phr))
266 break;
267 }
268 hw_message(pao, phm, phr);
269 break;
270 case HPI_CONTROL_GET_INFO:
271 hw_message(pao, phm, phr);
272 break;
273 case HPI_CONTROL_SET_STATE:
274 hw_message(pao, phm, phr);
275 if (pao->has_control_cache)
276 hpi_sync_control_cache(phw->p_cache, phm, phr);
277 break;
278 default:
279 phr->error = HPI_ERROR_INVALID_FUNC;
280 break;
281 }
282}
283
284static void adapter_message(struct hpi_adapter_obj *pao,
285 struct hpi_message *phm, struct hpi_response *phr)
286{
287 switch (phm->function) {
288 default:
289 hw_message(pao, phm, phr);
290 break;
291 }
292}
293
294static void outstream_message(struct hpi_adapter_obj *pao,
295 struct hpi_message *phm, struct hpi_response *phr)
296{
297
298 if (phm->obj_index >= HPI_MAX_STREAMS) {
299 phr->error = HPI_ERROR_INVALID_STREAM;
300 HPI_DEBUG_LOG(WARNING,
301 "message referencing invalid stream %d "
302 "on adapter index %d\n", phm->obj_index,
303 phm->adapter_index);
304 return;
305 }
306
307 switch (phm->function) {
308 case HPI_OSTREAM_WRITE:
309 outstream_write(pao, phm, phr);
310 break;
311 case HPI_OSTREAM_GET_INFO:
312 outstream_get_info(pao, phm, phr);
313 break;
314 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
315 outstream_host_buffer_allocate(pao, phm, phr);
316 break;
317 case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
318 outstream_host_buffer_get_info(pao, phm, phr);
319 break;
320 case HPI_OSTREAM_HOSTBUFFER_FREE:
321 outstream_host_buffer_free(pao, phm, phr);
322 break;
323 case HPI_OSTREAM_START:
324 outstream_start(pao, phm, phr);
325 break;
326 case HPI_OSTREAM_OPEN:
327 outstream_open(pao, phm, phr);
328 break;
329 case HPI_OSTREAM_RESET:
330 outstream_reset(pao, phm, phr);
331 break;
332 default:
333 hw_message(pao, phm, phr);
334 break;
335 }
336}
337
338static void instream_message(struct hpi_adapter_obj *pao,
339 struct hpi_message *phm, struct hpi_response *phr)
340{
341
342 if (phm->obj_index >= HPI_MAX_STREAMS) {
343 phr->error = HPI_ERROR_INVALID_STREAM;
344 HPI_DEBUG_LOG(WARNING,
345 "message referencing invalid stream %d "
346 "on adapter index %d\n", phm->obj_index,
347 phm->adapter_index);
348 return;
349 }
350
351 switch (phm->function) {
352 case HPI_ISTREAM_READ:
353 instream_read(pao, phm, phr);
354 break;
355 case HPI_ISTREAM_GET_INFO:
356 instream_get_info(pao, phm, phr);
357 break;
358 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
359 instream_host_buffer_allocate(pao, phm, phr);
360 break;
361 case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
362 instream_host_buffer_get_info(pao, phm, phr);
363 break;
364 case HPI_ISTREAM_HOSTBUFFER_FREE:
365 instream_host_buffer_free(pao, phm, phr);
366 break;
367 case HPI_ISTREAM_START:
368 instream_start(pao, phm, phr);
369 break;
370 default:
371 hw_message(pao, phm, phr);
372 break;
373 }
374}
375
376/*****************************************************************************/
377/** Entry point to this HPI backend
378 * All calls to the HPI start here
379 */
380void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
381{
382 struct hpi_adapter_obj *pao = NULL;
383
384 /* subsytem messages are processed by every HPI.
385 * All other messages are ignored unless the adapter index matches
386 * an adapter in the HPI
387 */
388 HPI_DEBUG_LOG(DEBUG, "HPI obj=%d, func=%d\n", phm->object,
389 phm->function);
390
391 /* if Dsp has crashed then do not communicate with it any more */
392 if (phm->object != HPI_OBJ_SUBSYSTEM) {
393 pao = hpi_find_adapter(phm->adapter_index);
394 if (!pao) {
395 HPI_DEBUG_LOG(DEBUG,
396 " %d,%d refused, for another HPI?\n",
397 phm->object, phm->function);
398 return;
399 }
400
401 if ((pao->dsp_crashed >= 10)
402 && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
403 /* allow last resort debug read even after crash */
404 hpi_init_response(phr, phm->object, phm->function,
405 HPI_ERROR_DSP_HARDWARE);
406 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n",
407 phm->object, phm->function);
408 return;
409 }
410 }
411
412 /* Init default response */
413 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
414 hpi_init_response(phr, phm->object, phm->function,
415 HPI_ERROR_PROCESSING_MESSAGE);
416
417 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
418 switch (phm->type) {
419 case HPI_TYPE_MESSAGE:
420 switch (phm->object) {
421 case HPI_OBJ_SUBSYSTEM:
422 subsys_message(phm, phr);
423 break;
424
425 case HPI_OBJ_ADAPTER:
426 phr->size =
427 sizeof(struct hpi_response_header) +
428 sizeof(struct hpi_adapter_res);
429 adapter_message(pao, phm, phr);
430 break;
431
432 case HPI_OBJ_CONTROLEX:
433 case HPI_OBJ_CONTROL:
434 control_message(pao, phm, phr);
435 break;
436
437 case HPI_OBJ_OSTREAM:
438 outstream_message(pao, phm, phr);
439 break;
440
441 case HPI_OBJ_ISTREAM:
442 instream_message(pao, phm, phr);
443 break;
444
445 default:
446 hw_message(pao, phm, phr);
447 break;
448 }
449 break;
450
451 default:
452 phr->error = HPI_ERROR_INVALID_TYPE;
453 break;
454 }
455}
456
457/*****************************************************************************/
458/* SUBSYSTEM */
459
460/** Create an adapter object and initialise it based on resource information
461 * passed in in the message
462 * *** NOTE - you cannot use this function AND the FindAdapters function at the
463 * same time, the application must use only one of them to get the adapters ***
464 */
465static void subsys_create_adapter(struct hpi_message *phm,
466 struct hpi_response *phr)
467{
468 /* create temp adapter obj, because we don't know what index yet */
469 struct hpi_adapter_obj ao;
470 u32 os_error_code;
471 u16 err;
472
473 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
474
475 memset(&ao, 0, sizeof(ao));
476
477 /* this HPI only creates adapters for TI/PCI devices */
478 if (phm->u.s.resource.bus_type != HPI_BUS_PCI)
479 return;
480 if (phm->u.s.resource.r.pci->vendor_id != HPI_PCI_VENDOR_ID_TI)
481 return;
482 if (phm->u.s.resource.r.pci->device_id != HPI_PCI_DEV_ID_DSP6205)
483 return;
484
485 ao.priv = kmalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
486 if (!ao.priv) {
487 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
488 phr->error = HPI_ERROR_MEMORY_ALLOC;
489 return;
490 }
491 memset(ao.priv, 0, sizeof(struct hpi_hw_obj));
492
493 ao.pci = *phm->u.s.resource.r.pci;
494 err = create_adapter_obj(&ao, &os_error_code);
495 if (!err)
496 err = hpi_add_adapter(&ao);
497 if (err) {
498 phr->u.s.data = os_error_code;
499 delete_adapter_obj(&ao);
500 phr->error = err;
501 return;
502 }
503
504 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
505 phr->u.s.adapter_index = ao.index;
506 phr->u.s.num_adapters++;
507 phr->error = 0;
508}
509
510/** delete an adapter - required by WDM driver */
511static void subsys_delete_adapter(struct hpi_message *phm,
512 struct hpi_response *phr)
513{
514 struct hpi_adapter_obj *pao;
515 struct hpi_hw_obj *phw;
516
517 pao = hpi_find_adapter(phm->adapter_index);
518 if (!pao) {
519 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
520 return;
521 }
522 phw = (struct hpi_hw_obj *)pao->priv;
523 /* reset adapter h/w */
524 /* Reset C6713 #1 */
525 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
526 /* reset C6205 */
527 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
528
529 delete_adapter_obj(pao);
530 phr->error = 0;
531}
532
533/** Create adapter object
534 allocate buffers, bootload DSPs, initialise control cache
535*/
536static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
537 u32 *pos_error_code)
538{
539 struct hpi_hw_obj *phw = pao->priv;
540 struct bus_master_interface *interface;
541 u32 phys_addr;
542#ifndef HPI6205_NO_HSR_POLL
543 u32 time_out = HPI6205_TIMEOUT;
544 u32 temp1;
545#endif
546 int i;
547 u16 err;
548
549 /* init error reporting */
550 pao->dsp_crashed = 0;
551
552 for (i = 0; i < HPI_MAX_STREAMS; i++)
553 phw->flag_outstream_just_reset[i] = 1;
554
555 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
556 phw->prHSR =
557 pao->pci.ap_mem_base[1] +
558 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
559 phw->prHDCR =
560 pao->pci.ap_mem_base[1] +
561 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
562 phw->prDSPP =
563 pao->pci.ap_mem_base[1] +
564 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
565
566 pao->has_control_cache = 0;
567
568 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
569 sizeof(struct bus_master_interface),
570 pao->pci.p_os_data))
571 phw->p_interface_buffer = NULL;
572 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
573 (void *)&phw->p_interface_buffer))
574 phw->p_interface_buffer = NULL;
575
576 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
577 phw->p_interface_buffer);
578
579 if (phw->p_interface_buffer) {
580 memset((void *)phw->p_interface_buffer, 0,
581 sizeof(struct bus_master_interface));
582 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
583 }
584
585 err = adapter_boot_load_dsp(pao, pos_error_code);
586 if (err)
587 /* no need to clean up as SubSysCreateAdapter */
588 /* calls DeleteAdapter on error. */
589 return err;
590
591 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
592
593 /* allow boot load even if mem alloc wont work */
594 if (!phw->p_interface_buffer)
595 return hpi6205_error(0, HPI_ERROR_MEMORY_ALLOC);
596
597 interface = phw->p_interface_buffer;
598
599#ifndef HPI6205_NO_HSR_POLL
600 /* wait for first interrupt indicating the DSP init is done */
601 time_out = HPI6205_TIMEOUT * 10;
602 temp1 = 0;
603 while (((temp1 & C6205_HSR_INTSRC) == 0) && --time_out)
604 temp1 = ioread32(phw->prHSR);
605
606 if (temp1 & C6205_HSR_INTSRC)
607 HPI_DEBUG_LOG(INFO,
608 "interrupt confirming DSP code running OK\n");
609 else {
610 HPI_DEBUG_LOG(ERROR,
611 "timed out waiting for interrupt "
612 "confirming DSP code running\n");
613 return hpi6205_error(0, HPI6205_ERROR_6205_NO_IRQ);
614 }
615
616 /* reset the interrupt */
617 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
618#endif
619
620 /* make sure the DSP has started ok */
621 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
622 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
623 return hpi6205_error(0, HPI6205_ERROR_6205_INIT_FAILED);
624 }
625 /* Note that *pao, *phw are zeroed after allocation,
626 * so pointers and flags are NULL by default.
627 * Allocate bus mastering control cache buffer and tell the DSP about it
628 */
629 if (interface->control_cache.number_of_controls) {
630 void *p_control_cache_virtual;
631
632 err = hpios_locked_mem_alloc(&phw->h_control_cache,
633 interface->control_cache.size_in_bytes,
634 pao->pci.p_os_data);
635 if (!err)
636 err = hpios_locked_mem_get_virt_addr(&phw->
637 h_control_cache, &p_control_cache_virtual);
638 if (!err) {
639 memset(p_control_cache_virtual, 0,
640 interface->control_cache.size_in_bytes);
641
642 phw->p_cache =
643 hpi_alloc_control_cache(interface->
644 control_cache.number_of_controls,
645 interface->control_cache.size_in_bytes,
646 (struct hpi_control_cache_info *)
647 p_control_cache_virtual);
648 }
649 if (!err) {
650 err = hpios_locked_mem_get_phys_addr(&phw->
651 h_control_cache, &phys_addr);
652 interface->control_cache.physical_address32 =
653 phys_addr;
654 }
655
656 if (!err)
657 pao->has_control_cache = 1;
658 else {
659 if (hpios_locked_mem_valid(&phw->h_control_cache))
660 hpios_locked_mem_free(&phw->h_control_cache);
661 pao->has_control_cache = 0;
662 }
663 }
664 /* allocate bus mastering async buffer and tell the DSP about it */
665 if (interface->async_buffer.b.size) {
666 err = hpios_locked_mem_alloc(&phw->h_async_event_buffer,
667 interface->async_buffer.b.size *
668 sizeof(struct hpi_async_event), pao->pci.p_os_data);
669 if (!err)
670 err = hpios_locked_mem_get_virt_addr
671 (&phw->h_async_event_buffer, (void *)
672 &phw->p_async_event_buffer);
673 if (!err)
674 memset((void *)phw->p_async_event_buffer, 0,
675 interface->async_buffer.b.size *
676 sizeof(struct hpi_async_event));
677 if (!err) {
678 err = hpios_locked_mem_get_phys_addr
679 (&phw->h_async_event_buffer, &phys_addr);
680 interface->async_buffer.physical_address32 =
681 phys_addr;
682 }
683 if (err) {
684 if (hpios_locked_mem_valid(&phw->
685 h_async_event_buffer)) {
686 hpios_locked_mem_free
687 (&phw->h_async_event_buffer);
688 phw->p_async_event_buffer = NULL;
689 }
690 }
691 }
692 send_dsp_command(phw, H620_HIF_IDLE);
693
694 {
695 struct hpi_message hM;
696 struct hpi_response hR;
697 u32 max_streams;
698
699 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
700 memset(&hM, 0, sizeof(hM));
701 hM.type = HPI_TYPE_MESSAGE;
702 hM.size = sizeof(hM);
703 hM.object = HPI_OBJ_ADAPTER;
704 hM.function = HPI_ADAPTER_GET_INFO;
705 hM.adapter_index = 0;
706 memset(&hR, 0, sizeof(hR));
707 hR.size = sizeof(hR);
708
709 err = message_response_sequence(pao, &hM, &hR);
710 if (err) {
711 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
712 err);
713 return err;
714 }
715 if (hR.error)
716 return hR.error;
717
718 pao->adapter_type = hR.u.a.adapter_type;
719 pao->index = hR.u.a.adapter_index;
720
721 max_streams = hR.u.a.num_outstreams + hR.u.a.num_instreams;
722
723 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams,
724 65536, pao->pci.p_os_data);
725
726 HPI_DEBUG_LOG(VERBOSE,
727 "got adapter info type %x index %d serial %d\n",
728 hR.u.a.adapter_type, hR.u.a.adapter_index,
729 hR.u.a.serial_number);
730 }
731
732 pao->open = 0; /* upon creation the adapter is closed */
733
734 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
735 return 0;
736}
737
738/** Free memory areas allocated by adapter
739 * this routine is called from SubSysDeleteAdapter,
740 * and SubSysCreateAdapter if duplicate index
741*/
742static void delete_adapter_obj(struct hpi_adapter_obj *pao)
743{
744 struct hpi_hw_obj *phw;
745 int i;
746
747 phw = pao->priv;
748
749 if (hpios_locked_mem_valid(&phw->h_async_event_buffer)) {
750 hpios_locked_mem_free(&phw->h_async_event_buffer);
751 phw->p_async_event_buffer = NULL;
752 }
753
754 if (hpios_locked_mem_valid(&phw->h_control_cache)) {
755 hpios_locked_mem_free(&phw->h_control_cache);
756 hpi_free_control_cache(phw->p_cache);
757 }
758
759 if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
760 hpios_locked_mem_free(&phw->h_locked_mem);
761 phw->p_interface_buffer = NULL;
762 }
763
764 for (i = 0; i < HPI_MAX_STREAMS; i++)
765 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
766 hpios_locked_mem_free(&phw->instream_host_buffers[i]);
767 /*?phw->InStreamHostBuffers[i] = NULL; */
768 phw->instream_host_buffer_size[i] = 0;
769 }
770
771 for (i = 0; i < HPI_MAX_STREAMS; i++)
772 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
773 hpios_locked_mem_free(&phw->outstream_host_buffers
774 [i]);
775 phw->outstream_host_buffer_size[i] = 0;
776 }
777
778 hpios_locked_mem_unprepare(pao->pci.p_os_data);
779
780 hpi_delete_adapter(pao);
781 kfree(phw);
782}
783
784/*****************************************************************************/
785/* OutStream Host buffer functions */
786
787/** Allocate or attach buffer for busmastering
788*/
789static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
790 struct hpi_message *phm, struct hpi_response *phr)
791{
792 u16 err = 0;
793 u32 command = phm->u.d.u.buffer.command;
794 struct hpi_hw_obj *phw = pao->priv;
795 struct bus_master_interface *interface = phw->p_interface_buffer;
796
797 hpi_init_response(phr, phm->object, phm->function, 0);
798
799 if (command == HPI_BUFFER_CMD_EXTERNAL
800 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
801 /* ALLOC phase, allocate a buffer with power of 2 size,
802 get its bus address for PCI bus mastering
803 */
804 phm->u.d.u.buffer.buffer_size =
805 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
806 /* return old size and allocated size,
807 so caller can detect change */
808 phr->u.d.u.stream_info.data_available =
809 phw->outstream_host_buffer_size[phm->obj_index];
810 phr->u.d.u.stream_info.buffer_size =
811 phm->u.d.u.buffer.buffer_size;
812
813 if (phw->outstream_host_buffer_size[phm->obj_index] ==
814 phm->u.d.u.buffer.buffer_size) {
815 /* Same size, no action required */
816 return;
817 }
818
819 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
820 obj_index]))
821 hpios_locked_mem_free(&phw->outstream_host_buffers
822 [phm->obj_index]);
823
824 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
825 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
826 pao->pci.p_os_data);
827
828 if (err) {
829 phr->error = HPI_ERROR_INVALID_DATASIZE;
830 phw->outstream_host_buffer_size[phm->obj_index] = 0;
831 return;
832 }
833
834 err = hpios_locked_mem_get_phys_addr
835 (&phw->outstream_host_buffers[phm->obj_index],
836 &phm->u.d.u.buffer.pci_address);
837 /* get the phys addr into msg for single call alloc caller
838 * needs to do this for split alloc (or use the same message)
839 * return the phy address for split alloc in the respose too
840 */
841 phr->u.d.u.stream_info.auxiliary_data_available =
842 phm->u.d.u.buffer.pci_address;
843
844 if (err) {
845 hpios_locked_mem_free(&phw->outstream_host_buffers
846 [phm->obj_index]);
847 phw->outstream_host_buffer_size[phm->obj_index] = 0;
848 phr->error = HPI_ERROR_MEMORY_ALLOC;
849 return;
850 }
851 }
852
853 if (command == HPI_BUFFER_CMD_EXTERNAL
854 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
855 /* GRANT phase. Set up the BBM status, tell the DSP about
856 the buffer so it can start using BBM.
857 */
858 struct hpi_hostbuffer_status *status;
859
860 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
861 buffer_size - 1)) {
862 HPI_DEBUG_LOG(ERROR,
863 "buffer size must be 2^N not %d\n",
864 phm->u.d.u.buffer.buffer_size);
865 phr->error = HPI_ERROR_INVALID_DATASIZE;
866 return;
867 }
868 phw->outstream_host_buffer_size[phm->obj_index] =
869 phm->u.d.u.buffer.buffer_size;
870 status = &interface->outstream_host_buffer_status[phm->
871 obj_index];
872 status->samples_processed = 0;
873 status->stream_state = HPI_STATE_STOPPED;
874 status->dSP_index = 0;
875 status->host_index = status->dSP_index;
876 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
877
878 hw_message(pao, phm, phr);
879
880 if (phr->error
881 && hpios_locked_mem_valid(&phw->
882 outstream_host_buffers[phm->obj_index])) {
883 hpios_locked_mem_free(&phw->outstream_host_buffers
884 [phm->obj_index]);
885 phw->outstream_host_buffer_size[phm->obj_index] = 0;
886 }
887 }
888}
889
890static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
891 struct hpi_message *phm, struct hpi_response *phr)
892{
893 struct hpi_hw_obj *phw = pao->priv;
894 struct bus_master_interface *interface = phw->p_interface_buffer;
895 struct hpi_hostbuffer_status *status;
896 u8 *p_bbm_data;
897
898 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
899 obj_index])) {
900 if (hpios_locked_mem_get_virt_addr(&phw->
901 outstream_host_buffers[phm->obj_index],
902 (void *)&p_bbm_data)) {
903 phr->error = HPI_ERROR_INVALID_OPERATION;
904 return;
905 }
906 status = &interface->outstream_host_buffer_status[phm->
907 obj_index];
908 hpi_init_response(phr, HPI_OBJ_OSTREAM,
909 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
910 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
911 phr->u.d.u.hostbuffer_info.p_status = status;
912 } else {
913 hpi_init_response(phr, HPI_OBJ_OSTREAM,
914 HPI_OSTREAM_HOSTBUFFER_GET_INFO,
915 HPI_ERROR_INVALID_OPERATION);
916 }
917}
918
919static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
920 struct hpi_message *phm, struct hpi_response *phr)
921{
922 struct hpi_hw_obj *phw = pao->priv;
923 u32 command = phm->u.d.u.buffer.command;
924
925 if (phw->outstream_host_buffer_size[phm->obj_index]) {
926 if (command == HPI_BUFFER_CMD_EXTERNAL
927 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
928 phw->outstream_host_buffer_size[phm->obj_index] = 0;
929 hw_message(pao, phm, phr);
930 /* Tell adapter to stop using the host buffer. */
931 }
932 if (command == HPI_BUFFER_CMD_EXTERNAL
933 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
934 hpios_locked_mem_free(&phw->outstream_host_buffers
935 [phm->obj_index]);
936 }
937 /* Should HPI_ERROR_INVALID_OPERATION be returned
938 if no host buffer is allocated? */
939 else
940 hpi_init_response(phr, HPI_OBJ_OSTREAM,
941 HPI_OSTREAM_HOSTBUFFER_FREE, 0);
942
943}
944
945static long outstream_get_space_available(struct hpi_hostbuffer_status
946 *status)
947{
948 return status->size_in_bytes - ((long)(status->host_index) -
949 (long)(status->dSP_index));
950}
951
952static void outstream_write(struct hpi_adapter_obj *pao,
953 struct hpi_message *phm, struct hpi_response *phr)
954{
955 struct hpi_hw_obj *phw = pao->priv;
956 struct bus_master_interface *interface = phw->p_interface_buffer;
957 struct hpi_hostbuffer_status *status;
958 long space_available;
959
960 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
961 /* there is no BBM buffer, write via message */
962 hw_message(pao, phm, phr);
963 return;
964 }
965
966 hpi_init_response(phr, phm->object, phm->function, 0);
967 status = &interface->outstream_host_buffer_status[phm->obj_index];
968
969 if (phw->flag_outstream_just_reset[phm->obj_index]) {
970 /* Format can only change after reset. Must tell DSP. */
971 u16 function = phm->function;
972 phw->flag_outstream_just_reset[phm->obj_index] = 0;
973 phm->function = HPI_OSTREAM_SET_FORMAT;
974 hw_message(pao, phm, phr); /* send the format to the DSP */
975 phm->function = function;
976 if (phr->error)
977 return;
978 }
979#if 1
980 if (phw->flag_outstream_just_reset[phm->obj_index]) {
981 /* First OutStremWrite() call following reset will write data to the
982 adapter's buffers, reducing delay before stream can start
983 */
984 int partial_write = 0;
985 unsigned int original_size = 0;
986
987 /* Send the first buffer to the DSP the old way. */
988 /* Limit size of first transfer - */
989 /* expect that this will not usually be triggered. */
990 if (phm->u.d.u.data.data_size > HPI6205_SIZEOF_DATA) {
991 partial_write = 1;
992 original_size = phm->u.d.u.data.data_size;
993 phm->u.d.u.data.data_size = HPI6205_SIZEOF_DATA;
994 }
995 /* write it */
996 phm->function = HPI_OSTREAM_WRITE;
997 hw_message(pao, phm, phr);
998 /* update status information that the DSP would typically
999 * update (and will update next time the DSP
1000 * buffer update task reads data from the host BBM buffer)
1001 */
1002 status->auxiliary_data_available = phm->u.d.u.data.data_size;
1003 status->host_index += phm->u.d.u.data.data_size;
1004 status->dSP_index += phm->u.d.u.data.data_size;
1005
1006 /* if we did a full write, we can return from here. */
1007 if (!partial_write)
1008 return;
1009
1010 /* tweak buffer parameters and let the rest of the */
1011 /* buffer land in internal BBM buffer */
1012 phm->u.d.u.data.data_size =
1013 original_size - HPI6205_SIZEOF_DATA;
1014 phm->u.d.u.data.pb_data += HPI6205_SIZEOF_DATA;
1015 }
1016#endif
1017
1018 space_available = outstream_get_space_available(status);
1019 if (space_available < (long)phm->u.d.u.data.data_size) {
1020 phr->error = HPI_ERROR_INVALID_DATASIZE;
1021 return;
1022 }
1023
1024 /* HostBuffers is used to indicate host buffer is internally allocated.
1025 otherwise, assumed external, data written externally */
1026 if (phm->u.d.u.data.pb_data
1027 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
1028 obj_index])) {
1029 u8 *p_bbm_data;
1030 long l_first_write;
1031 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1032
1033 if (hpios_locked_mem_get_virt_addr(&phw->
1034 outstream_host_buffers[phm->obj_index],
1035 (void *)&p_bbm_data)) {
1036 phr->error = HPI_ERROR_INVALID_OPERATION;
1037 return;
1038 }
1039
1040 /* either all data,
1041 or enough to fit from current to end of BBM buffer */
1042 l_first_write =
1043 min(phm->u.d.u.data.data_size,
1044 status->size_in_bytes -
1045 (status->host_index & (status->size_in_bytes - 1)));
1046
1047 memcpy(p_bbm_data +
1048 (status->host_index & (status->size_in_bytes - 1)),
1049 p_app_data, l_first_write);
1050 /* remaining data if any */
1051 memcpy(p_bbm_data, p_app_data + l_first_write,
1052 phm->u.d.u.data.data_size - l_first_write);
1053 }
1054 status->host_index += phm->u.d.u.data.data_size;
1055}
1056
1057static void outstream_get_info(struct hpi_adapter_obj *pao,
1058 struct hpi_message *phm, struct hpi_response *phr)
1059{
1060 struct hpi_hw_obj *phw = pao->priv;
1061 struct bus_master_interface *interface = phw->p_interface_buffer;
1062 struct hpi_hostbuffer_status *status;
1063
1064 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
1065 hw_message(pao, phm, phr);
1066 return;
1067 }
1068
1069 hpi_init_response(phr, phm->object, phm->function, 0);
1070
1071 status = &interface->outstream_host_buffer_status[phm->obj_index];
1072
1073 phr->u.d.u.stream_info.state = (u16)status->stream_state;
1074 phr->u.d.u.stream_info.samples_transferred =
1075 status->samples_processed;
1076 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1077 phr->u.d.u.stream_info.data_available =
1078 status->size_in_bytes - outstream_get_space_available(status);
1079 phr->u.d.u.stream_info.auxiliary_data_available =
1080 status->auxiliary_data_available;
1081}
1082
1083static void outstream_start(struct hpi_adapter_obj *pao,
1084 struct hpi_message *phm, struct hpi_response *phr)
1085{
1086 hw_message(pao, phm, phr);
1087}
1088
1089static void outstream_reset(struct hpi_adapter_obj *pao,
1090 struct hpi_message *phm, struct hpi_response *phr)
1091{
1092 struct hpi_hw_obj *phw = pao->priv;
1093 phw->flag_outstream_just_reset[phm->obj_index] = 1;
1094 hw_message(pao, phm, phr);
1095}
1096
1097static void outstream_open(struct hpi_adapter_obj *pao,
1098 struct hpi_message *phm, struct hpi_response *phr)
1099{
1100 outstream_reset(pao, phm, phr);
1101}
1102
1103/*****************************************************************************/
1104/* InStream Host buffer functions */
1105
1106static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1107 struct hpi_message *phm, struct hpi_response *phr)
1108{
1109 u16 err = 0;
1110 u32 command = phm->u.d.u.buffer.command;
1111 struct hpi_hw_obj *phw = pao->priv;
1112 struct bus_master_interface *interface = phw->p_interface_buffer;
1113
1114 hpi_init_response(phr, phm->object, phm->function, 0);
1115
1116 if (command == HPI_BUFFER_CMD_EXTERNAL
1117 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1118
1119 phm->u.d.u.buffer.buffer_size =
1120 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1121 phr->u.d.u.stream_info.data_available =
1122 phw->instream_host_buffer_size[phm->obj_index];
1123 phr->u.d.u.stream_info.buffer_size =
1124 phm->u.d.u.buffer.buffer_size;
1125
1126 if (phw->instream_host_buffer_size[phm->obj_index] ==
1127 phm->u.d.u.buffer.buffer_size) {
1128 /* Same size, no action required */
1129 return;
1130 }
1131
1132 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1133 obj_index]))
1134 hpios_locked_mem_free(&phw->instream_host_buffers
1135 [phm->obj_index]);
1136
1137 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1138 obj_index], phm->u.d.u.buffer.buffer_size,
1139 pao->pci.p_os_data);
1140
1141 if (err) {
1142 phr->error = HPI_ERROR_INVALID_DATASIZE;
1143 phw->instream_host_buffer_size[phm->obj_index] = 0;
1144 return;
1145 }
1146
1147 err = hpios_locked_mem_get_phys_addr
1148 (&phw->instream_host_buffers[phm->obj_index],
1149 &phm->u.d.u.buffer.pci_address);
1150 /* get the phys addr into msg for single call alloc. Caller
1151 needs to do this for split alloc so return the phy address */
1152 phr->u.d.u.stream_info.auxiliary_data_available =
1153 phm->u.d.u.buffer.pci_address;
1154 if (err) {
1155 hpios_locked_mem_free(&phw->instream_host_buffers
1156 [phm->obj_index]);
1157 phw->instream_host_buffer_size[phm->obj_index] = 0;
1158 phr->error = HPI_ERROR_MEMORY_ALLOC;
1159 return;
1160 }
1161 }
1162
1163 if (command == HPI_BUFFER_CMD_EXTERNAL
1164 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1165 struct hpi_hostbuffer_status *status;
1166
1167 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1168 buffer_size - 1)) {
1169 HPI_DEBUG_LOG(ERROR,
1170 "buffer size must be 2^N not %d\n",
1171 phm->u.d.u.buffer.buffer_size);
1172 phr->error = HPI_ERROR_INVALID_DATASIZE;
1173 return;
1174 }
1175
1176 phw->instream_host_buffer_size[phm->obj_index] =
1177 phm->u.d.u.buffer.buffer_size;
1178 status = &interface->instream_host_buffer_status[phm->
1179 obj_index];
1180 status->samples_processed = 0;
1181 status->stream_state = HPI_STATE_STOPPED;
1182 status->dSP_index = 0;
1183 status->host_index = status->dSP_index;
1184 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
1185
1186 hw_message(pao, phm, phr);
1187 if (phr->error
1188 && hpios_locked_mem_valid(&phw->
1189 instream_host_buffers[phm->obj_index])) {
1190 hpios_locked_mem_free(&phw->instream_host_buffers
1191 [phm->obj_index]);
1192 phw->instream_host_buffer_size[phm->obj_index] = 0;
1193 }
1194 }
1195}
1196
1197static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1198 struct hpi_message *phm, struct hpi_response *phr)
1199{
1200 struct hpi_hw_obj *phw = pao->priv;
1201 struct bus_master_interface *interface = phw->p_interface_buffer;
1202 struct hpi_hostbuffer_status *status;
1203 u8 *p_bbm_data;
1204
1205 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1206 obj_index])) {
1207 if (hpios_locked_mem_get_virt_addr(&phw->
1208 instream_host_buffers[phm->obj_index],
1209 (void *)&p_bbm_data)) {
1210 phr->error = HPI_ERROR_INVALID_OPERATION;
1211 return;
1212 }
1213 status = &interface->instream_host_buffer_status[phm->
1214 obj_index];
1215 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1216 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1217 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1218 phr->u.d.u.hostbuffer_info.p_status = status;
1219 } else {
1220 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1221 HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1222 HPI_ERROR_INVALID_OPERATION);
1223 }
1224}
1225
1226static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1227 struct hpi_message *phm, struct hpi_response *phr)
1228{
1229 struct hpi_hw_obj *phw = pao->priv;
1230 u32 command = phm->u.d.u.buffer.command;
1231
1232 if (phw->instream_host_buffer_size[phm->obj_index]) {
1233 if (command == HPI_BUFFER_CMD_EXTERNAL
1234 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1235 phw->instream_host_buffer_size[phm->obj_index] = 0;
1236 hw_message(pao, phm, phr);
1237 }
1238
1239 if (command == HPI_BUFFER_CMD_EXTERNAL
1240 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1241 hpios_locked_mem_free(&phw->instream_host_buffers
1242 [phm->obj_index]);
1243
1244 } else {
1245 /* Should HPI_ERROR_INVALID_OPERATION be returned
1246 if no host buffer is allocated? */
1247 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1248 HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1249
1250 }
1251
1252}
1253
1254static void instream_start(struct hpi_adapter_obj *pao,
1255 struct hpi_message *phm, struct hpi_response *phr)
1256{
1257 hw_message(pao, phm, phr);
1258}
1259
1260static long instream_get_bytes_available(struct hpi_hostbuffer_status *status)
1261{
1262 return (long)(status->dSP_index) - (long)(status->host_index);
1263}
1264
1265static void instream_read(struct hpi_adapter_obj *pao,
1266 struct hpi_message *phm, struct hpi_response *phr)
1267{
1268 struct hpi_hw_obj *phw = pao->priv;
1269 struct bus_master_interface *interface = phw->p_interface_buffer;
1270 struct hpi_hostbuffer_status *status;
1271 long data_available;
1272 u8 *p_bbm_data;
1273 long l_first_read;
1274 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1275
1276 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1277 hw_message(pao, phm, phr);
1278 return;
1279 }
1280 hpi_init_response(phr, phm->object, phm->function, 0);
1281
1282 status = &interface->instream_host_buffer_status[phm->obj_index];
1283 data_available = instream_get_bytes_available(status);
1284 if (data_available < (long)phm->u.d.u.data.data_size) {
1285 phr->error = HPI_ERROR_INVALID_DATASIZE;
1286 return;
1287 }
1288
1289 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1290 obj_index])) {
1291 if (hpios_locked_mem_get_virt_addr(&phw->
1292 instream_host_buffers[phm->obj_index],
1293 (void *)&p_bbm_data)) {
1294 phr->error = HPI_ERROR_INVALID_OPERATION;
1295 return;
1296 }
1297
1298 /* either all data,
1299 or enough to fit from current to end of BBM buffer */
1300 l_first_read =
1301 min(phm->u.d.u.data.data_size,
1302 status->size_in_bytes -
1303 (status->host_index & (status->size_in_bytes - 1)));
1304
1305 memcpy(p_app_data,
1306 p_bbm_data +
1307 (status->host_index & (status->size_in_bytes - 1)),
1308 l_first_read);
1309 /* remaining data if any */
1310 memcpy(p_app_data + l_first_read, p_bbm_data,
1311 phm->u.d.u.data.data_size - l_first_read);
1312 }
1313 status->host_index += phm->u.d.u.data.data_size;
1314}
1315
1316static void instream_get_info(struct hpi_adapter_obj *pao,
1317 struct hpi_message *phm, struct hpi_response *phr)
1318{
1319 struct hpi_hw_obj *phw = pao->priv;
1320 struct bus_master_interface *interface = phw->p_interface_buffer;
1321 struct hpi_hostbuffer_status *status;
1322 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1323 hw_message(pao, phm, phr);
1324 return;
1325 }
1326
1327 status = &interface->instream_host_buffer_status[phm->obj_index];
1328
1329 hpi_init_response(phr, phm->object, phm->function, 0);
1330
1331 phr->u.d.u.stream_info.state = (u16)status->stream_state;
1332 phr->u.d.u.stream_info.samples_transferred =
1333 status->samples_processed;
1334 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1335 phr->u.d.u.stream_info.data_available =
1336 instream_get_bytes_available(status);
1337 phr->u.d.u.stream_info.auxiliary_data_available =
1338 status->auxiliary_data_available;
1339}
1340
1341/*****************************************************************************/
1342/* LOW-LEVEL */
1343#define HPI6205_MAX_FILES_TO_LOAD 2
1344
1345static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1346 u32 *pos_error_code)
1347{
1348 struct hpi_hw_obj *phw = pao->priv;
1349 struct dsp_code dsp_code;
1350 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1351 u16 firmware_id = pao->pci.subsys_device_id;
1352 u32 temp;
1353 int dsp = 0, i = 0;
1354 u16 err = 0;
1355
1356 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1357
1358 /* special cases where firmware_id != subsys ID */
1359 switch (firmware_id) {
1360 case HPI_ADAPTER_FAMILY_ASI(0x5000):
1361 boot_code_id[0] = firmware_id;
1362 firmware_id = 0;
1363 break;
1364 case HPI_ADAPTER_FAMILY_ASI(0x5300):
1365 case HPI_ADAPTER_FAMILY_ASI(0x5400):
1366 case HPI_ADAPTER_FAMILY_ASI(0x6300):
1367 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x6400);
1368 break;
1369 case HPI_ADAPTER_FAMILY_ASI(0x5600):
1370 case HPI_ADAPTER_FAMILY_ASI(0x6500):
1371 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x6600);
1372 break;
1373 }
1374 boot_code_id[1] = firmware_id;
1375
1376 /* reset DSP by writing a 1 to the WARMRESET bit */
1377 temp = C6205_HDCR_WARMRESET;
1378 iowrite32(temp, phw->prHDCR);
1379 hpios_delay_micro_seconds(1000);
1380
1381 /* check that PCI i/f was configured by EEPROM */
1382 temp = ioread32(phw->prHSR);
1383 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1384 C6205_HSR_EEREAD)
1385 return hpi6205_error(0, HPI6205_ERROR_6205_EEPROM);
1386 temp |= 0x04;
1387 /* disable PINTA interrupt */
1388 iowrite32(temp, phw->prHSR);
1389
1390 /* check control register reports PCI boot mode */
1391 temp = ioread32(phw->prHDCR);
1392 if (!(temp & C6205_HDCR_PCIBOOT))
1393 return hpi6205_error(0, HPI6205_ERROR_6205_REG);
1394
1395 /* try writing a couple of numbers to the DSP page register */
1396 /* and reading them back. */
1397 temp = 1;
1398 iowrite32(temp, phw->prDSPP);
1399 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1400 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1401 temp = 2;
1402 iowrite32(temp, phw->prDSPP);
1403 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1404 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1405 temp = 3;
1406 iowrite32(temp, phw->prDSPP);
1407 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1408 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1409 /* reset DSP page to the correct number */
1410 temp = 0;
1411 iowrite32(temp, phw->prDSPP);
1412 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1413 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1414 phw->dsp_page = 0;
1415
1416 /* release 6713 from reset before 6205 is bootloaded.
1417 This ensures that the EMIF is inactive,
1418 and the 6713 HPI gets the correct bootmode etc
1419 */
1420 if (boot_code_id[1] != 0) {
1421 /* DSP 1 is a C6713 */
1422 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1423 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202);
1424 hpios_delay_micro_seconds(100);
1425 /* Reset the 6713 #1 - revB */
1426 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1427
1428 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1429 boot_loader_read_mem32(pao, 0, 0);
1430
1431 hpios_delay_micro_seconds(100);
1432 /* Release C6713 from reset - revB */
1433 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1434 hpios_delay_micro_seconds(100);
1435 }
1436
1437 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1438 /* is there a DSP to load? */
1439 if (boot_code_id[dsp] == 0)
1440 continue;
1441
1442 err = boot_loader_config_emif(pao, dsp);
1443 if (err)
1444 return err;
1445
1446 err = boot_loader_test_internal_memory(pao, dsp);
1447 if (err)
1448 return err;
1449
1450 err = boot_loader_test_external_memory(pao, dsp);
1451 if (err)
1452 return err;
1453
1454 err = boot_loader_test_pld(pao, dsp);
1455 if (err)
1456 return err;
1457
1458 /* write the DSP code down into the DSPs memory */
1459 dsp_code.ps_dev = pao->pci.p_os_data;
1460 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code,
1461 pos_error_code);
1462 if (err)
1463 return err;
1464
1465 while (1) {
1466 u32 length;
1467 u32 address;
1468 u32 type;
1469 u32 *pcode;
1470
1471 err = hpi_dsp_code_read_word(&dsp_code, &length);
1472 if (err)
1473 break;
1474 if (length == 0xFFFFFFFF)
1475 break; /* end of code */
1476
1477 err = hpi_dsp_code_read_word(&dsp_code, &address);
1478 if (err)
1479 break;
1480 err = hpi_dsp_code_read_word(&dsp_code, &type);
1481 if (err)
1482 break;
1483 err = hpi_dsp_code_read_block(length, &dsp_code,
1484 &pcode);
1485 if (err)
1486 break;
1487 for (i = 0; i < (int)length; i++) {
1488 err = boot_loader_write_mem32(pao, dsp,
1489 address, *pcode);
1490 if (err)
1491 break;
1492 /* dummy read every 4 words */
1493 /* for 6205 advisory 1.4.4 */
1494 if (i % 4 == 0)
1495 boot_loader_read_mem32(pao, dsp,
1496 address);
1497 pcode++;
1498 address += 4;
1499 }
1500
1501 }
1502 if (err) {
1503 hpi_dsp_code_close(&dsp_code);
1504 return err;
1505 }
1506
1507 /* verify code */
1508 hpi_dsp_code_rewind(&dsp_code);
1509 while (1) {
1510 u32 length = 0;
1511 u32 address = 0;
1512 u32 type = 0;
1513 u32 *pcode = NULL;
1514 u32 data = 0;
1515
1516 hpi_dsp_code_read_word(&dsp_code, &length);
1517 if (length == 0xFFFFFFFF)
1518 break; /* end of code */
1519
1520 hpi_dsp_code_read_word(&dsp_code, &address);
1521 hpi_dsp_code_read_word(&dsp_code, &type);
1522 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1523
1524 for (i = 0; i < (int)length; i++) {
1525 data = boot_loader_read_mem32(pao, dsp,
1526 address);
1527 if (data != *pcode) {
1528 err = 0;
1529 break;
1530 }
1531 pcode++;
1532 address += 4;
1533 }
1534 if (err)
1535 break;
1536 }
1537 hpi_dsp_code_close(&dsp_code);
1538 if (err)
1539 return err;
1540 }
1541
1542 /* After bootloading all DSPs, start DSP0 running
1543 * The DSP0 code will handle starting and synchronizing with its slaves
1544 */
1545 if (phw->p_interface_buffer) {
1546 /* we need to tell the card the physical PCI address */
1547 u32 physicalPC_iaddress;
1548 struct bus_master_interface *interface =
1549 phw->p_interface_buffer;
1550 u32 host_mailbox_address_on_dsp;
1551 u32 physicalPC_iaddress_verify = 0;
1552 int time_out = 10;
1553 /* set ack so we know when DSP is ready to go */
1554 /* (dwDspAck will be changed to HIF_RESET) */
1555 interface->dsp_ack = H620_HIF_UNKNOWN;
1556 wmb(); /* ensure ack is written before dsp writes back */
1557
1558 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1559 &physicalPC_iaddress);
1560
1561 /* locate the host mailbox on the DSP. */
1562 host_mailbox_address_on_dsp = 0x80000000;
1563 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1564 && time_out--) {
1565 err = boot_loader_write_mem32(pao, 0,
1566 host_mailbox_address_on_dsp,
1567 physicalPC_iaddress);
1568 physicalPC_iaddress_verify =
1569 boot_loader_read_mem32(pao, 0,
1570 host_mailbox_address_on_dsp);
1571 }
1572 }
1573 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1574 /* enable interrupts */
1575 temp = ioread32(phw->prHSR);
1576 temp &= ~(u32)C6205_HSR_INTAM;
1577 iowrite32(temp, phw->prHSR);
1578
1579 /* start code running... */
1580 temp = ioread32(phw->prHDCR);
1581 temp |= (u32)C6205_HDCR_DSPINT;
1582 iowrite32(temp, phw->prHDCR);
1583
1584 /* give the DSP 10ms to start up */
1585 hpios_delay_micro_seconds(10000);
1586 return err;
1587
1588}
1589
1590/*****************************************************************************/
1591/* Bootloader utility functions */
1592
1593static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1594 u32 address)
1595{
1596 struct hpi_hw_obj *phw = pao->priv;
1597 u32 data = 0;
1598 __iomem u32 *p_data;
1599
1600 if (dsp_index == 0) {
1601 /* DSP 0 is always C6205 */
1602 if ((address >= 0x01800000) & (address < 0x02000000)) {
1603 /* BAR1 register access */
1604 p_data = pao->pci.ap_mem_base[1] +
1605 (address & 0x007fffff) /
1606 sizeof(*pao->pci.ap_mem_base[1]);
1607 /* HPI_DEBUG_LOG(WARNING,
1608 "BAR1 access %08x\n", dwAddress); */
1609 } else {
1610 u32 dw4M_page = address >> 22L;
1611 if (dw4M_page != phw->dsp_page) {
1612 phw->dsp_page = dw4M_page;
1613 /* *INDENT OFF* */
1614 iowrite32(phw->dsp_page, phw->prDSPP);
1615 /* *INDENT-ON* */
1616 }
1617 address &= 0x3fffff; /* address within 4M page */
1618 /* BAR0 memory access */
1619 p_data = pao->pci.ap_mem_base[0] +
1620 address / sizeof(u32);
1621 }
1622 data = ioread32(p_data);
1623 } else if (dsp_index == 1) {
1624 /* DSP 1 is a C6713 */
1625 u32 lsb;
1626 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1627 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1628 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1629 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1630 data = (data << 16) | (lsb & 0xFFFF);
1631 }
1632 return data;
1633}
1634
1635static u16 boot_loader_write_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1636 u32 address, u32 data)
1637{
1638 struct hpi_hw_obj *phw = pao->priv;
1639 u16 err = 0;
1640 __iomem u32 *p_data;
1641 /* u32 dwVerifyData=0; */
1642
1643 if (dsp_index == 0) {
1644 /* DSP 0 is always C6205 */
1645 if ((address >= 0x01800000) & (address < 0x02000000)) {
1646 /* BAR1 - DSP register access using */
1647 /* Non-prefetchable PCI access */
1648 p_data = pao->pci.ap_mem_base[1] +
1649 (address & 0x007fffff) /
1650 sizeof(*pao->pci.ap_mem_base[1]);
1651 } else {
1652 /* BAR0 access - all of DSP memory using */
1653 /* pre-fetchable PCI access */
1654 u32 dw4M_page = address >> 22L;
1655 if (dw4M_page != phw->dsp_page) {
1656 phw->dsp_page = dw4M_page;
1657 /* *INDENT-OFF* */
1658 iowrite32(phw->dsp_page, phw->prDSPP);
1659 /* *INDENT-ON* */
1660 }
1661 address &= 0x3fffff; /* address within 4M page */
1662 p_data = pao->pci.ap_mem_base[0] +
1663 address / sizeof(u32);
1664 }
1665 iowrite32(data, p_data);
1666 } else if (dsp_index == 1) {
1667 /* DSP 1 is a C6713 */
1668 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1669 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1670
1671 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1672 boot_loader_read_mem32(pao, 0, 0);
1673
1674 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1675 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1676
1677 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1678 boot_loader_read_mem32(pao, 0, 0);
1679 } else
1680 err = hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1681 return err;
1682}
1683
1684static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1685{
1686 u16 err = 0;
1687
1688 if (dsp_index == 0) {
1689 u32 setting;
1690
1691 /* DSP 0 is always C6205 */
1692
1693 /* Set the EMIF */
1694 /* memory map of C6205 */
1695 /* 00000000-0000FFFF 16Kx32 internal program */
1696 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */
1697
1698 /* EMIF config */
1699 /*------------ */
1700 /* Global EMIF control */
1701 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1702#define WS_OFS 28
1703#define WST_OFS 22
1704#define WH_OFS 20
1705#define RS_OFS 16
1706#define RST_OFS 8
1707#define MTYPE_OFS 4
1708#define RH_OFS 0
1709
1710 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1711 setting = 0x00000030;
1712 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1713 if (setting != boot_loader_read_mem32(pao, dsp_index,
1714 0x01800008))
1715 return hpi6205_error(dsp_index,
1716 HPI6205_ERROR_DSP_EMIF);
1717
1718 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1719 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1720 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1721 /* WST should be 71, but 63 is max possible */
1722 setting =
1723 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1724 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1725 (2L << MTYPE_OFS);
1726 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1727 if (setting != boot_loader_read_mem32(pao, dsp_index,
1728 0x01800004))
1729 return hpi6205_error(dsp_index,
1730 HPI6205_ERROR_DSP_EMIF);
1731
1732 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1733 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1734 /* plenty of wait states */
1735 setting =
1736 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1737 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1738 (2L << MTYPE_OFS);
1739 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1740 if (setting != boot_loader_read_mem32(pao, dsp_index,
1741 0x01800010))
1742 return hpi6205_error(dsp_index,
1743 HPI6205_ERROR_DSP_EMIF);
1744
1745 /* EMIF CE3 setup - 32 bit async. */
1746 /* This is the PLD on the ASI5000 cards only */
1747 setting =
1748 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1749 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1750 (2L << MTYPE_OFS);
1751 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1752 if (setting != boot_loader_read_mem32(pao, dsp_index,
1753 0x01800014))
1754 return hpi6205_error(dsp_index,
1755 HPI6205_ERROR_DSP_EMIF);
1756
1757 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1758 /* need to use this else DSP code crashes? */
1759 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1760 0x07117000);
1761
1762 /* EMIF SDRAM Refresh Timing */
1763 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */
1764 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1765 0x00000410);
1766
1767 } else if (dsp_index == 1) {
1768 /* test access to the C6713s HPI registers */
1769 u32 write_data = 0, read_data = 0, i = 0;
1770
1771 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1772 write_data = 1;
1773 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1774 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1775 /* C67 HPI is on lower 16bits of 32bit EMIF */
1776 read_data =
1777 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1778 if (write_data != read_data) {
1779 err = hpi6205_error(dsp_index,
1780 HPI6205_ERROR_C6713_HPIC);
1781 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1782 read_data);
1783
1784 return err;
1785 }
1786 /* HPIA - walking ones test */
1787 write_data = 1;
1788 for (i = 0; i < 32; i++) {
1789 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1790 write_data);
1791 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1792 (write_data >> 16));
1793 read_data =
1794 0xFFFF & boot_loader_read_mem32(pao, 0,
1795 HPIAL_ADDR);
1796 read_data =
1797 read_data | ((0xFFFF &
1798 boot_loader_read_mem32(pao, 0,
1799 HPIAH_ADDR))
1800 << 16);
1801 if (read_data != write_data) {
1802 err = hpi6205_error(dsp_index,
1803 HPI6205_ERROR_C6713_HPIA);
1804 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1805 write_data, read_data);
1806 return err;
1807 }
1808 write_data = write_data << 1;
1809 }
1810
1811 /* setup C67x PLL
1812 * ** C6713 datasheet says we cannot program PLL from HPI,
1813 * and indeed if we try to set the PLL multiply from the HPI,
1814 * the PLL does not seem to lock, so we enable the PLL and
1815 * use the default multiply of x 7, which for a 27MHz clock
1816 * gives a DSP speed of 189MHz
1817 */
1818 /* bypass PLL */
1819 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1820 hpios_delay_micro_seconds(1000);
1821 /* EMIF = 189/3=63MHz */
1822 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1823 /* peri = 189/2 */
1824 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1825 /* cpu = 189/1 */
1826 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1827 hpios_delay_micro_seconds(1000);
1828 /* ** SGT test to take GPO3 high when we start the PLL */
1829 /* and low when the delay is completed */
1830 /* FSX0 <- '1' (GPO3) */
1831 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1832 /* PLL not bypassed */
1833 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1834 hpios_delay_micro_seconds(1000);
1835 /* FSX0 <- '0' (GPO3) */
1836 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1837
1838 /* 6205 EMIF CE1 resetup - 32 bit async. */
1839 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1840 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */
1841 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1842 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1843 (2L << MTYPE_OFS));
1844
1845 hpios_delay_micro_seconds(1000);
1846
1847 /* check that we can read one of the PLL registers */
1848 /* PLL should not be bypassed! */
1849 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1850 != 0x0001) {
1851 err = hpi6205_error(dsp_index,
1852 HPI6205_ERROR_C6713_PLL);
1853 return err;
1854 }
1855 /* setup C67x EMIF (note this is the only use of
1856 BAR1 via BootLoader_WriteMem32) */
1857 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1858 0x000034A8);
1859 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1860 0x00000030);
1861 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1862 0x001BDF29);
1863 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1864 0x47117000);
1865 boot_loader_write_mem32(pao, dsp_index,
1866 C6713_EMIF_SDRAMTIMING, 0x00000410);
1867
1868 hpios_delay_micro_seconds(1000);
1869 } else if (dsp_index == 2) {
1870 /* DSP 2 is a C6713 */
1871
1872 } else
1873 err = hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1874 return err;
1875}
1876
1877static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1878 u32 start_address, u32 length)
1879{
1880 u32 i = 0, j = 0;
1881 u32 test_addr = 0;
1882 u32 test_data = 0, data = 0;
1883
1884 length = 1000;
1885
1886 /* for 1st word, test each bit in the 32bit word, */
1887 /* dwLength specifies number of 32bit words to test */
1888 /*for(i=0; i<dwLength; i++) */
1889 i = 0;
1890 {
1891 test_addr = start_address + i * 4;
1892 test_data = 0x00000001;
1893 for (j = 0; j < 32; j++) {
1894 boot_loader_write_mem32(pao, dsp_index, test_addr,
1895 test_data);
1896 data = boot_loader_read_mem32(pao, dsp_index,
1897 test_addr);
1898 if (data != test_data) {
1899 HPI_DEBUG_LOG(VERBOSE,
1900 "memtest error details "
1901 "%08x %08x %08x %i\n", test_addr,
1902 test_data, data, dsp_index);
1903 return 1; /* error */
1904 }
1905 test_data = test_data << 1;
1906 } /* for(j) */
1907 } /* for(i) */
1908
1909 /* for the next 100 locations test each location, leaving it as zero */
1910 /* write a zero to the next word in memory before we read */
1911 /* the previous write to make sure every memory location is unique */
1912 for (i = 0; i < 100; i++) {
1913 test_addr = start_address + i * 4;
1914 test_data = 0xA5A55A5A;
1915 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1916 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1917 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1918 if (data != test_data) {
1919 HPI_DEBUG_LOG(VERBOSE,
1920 "memtest error details "
1921 "%08x %08x %08x %i\n", test_addr, test_data,
1922 data, dsp_index);
1923 return 1; /* error */
1924 }
1925 /* leave location as zero */
1926 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1927 }
1928
1929 /* zero out entire memory block */
1930 for (i = 0; i < length; i++) {
1931 test_addr = start_address + i * 4;
1932 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1933 }
1934 return 0;
1935}
1936
1937static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1938 int dsp_index)
1939{
1940 int err = 0;
1941 if (dsp_index == 0) {
1942 /* DSP 0 is a C6205 */
1943 /* 64K prog mem */
1944 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1945 0x10000);
1946 if (!err)
1947 /* 64K data mem */
1948 err = boot_loader_test_memory(pao, dsp_index,
1949 0x80000000, 0x10000);
1950 } else if ((dsp_index == 1) || (dsp_index == 2)) {
1951 /* DSP 1&2 are a C6713 */
1952 /* 192K internal mem */
1953 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1954 0x30000);
1955 if (!err)
1956 /* 64K internal mem / L2 cache */
1957 err = boot_loader_test_memory(pao, dsp_index,
1958 0x00030000, 0x10000);
1959 } else
1960 return hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1961
1962 if (err)
1963 return hpi6205_error(dsp_index, HPI6205_ERROR_DSP_INTMEM);
1964 else
1965 return 0;
1966}
1967
1968static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1969 int dsp_index)
1970{
1971 u32 dRAM_start_address = 0;
1972 u32 dRAM_size = 0;
1973
1974 if (dsp_index == 0) {
1975 /* only test for SDRAM if an ASI5000 card */
1976 if (pao->pci.subsys_device_id == 0x5000) {
1977 /* DSP 0 is always C6205 */
1978 dRAM_start_address = 0x00400000;
1979 dRAM_size = 0x200000;
1980 /*dwDRAMinc=1024; */
1981 } else
1982 return 0;
1983 } else if ((dsp_index == 1) || (dsp_index == 2)) {
1984 /* DSP 1 is a C6713 */
1985 dRAM_start_address = 0x80000000;
1986 dRAM_size = 0x200000;
1987 /*dwDRAMinc=1024; */
1988 } else
1989 return hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1990
1991 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1992 dRAM_size))
1993 return hpi6205_error(dsp_index, HPI6205_ERROR_DSP_EXTMEM);
1994 return 0;
1995}
1996
1997static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1998{
1999 u32 data = 0;
2000 if (dsp_index == 0) {
2001 /* only test for DSP0 PLD on ASI5000 card */
2002 if (pao->pci.subsys_device_id == 0x5000) {
2003 /* PLD is located at CE3=0x03000000 */
2004 data = boot_loader_read_mem32(pao, dsp_index,
2005 0x03000008);
2006 if ((data & 0xF) != 0x5)
2007 return hpi6205_error(dsp_index,
2008 HPI6205_ERROR_DSP_PLD);
2009 data = boot_loader_read_mem32(pao, dsp_index,
2010 0x0300000C);
2011 if ((data & 0xF) != 0xA)
2012 return hpi6205_error(dsp_index,
2013 HPI6205_ERROR_DSP_PLD);
2014 }
2015 } else if (dsp_index == 1) {
2016 /* DSP 1 is a C6713 */
2017 if (pao->pci.subsys_device_id == 0x8700) {
2018 /* PLD is located at CE1=0x90000000 */
2019 data = boot_loader_read_mem32(pao, dsp_index,
2020 0x90000010);
2021 if ((data & 0xFF) != 0xAA)
2022 return hpi6205_error(dsp_index,
2023 HPI6205_ERROR_DSP_PLD);
2024 /* 8713 - LED on */
2025 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
2026 0x02);
2027 }
2028 }
2029 return 0;
2030}
2031
2032/** Transfer data to or from DSP
2033 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
2034*/
2035static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
2036 u32 data_size, int operation)
2037{
2038 struct hpi_hw_obj *phw = pao->priv;
2039 u32 data_transferred = 0;
2040 u16 err = 0;
2041#ifndef HPI6205_NO_HSR_POLL
2042 u32 time_out;
2043#endif
2044 u32 temp2;
2045 struct bus_master_interface *interface = phw->p_interface_buffer;
2046
2047 if (!p_data)
2048 return HPI_ERROR_INVALID_DATA_TRANSFER;
2049
2050 data_size &= ~3L; /* round data_size down to nearest 4 bytes */
2051
2052 /* make sure state is IDLE */
2053 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
2054 return HPI_ERROR_DSP_HARDWARE;
2055
2056 while (data_transferred < data_size) {
2057 u32 this_copy = data_size - data_transferred;
2058
2059 if (this_copy > HPI6205_SIZEOF_DATA)
2060 this_copy = HPI6205_SIZEOF_DATA;
2061
2062 if (operation == H620_HIF_SEND_DATA)
2063 memcpy((void *)&interface->u.b_data[0],
2064 &p_data[data_transferred], this_copy);
2065
2066 interface->transfer_size_in_bytes = this_copy;
2067
2068#ifdef HPI6205_NO_HSR_POLL
2069 /* DSP must change this back to nOperation */
2070 interface->dsp_ack = H620_HIF_IDLE;
2071#endif
2072
2073 send_dsp_command(phw, operation);
2074
2075#ifdef HPI6205_NO_HSR_POLL
2076 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2077 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2078 HPI6205_TIMEOUT - temp2, this_copy);
2079
2080 if (!temp2) {
2081 /* timed out */
2082 HPI_DEBUG_LOG(ERROR,
2083 "timed out waiting for " "state %d got %d\n",
2084 operation, interface->dsp_ack);
2085
2086 break;
2087 }
2088#else
2089 /* spin waiting on the result */
2090 time_out = HPI6205_TIMEOUT;
2091 temp2 = 0;
2092 while ((temp2 == 0) && time_out--) {
2093 /* give 16k bus mastering transfer time to happen */
2094 /*(16k / 132Mbytes/s = 122usec) */
2095 hpios_delay_micro_seconds(20);
2096 temp2 = ioread32(phw->prHSR);
2097 temp2 &= C6205_HSR_INTSRC;
2098 }
2099 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2100 HPI6205_TIMEOUT - time_out, this_copy);
2101 if (temp2 == C6205_HSR_INTSRC) {
2102 HPI_DEBUG_LOG(VERBOSE,
2103 "interrupt from HIF <data> OK\n");
2104 /*
2105 if(interface->dwDspAck != nOperation) {
2106 HPI_DEBUG_LOG(DEBUG("interface->dwDspAck=%d,
2107 expected %d \n",
2108 interface->dwDspAck,nOperation);
2109 }
2110 */
2111 }
2112/* need to handle this differently... */
2113 else {
2114 HPI_DEBUG_LOG(ERROR,
2115 "interrupt from HIF <data> BAD\n");
2116 err = HPI_ERROR_DSP_HARDWARE;
2117 }
2118
2119 /* reset the interrupt from the DSP */
2120 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2121#endif
2122 if (operation == H620_HIF_GET_DATA)
2123 memcpy(&p_data[data_transferred],
2124 (void *)&interface->u.b_data[0], this_copy);
2125
2126 data_transferred += this_copy;
2127 }
2128 if (interface->dsp_ack != operation)
2129 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2130 interface->dsp_ack, operation);
2131 /* err=HPI_ERROR_DSP_HARDWARE; */
2132
2133 send_dsp_command(phw, H620_HIF_IDLE);
2134
2135 return err;
2136}
2137
2138/* wait for up to timeout_us microseconds for the DSP
2139 to signal state by DMA into dwDspAck
2140*/
2141static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2142{
2143 struct bus_master_interface *interface = phw->p_interface_buffer;
2144 int t = timeout_us / 4;
2145
2146 rmb(); /* ensure interface->dsp_ack is up to date */
2147 while ((interface->dsp_ack != state) && --t) {
2148 hpios_delay_micro_seconds(4);
2149 rmb(); /* DSP changes dsp_ack by DMA */
2150 }
2151
2152 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2153 return t * 4;
2154}
2155
2156/* set the busmaster interface to cmd, then interrupt the DSP */
2157static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2158{
2159 struct bus_master_interface *interface = phw->p_interface_buffer;
2160
2161 u32 r;
2162
2163 interface->host_cmd = cmd;
2164 wmb(); /* DSP gets state by DMA, make sure it is written to memory */
2165 /* before we interrupt the DSP */
2166 r = ioread32(phw->prHDCR);
2167 r |= (u32)C6205_HDCR_DSPINT;
2168 iowrite32(r, phw->prHDCR);
2169 r &= ~(u32)C6205_HDCR_DSPINT;
2170 iowrite32(r, phw->prHDCR);
2171}
2172
2173static unsigned int message_count;
2174
2175static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2176 struct hpi_message *phm, struct hpi_response *phr)
2177{
2178#ifndef HPI6205_NO_HSR_POLL
2179 u32 temp2;
2180#endif
2181 u32 time_out, time_out2;
2182 struct hpi_hw_obj *phw = pao->priv;
2183 struct bus_master_interface *interface = phw->p_interface_buffer;
2184 u16 err = 0;
2185
2186 message_count++;
2187 /* Assume buffer of type struct bus_master_interface
2188 is allocated "noncacheable" */
2189
2190 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2191 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2192 return hpi6205_error(0, HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT);
2193 }
2194 interface->u.message_buffer = *phm;
2195 /* signal we want a response */
2196 send_dsp_command(phw, H620_HIF_GET_RESP);
2197
2198 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2199
2200 if (time_out2 == 0) {
2201 HPI_DEBUG_LOG(ERROR,
2202 "(%u) timed out waiting for " "GET_RESP state [%x]\n",
2203 message_count, interface->dsp_ack);
2204 } else {
2205 HPI_DEBUG_LOG(VERBOSE,
2206 "(%u) transition to GET_RESP after %u\n",
2207 message_count, HPI6205_TIMEOUT - time_out2);
2208 }
2209 /* spin waiting on HIF interrupt flag (end of msg process) */
2210 time_out = HPI6205_TIMEOUT;
2211
2212#ifndef HPI6205_NO_HSR_POLL
2213 temp2 = 0;
2214 while ((temp2 == 0) && --time_out) {
2215 temp2 = ioread32(phw->prHSR);
2216 temp2 &= C6205_HSR_INTSRC;
2217 hpios_delay_micro_seconds(1);
2218 }
2219 if (temp2 == C6205_HSR_INTSRC) {
2220 rmb(); /* ensure we see latest value for dsp_ack */
2221 if ((interface->dsp_ack != H620_HIF_GET_RESP)) {
2222 HPI_DEBUG_LOG(DEBUG,
2223 "(%u)interface->dsp_ack(0x%x) != "
2224 "H620_HIF_GET_RESP, t=%u\n", message_count,
2225 interface->dsp_ack,
2226 HPI6205_TIMEOUT - time_out);
2227 } else {
2228 HPI_DEBUG_LOG(VERBOSE,
2229 "(%u)int with GET_RESP after %u\n",
2230 message_count, HPI6205_TIMEOUT - time_out);
2231 }
2232
2233 } else {
2234 /* can we do anything else in response to the error ? */
2235 HPI_DEBUG_LOG(ERROR,
2236 "interrupt from HIF module BAD (function %x)\n",
2237 phm->function);
2238 }
2239
2240 /* reset the interrupt from the DSP */
2241 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2242#endif
2243
2244 /* read the result */
2245 if (time_out != 0)
2246 *phr = interface->u.response_buffer;
2247
2248 /* set interface back to idle */
2249 send_dsp_command(phw, H620_HIF_IDLE);
2250
2251 if ((time_out == 0) || (time_out2 == 0)) {
2252 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2253 return hpi6205_error(0, HPI6205_ERROR_MSG_RESP_TIMEOUT);
2254 }
2255 /* special case for adapter close - */
2256 /* wait for the DSP to indicate it is idle */
2257 if (phm->function == HPI_ADAPTER_CLOSE) {
2258 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2259 HPI_DEBUG_LOG(DEBUG,
2260 "timeout waiting for idle "
2261 "(on adapter_close)\n");
2262 return hpi6205_error(0,
2263 HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT);
2264 }
2265 }
2266 err = hpi_validate_response(phm, phr);
2267 return err;
2268}
2269
2270static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2271 struct hpi_response *phr)
2272{
2273
2274 u16 err = 0;
2275
2276 hpios_dsplock_lock(pao);
2277
2278 err = message_response_sequence(pao, phm, phr);
2279
2280 /* maybe an error response */
2281 if (err) {
2282 /* something failed in the HPI/DSP interface */
2283 phr->error = err;
2284 pao->dsp_crashed++;
2285
2286 /* just the header of the response is valid */
2287 phr->size = sizeof(struct hpi_response_header);
2288 goto err;
2289 } else
2290 pao->dsp_crashed = 0;
2291
2292 if (phr->error != 0) /* something failed in the DSP */
2293 goto err;
2294
2295 switch (phm->function) {
2296 case HPI_OSTREAM_WRITE:
2297 case HPI_ISTREAM_ANC_WRITE:
2298 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2299 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2300 break;
2301
2302 case HPI_ISTREAM_READ:
2303 case HPI_OSTREAM_ANC_READ:
2304 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2305 phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2306 break;
2307
2308 case HPI_CONTROL_SET_STATE:
2309 if (phm->object == HPI_OBJ_CONTROLEX
2310 && phm->u.cx.attribute == HPI_COBRANET_SET_DATA)
2311 err = hpi6205_transfer_data(pao,
2312 phm->u.cx.u.cobranet_bigdata.pb_data,
2313 phm->u.cx.u.cobranet_bigdata.byte_count,
2314 H620_HIF_SEND_DATA);
2315 break;
2316
2317 case HPI_CONTROL_GET_STATE:
2318 if (phm->object == HPI_OBJ_CONTROLEX
2319 && phm->u.cx.attribute == HPI_COBRANET_GET_DATA)
2320 err = hpi6205_transfer_data(pao,
2321 phm->u.cx.u.cobranet_bigdata.pb_data,
2322 phr->u.cx.u.cobranet_data.byte_count,
2323 H620_HIF_GET_DATA);
2324 break;
2325 }
2326 phr->error = err;
2327
2328err:
2329 hpios_dsplock_unlock(pao);
2330
2331 return;
2332}
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