[net-next-2.6.git] / sound / arm / pxa2xx-ac97.c

/*
 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/delay.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>

#include <asm/irq.h>
#include <linux/mutex.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/audio.h>

#include "pxa2xx-pcm.h"


static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
#ifdef CONFIG_PXA27x
static struct clk *ac97conf_clk;
#endif

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */ 

static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;			
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}

static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}

static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
{
	/* First, try cold reset */
#ifdef CONFIG_PXA3xx
	int timeout;

	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;
#endif

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;
#ifdef CONFIG_PXA27x
	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_enable(ac97conf_clk);
	udelay(5);
	clk_disable(ac97conf_clk);
	GCR = GCR_COLD_RST;
	udelay(50);
#elif defined(CONFIG_PXA3xx)
	timeout = 1000;
	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
	while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(10);
#else
	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif

	if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr_bits);

		/* let's try warm reset */
		gsr_bits = 0;
#ifdef CONFIG_PXA27x
		/* warm reset broken on Bulverde,
		   so manually keep AC97 reset high */
		pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 
		udelay(10);
		GCR |= GCR_WARM_RST;
		pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
		udelay(500);
#elif defined(CONFIG_PXA3xx)
		timeout = 100;
		/* Can't use interrupts */
		GCR |= GCR_WARM_RST;
		while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
			mdelay(1);
#else
		GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;
		wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif			

		if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
			printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
					 __func__, gsr_bits);
	}

	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

#ifdef CONFIG_PXA27x
		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		MISR = MISR_EOC;
		PISR = PISR_EOC;
		MCSR = MCSR_EOC;
#endif

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
	.read	= pxa2xx_ac97_read,
	.write	= pxa2xx_ac97_write,
	.reset	= pxa2xx_ac97_reset,
};

static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
	.name			= "AC97 PCM out",
	.dev_addr		= __PREG(PCDR),
	.drcmr			= &DRCMRTXPCDR,
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
	.name			= "AC97 PCM in",
	.dev_addr		= __PREG(PCDR),
	.drcmr			= &DRCMRRXPCDR,
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct snd_pcm *pxa2xx_ac97_pcm;
static struct snd_ac97 *pxa2xx_ac97_ac97;

static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	pxa2xx_audio_ops_t *platform_ops;
	int r;

	runtime->hw.channels_min = 2;
	runtime->hw.channels_max = 2;

	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	    AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
	snd_pcm_limit_hw_rates(runtime);

       	platform_ops = substream->pcm->card->dev->platform_data;
	if (platform_ops && platform_ops->startup)
		return platform_ops->startup(substream, platform_ops->priv);
	else
		return 0;
}

static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
{
	pxa2xx_audio_ops_t *platform_ops;

       	platform_ops = substream->pcm->card->dev->platform_data;
	if (platform_ops && platform_ops->shutdown)
		platform_ops->shutdown(substream, platform_ops->priv);
}

static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
		  AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
}

static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
	.playback_params	= &pxa2xx_ac97_pcm_out,
	.capture_params		= &pxa2xx_ac97_pcm_in,
	.startup		= pxa2xx_ac97_pcm_startup,
	.shutdown		= pxa2xx_ac97_pcm_shutdown,
	.prepare		= pxa2xx_ac97_pcm_prepare,
};

#ifdef CONFIG_PM

static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
{
	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;

	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
	snd_pcm_suspend_all(pxa2xx_ac97_pcm);
	snd_ac97_suspend(pxa2xx_ac97_ac97);
	if (platform_ops && platform_ops->suspend)
		platform_ops->suspend(platform_ops->priv);
	GCR |= GCR_ACLINK_OFF;
	clk_disable(ac97_clk);

	return 0;
}

static int pxa2xx_ac97_do_resume(struct snd_card *card)
{
	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;

	clk_enable(ac97_clk);
	if (platform_ops && platform_ops->resume)
		platform_ops->resume(platform_ops->priv);
	snd_ac97_resume(pxa2xx_ac97_ac97);
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}

static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
{
	struct snd_card *card = platform_get_drvdata(dev);
	int ret = 0;

	if (card)
		ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);

	return ret;
}

static int pxa2xx_ac97_resume(struct platform_device *dev)
{
	struct snd_card *card = platform_get_drvdata(dev);
	int ret = 0;

	if (card)
		ret = pxa2xx_ac97_do_resume(card);

	return ret;
}

#else
#define pxa2xx_ac97_suspend	NULL
#define pxa2xx_ac97_resume	NULL
#endif

static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
{
	struct snd_card *card;
	struct snd_ac97_bus *ac97_bus;
	struct snd_ac97_template ac97_template;
	int ret;

	ret = -ENOMEM;
	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			    THIS_MODULE, 0);
	if (!card)
		goto err;

	card->dev = &dev->dev;
	strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));

	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
	if (ret)
		goto err;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err;

	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
#ifdef CONFIG_PXA27x
	/* Use GPIO 113 as AC97 Reset on Bulverde */
	pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	if (IS_ERR(ac97conf_clk)) {
		ret = PTR_ERR(ac97conf_clk);
		ac97conf_clk = NULL;
		goto err;
	}
#endif

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err;
	}
	clk_enable(ac97_clk);

	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
	if (ret)
		goto err;
	memset(&ac97_template, 0, sizeof(ac97_template));
	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
	if (ret)
		goto err;

	snprintf(card->shortname, sizeof(card->shortname),
		 "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
	snprintf(card->longname, sizeof(card->longname),
		 "%s (%s)", dev->dev.driver->name, card->mixername);

	snd_card_set_dev(card, &dev->dev);
	ret = snd_card_register(card);
	if (ret == 0) {
		platform_set_drvdata(dev, card);
		return 0;
	}

 err:
	if (card)
		snd_card_free(card);
	if (ac97_clk) {
		GCR |= GCR_ACLINK_OFF;
		free_irq(IRQ_AC97, NULL);
		clk_disable(ac97_clk);
		clk_put(ac97_clk);
		ac97_clk = NULL;
	}
#ifdef CONFIG_PXA27x
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
#endif
	return ret;
}

static int __devexit pxa2xx_ac97_remove(struct platform_device *dev)
{
	struct snd_card *card = platform_get_drvdata(dev);

	if (card) {
		snd_card_free(card);
		platform_set_drvdata(dev, NULL);
		GCR |= GCR_ACLINK_OFF;
		free_irq(IRQ_AC97, NULL);
		clk_disable(ac97_clk);
		clk_put(ac97_clk);
		ac97_clk = NULL;
#ifdef CONFIG_PXA27x
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
#endif
	}

	return 0;
}

static struct platform_driver pxa2xx_ac97_driver = {
	.probe		= pxa2xx_ac97_probe,
	.remove		= __devexit_p(pxa2xx_ac97_remove),
	.suspend	= pxa2xx_ac97_suspend,
	.resume		= pxa2xx_ac97_resume,
	.driver		= {
		.name	= "pxa2xx-ac97",
		.owner	= THIS_MODULE,
	},
};

static int __init pxa2xx_ac97_init(void)
{
	return platform_driver_register(&pxa2xx_ac97_driver);
}

static void __exit pxa2xx_ac97_exit(void)
{
	platform_driver_unregister(&pxa2xx_ac97_driver);
}

module_init(pxa2xx_ac97_init);
module_exit(pxa2xx_ac97_exit);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-ac97");
Commit	Line	Data
2c484df0 TI	1	/*
	2	* linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Dec 02, 2004
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
d052d1be	16	#include <linux/platform_device.h>
2c484df0 TI	17	#include <linux/interrupt.h>
2c484df0 TI	18	#include <linux/wait.h>
93873fbf	19	#include <linux/clk.h>
2c484df0 TI	20	#include <linux/delay.h>
2c484df0 TI	21
2c484df0 TI	22	#include <sound/core.h>
	23	#include <sound/pcm.h>
	24	#include <sound/ac97_codec.h>
	25	#include <sound/initval.h>
	26
	27	#include <asm/irq.h>
12aa7579	28	#include <linux/mutex.h>
a09e64fb RK	29	#include <mach/hardware.h>
	30	#include <mach/pxa-regs.h>
	31	#include <mach/pxa2xx-gpio.h>
	32	#include <mach/audio.h>
2c484df0 TI	33
	34	#include "pxa2xx-pcm.h"
	35
	36
12aa7579	37	static DEFINE_MUTEX(car_mutex);
2c484df0 TI	38	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
2c484df0 TI	39	static volatile long gsr_bits;
93873fbf MB	40	static struct clk *ac97_clk;
	41	#ifdef CONFIG_PXA27x
	42	static struct clk *ac97conf_clk;
	43	#endif
2c484df0	44
ea265c0a NP	45	/*
	46	* Beware PXA27x bugs:
	47	*
	48	* o Slot 12 read from modem space will hang controller.
	49	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	50	*
	51	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	52	* 1 jiffy timeout if interrupt never comes).
	53	*/
	54
d18f8376	55	static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
2c484df0 TI	56	{
	57	unsigned short val = -1;
	58	volatile u32 *reg_addr;
	59
12aa7579	60	mutex_lock(&car_mutex);
2c484df0 TI	61
	62	/* set up primary or secondary codec space */
	63	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	64	reg_addr += (reg >> 1);
	65
	66	/* start read access across the ac97 link */
ea265c0a	67	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	68	gsr_bits = 0;
	69	val = *reg_addr;
	70	if (reg == AC97_GPIO_STATUS)
	71	goto out;
ea265c0a NP	72	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
ea265c0a NP	73	!((GSR \| gsr_bits) & GSR_SDONE)) {
2c484df0	74	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
9bf8e7dd	75	__func__, reg, GSR \| gsr_bits);
2c484df0 TI	76	val = -1;
	77	goto out;
	78	}
	79
	80	/* valid data now */
ea265c0a	81	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	82	gsr_bits = 0;
	83	val = *reg_addr;
	84	/* but we've just started another cycle... */
ea265c0a	85	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
2c484df0	86
12aa7579	87	out: mutex_unlock(&car_mutex);
2c484df0 TI	88	return val;
	89	}
	90
d18f8376	91	static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
2c484df0 TI	92	{
	93	volatile u32 *reg_addr;
	94
12aa7579	95	mutex_lock(&car_mutex);
2c484df0	96
2c484df0 TI	97	/* set up primary or secondary codec space */
	98	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	99	reg_addr += (reg >> 1);
ea265c0a NP	100
ea265c0a NP	101	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	102	gsr_bits = 0;
2c484df0 TI	103	*reg_addr = val;
ea265c0a NP	104	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
ea265c0a NP	105	!((GSR \| gsr_bits) & GSR_CDONE))
2c484df0	106	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
9bf8e7dd	107	__func__, reg, GSR \| gsr_bits);
2c484df0	108
12aa7579	109	mutex_unlock(&car_mutex);
2c484df0 TI	110	}
2c484df0 TI	111
d18f8376	112	static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
2c484df0 TI	113	{
2c484df0 TI	114	/* First, try cold reset */
815c1be3 MB	115	#ifdef CONFIG_PXA3xx
	116	int timeout;
	117
	118	/* Hold CLKBPB for 100us */
	119	GCR = 0;
	120	GCR = GCR_CLKBPB;
	121	udelay(100);
	122	GCR = 0;
	123	#endif
	124
2c484df0 TI	125	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	126	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	127
	128	gsr_bits = 0;
	129	#ifdef CONFIG_PXA27x
	130	/* PXA27x Developers Manual section 13.5.2.2.1 */
93873fbf	131	clk_enable(ac97conf_clk);
2c484df0	132	udelay(5);
93873fbf	133	clk_disable(ac97conf_clk);
2c484df0 TI	134	GCR = GCR_COLD_RST;
2c484df0 TI	135	udelay(50);
815c1be3 MB	136	#elif defined(CONFIG_PXA3xx)
	137	timeout = 1000;
	138	/* Can't use interrupts on PXA3xx */
	139	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	140
	141	GCR = GCR_WARM_RST \| GCR_COLD_RST;
	142	while (!(GSR & (GSR_PCR \| GSR_SCR)) && timeout--)
	143	mdelay(10);
2c484df0 TI	144	#else
	145	GCR = GCR_COLD_RST;
	146	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	147	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	148	#endif
	149
	150	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR))) {
	151	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
9bf8e7dd	152	__func__, gsr_bits);
2c484df0 TI	153
	154	/* let's try warm reset */
	155	gsr_bits = 0;
	156	#ifdef CONFIG_PXA27x
	157	/* warm reset broken on Bulverde,
	158	so manually keep AC97 reset high */
	159	pxa_gpio_mode(113 \| GPIO_OUT \| GPIO_DFLT_HIGH);
	160	udelay(10);
	161	GCR \|= GCR_WARM_RST;
	162	pxa_gpio_mode(113 \| GPIO_ALT_FN_2_OUT);
4a677ac5	163	udelay(500);
815c1be3 MB	164	#elif defined(CONFIG_PXA3xx)
	165	timeout = 100;
	166	/* Can't use interrupts */
	167	GCR \|= GCR_WARM_RST;
	168	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	169	mdelay(1);
2c484df0	170	#else
4a677ac5	171	GCR \|= GCR_WARM_RST\|GCR_PRIRDY_IEN\|GCR_SECRDY_IEN;
2c484df0 TI	172	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	173	#endif
	174
	175	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)))
	176	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
9bf8e7dd	177	__func__, gsr_bits);
2c484df0 TI	178	}
	179
	180	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	181	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	182	}
	183
7d12e780	184	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
2c484df0 TI	185	{
	186	long status;
	187
	188	status = GSR;
	189	if (status) {
	190	GSR = status;
	191	gsr_bits \|= status;
	192	wake_up(&gsr_wq);
	193
	194	#ifdef CONFIG_PXA27x
	195	/* Although we don't use those we still need to clear them
	196	since they tend to spuriously trigger when MMC is used
	197	(hardware bug? go figure)... */
	198	MISR = MISR_EOC;
	199	PISR = PISR_EOC;
	200	MCSR = MCSR_EOC;
	201	#endif
	202
	203	return IRQ_HANDLED;
	204	}
	205
	206	return IRQ_NONE;
	207	}
	208
d18f8376	209	static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
2c484df0 TI	210	.read = pxa2xx_ac97_read,
	211	.write = pxa2xx_ac97_write,
	212	.reset = pxa2xx_ac97_reset,
	213	};
	214
d18f8376	215	static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
2c484df0 TI	216	.name = "AC97 PCM out",
	217	.dev_addr = __PREG(PCDR),
	218	.drcmr = &DRCMRTXPCDR,
	219	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	220	DCMD_BURST32 \| DCMD_WIDTH4,
	221	};
	222
d18f8376	223	static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
2c484df0 TI	224	.name = "AC97 PCM in",
	225	.dev_addr = __PREG(PCDR),
	226	.drcmr = &DRCMRRXPCDR,
	227	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	228	DCMD_BURST32 \| DCMD_WIDTH4,
	229	};
	230
d18f8376 TI	231	static struct snd_pcm *pxa2xx_ac97_pcm;
d18f8376 TI	232	static struct snd_ac97 *pxa2xx_ac97_ac97;
2c484df0	233
d18f8376	234	static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
2c484df0	235	{
d18f8376	236	struct snd_pcm_runtime *runtime = substream->runtime;
2c484df0 TI	237	pxa2xx_audio_ops_t *platform_ops;
	238	int r;
	239
	240	runtime->hw.channels_min = 2;
	241	runtime->hw.channels_max = 2;
	242
	243	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	244	AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
	245	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
	246	snd_pcm_limit_hw_rates(runtime);
	247
	248	platform_ops = substream->pcm->card->dev->platform_data;
	249	if (platform_ops && platform_ops->startup)
	250	return platform_ops->startup(substream, platform_ops->priv);
	251	else
	252	return 0;
	253	}
	254
d18f8376	255	static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
2c484df0 TI	256	{
	257	pxa2xx_audio_ops_t *platform_ops;
	258
	259	platform_ops = substream->pcm->card->dev->platform_data;
	260	if (platform_ops && platform_ops->shutdown)
	261	platform_ops->shutdown(substream, platform_ops->priv);
	262	}
	263
d18f8376	264	static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
2c484df0	265	{
d18f8376	266	struct snd_pcm_runtime *runtime = substream->runtime;
2c484df0 TI	267	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	268	AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
	269	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
	270	}
	271
d18f8376	272	static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
2c484df0 TI	273	.playback_params = &pxa2xx_ac97_pcm_out,
	274	.capture_params = &pxa2xx_ac97_pcm_in,
	275	.startup = pxa2xx_ac97_pcm_startup,
	276	.shutdown = pxa2xx_ac97_pcm_shutdown,
	277	.prepare = pxa2xx_ac97_pcm_prepare,
	278	};
	279
	280	#ifdef CONFIG_PM
	281
d18f8376	282	static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
2c484df0	283	{
792a6c51 TI	284	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
	285
	286	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
	287	snd_pcm_suspend_all(pxa2xx_ac97_pcm);
	288	snd_ac97_suspend(pxa2xx_ac97_ac97);
	289	if (platform_ops && platform_ops->suspend)
	290	platform_ops->suspend(platform_ops->priv);
	291	GCR \|= GCR_ACLINK_OFF;
93873fbf	292	clk_disable(ac97_clk);
2c484df0 TI	293
	294	return 0;
	295	}
	296
d18f8376	297	static int pxa2xx_ac97_do_resume(struct snd_card *card)
2c484df0	298	{
792a6c51 TI	299	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
792a6c51 TI	300
93873fbf	301	clk_enable(ac97_clk);
792a6c51 TI	302	if (platform_ops && platform_ops->resume)
	303	platform_ops->resume(platform_ops->priv);
	304	snd_ac97_resume(pxa2xx_ac97_ac97);
	305	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2c484df0 TI	306
	307	return 0;
	308	}
	309
3ae5eaec	310	static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
2c484df0	311	{
d18f8376	312	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	313	int ret = 0;
2c484df0 TI	314
9480e307	315	if (card)
a55bfdc5	316	ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);
2c484df0 TI	317
	318	return ret;
	319	}
	320
3ae5eaec	321	static int pxa2xx_ac97_resume(struct platform_device *dev)
2c484df0	322	{
d18f8376	323	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	324	int ret = 0;
2c484df0 TI	325
9480e307	326	if (card)
a55bfdc5	327	ret = pxa2xx_ac97_do_resume(card);
2c484df0 TI	328
	329	return ret;
	330	}
	331
	332	#else
	333	#define pxa2xx_ac97_suspend NULL
	334	#define pxa2xx_ac97_resume NULL
	335	#endif
	336
788c6043	337	static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
2c484df0	338	{
d18f8376 TI	339	struct snd_card *card;
	340	struct snd_ac97_bus *ac97_bus;
	341	struct snd_ac97_template ac97_template;
2c484df0 TI	342	int ret;
	343
	344	ret = -ENOMEM;
	345	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	346	THIS_MODULE, 0);
	347	if (!card)
	348	goto err;
	349
3ae5eaec RK	350	card->dev = &dev->dev;
3ae5eaec RK	351	strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));
2c484df0 TI	352
	353	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
	354	if (ret)
	355	goto err;
	356
	357	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	358	if (ret < 0)
	359	goto err;
	360
	361	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	362	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	363	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	364	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	365	#ifdef CONFIG_PXA27x
	366	/* Use GPIO 113 as AC97 Reset on Bulverde */
	367	pxa_gpio_mode(113 \| GPIO_ALT_FN_2_OUT);
93873fbf MB	368	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	369	if (IS_ERR(ac97conf_clk)) {
	370	ret = PTR_ERR(ac97conf_clk);
	371	ac97conf_clk = NULL;
	372	goto err;
	373	}
2c484df0	374	#endif
93873fbf MB	375
	376	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	377	if (IS_ERR(ac97_clk)) {
	378	ret = PTR_ERR(ac97_clk);
	379	ac97_clk = NULL;
	380	goto err;
	381	}
	382	clk_enable(ac97_clk);
2c484df0 TI	383
	384	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
	385	if (ret)
	386	goto err;
	387	memset(&ac97_template, 0, sizeof(ac97_template));
	388	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
	389	if (ret)
	390	goto err;
	391
	392	snprintf(card->shortname, sizeof(card->shortname),
	393	"%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
	394	snprintf(card->longname, sizeof(card->longname),
3ae5eaec	395	"%s (%s)", dev->dev.driver->name, card->mixername);
2c484df0	396
f78dfac9	397	snd_card_set_dev(card, &dev->dev);
2c484df0 TI	398	ret = snd_card_register(card);
2c484df0 TI	399	if (ret == 0) {
3ae5eaec	400	platform_set_drvdata(dev, card);
2c484df0 TI	401	return 0;
	402	}
	403
	404	err:
	405	if (card)
	406	snd_card_free(card);
93873fbf	407	if (ac97_clk) {
2c484df0 TI	408	GCR \|= GCR_ACLINK_OFF;
2c484df0 TI	409	free_irq(IRQ_AC97, NULL);
93873fbf MB	410	clk_disable(ac97_clk);
	411	clk_put(ac97_clk);
	412	ac97_clk = NULL;
	413	}
	414	#ifdef CONFIG_PXA27x
	415	if (ac97conf_clk) {
	416	clk_put(ac97conf_clk);
	417	ac97conf_clk = NULL;
2c484df0	418	}
93873fbf	419	#endif
2c484df0 TI	420	return ret;
	421	}
	422
788c6043	423	static int __devexit pxa2xx_ac97_remove(struct platform_device *dev)
2c484df0	424	{
d18f8376	425	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	426
	427	if (card) {
	428	snd_card_free(card);
3ae5eaec	429	platform_set_drvdata(dev, NULL);
2c484df0 TI	430	GCR \|= GCR_ACLINK_OFF;
2c484df0 TI	431	free_irq(IRQ_AC97, NULL);
93873fbf MB	432	clk_disable(ac97_clk);
	433	clk_put(ac97_clk);
	434	ac97_clk = NULL;
	435	#ifdef CONFIG_PXA27x
	436	clk_put(ac97conf_clk);
	437	ac97conf_clk = NULL;
	438	#endif
2c484df0 TI	439	}
	440
	441	return 0;
	442	}
	443
3ae5eaec	444	static struct platform_driver pxa2xx_ac97_driver = {
2c484df0	445	.probe = pxa2xx_ac97_probe,
788c6043	446	.remove = __devexit_p(pxa2xx_ac97_remove),
2c484df0 TI	447	.suspend = pxa2xx_ac97_suspend,
2c484df0 TI	448	.resume = pxa2xx_ac97_resume,
3ae5eaec RK	449	.driver = {
3ae5eaec RK	450	.name = "pxa2xx-ac97",
8b45a209	451	.owner = THIS_MODULE,
3ae5eaec	452	},
2c484df0 TI	453	};
	454
	455	static int __init pxa2xx_ac97_init(void)
	456	{
3ae5eaec	457	return platform_driver_register(&pxa2xx_ac97_driver);
2c484df0 TI	458	}
	459
	460	static void __exit pxa2xx_ac97_exit(void)
	461	{
3ae5eaec	462	platform_driver_unregister(&pxa2xx_ac97_driver);
2c484df0 TI	463	}
	464
	465	module_init(pxa2xx_ac97_init);
	466	module_exit(pxa2xx_ac97_exit);
	467
	468	MODULE_AUTHOR("Nicolas Pitre");
	469	MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
	470	MODULE_LICENSE("GPL");
8b45a209	471	MODULE_ALIAS("platform:pxa2xx-ac97");