[net-next-2.6.git] / sound / arm / pxa2xx-ac97.c

/*
 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/delay.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>

#include <asm/irq.h>
#include <linux/mutex.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/audio.h>

#include "pxa2xx-pcm.h"


static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */ 

static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__FUNCTION__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;			
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}

static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__FUNCTION__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}

static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
{
	/* First, try cold reset */
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;
#ifdef CONFIG_PXA27x
	/* PXA27x Developers Manual section 13.5.2.2.1 */
	pxa_set_cken(CKEN_AC97CONF, 1);
	udelay(5);
	pxa_set_cken(CKEN_AC97CONF, 0);
	GCR = GCR_COLD_RST;
	udelay(50);
#else
	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif

	if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __FUNCTION__, gsr_bits);

		/* let's try warm reset */
		gsr_bits = 0;
#ifdef CONFIG_PXA27x
		/* warm reset broken on Bulverde,
		   so manually keep AC97 reset high */
		pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 
		udelay(10);
		GCR |= GCR_WARM_RST;
		pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
		udelay(500);
#else
		GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;
		wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif			

		if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
			printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
					 __FUNCTION__, gsr_bits);
	}

	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

#ifdef CONFIG_PXA27x
		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		MISR = MISR_EOC;
		PISR = PISR_EOC;
		MCSR = MCSR_EOC;
#endif

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
	.read	= pxa2xx_ac97_read,
	.write	= pxa2xx_ac97_write,
	.reset	= pxa2xx_ac97_reset,
};

static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
	.name			= "AC97 PCM out",
	.dev_addr		= __PREG(PCDR),
	.drcmr			= &DRCMRTXPCDR,
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
	.name			= "AC97 PCM in",
	.dev_addr		= __PREG(PCDR),
	.drcmr			= &DRCMRRXPCDR,
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct snd_pcm *pxa2xx_ac97_pcm;
static struct snd_ac97 *pxa2xx_ac97_ac97;

static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	pxa2xx_audio_ops_t *platform_ops;
	int r;

	runtime->hw.channels_min = 2;
	runtime->hw.channels_max = 2;

	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	    AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
	snd_pcm_limit_hw_rates(runtime);

       	platform_ops = substream->pcm->card->dev->platform_data;
	if (platform_ops && platform_ops->startup)
		return platform_ops->startup(substream, platform_ops->priv);
	else
		return 0;
}

static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
{
	pxa2xx_audio_ops_t *platform_ops;

       	platform_ops = substream->pcm->card->dev->platform_data;
	if (platform_ops && platform_ops->shutdown)
		platform_ops->shutdown(substream, platform_ops->priv);
}

static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
		  AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
}

static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
	.playback_params	= &pxa2xx_ac97_pcm_out,
	.capture_params		= &pxa2xx_ac97_pcm_in,
	.startup		= pxa2xx_ac97_pcm_startup,
	.shutdown		= pxa2xx_ac97_pcm_shutdown,
	.prepare		= pxa2xx_ac97_pcm_prepare,
};

#ifdef CONFIG_PM

static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
{
	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;

	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
	snd_pcm_suspend_all(pxa2xx_ac97_pcm);
	snd_ac97_suspend(pxa2xx_ac97_ac97);
	if (platform_ops && platform_ops->suspend)
		platform_ops->suspend(platform_ops->priv);
	GCR |= GCR_ACLINK_OFF;
	pxa_set_cken(CKEN_AC97, 0);

	return 0;
}

static int pxa2xx_ac97_do_resume(struct snd_card *card)
{
	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;

	pxa_set_cken(CKEN_AC97, 1);
	if (platform_ops && platform_ops->resume)
		platform_ops->resume(platform_ops->priv);
	snd_ac97_resume(pxa2xx_ac97_ac97);
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}

static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
{
	struct snd_card *card = platform_get_drvdata(dev);
	int ret = 0;

	if (card)
		ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);

	return ret;
}

static int pxa2xx_ac97_resume(struct platform_device *dev)
{
	struct snd_card *card = platform_get_drvdata(dev);
	int ret = 0;

	if (card)
		ret = pxa2xx_ac97_do_resume(card);

	return ret;
}

#else
#define pxa2xx_ac97_suspend	NULL
#define pxa2xx_ac97_resume	NULL
#endif

static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
{
	struct snd_card *card;
	struct snd_ac97_bus *ac97_bus;
	struct snd_ac97_template ac97_template;
	int ret;

	ret = -ENOMEM;
	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			    THIS_MODULE, 0);
	if (!card)
		goto err;

	card->dev = &dev->dev;
	strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));

	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
	if (ret)
		goto err;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err;

	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
#ifdef CONFIG_PXA27x
	/* Use GPIO 113 as AC97 Reset on Bulverde */
	pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
#endif
	pxa_set_cken(CKEN_AC97, 1);

	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
	if (ret)
		goto err;
	memset(&ac97_template, 0, sizeof(ac97_template));
	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
	if (ret)
		goto err;

	snprintf(card->shortname, sizeof(card->shortname),
		 "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
	snprintf(card->longname, sizeof(card->longname),
		 "%s (%s)", dev->dev.driver->name, card->mixername);

	snd_card_set_dev(card, &dev->dev);
	ret = snd_card_register(card);
	if (ret == 0) {
		platform_set_drvdata(dev, card);
		return 0;
	}

 err:
	if (card)
		snd_card_free(card);
	if (CKEN & (1 << CKEN_AC97)) {
		GCR |= GCR_ACLINK_OFF;
		free_irq(IRQ_AC97, NULL);
		pxa_set_cken(CKEN_AC97, 0);
	}
	return ret;
}

static int __devexit pxa2xx_ac97_remove(struct platform_device *dev)
{
	struct snd_card *card = platform_get_drvdata(dev);

	if (card) {
		snd_card_free(card);
		platform_set_drvdata(dev, NULL);
		GCR |= GCR_ACLINK_OFF;
		free_irq(IRQ_AC97, NULL);
		pxa_set_cken(CKEN_AC97, 0);
	}

	return 0;
}

static struct platform_driver pxa2xx_ac97_driver = {
	.probe		= pxa2xx_ac97_probe,
	.remove		= __devexit_p(pxa2xx_ac97_remove),
	.suspend	= pxa2xx_ac97_suspend,
	.resume		= pxa2xx_ac97_resume,
	.driver		= {
		.name	= "pxa2xx-ac97",
	},
};

static int __init pxa2xx_ac97_init(void)
{
	return platform_driver_register(&pxa2xx_ac97_driver);
}

static void __exit pxa2xx_ac97_exit(void)
{
	platform_driver_unregister(&pxa2xx_ac97_driver);
}

module_init(pxa2xx_ac97_init);
module_exit(pxa2xx_ac97_exit);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
MODULE_LICENSE("GPL");
Commit	Line	Data
2c484df0 TI	1	/*
	2	* linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Dec 02, 2004
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
d052d1be	16	#include <linux/platform_device.h>
2c484df0 TI	17	#include <linux/interrupt.h>
	18	#include <linux/wait.h>
	19	#include <linux/delay.h>
	20
2c484df0 TI	21	#include <sound/core.h>
	22	#include <sound/pcm.h>
	23	#include <sound/ac97_codec.h>
	24	#include <sound/initval.h>
	25
	26	#include <asm/irq.h>
12aa7579	27	#include <linux/mutex.h>
2c484df0 TI	28	#include <asm/hardware.h>
	29	#include <asm/arch/pxa-regs.h>
	30	#include <asm/arch/audio.h>
	31
	32	#include "pxa2xx-pcm.h"
	33
	34
12aa7579	35	static DEFINE_MUTEX(car_mutex);
2c484df0 TI	36	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	37	static volatile long gsr_bits;
	38
ea265c0a NP	39	/*
	40	* Beware PXA27x bugs:
	41	*
	42	* o Slot 12 read from modem space will hang controller.
	43	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	44	*
	45	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	46	* 1 jiffy timeout if interrupt never comes).
	47	*/
	48
d18f8376	49	static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
2c484df0 TI	50	{
	51	unsigned short val = -1;
	52	volatile u32 *reg_addr;
	53
12aa7579	54	mutex_lock(&car_mutex);
2c484df0 TI	55
	56	/* set up primary or secondary codec space */
	57	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	58	reg_addr += (reg >> 1);
	59
	60	/* start read access across the ac97 link */
ea265c0a	61	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	62	gsr_bits = 0;
	63	val = *reg_addr;
	64	if (reg == AC97_GPIO_STATUS)
	65	goto out;
ea265c0a NP	66	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
ea265c0a NP	67	!((GSR \| gsr_bits) & GSR_SDONE)) {
2c484df0	68	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
ea265c0a	69	__FUNCTION__, reg, GSR \| gsr_bits);
2c484df0 TI	70	val = -1;
	71	goto out;
	72	}
	73
	74	/* valid data now */
ea265c0a	75	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	76	gsr_bits = 0;
	77	val = *reg_addr;
	78	/* but we've just started another cycle... */
ea265c0a	79	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
2c484df0	80
12aa7579	81	out: mutex_unlock(&car_mutex);
2c484df0 TI	82	return val;
	83	}
	84
d18f8376	85	static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
2c484df0 TI	86	{
	87	volatile u32 *reg_addr;
	88
12aa7579	89	mutex_lock(&car_mutex);
2c484df0	90
2c484df0 TI	91	/* set up primary or secondary codec space */
	92	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
	93	reg_addr += (reg >> 1);
ea265c0a NP	94
ea265c0a NP	95	GSR = GSR_CDONE \| GSR_SDONE;
2c484df0 TI	96	gsr_bits = 0;
2c484df0 TI	97	*reg_addr = val;
ea265c0a NP	98	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
ea265c0a NP	99	!((GSR \| gsr_bits) & GSR_CDONE))
2c484df0	100	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
ea265c0a	101	__FUNCTION__, reg, GSR \| gsr_bits);
2c484df0	102
12aa7579	103	mutex_unlock(&car_mutex);
2c484df0 TI	104	}
2c484df0 TI	105
d18f8376	106	static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
2c484df0 TI	107	{
	108	/* First, try cold reset */
	109	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	110	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	111
	112	gsr_bits = 0;
	113	#ifdef CONFIG_PXA27x
	114	/* PXA27x Developers Manual section 13.5.2.2.1 */
03d14a55	115	pxa_set_cken(CKEN_AC97CONF, 1);
2c484df0	116	udelay(5);
03d14a55	117	pxa_set_cken(CKEN_AC97CONF, 0);
2c484df0 TI	118	GCR = GCR_COLD_RST;
	119	udelay(50);
	120	#else
	121	GCR = GCR_COLD_RST;
	122	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	123	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	124	#endif
	125
	126	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR))) {
	127	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
	128	__FUNCTION__, gsr_bits);
	129
	130	/* let's try warm reset */
	131	gsr_bits = 0;
	132	#ifdef CONFIG_PXA27x
	133	/* warm reset broken on Bulverde,
	134	so manually keep AC97 reset high */
	135	pxa_gpio_mode(113 \| GPIO_OUT \| GPIO_DFLT_HIGH);
	136	udelay(10);
	137	GCR \|= GCR_WARM_RST;
	138	pxa_gpio_mode(113 \| GPIO_ALT_FN_2_OUT);
4a677ac5	139	udelay(500);
2c484df0	140	#else
4a677ac5	141	GCR \|= GCR_WARM_RST\|GCR_PRIRDY_IEN\|GCR_SECRDY_IEN;
2c484df0 TI	142	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	143	#endif
	144
	145	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)))
	146	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
	147	__FUNCTION__, gsr_bits);
	148	}
	149
	150	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	151	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	152	}
	153
7d12e780	154	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
2c484df0 TI	155	{
	156	long status;
	157
	158	status = GSR;
	159	if (status) {
	160	GSR = status;
	161	gsr_bits \|= status;
	162	wake_up(&gsr_wq);
	163
	164	#ifdef CONFIG_PXA27x
	165	/* Although we don't use those we still need to clear them
	166	since they tend to spuriously trigger when MMC is used
	167	(hardware bug? go figure)... */
	168	MISR = MISR_EOC;
	169	PISR = PISR_EOC;
	170	MCSR = MCSR_EOC;
	171	#endif
	172
	173	return IRQ_HANDLED;
	174	}
	175
	176	return IRQ_NONE;
	177	}
	178
d18f8376	179	static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
2c484df0 TI	180	.read = pxa2xx_ac97_read,
	181	.write = pxa2xx_ac97_write,
	182	.reset = pxa2xx_ac97_reset,
	183	};
	184
d18f8376	185	static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
2c484df0 TI	186	.name = "AC97 PCM out",
	187	.dev_addr = __PREG(PCDR),
	188	.drcmr = &DRCMRTXPCDR,
	189	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	190	DCMD_BURST32 \| DCMD_WIDTH4,
	191	};
	192
d18f8376	193	static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
2c484df0 TI	194	.name = "AC97 PCM in",
	195	.dev_addr = __PREG(PCDR),
	196	.drcmr = &DRCMRRXPCDR,
	197	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	198	DCMD_BURST32 \| DCMD_WIDTH4,
	199	};
	200
d18f8376 TI	201	static struct snd_pcm *pxa2xx_ac97_pcm;
d18f8376 TI	202	static struct snd_ac97 *pxa2xx_ac97_ac97;
2c484df0	203
d18f8376	204	static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
2c484df0	205	{
d18f8376	206	struct snd_pcm_runtime *runtime = substream->runtime;
2c484df0 TI	207	pxa2xx_audio_ops_t *platform_ops;
	208	int r;
	209
	210	runtime->hw.channels_min = 2;
	211	runtime->hw.channels_max = 2;
	212
	213	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	214	AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
	215	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
	216	snd_pcm_limit_hw_rates(runtime);
	217
	218	platform_ops = substream->pcm->card->dev->platform_data;
	219	if (platform_ops && platform_ops->startup)
	220	return platform_ops->startup(substream, platform_ops->priv);
	221	else
	222	return 0;
	223	}
	224
d18f8376	225	static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
2c484df0 TI	226	{
	227	pxa2xx_audio_ops_t *platform_ops;
	228
	229	platform_ops = substream->pcm->card->dev->platform_data;
	230	if (platform_ops && platform_ops->shutdown)
	231	platform_ops->shutdown(substream, platform_ops->priv);
	232	}
	233
d18f8376	234	static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
2c484df0	235	{
d18f8376	236	struct snd_pcm_runtime *runtime = substream->runtime;
2c484df0 TI	237	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
	238	AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
	239	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
	240	}
	241
d18f8376	242	static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
2c484df0 TI	243	.playback_params = &pxa2xx_ac97_pcm_out,
	244	.capture_params = &pxa2xx_ac97_pcm_in,
	245	.startup = pxa2xx_ac97_pcm_startup,
	246	.shutdown = pxa2xx_ac97_pcm_shutdown,
	247	.prepare = pxa2xx_ac97_pcm_prepare,
	248	};
	249
	250	#ifdef CONFIG_PM
	251
d18f8376	252	static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
2c484df0	253	{
792a6c51 TI	254	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
	255
	256	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
	257	snd_pcm_suspend_all(pxa2xx_ac97_pcm);
	258	snd_ac97_suspend(pxa2xx_ac97_ac97);
	259	if (platform_ops && platform_ops->suspend)
	260	platform_ops->suspend(platform_ops->priv);
	261	GCR \|= GCR_ACLINK_OFF;
7053acbd	262	pxa_set_cken(CKEN_AC97, 0);
2c484df0 TI	263
	264	return 0;
	265	}
	266
d18f8376	267	static int pxa2xx_ac97_do_resume(struct snd_card *card)
2c484df0	268	{
792a6c51 TI	269	pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
792a6c51 TI	270
7053acbd	271	pxa_set_cken(CKEN_AC97, 1);
792a6c51 TI	272	if (platform_ops && platform_ops->resume)
	273	platform_ops->resume(platform_ops->priv);
	274	snd_ac97_resume(pxa2xx_ac97_ac97);
	275	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2c484df0 TI	276
	277	return 0;
	278	}
	279
3ae5eaec	280	static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
2c484df0	281	{
d18f8376	282	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	283	int ret = 0;
2c484df0 TI	284
9480e307	285	if (card)
a55bfdc5	286	ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);
2c484df0 TI	287
	288	return ret;
	289	}
	290
3ae5eaec	291	static int pxa2xx_ac97_resume(struct platform_device *dev)
2c484df0	292	{
d18f8376	293	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	294	int ret = 0;
2c484df0 TI	295
9480e307	296	if (card)
a55bfdc5	297	ret = pxa2xx_ac97_do_resume(card);
2c484df0 TI	298
	299	return ret;
	300	}
	301
	302	#else
	303	#define pxa2xx_ac97_suspend NULL
	304	#define pxa2xx_ac97_resume NULL
	305	#endif
	306
788c6043	307	static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
2c484df0	308	{
d18f8376 TI	309	struct snd_card *card;
	310	struct snd_ac97_bus *ac97_bus;
	311	struct snd_ac97_template ac97_template;
2c484df0 TI	312	int ret;
	313
	314	ret = -ENOMEM;
	315	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	316	THIS_MODULE, 0);
	317	if (!card)
	318	goto err;
	319
3ae5eaec RK	320	card->dev = &dev->dev;
3ae5eaec RK	321	strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));
2c484df0 TI	322
	323	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
	324	if (ret)
	325	goto err;
	326
	327	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	328	if (ret < 0)
	329	goto err;
	330
	331	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	332	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	333	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	334	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	335	#ifdef CONFIG_PXA27x
	336	/* Use GPIO 113 as AC97 Reset on Bulverde */
	337	pxa_gpio_mode(113 \| GPIO_ALT_FN_2_OUT);
	338	#endif
7053acbd	339	pxa_set_cken(CKEN_AC97, 1);
2c484df0 TI	340
	341	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
	342	if (ret)
	343	goto err;
	344	memset(&ac97_template, 0, sizeof(ac97_template));
	345	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
	346	if (ret)
	347	goto err;
	348
	349	snprintf(card->shortname, sizeof(card->shortname),
	350	"%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
	351	snprintf(card->longname, sizeof(card->longname),
3ae5eaec	352	"%s (%s)", dev->dev.driver->name, card->mixername);
2c484df0	353
f78dfac9	354	snd_card_set_dev(card, &dev->dev);
2c484df0 TI	355	ret = snd_card_register(card);
2c484df0 TI	356	if (ret == 0) {
3ae5eaec	357	platform_set_drvdata(dev, card);
2c484df0 TI	358	return 0;
	359	}
	360
	361	err:
	362	if (card)
	363	snd_card_free(card);
1f750a78	364	if (CKEN & (1 << CKEN_AC97)) {
2c484df0 TI	365	GCR \|= GCR_ACLINK_OFF;
2c484df0 TI	366	free_irq(IRQ_AC97, NULL);
7053acbd	367	pxa_set_cken(CKEN_AC97, 0);
2c484df0 TI	368	}
	369	return ret;
	370	}
	371
788c6043	372	static int __devexit pxa2xx_ac97_remove(struct platform_device *dev)
2c484df0	373	{
d18f8376	374	struct snd_card *card = platform_get_drvdata(dev);
2c484df0 TI	375
	376	if (card) {
	377	snd_card_free(card);
3ae5eaec	378	platform_set_drvdata(dev, NULL);
2c484df0 TI	379	GCR \|= GCR_ACLINK_OFF;
2c484df0 TI	380	free_irq(IRQ_AC97, NULL);
7053acbd	381	pxa_set_cken(CKEN_AC97, 0);
2c484df0 TI	382	}
	383
	384	return 0;
	385	}
	386
3ae5eaec	387	static struct platform_driver pxa2xx_ac97_driver = {
2c484df0	388	.probe = pxa2xx_ac97_probe,
788c6043	389	.remove = __devexit_p(pxa2xx_ac97_remove),
2c484df0 TI	390	.suspend = pxa2xx_ac97_suspend,
2c484df0 TI	391	.resume = pxa2xx_ac97_resume,
3ae5eaec RK	392	.driver = {
	393	.name = "pxa2xx-ac97",
	394	},
2c484df0 TI	395	};
	396
	397	static int __init pxa2xx_ac97_init(void)
	398	{
3ae5eaec	399	return platform_driver_register(&pxa2xx_ac97_driver);
2c484df0 TI	400	}
	401
	402	static void __exit pxa2xx_ac97_exit(void)
	403	{
3ae5eaec	404	platform_driver_unregister(&pxa2xx_ac97_driver);
2c484df0 TI	405	}
	406
	407	module_init(pxa2xx_ac97_init);
	408	module_exit(pxa2xx_ac97_exit);
	409
	410	MODULE_AUTHOR("Nicolas Pitre");
	411	MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
	412	MODULE_LICENSE("GPL");