[net-next-2.6.git] / sound / arm / pxa2xx-ac97-lib.c

/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>

#include <sound/ac97_codec.h>
#include <sound/pxa2xx-lib.h>

#include <asm/irq.h>
#include <mach/regs-ac97.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

extern void pxa27x_assert_ac97reset(int reset_gpio, int on);

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
			unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
	pxa27x_assert_ac97reset(reset_gpio, 1);
	udelay(10);
	GCR |= GCR_WARM_RST;
	pxa27x_assert_ac97reset(reset_gpio, 0);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_enable(ac97conf_clk);
	udelay(5);
	clk_disable(ac97conf_clk);
	GCR = GCR_COLD_RST;
	udelay(50);
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	int timeout = 100;

	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	int timeout = 1000;

	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
	while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(10);
}
#endif

bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		BUG();
	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		BUG();

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	clk_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa27x()) {
		/* Use GPIO 113 as AC97 Reset on Bulverde */
		pxa27x_assert_ac97reset(reset_gpio, 0);
		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9c636342 DES	1	/*
	2	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	3	* which contain:
	4	*
	5	* Author: Nicolas Pitre
	6	* Created: Dec 02, 2004
	7	* Copyright: MontaVista Software Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
	19
	20	#include <sound/ac97_codec.h>
	21	#include <sound/pxa2xx-lib.h>
	22
	23	#include <asm/irq.h>
1f017a99	24	#include <mach/regs-ac97.h>
9c636342 DES	25	#include <mach/audio.h>
	26
	27	static DEFINE_MUTEX(car_mutex);
	28	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	29	static volatile long gsr_bits;
	30	static struct clk *ac97_clk;
9c636342	31	static struct clk *ac97conf_clk;
26ade896	32	static int reset_gpio;
9c636342	33
fb1bf8cd EM	34	extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
fb1bf8cd EM	35
9c636342 DES	36	/*
	37	* Beware PXA27x bugs:
	38	*
	39	* o Slot 12 read from modem space will hang controller.
	40	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	41	*
	42	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	43	* 1 jiffy timeout if interrupt never comes).
	44	*/
	45
	46	unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
	47	{
	48	unsigned short val = -1;
	49	volatile u32 *reg_addr;
	50
	51	mutex_lock(&car_mutex);
	52
	53	/* set up primary or secondary codec space */
8825e8e8	54	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DES	55	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	56	else
	57	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DES	58	reg_addr += (reg >> 1);
	59
	60	/* start read access across the ac97 link */
	61	GSR = GSR_CDONE \| GSR_SDONE;
	62	gsr_bits = 0;
	63	val = *reg_addr;
	64	if (reg == AC97_GPIO_STATUS)
	65	goto out;
	66	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	67	!((GSR \| gsr_bits) & GSR_SDONE)) {
	68	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	69	__func__, reg, GSR \| gsr_bits);
	70	val = -1;
	71	goto out;
	72	}
	73
	74	/* valid data now */
	75	GSR = GSR_CDONE \| GSR_SDONE;
	76	gsr_bits = 0;
	77	val = *reg_addr;
	78	/* but we've just started another cycle... */
	79	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	80
	81	out: mutex_unlock(&car_mutex);
	82	return val;
	83	}
	84	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	85
	86	void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	87	unsigned short val)
	88	{
	89	volatile u32 *reg_addr;
	90
	91	mutex_lock(&car_mutex);
	92
	93	/* set up primary or secondary codec space */
8825e8e8	94	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DES	95	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	96	else
	97	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DES	98	reg_addr += (reg >> 1);
	99
	100	GSR = GSR_CDONE \| GSR_SDONE;
	101	gsr_bits = 0;
	102	*reg_addr = val;
	103	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
	104	!((GSR \| gsr_bits) & GSR_CDONE))
	105	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
	106	__func__, reg, GSR \| gsr_bits);
	107
	108	mutex_unlock(&car_mutex);
	109	}
	110	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	111
9d1cf39b DES	112	#ifdef CONFIG_PXA25x
9d1cf39b DES	113	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	114	{
9c636342 DES	115	gsr_bits = 0;
9c636342 DES	116
9d1cf39b DES	117	GCR \|= GCR_WARM_RST \| GCR_PRIRDY_IEN \| GCR_SECRDY_IEN;
	118	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	119	}
	120
	121	static inline void pxa_ac97_cold_pxa25x(void)
	122	{
	123	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	124	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	125
	126	gsr_bits = 0;
	127
	128	GCR = GCR_COLD_RST;
	129	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	130	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	131	}
	132	#endif
	133
9c636342	134	#ifdef CONFIG_PXA27x
9d1cf39b DES	135	static inline void pxa_ac97_warm_pxa27x(void)
	136	{
	137	gsr_bits = 0;
	138
fb1bf8cd EM	139	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
fb1bf8cd EM	140	pxa27x_assert_ac97reset(reset_gpio, 1);
9c636342 DES	141	udelay(10);
9c636342 DES	142	GCR \|= GCR_WARM_RST;
fb1bf8cd	143	pxa27x_assert_ac97reset(reset_gpio, 0);
9c636342	144	udelay(500);
9d1cf39b DES	145	}
	146
	147	static inline void pxa_ac97_cold_pxa27x(void)
	148	{
	149	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	150	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	151
	152	gsr_bits = 0;
	153
	154	/* PXA27x Developers Manual section 13.5.2.2.1 */
	155	clk_enable(ac97conf_clk);
	156	udelay(5);
	157	clk_disable(ac97conf_clk);
	158	GCR = GCR_COLD_RST;
	159	udelay(50);
	160	}
9c636342 DES	161	#endif
9c636342 DES	162
9d1cf39b DES	163	#ifdef CONFIG_PXA3xx
	164	static inline void pxa_ac97_warm_pxa3xx(void)
	165	{
	166	int timeout = 100;
9c636342	167
9d1cf39b	168	gsr_bits = 0;
9c636342	169
9d1cf39b DES	170	/* Can't use interrupts */
	171	GCR \|= GCR_WARM_RST;
	172	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	173	mdelay(1);
9c636342	174	}
9c636342	175
9d1cf39b	176	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	177	{
9c636342 DES	178	int timeout = 1000;
	179
	180	/* Hold CLKBPB for 100us */
	181	GCR = 0;
	182	GCR = GCR_CLKBPB;
	183	udelay(100);
	184	GCR = 0;
9c636342 DES	185
	186	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	187	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	188
	189	gsr_bits = 0;
9d1cf39b	190
9c636342 DES	191	/* Can't use interrupts on PXA3xx */
	192	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	193
	194	GCR = GCR_WARM_RST \| GCR_COLD_RST;
	195	while (!(GSR & (GSR_PCR \| GSR_SCR)) && timeout--)
	196	mdelay(10);
9d1cf39b DES	197	}
	198	#endif
	199
	200	bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
	201	{
057de50c LF	202	unsigned long gsr;
057de50c LF	203
9d1cf39b	204	#ifdef CONFIG_PXA25x
8825e8e8	205	if (cpu_is_pxa25x())
9d1cf39b DES	206	pxa_ac97_warm_pxa25x();
9d1cf39b DES	207	else
9c636342	208	#endif
9d1cf39b DES	209	#ifdef CONFIG_PXA27x
	210	if (cpu_is_pxa27x())
	211	pxa_ac97_warm_pxa27x();
	212	else
	213	#endif
	214	#ifdef CONFIG_PXA3xx
	215	if (cpu_is_pxa3xx())
	216	pxa_ac97_warm_pxa3xx();
	217	else
	218	#endif
	219	BUG();
057de50c LF	220	gsr = GSR \| gsr_bits;
057de50c LF	221	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9d1cf39b	222	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
057de50c	223	__func__, gsr);
9d1cf39b DES	224
	225	return false;
	226	}
	227
	228	return true;
	229	}
	230	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	231
	232	bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
	233	{
057de50c LF	234	unsigned long gsr;
057de50c LF	235
9d1cf39b	236	#ifdef CONFIG_PXA25x
8825e8e8	237	if (cpu_is_pxa25x())
9d1cf39b DES	238	pxa_ac97_cold_pxa25x();
	239	else
	240	#endif
	241	#ifdef CONFIG_PXA27x
	242	if (cpu_is_pxa27x())
	243	pxa_ac97_cold_pxa27x();
	244	else
	245	#endif
	246	#ifdef CONFIG_PXA3xx
	247	if (cpu_is_pxa3xx())
	248	pxa_ac97_cold_pxa3xx();
	249	else
	250	#endif
	251	BUG();
9c636342	252
057de50c LF	253	gsr = GSR \| gsr_bits;
057de50c LF	254	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9c636342	255	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
057de50c	256	__func__, gsr);
9c636342 DES	257
	258	return false;
	259	}
	260
	261	return true;
	262	}
	263	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	264
	265
	266	void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
	267	{
	268	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	269	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	270	}
	271	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	272
	273	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	274	{
	275	long status;
	276
	277	status = GSR;
	278	if (status) {
	279	GSR = status;
	280	gsr_bits \|= status;
	281	wake_up(&gsr_wq);
	282
9c636342 DES	283	/* Although we don't use those we still need to clear them
	284	since they tend to spuriously trigger when MMC is used
	285	(hardware bug? go figure)... */
9d1cf39b DES	286	if (cpu_is_pxa27x()) {
	287	MISR = MISR_EOC;
	288	PISR = PISR_EOC;
	289	MCSR = MCSR_EOC;
	290	}
9c636342 DES	291
	292	return IRQ_HANDLED;
	293	}
	294
	295	return IRQ_NONE;
	296	}
	297
	298	#ifdef CONFIG_PM
	299	int pxa2xx_ac97_hw_suspend(void)
	300	{
	301	GCR \|= GCR_ACLINK_OFF;
	302	clk_disable(ac97_clk);
	303	return 0;
	304	}
	305	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	306
	307	int pxa2xx_ac97_hw_resume(void)
	308	{
9c636342 DES	309	clk_enable(ac97_clk);
	310	return 0;
	311	}
	312	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	313	#endif
	314
	315	int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
	316	{
	317	int ret;
eae17754	318	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
26ade896 RJ	319
	320	if (pdata) {
	321	switch (pdata->reset_gpio) {
	322	case 95:
	323	case 113:
	324	reset_gpio = pdata->reset_gpio;
	325	break;
	326	case 0:
	327	reset_gpio = 113;
	328	break;
	329	case -1:
	330	break;
	331	default:
1f218695	332	dev_err(&dev->dev, "Invalid reset GPIO %d\n",
26ade896 RJ	333	pdata->reset_gpio);
	334	}
	335	} else {
	336	if (cpu_is_pxa27x())
	337	reset_gpio = 113;
	338	}
9c636342	339
9d1cf39b DES	340	if (cpu_is_pxa27x()) {
9d1cf39b DES	341	/* Use GPIO 113 as AC97 Reset on Bulverde */
fb1bf8cd	342	pxa27x_assert_ac97reset(reset_gpio, 0);
9d1cf39b DES	343	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	344	if (IS_ERR(ac97conf_clk)) {
	345	ret = PTR_ERR(ac97conf_clk);
	346	ac97conf_clk = NULL;
79612336	347	goto err_conf;
9d1cf39b	348	}
9c636342	349	}
9c636342 DES	350
	351	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	352	if (IS_ERR(ac97_clk)) {
	353	ret = PTR_ERR(ac97_clk);
	354	ac97_clk = NULL;
79612336	355	goto err_clk;
9c636342 DES	356	}
9c636342 DES	357
79612336 DES	358	ret = clk_enable(ac97_clk);
	359	if (ret)
	360	goto err_clk2;
	361
	362	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
	363	if (ret < 0)
	364	goto err_irq;
	365
	366	return 0;
9c636342 DES	367
	368	err_irq:
	369	GCR \|= GCR_ACLINK_OFF;
79612336 DES	370	err_clk2:
	371	clk_put(ac97_clk);
	372	ac97_clk = NULL;
	373	err_clk:
9c636342 DES	374	if (ac97conf_clk) {
	375	clk_put(ac97conf_clk);
	376	ac97conf_clk = NULL;
	377	}
79612336	378	err_conf:
9c636342 DES	379	return ret;
	380	}
	381	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	382
	383	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	384	{
	385	GCR \|= GCR_ACLINK_OFF;
	386	free_irq(IRQ_AC97, NULL);
9d1cf39b DES	387	if (ac97conf_clk) {
	388	clk_put(ac97conf_clk);
	389	ac97conf_clk = NULL;
	390	}
9c636342 DES	391	clk_disable(ac97_clk);
	392	clk_put(ac97_clk);
	393	ac97_clk = NULL;
	394	}
	395	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	396
	397	MODULE_AUTHOR("Nicolas Pitre");
	398	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	399	MODULE_LICENSE("GPL");
	400