[net-next-2.6.git] / include / linux / sh_intc.h

#ifndef __SH_INTC_H
#define __SH_INTC_H

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_group {
	intc_enum enum_id;
	intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_prio_reg {
	unsigned long set_reg, clr_reg, reg_width, field_width;
	intc_enum enum_ids[16];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

#ifdef CONFIG_SMP
#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
#else
#define INTC_SMP(stride, nr)
#endif

struct intc_hw_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	struct intc_mask_reg *ack_regs;
	unsigned int nr_ack_regs;
};

#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
#define INTC_HW_DESC(vectors, groups, mask_regs,	\
		     prio_regs,	sense_regs, ack_regs)	\
{							\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),	\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),	\
	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs),	\
}

struct intc_desc {
	char *name;
	intc_enum force_enable;
	struct intc_hw_desc hw;
};

#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	mask_regs, prio_regs, sense_regs)				\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, NULL),		\
}

#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
	mask_regs, prio_regs, sense_regs, ack_regs)			\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, ack_regs),		\
}

void __init register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);

int reserve_irq_vector(unsigned int irq);
void reserve_irq_legacy(void);

#endif /* __SH_INTC_H */
Commit	Line	Data
bbfbd8b1 PM	1	#ifndef __SH_INTC_H
	2	#define __SH_INTC_H
	3
	4	typedef unsigned char intc_enum;
	5
	6	struct intc_vect {
	7	intc_enum enum_id;
	8	unsigned short vect;
	9	};
	10
	11	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	12	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
	13
	14	struct intc_group {
	15	intc_enum enum_id;
	16	intc_enum enum_ids[32];
	17	};
	18
	19	#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
	20
	21	struct intc_mask_reg {
	22	unsigned long set_reg, clr_reg, reg_width;
	23	intc_enum enum_ids[32];
	24	#ifdef CONFIG_SMP
	25	unsigned long smp;
	26	#endif
	27	};
	28
	29	struct intc_prio_reg {
	30	unsigned long set_reg, clr_reg, reg_width, field_width;
	31	intc_enum enum_ids[16];
	32	#ifdef CONFIG_SMP
	33	unsigned long smp;
	34	#endif
	35	};
	36
	37	struct intc_sense_reg {
	38	unsigned long reg, reg_width, field_width;
	39	intc_enum enum_ids[16];
	40	};
	41
	42	#ifdef CONFIG_SMP
	43	#define INTC_SMP(stride, nr) .smp = (stride) \| ((nr) << 8)
	44	#else
	45	#define INTC_SMP(stride, nr)
	46	#endif
	47
577cd758	48	struct intc_hw_desc {
bbfbd8b1 PM	49	struct intc_vect *vectors;
	50	unsigned int nr_vectors;
	51	struct intc_group *groups;
	52	unsigned int nr_groups;
	53	struct intc_mask_reg *mask_regs;
	54	unsigned int nr_mask_regs;
	55	struct intc_prio_reg *prio_regs;
	56	unsigned int nr_prio_regs;
	57	struct intc_sense_reg *sense_regs;
	58	unsigned int nr_sense_regs;
bbfbd8b1 PM	59	struct intc_mask_reg *ack_regs;
bbfbd8b1 PM	60	unsigned int nr_ack_regs;
bbfbd8b1 PM	61	};
	62
	63	#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
577cd758 MD	64	#define INTC_HW_DESC(vectors, groups, mask_regs, \
	65	prio_regs, sense_regs, ack_regs) \
	66	{ \
	67	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	68	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	69	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
	70	}
	71
	72	struct intc_desc {
	73	char *name;
d5190953	74	intc_enum force_enable;
577cd758 MD	75	struct intc_hw_desc hw;
	76	};
	77
bbfbd8b1 PM	78	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
	79	mask_regs, prio_regs, sense_regs) \
	80	struct intc_desc symbol __initdata = { \
577cd758 MD	81	.name = chipname, \
	82	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	83	prio_regs, sense_regs, NULL), \
bbfbd8b1 PM	84	}
bbfbd8b1 PM	85
bbfbd8b1 PM	86	#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
	87	mask_regs, prio_regs, sense_regs, ack_regs) \
	88	struct intc_desc symbol __initdata = { \
577cd758 MD	89	.name = chipname, \
	90	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	91	prio_regs, sense_regs, ack_regs), \
bbfbd8b1	92	}
bbfbd8b1 PM	93
	94	void __init register_intc_controller(struct intc_desc *desc);
	95	int intc_set_priority(unsigned int irq, unsigned int prio);
	96
45b9deaf PM	97	int reserve_irq_vector(unsigned int irq);
	98	void reserve_irq_legacy(void);
	99
bbfbd8b1	100	#endif /* __SH_INTC_H */