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[net-next-2.6.git] / include / linux / pci.h
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1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20#include <linux/mod_devicetable.h>
21
4352dfd5
GKH		 22/* Include the pci register defines */
23#include <linux/pci_regs.h>
1da177e4
LT		 24
25/* Include the ID list */
1da177e4
LT		 26#include <linux/pci_ids.h>
27
28/*
29 * The PCI interface treats multi-function devices as independent
30 * devices. The slot/function address of each device is encoded
31 * in a single byte as follows:
32 *
33 * 7:3 = slot
34 * 2:0 = function
35 */
36#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
37#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
38#define PCI_FUNC(devfn) ((devfn) & 0x07)
39
40/* Ioctls for /proc/bus/pci/X/Y nodes. */
41#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
42#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
43#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
44#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
45#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
46
47#ifdef __KERNEL__
48
49#include <linux/types.h>
50#include <linux/config.h>
51#include <linux/ioport.h>
52#include <linux/list.h>
53#include <linux/errno.h>
54#include <linux/device.h>
55
56/* File state for mmap()s on /proc/bus/pci/X/Y */
57enum pci_mmap_state {
58 pci_mmap_io,
59 pci_mmap_mem
60};
61
62/* This defines the direction arg to the DMA mapping routines. */
63#define PCI_DMA_BIDIRECTIONAL 0
64#define PCI_DMA_TODEVICE 1
65#define PCI_DMA_FROMDEVICE 2
66#define PCI_DMA_NONE 3
67
68#define DEVICE_COUNT_COMPATIBLE 4
69#define DEVICE_COUNT_RESOURCE 12
70
71typedef int __bitwise pci_power_t;
72
4352dfd5
GKH		 73#define PCI_D0 ((pci_power_t __force) 0)
74#define PCI_D1 ((pci_power_t __force) 1)
75#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 76#define PCI_D3hot ((pci_power_t __force) 3)
77#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 78#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 79#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4
LT		 80
81/*
82 * The pci_dev structure is used to describe PCI devices.
83 */
84struct pci_dev {
85 struct list_head global_list; /* node in list of all PCI devices */
86 struct list_head bus_list; /* node in per-bus list */
87 struct pci_bus *bus; /* bus this device is on */
88 struct pci_bus *subordinate; /* bus this device bridges to */
89
90 void *sysdata; /* hook for sys-specific extension */
91 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
92
93 unsigned int devfn; /* encoded device & function index */
94 unsigned short vendor;
95 unsigned short device;
96 unsigned short subsystem_vendor;
97 unsigned short subsystem_device;
98 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
99 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
100 u8 rom_base_reg; /* which config register controls the ROM */
101
102 struct pci_driver *driver; /* which driver has allocated this device */
103 u64 dma_mask; /* Mask of the bits of bus address this
104 device implements. Normally this is
105 0xffffffff. You only need to change
106 this if your device has broken DMA
107 or supports 64-bit transfers. */
108
109 pci_power_t current_state; /* Current operating state. In ACPI-speak,
110 this is D0-D3, D0 being fully functional,
111 and D3 being off. */
112
113 struct device dev; /* Generic device interface */
114
115 /* device is compatible with these IDs */
116 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
117 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
118
119 int cfg_size; /* Size of configuration space */
120
121 /*
122 * Instead of touching interrupt line and base address registers
123 * directly, use the values stored here. They might be different!
124 */
125 unsigned int irq;
126 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
127
128 /* These fields are used by common fixups */
129 unsigned int transparent:1; /* Transparent PCI bridge */
130 unsigned int multifunction:1;/* Part of multi-function device */
131 /* keep track of device state */
132 unsigned int is_enabled:1; /* pci_enable_device has been called */
133 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d
KA		 134 unsigned int no_msi:1; /* device may not use msi */
135
1da177e4
LT		 136 u32 saved_config_space[16]; /* config space saved at suspend time */
137 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
138 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
139 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
1da177e4
LT		 140};
141
142#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
143#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
144#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
145#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
146
147/*
148 * For PCI devices, the region numbers are assigned this way:
149 *
150 * 0-5 standard PCI regions
151 * 6 expansion ROM
152 * 7-10 bridges: address space assigned to buses behind the bridge
153 */
154
4352dfd5
GKH		 155#define PCI_ROM_RESOURCE 6
156#define PCI_BRIDGE_RESOURCES 7
157#define PCI_NUM_RESOURCES 11
1da177e4
LT		 158
159#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 160#define PCI_BUS_NUM_RESOURCES 8
1da177e4 161#endif
4352dfd5
GKH		 162
163#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 164
165struct pci_bus {
166 struct list_head node; /* node in list of buses */
167 struct pci_bus *parent; /* parent bus this bridge is on */
168 struct list_head children; /* list of child buses */
169 struct list_head devices; /* list of devices on this bus */
170 struct pci_dev *self; /* bridge device as seen by parent */
171 struct resource *resource[PCI_BUS_NUM_RESOURCES];
172 /* address space routed to this bus */
173
174 struct pci_ops *ops; /* configuration access functions */
175 void *sysdata; /* hook for sys-specific extension */
176 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
177
178 unsigned char number; /* bus number */
179 unsigned char primary; /* number of primary bridge */
180 unsigned char secondary; /* number of secondary bridge */
181 unsigned char subordinate; /* max number of subordinate buses */
182
183 char name[48];
184
185 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
186 unsigned short pad2;
187 struct device *bridge;
188 struct class_device class_dev;
189 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
190 struct bin_attribute *legacy_mem; /* legacy mem */
191};
192
193#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
194#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
195
196/*
197 * Error values that may be returned by PCI functions.
198 */
199#define PCIBIOS_SUCCESSFUL 0x00
200#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
201#define PCIBIOS_BAD_VENDOR_ID 0x83
202#define PCIBIOS_DEVICE_NOT_FOUND 0x86
203#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
204#define PCIBIOS_SET_FAILED 0x88
205#define PCIBIOS_BUFFER_TOO_SMALL 0x89
206
207/* Low-level architecture-dependent routines */
208
209struct pci_ops {
210 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
211 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
212};
213
214struct pci_raw_ops {
215 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
216 int reg, int len, u32 *val);
217 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
218 int reg, int len, u32 val);
219};
220
221extern struct pci_raw_ops *raw_pci_ops;
222
223struct pci_bus_region {
224 unsigned long start;
225 unsigned long end;
226};
227
228struct pci_dynids {
229 spinlock_t lock; /* protects list, index */
230 struct list_head list; /* for IDs added at runtime */
231 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
232};
233
234struct module;
235struct pci_driver {
236 struct list_head node;
237 char *name;
238 struct module *owner;
239 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
240 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
241 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
242 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
243 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 244 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 245 void (*shutdown) (struct pci_dev *dev);
1da177e4
LT		 246
247 struct device_driver driver;
248 struct pci_dynids dynids;
249};
250
251#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
252
253/**
254 * PCI_DEVICE - macro used to describe a specific pci device
255 * @vend: the 16 bit PCI Vendor ID
256 * @dev: the 16 bit PCI Device ID
257 *
258 * This macro is used to create a struct pci_device_id that matches a
259 * specific device. The subvendor and subdevice fields will be set to
260 * PCI_ANY_ID.
261 */
262#define PCI_DEVICE(vend,dev) \
263 .vendor = (vend), .device = (dev), \
264 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
265
266/**
267 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
268 * @dev_class: the class, subclass, prog-if triple for this device
269 * @dev_class_mask: the class mask for this device
270 *
271 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 272 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 273 * fields will be set to PCI_ANY_ID.
274 */
275#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
276 .class = (dev_class), .class_mask = (dev_class_mask), \
277 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
278 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
279
4352dfd5 280/*
1da177e4
LT		 281 * pci_module_init is obsolete, this stays here till we fix up all usages of it
282 * in the tree.
283 */
284#define pci_module_init pci_register_driver
285
286/* these external functions are only available when PCI support is enabled */
287#ifdef CONFIG_PCI
288
289extern struct bus_type pci_bus_type;
290
291/* Do NOT directly access these two variables, unless you are arch specific pci
292 * code, or pci core code. */
293extern struct list_head pci_root_buses; /* list of all known PCI buses */
294extern struct list_head pci_devices; /* list of all devices */
295
296void pcibios_fixup_bus(struct pci_bus *);
297int pcibios_enable_device(struct pci_dev *, int mask);
298char *pcibios_setup (char *str);
299
300/* Used only when drivers/pci/setup.c is used */
301void pcibios_align_resource(void *, struct resource *,
302 unsigned long, unsigned long);
303void pcibios_update_irq(struct pci_dev *, int irq);
304
305/* Generic PCI functions used internally */
306
307extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 308void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 309struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
310static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
311{
c431ada4
RS		 312 struct pci_bus *root_bus;
313 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
314 if (root_bus)
315 pci_bus_add_devices(root_bus);
316 return root_bus;
1da177e4
LT		 317}
318int pci_scan_slot(struct pci_bus *bus, int devfn);
319struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
320unsigned int pci_scan_child_bus(struct pci_bus *bus);
321void pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 322void pci_read_bridge_bases(struct pci_bus *child);
323struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
324int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
325extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
326extern void pci_dev_put(struct pci_dev *dev);
327extern void pci_remove_bus(struct pci_bus *b);
328extern void pci_remove_bus_device(struct pci_dev *dev);
329
330/* Generic PCI functions exported to card drivers */
331
332struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
333struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
334struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
335int pci_find_capability (struct pci_dev *dev, int cap);
336int pci_find_ext_capability (struct pci_dev *dev, int cap);
337struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
338
339struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
340struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
341 unsigned int ss_vendor, unsigned int ss_device,
342 struct pci_dev *from);
343struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
344struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
345int pci_dev_present(const struct pci_device_id *ids);
346
347int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
348int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
349int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
350int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
351int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
352int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
353
354static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
355{
356 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
357}
358static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
359{
360 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
361}
362static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
363{
364 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
365}
366static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
367{
368 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
369}
370static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
371{
372 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
373}
374static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
375{
376 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
377}
378
144a50ea
DJ		 379int __must_check pci_enable_device(struct pci_dev *dev);
380int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
1da177e4
LT		 381void pci_disable_device(struct pci_dev *dev);
382void pci_set_master(struct pci_dev *dev);
383#define HAVE_PCI_SET_MWI
144a50ea 384int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 385void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 386void pci_intx(struct pci_dev *dev, int enable);
144a50ea
DJ		 387int __must_check pci_set_dma_mask(struct pci_dev *dev, u64 mask);
388int __must_check pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 389void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
1da177e4 390int pci_assign_resource(struct pci_dev *dev, int i);
064b53db 391void pci_restore_bars(struct pci_dev *dev);
1da177e4
LT		 392
393/* ROM control related routines */
144a50ea
DJ		 394void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
395void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 396void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
397void pci_remove_rom(struct pci_dev *pdev);
398
399/* Power management related routines */
400int pci_save_state(struct pci_dev *dev);
401int pci_restore_state(struct pci_dev *dev);
144a50ea
DJ		 402int __must_check pci_set_power_state(struct pci_dev *dev, pci_power_t state);
403pci_power_t __must_check pci_choose_state(struct pci_dev *dev, pm_message_t state);
404int __must_check pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 405
406/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
407void pci_bus_assign_resources(struct pci_bus *bus);
408void pci_bus_size_bridges(struct pci_bus *bus);
409int pci_claim_resource(struct pci_dev *, int);
410void pci_assign_unassigned_resources(void);
411void pdev_enable_device(struct pci_dev *);
412void pdev_sort_resources(struct pci_dev *, struct resource_list *);
413void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
414 int (*)(struct pci_dev *, u8, u8));
415#define HAVE_PCI_REQ_REGIONS 2
416int pci_request_regions(struct pci_dev *, char *);
417void pci_release_regions(struct pci_dev *);
418int pci_request_region(struct pci_dev *, int, char *);
419void pci_release_region(struct pci_dev *, int);
420
421/* drivers/pci/bus.c */
422int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
423 unsigned long size, unsigned long align,
424 unsigned long min, unsigned int type_mask,
425 void (*alignf)(void *, struct resource *,
426 unsigned long, unsigned long),
427 void *alignf_data);
428void pci_enable_bridges(struct pci_bus *bus);
429
430/* New-style probing supporting hot-pluggable devices */
431int pci_register_driver(struct pci_driver *);
432void pci_unregister_driver(struct pci_driver *);
433void pci_remove_behind_bridge(struct pci_dev *);
434struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 435const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
436const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 437int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
438
cecf4864
PM		 439void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
440 void *userdata);
441
1da177e4
LT		 442/* kmem_cache style wrapper around pci_alloc_consistent() */
443
444#include <linux/dmapool.h>
445
446#define pci_pool dma_pool
447#define pci_pool_create(name, pdev, size, align, allocation) \
448 dma_pool_create(name, &pdev->dev, size, align, allocation)
449#define pci_pool_destroy(pool) dma_pool_destroy(pool)
450#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
451#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
452
e24c2d96
DM		 453enum pci_dma_burst_strategy {
454 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
455 strategy_parameter is N/A */
456 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
457 byte boundaries */
458 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
459 strategy_parameter byte boundaries */
460};
461
1da177e4
LT		 462#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
463extern struct pci_dev *isa_bridge;
464#endif
465
466struct msix_entry {
467 u16 vector; /* kernel uses to write allocated vector */
468 u16 entry; /* driver uses to specify entry, OS writes */
469};
470
471#ifndef CONFIG_PCI_MSI
472static inline void pci_scan_msi_device(struct pci_dev *dev) {}
473static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
474static inline void pci_disable_msi(struct pci_dev *dev) {}
475static inline int pci_enable_msix(struct pci_dev* dev,
476 struct msix_entry *entries, int nvec) {return -1;}
477static inline void pci_disable_msix(struct pci_dev *dev) {}
478static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
479#else
480extern void pci_scan_msi_device(struct pci_dev *dev);
481extern int pci_enable_msi(struct pci_dev *dev);
482extern void pci_disable_msi(struct pci_dev *dev);
483extern int pci_enable_msix(struct pci_dev* dev,
484 struct msix_entry *entries, int nvec);
485extern void pci_disable_msix(struct pci_dev *dev);
486extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
487#endif
488
4352dfd5
GKH		 489/*
490 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
491 * a PCI domain is defined to be a set of PCI busses which share
492 * configuration space.
493 */
494#ifndef CONFIG_PCI_DOMAINS
495static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
496static inline int pci_proc_domain(struct pci_bus *bus)
497{
498 return 0;
499}
500#endif
1da177e4 501
4352dfd5 502#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 503
504/*
505 * If the system does not have PCI, clearly these return errors. Define
506 * these as simple inline functions to avoid hair in drivers.
507 */
508
1da177e4
LT		 509#define _PCI_NOP(o,s,t) \
510 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
511 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
512#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
513 _PCI_NOP(o,word,u16 x) \
514 _PCI_NOP(o,dword,u32 x)
515_PCI_NOP_ALL(read, *)
516_PCI_NOP_ALL(write,)
517
518static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
519{ return NULL; }
520
521static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
522{ return NULL; }
523
524static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from)
525{ return NULL; }
526
527static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
528unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
529{ return NULL; }
530
531static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
532{ return NULL; }
533
534#define pci_dev_present(ids) (0)
535#define pci_dev_put(dev) do { } while (0)
536
537static inline void pci_set_master(struct pci_dev *dev) { }
538static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
539static inline void pci_disable_device(struct pci_dev *dev) { }
540static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4
LT		 541static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
542static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
543static inline void pci_unregister_driver(struct pci_driver *drv) { }
544static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
545static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
546static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
547
548/* Power management related routines */
549static inline int pci_save_state(struct pci_dev *dev) { return 0; }
550static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
551static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 552static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 553static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
554
555#define isa_bridge ((struct pci_dev *)NULL)
556
a46e8126
KG		 557#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
558
4352dfd5 559#endif /* CONFIG_PCI */
1da177e4 560
4352dfd5
GKH		 561/* Include architecture-dependent settings and functions */
562
563#include <asm/pci.h>
1da177e4
LT		 564
565/* these helpers provide future and backwards compatibility
566 * for accessing popular PCI BAR info */
567#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
568#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
569#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
570#define pci_resource_len(dev,bar) \
571 ((pci_resource_start((dev),(bar)) == 0 && \
572 pci_resource_end((dev),(bar)) == \
573 pci_resource_start((dev),(bar))) ? 0 : \
574 \
575 (pci_resource_end((dev),(bar)) - \
576 pci_resource_start((dev),(bar)) + 1))
577
578/* Similar to the helpers above, these manipulate per-pci_dev
579 * driver-specific data. They are really just a wrapper around
580 * the generic device structure functions of these calls.
581 */
582static inline void *pci_get_drvdata (struct pci_dev *pdev)
583{
584 return dev_get_drvdata(&pdev->dev);
585}
586
587static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
588{
589 dev_set_drvdata(&pdev->dev, data);
590}
591
592/* If you want to know what to call your pci_dev, ask this function.
593 * Again, it's a wrapper around the generic device.
594 */
595static inline char *pci_name(struct pci_dev *pdev)
596{
597 return pdev->dev.bus_id;
598}
599
2311b1f2
ME		 600
601/* Some archs don't want to expose struct resource to userland as-is
602 * in sysfs and /proc
603 */
604#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
605static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
606 const struct resource *rsrc, u64 *start, u64 *end)
607{
608 *start = rsrc->start;
609 *end = rsrc->end;
610}
611#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
612
613
1da177e4
LT		 614/*
615 * The world is not perfect and supplies us with broken PCI devices.
616 * For at least a part of these bugs we need a work-around, so both
617 * generic (drivers/pci/quirks.c) and per-architecture code can define
618 * fixup hooks to be called for particular buggy devices.
619 */
620
621struct pci_fixup {
622 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
623 void (*hook)(struct pci_dev *dev);
624};
625
626enum pci_fixup_pass {
627 pci_fixup_early, /* Before probing BARs */
628 pci_fixup_header, /* After reading configuration header */
629 pci_fixup_final, /* Final phase of device fixups */
630 pci_fixup_enable, /* pci_enable_device() time */
631};
632
633/* Anonymous variables would be nice... */
634#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 635 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 636 __attribute__((__section__(#section))) = { vendor, device, hook };
637#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
638 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
639 vendor##device##hook, vendor, device, hook)
640#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
641 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
642 vendor##device##hook, vendor, device, hook)
643#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
644 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
645 vendor##device##hook, vendor, device, hook)
646#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
647 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
648 vendor##device##hook, vendor, device, hook)
649
650
651void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
652
653extern int pci_pci_problems;
654#define PCIPCI_FAIL 1
655#define PCIPCI_TRITON 2
656#define PCIPCI_NATOMA 4
657#define PCIPCI_VIAETBF 8
658#define PCIPCI_VSFX 16
659#define PCIPCI_ALIMAGIK 32
660
661#endif /* __KERNEL__ */
662#endif /* LINUX_PCI_H */
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