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[PATCH] clocksource: acpi_pm: add another greylist chipset
[net-next-2.6.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4
LT		 22
23/* Include the ID list */
1da177e4
LT		 24#include <linux/pci_ids.h>
25
26/*
27 * The PCI interface treats multi-function devices as independent
28 * devices. The slot/function address of each device is encoded
29 * in a single byte as follows:
30 *
31 * 7:3 = slot
32 * 2:0 = function
33 */
34#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
35#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
36#define PCI_FUNC(devfn) ((devfn) & 0x07)
37
38/* Ioctls for /proc/bus/pci/X/Y nodes. */
39#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
40#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
41#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
42#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
43#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
44
45#ifdef __KERNEL__
46
778382e0
DW		 47#include <linux/mod_devicetable.h>
48
1da177e4 49#include <linux/types.h>
1da177e4
LT		 50#include <linux/ioport.h>
51#include <linux/list.h>
4a7fb636 52#include <linux/compiler.h>
1da177e4
LT		 53#include <linux/errno.h>
54#include <linux/device.h>
55
56/* File state for mmap()s on /proc/bus/pci/X/Y */
57enum pci_mmap_state {
58 pci_mmap_io,
59 pci_mmap_mem
60};
61
62/* This defines the direction arg to the DMA mapping routines. */
63#define PCI_DMA_BIDIRECTIONAL 0
64#define PCI_DMA_TODEVICE 1
65#define PCI_DMA_FROMDEVICE 2
66#define PCI_DMA_NONE 3
67
68#define DEVICE_COUNT_COMPATIBLE 4
69#define DEVICE_COUNT_RESOURCE 12
70
71typedef int __bitwise pci_power_t;
72
4352dfd5
GKH		 73#define PCI_D0 ((pci_power_t __force) 0)
74#define PCI_D1 ((pci_power_t __force) 1)
75#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 76#define PCI_D3hot ((pci_power_t __force) 3)
77#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 78#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 79#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 80
392a1ce7
LV		 81/** The pci_channel state describes connectivity between the CPU and
82 * the pci device. If some PCI bus between here and the pci device
83 * has crashed or locked up, this info is reflected here.
84 */
85typedef unsigned int __bitwise pci_channel_state_t;
86
87enum pci_channel_state {
88 /* I/O channel is in normal state */
89 pci_channel_io_normal = (__force pci_channel_state_t) 1,
90
91 /* I/O to channel is blocked */
92 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
93
94 /* PCI card is dead */
95 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
96};
97
6e325a62
MT		 98typedef unsigned short __bitwise pci_bus_flags_t;
99enum pci_bus_flags {
e778272d 100 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 101};
102
41017f0c
SL		 103struct pci_cap_saved_state {
104 struct hlist_node next;
105 char cap_nr;
106 u32 data[0];
107};
108
1da177e4
LT		 109/*
110 * The pci_dev structure is used to describe PCI devices.
111 */
112struct pci_dev {
113 struct list_head global_list; /* node in list of all PCI devices */
114 struct list_head bus_list; /* node in per-bus list */
115 struct pci_bus *bus; /* bus this device is on */
116 struct pci_bus *subordinate; /* bus this device bridges to */
117
118 void *sysdata; /* hook for sys-specific extension */
119 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
120
121 unsigned int devfn; /* encoded device & function index */
122 unsigned short vendor;
123 unsigned short device;
124 unsigned short subsystem_vendor;
125 unsigned short subsystem_device;
126 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
127 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
128 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 129 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 130
131 struct pci_driver *driver; /* which driver has allocated this device */
132 u64 dma_mask; /* Mask of the bits of bus address this
133 device implements. Normally this is
134 0xffffffff. You only need to change
135 this if your device has broken DMA
136 or supports 64-bit transfers. */
137
138 pci_power_t current_state; /* Current operating state. In ACPI-speak,
139 this is D0-D3, D0 being fully functional,
140 and D3 being off. */
141
392a1ce7 142 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 143 struct device dev; /* Generic device interface */
144
145 /* device is compatible with these IDs */
146 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
147 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
148
149 int cfg_size; /* Size of configuration space */
150
151 /*
152 * Instead of touching interrupt line and base address registers
153 * directly, use the values stored here. They might be different!
154 */
155 unsigned int irq;
156 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
157
158 /* These fields are used by common fixups */
159 unsigned int transparent:1; /* Transparent PCI bridge */
160 unsigned int multifunction:1;/* Part of multi-function device */
161 /* keep track of device state */
162 unsigned int is_enabled:1; /* pci_enable_device has been called */
163 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 164 unsigned int no_msi:1; /* device may not use msi */
ffadcc2f 165 unsigned int no_d1d2:1; /* only allow d0 or d3 */
e04b0ea2 166 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 167 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 168 unsigned int msi_enabled:1;
169 unsigned int msix_enabled:1;
4602b88d 170
1da177e4 171 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 172 struct hlist_head saved_cap_space;
1da177e4
LT		 173 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
174 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
175 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
1da177e4
LT		 176};
177
178#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
179#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
180#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
181#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
182
41017f0c
SL		 183static inline struct pci_cap_saved_state *pci_find_saved_cap(
184 struct pci_dev *pci_dev,char cap)
185{
186 struct pci_cap_saved_state *tmp;
187 struct hlist_node *pos;
188
189 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
190 if (tmp->cap_nr == cap)
191 return tmp;
192 }
193 return NULL;
194}
195
196static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
197 struct pci_cap_saved_state *new_cap)
198{
199 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
200}
201
202static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
203{
204 hlist_del(&cap->next);
205}
206
1da177e4
LT		 207/*
208 * For PCI devices, the region numbers are assigned this way:
209 *
210 * 0-5 standard PCI regions
211 * 6 expansion ROM
212 * 7-10 bridges: address space assigned to buses behind the bridge
213 */
214
4352dfd5
GKH		 215#define PCI_ROM_RESOURCE 6
216#define PCI_BRIDGE_RESOURCES 7
217#define PCI_NUM_RESOURCES 11
1da177e4
LT		 218
219#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 220#define PCI_BUS_NUM_RESOURCES 8
1da177e4 221#endif
4352dfd5
GKH		 222
223#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 224
225struct pci_bus {
226 struct list_head node; /* node in list of buses */
227 struct pci_bus *parent; /* parent bus this bridge is on */
228 struct list_head children; /* list of child buses */
229 struct list_head devices; /* list of devices on this bus */
230 struct pci_dev *self; /* bridge device as seen by parent */
231 struct resource *resource[PCI_BUS_NUM_RESOURCES];
232 /* address space routed to this bus */
233
234 struct pci_ops *ops; /* configuration access functions */
235 void *sysdata; /* hook for sys-specific extension */
236 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
237
238 unsigned char number; /* bus number */
239 unsigned char primary; /* number of primary bridge */
240 unsigned char secondary; /* number of secondary bridge */
241 unsigned char subordinate; /* max number of subordinate buses */
242
243 char name[48];
244
245 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 246 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 247 struct device *bridge;
248 struct class_device class_dev;
249 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
250 struct bin_attribute *legacy_mem; /* legacy mem */
251};
252
253#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
254#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
255
256/*
257 * Error values that may be returned by PCI functions.
258 */
259#define PCIBIOS_SUCCESSFUL 0x00
260#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
261#define PCIBIOS_BAD_VENDOR_ID 0x83
262#define PCIBIOS_DEVICE_NOT_FOUND 0x86
263#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
264#define PCIBIOS_SET_FAILED 0x88
265#define PCIBIOS_BUFFER_TOO_SMALL 0x89
266
267/* Low-level architecture-dependent routines */
268
269struct pci_ops {
270 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
271 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
272};
273
274struct pci_raw_ops {
275 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
276 int reg, int len, u32 *val);
277 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
278 int reg, int len, u32 val);
279};
280
281extern struct pci_raw_ops *raw_pci_ops;
282
283struct pci_bus_region {
284 unsigned long start;
285 unsigned long end;
286};
287
288struct pci_dynids {
289 spinlock_t lock; /* protects list, index */
290 struct list_head list; /* for IDs added at runtime */
291 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
292};
293
392a1ce7
LV		 294/* ---------------------------------------------------------------- */
295/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
296 * a set fof callbacks in struct pci_error_handlers, then that device driver
297 * will be notified of PCI bus errors, and will be driven to recovery
298 * when an error occurs.
299 */
300
301typedef unsigned int __bitwise pci_ers_result_t;
302
303enum pci_ers_result {
304 /* no result/none/not supported in device driver */
305 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
306
307 /* Device driver can recover without slot reset */
308 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
309
310 /* Device driver wants slot to be reset. */
311 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
312
313 /* Device has completely failed, is unrecoverable */
314 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
315
316 /* Device driver is fully recovered and operational */
317 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
318};
319
320/* PCI bus error event callbacks */
321struct pci_error_handlers
322{
323 /* PCI bus error detected on this device */
324 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
325 enum pci_channel_state error);
326
327 /* MMIO has been re-enabled, but not DMA */
328 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
329
330 /* PCI Express link has been reset */
331 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
332
333 /* PCI slot has been reset */
334 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
335
336 /* Device driver may resume normal operations */
337 void (*resume)(struct pci_dev *dev);
338};
339
340/* ---------------------------------------------------------------- */
341
1da177e4
LT		 342struct module;
343struct pci_driver {
344 struct list_head node;
345 char *name;
1da177e4
LT		 346 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
347 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
348 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
349 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 350 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
351 int (*resume_early) (struct pci_dev *dev);
1da177e4 352 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 353 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 354 void (*shutdown) (struct pci_dev *dev);
1da177e4 355
392a1ce7 356 struct pci_error_handlers *err_handler;
1da177e4
LT		 357 struct device_driver driver;
358 struct pci_dynids dynids;
50b00755
AC		 359
360 int multithread_probe;
1da177e4
LT		 361};
362
363#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
364
365/**
366 * PCI_DEVICE - macro used to describe a specific pci device
367 * @vend: the 16 bit PCI Vendor ID
368 * @dev: the 16 bit PCI Device ID
369 *
370 * This macro is used to create a struct pci_device_id that matches a
371 * specific device. The subvendor and subdevice fields will be set to
372 * PCI_ANY_ID.
373 */
374#define PCI_DEVICE(vend,dev) \
375 .vendor = (vend), .device = (dev), \
376 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
377
378/**
379 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
380 * @dev_class: the class, subclass, prog-if triple for this device
381 * @dev_class_mask: the class mask for this device
382 *
383 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 384 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 385 * fields will be set to PCI_ANY_ID.
386 */
387#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
388 .class = (dev_class), .class_mask = (dev_class_mask), \
389 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
390 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
391
4352dfd5 392/*
1da177e4
LT		 393 * pci_module_init is obsolete, this stays here till we fix up all usages of it
394 * in the tree.
395 */
396#define pci_module_init pci_register_driver
397
398/* these external functions are only available when PCI support is enabled */
399#ifdef CONFIG_PCI
400
401extern struct bus_type pci_bus_type;
402
403/* Do NOT directly access these two variables, unless you are arch specific pci
404 * code, or pci core code. */
405extern struct list_head pci_root_buses; /* list of all known PCI buses */
406extern struct list_head pci_devices; /* list of all devices */
407
408void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 409int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1da177e4
LT		 410char *pcibios_setup (char *str);
411
412/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 413void pcibios_align_resource(void *, struct resource *, resource_size_t,
414 resource_size_t);
1da177e4
LT		 415void pcibios_update_irq(struct pci_dev *, int irq);
416
417/* Generic PCI functions used internally */
418
419extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 420void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 421struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
422static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
423{
c431ada4
RS		 424 struct pci_bus *root_bus;
425 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
426 if (root_bus)
427 pci_bus_add_devices(root_bus);
428 return root_bus;
1da177e4 429}
cdb9b9f7
PM		 430struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
431struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 432int pci_scan_slot(struct pci_bus *bus, int devfn);
433struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 434void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 435unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 436int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 437void pci_read_bridge_bases(struct pci_bus *child);
438struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
439int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
440extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
441extern void pci_dev_put(struct pci_dev *dev);
442extern void pci_remove_bus(struct pci_bus *b);
443extern void pci_remove_bus_device(struct pci_dev *dev);
24f8aa9b 444extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 445void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 446extern void pci_sort_breadthfirst(void);
1da177e4
LT		 447
448/* Generic PCI functions exported to card drivers */
449
450struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
451struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
452struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
453int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 454int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 455int pci_find_ext_capability (struct pci_dev *dev, int cap);
29f3eb64 456struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4
LT		 457
458struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
459struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
460 unsigned int ss_vendor, unsigned int ss_device,
461 struct pci_dev *from);
462struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
29f3eb64 463struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
1da177e4
LT		 464struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
465int pci_dev_present(const struct pci_device_id *ids);
466
467int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
468int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
469int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
470int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
471int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
472int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
473
474static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
475{
476 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
477}
478static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
479{
480 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
481}
482static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
483{
484 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
485}
486static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
487{
488 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
489}
490static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
491{
492 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
493}
494static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
495{
496 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
497}
498
4a7fb636
AM		 499int __must_check pci_enable_device(struct pci_dev *dev);
500int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
1da177e4
LT		 501void pci_disable_device(struct pci_dev *dev);
502void pci_set_master(struct pci_dev *dev);
503#define HAVE_PCI_SET_MWI
4a7fb636 504int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 505void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 506void pci_intx(struct pci_dev *dev, int enable);
9c8550ee
LT		 507int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
508int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 509void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
4a7fb636
AM		 510int __must_check pci_assign_resource(struct pci_dev *dev, int i);
511int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 512void pci_restore_bars(struct pci_dev *dev);
1da177e4
LT		 513
514/* ROM control related routines */
144a50ea
DJ		 515void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
516void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 517void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
518void pci_remove_rom(struct pci_dev *pdev);
519
520/* Power management related routines */
521int pci_save_state(struct pci_dev *dev);
522int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 523int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
524pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
525int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 526
527/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
528void pci_bus_assign_resources(struct pci_bus *bus);
529void pci_bus_size_bridges(struct pci_bus *bus);
530int pci_claim_resource(struct pci_dev *, int);
531void pci_assign_unassigned_resources(void);
532void pdev_enable_device(struct pci_dev *);
533void pdev_sort_resources(struct pci_dev *, struct resource_list *);
534void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
535 int (*)(struct pci_dev *, u8, u8));
536#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 537int __must_check pci_request_regions(struct pci_dev *, const char *);
1da177e4 538void pci_release_regions(struct pci_dev *);
4a7fb636 539int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4
LT		 540void pci_release_region(struct pci_dev *, int);
541
542/* drivers/pci/bus.c */
4a7fb636
AM		 543int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
544 struct resource *res, resource_size_t size,
545 resource_size_t align, resource_size_t min,
546 unsigned int type_mask,
547 void (*alignf)(void *, struct resource *,
548 resource_size_t, resource_size_t),
549 void *alignf_data);
1da177e4
LT		 550void pci_enable_bridges(struct pci_bus *bus);
551
863b18f4 552/* Proper probing supporting hot-pluggable devices */
4a7fb636
AM		 553int __must_check __pci_register_driver(struct pci_driver *, struct module *);
554static inline int __must_check pci_register_driver(struct pci_driver *driver)
863b18f4
L		 555{
556 return __pci_register_driver(driver, THIS_MODULE);
557}
558
1da177e4
LT		 559void pci_unregister_driver(struct pci_driver *);
560void pci_remove_behind_bridge(struct pci_dev *);
561struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 562const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
563const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 564int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
565
cecf4864
PM		 566void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
567 void *userdata);
ac7dc65a 568int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 569unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 570
1da177e4
LT		 571/* kmem_cache style wrapper around pci_alloc_consistent() */
572
573#include <linux/dmapool.h>
574
575#define pci_pool dma_pool
576#define pci_pool_create(name, pdev, size, align, allocation) \
577 dma_pool_create(name, &pdev->dev, size, align, allocation)
578#define pci_pool_destroy(pool) dma_pool_destroy(pool)
579#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
580#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
581
e24c2d96
DM		 582enum pci_dma_burst_strategy {
583 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
584 strategy_parameter is N/A */
585 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
586 byte boundaries */
587 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
588 strategy_parameter byte boundaries */
589};
590
1da177e4
LT		 591#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
592extern struct pci_dev *isa_bridge;
593#endif
594
595struct msix_entry {
596 u16 vector; /* kernel uses to write allocated vector */
597 u16 entry; /* driver uses to specify entry, OS writes */
598};
599
0366f8f7 600
1da177e4
LT		 601#ifndef CONFIG_PCI_MSI
602static inline void pci_scan_msi_device(struct pci_dev *dev) {}
603static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
604static inline void pci_disable_msi(struct pci_dev *dev) {}
605static inline int pci_enable_msix(struct pci_dev* dev,
606 struct msix_entry *entries, int nvec) {return -1;}
607static inline void pci_disable_msix(struct pci_dev *dev) {}
608static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
609#else
610extern void pci_scan_msi_device(struct pci_dev *dev);
611extern int pci_enable_msi(struct pci_dev *dev);
612extern void pci_disable_msi(struct pci_dev *dev);
613extern int pci_enable_msix(struct pci_dev* dev,
614 struct msix_entry *entries, int nvec);
615extern void pci_disable_msix(struct pci_dev *dev);
616extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
617#endif
618
8b955b0d 619#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 620/* The functions a driver should call */
621int ht_create_irq(struct pci_dev *dev, int idx);
622void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 623#endif /* CONFIG_HT_IRQ */
624
e04b0ea2
BK		 625extern void pci_block_user_cfg_access(struct pci_dev *dev);
626extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
627
4352dfd5
GKH		 628/*
629 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
630 * a PCI domain is defined to be a set of PCI busses which share
631 * configuration space.
632 */
633#ifndef CONFIG_PCI_DOMAINS
634static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
635static inline int pci_proc_domain(struct pci_bus *bus)
636{
637 return 0;
638}
639#endif
1da177e4 640
4352dfd5 641#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 642
643/*
644 * If the system does not have PCI, clearly these return errors. Define
645 * these as simple inline functions to avoid hair in drivers.
646 */
647
1da177e4
LT		 648#define _PCI_NOP(o,s,t) \
649 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
650 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
651#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
652 _PCI_NOP(o,word,u16 x) \
653 _PCI_NOP(o,dword,u32 x)
654_PCI_NOP_ALL(read, *)
655_PCI_NOP_ALL(write,)
656
657static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
658{ return NULL; }
659
660static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
661{ return NULL; }
662
663static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from)
664{ return NULL; }
665
666static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
667unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
668{ return NULL; }
669
670static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
671{ return NULL; }
672
673#define pci_dev_present(ids) (0)
674#define pci_dev_put(dev) do { } while (0)
675
676static inline void pci_set_master(struct pci_dev *dev) { }
677static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
678static inline void pci_disable_device(struct pci_dev *dev) { }
679static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 680static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 681static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 682static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
683static inline void pci_unregister_driver(struct pci_driver *drv) { }
684static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 685static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 686static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 687static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
688
689/* Power management related routines */
690static inline int pci_save_state(struct pci_dev *dev) { return 0; }
691static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
692static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 693static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 694static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
695
696#define isa_bridge ((struct pci_dev *)NULL)
697
a46e8126
KG		 698#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
699
e04b0ea2
BK		 700static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
701static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
702
4352dfd5 703#endif /* CONFIG_PCI */
1da177e4 704
4352dfd5
GKH		 705/* Include architecture-dependent settings and functions */
706
707#include <asm/pci.h>
1da177e4
LT		 708
709/* these helpers provide future and backwards compatibility
710 * for accessing popular PCI BAR info */
711#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
712#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
713#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
714#define pci_resource_len(dev,bar) \
715 ((pci_resource_start((dev),(bar)) == 0 && \
716 pci_resource_end((dev),(bar)) == \
717 pci_resource_start((dev),(bar))) ? 0 : \
718 \
719 (pci_resource_end((dev),(bar)) - \
720 pci_resource_start((dev),(bar)) + 1))
721
722/* Similar to the helpers above, these manipulate per-pci_dev
723 * driver-specific data. They are really just a wrapper around
724 * the generic device structure functions of these calls.
725 */
726static inline void *pci_get_drvdata (struct pci_dev *pdev)
727{
728 return dev_get_drvdata(&pdev->dev);
729}
730
731static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
732{
733 dev_set_drvdata(&pdev->dev, data);
734}
735
736/* If you want to know what to call your pci_dev, ask this function.
737 * Again, it's a wrapper around the generic device.
738 */
739static inline char *pci_name(struct pci_dev *pdev)
740{
741 return pdev->dev.bus_id;
742}
743
2311b1f2
ME		 744
745/* Some archs don't want to expose struct resource to userland as-is
746 * in sysfs and /proc
747 */
748#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
749static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 750 const struct resource *rsrc, resource_size_t *start,
751 resource_size_t *end)
2311b1f2
ME		 752{
753 *start = rsrc->start;
754 *end = rsrc->end;
755}
756#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
757
758
1da177e4
LT		 759/*
760 * The world is not perfect and supplies us with broken PCI devices.
761 * For at least a part of these bugs we need a work-around, so both
762 * generic (drivers/pci/quirks.c) and per-architecture code can define
763 * fixup hooks to be called for particular buggy devices.
764 */
765
766struct pci_fixup {
767 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
768 void (*hook)(struct pci_dev *dev);
769};
770
771enum pci_fixup_pass {
772 pci_fixup_early, /* Before probing BARs */
773 pci_fixup_header, /* After reading configuration header */
774 pci_fixup_final, /* Final phase of device fixups */
775 pci_fixup_enable, /* pci_enable_device() time */
776};
777
778/* Anonymous variables would be nice... */
779#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 780 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 781 __attribute__((__section__(#section))) = { vendor, device, hook };
782#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
783 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
784 vendor##device##hook, vendor, device, hook)
785#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
786 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
787 vendor##device##hook, vendor, device, hook)
788#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
789 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
790 vendor##device##hook, vendor, device, hook)
791#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
792 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
793 vendor##device##hook, vendor, device, hook)
794
795
796void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
797
798extern int pci_pci_problems;
236561e5 799#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 800#define PCIPCI_TRITON 2
801#define PCIPCI_NATOMA 4
802#define PCIPCI_VIAETBF 8
803#define PCIPCI_VSFX 16
236561e5
AC		 804#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
805#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4
LT		 806
807#endif /* __KERNEL__ */
808#endif /* LINUX_PCI_H */
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